Memory management method and storage device

Abstract

The present invention provides a memory management method and a storage device. The method includes: determining multiple candidate physical units, which are dispersed in different memory areas of a memory module; detecting a system event, which includes a power-on event of the storage device; selecting a first physical unit from the multiple candidate physical units in response to the system event and reading the first physical unit; obtaining read data corresponding to a read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data; generating cryptographic information based on the error rate information; encrypting the original data based on the cryptographic information to generate encrypted data; and storing the encrypted data in a second physical unit. This improves the data encryption efficiency of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method and a storage device. Background Art

[0002] In today's digital age, with the rapid development of information technology and the increasing value of big data, data security has become a core element that cannot be ignored in storage system design. Traditional mechanical hard disk drives (HDDs) and early solid-state drives (SSDs), lacking built-in security mechanisms, are particularly vulnerable to unauthorized access and data leaks. Especially in emerging application scenarios such as cloud computing and edge computing, these traditional storage media cannot meet the stringent requirements for data integrity and confidentiality.

[0003] To address these challenges, data encryption has become a mainstream method for protecting sensitive information. Hardware-based encryption solutions are highly favored for their high performance and security. This has led to the emergence of encrypted solid-state drives (SSDs). These SSDs not only inherit the high-speed read and write capabilities of traditional SSDs, but also integrate advanced encryption algorithms and key management strategies, providing users with a fast and secure data storage platform.

[0004] Therefore, developing and optimizing high-quality encrypted SSDs has become a key focus for technical personnel in the storage field. Summary of the Invention

[0005] The present invention provides a memory management method and a storage device, which can improve the above-mentioned problem and enhance the data encryption efficiency of the storage device.

[0006] An embodiment of the present invention provides a memory management method for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the memory management method includes: determining multiple candidate physical units from the multiple physical units, wherein the multiple candidate physical units are dispersed in different memory areas in the memory module; detecting a system event, wherein the system event includes a power-on event of the storage device; in response to the system event, selecting at least one of the multiple candidate physical units as a first physical unit, and sending a read instruction sequence to the memory module to instruct the memory module to read the first physical unit; obtaining read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; generating password information based on the error rate information; encrypting original data based on the password information to generate encrypted data corresponding to the original data; and sending a write instruction sequence to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the multiple physical units.

[0007] An embodiment of the present invention further provides a storage device comprising a connection interface, a memory module, and a memory controller. The connection interface is configured to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module comprises a plurality of physical units, and the memory controller is configured to: determine a plurality of candidate physical units from the plurality of physical units, wherein the plurality of candidate physical units are dispersed across different memory regions in the memory module; detect a system event, wherein the system event comprises a power-on event of the storage device; in response to the system event, select at least one of the plurality of candidate physical units as a first physical unit, and send a read instruction sequence to the memory module to instruct the memory module to read the first physical unit; obtain read data corresponding to the read instruction sequence from the memory module; perform error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; generate cryptographic information based on the error rate information; encrypt original data based on the cryptographic information to generate encrypted data corresponding to the original data; and send a write instruction sequence to the memory module to instruct the memory module to store the encrypted data in a second physical unit of the plurality of physical units.

[0008] Based on the above, the present invention can effectively improve the problem that random numbers traditionally used for encrypting data are not random enough, thereby improving the data encryption efficiency of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of generating password information according to an embodiment of the present invention;

[0013] Figure 5 is a schematic diagram showing how encrypted data and unencrypted data are synchronously stored in a second entity unit according to an embodiment of the present invention;

[0014] Figure 6 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Figure 1 Schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, a tablet computer, a laptop computer, a desktop computer, an industrial computer, a game console, a server, or a computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to this. In addition, the storage device 12 can include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0017] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 may support an embedded Multi-Media Card (eMMC), Universal Flash Storage (UFS), Peripheral Component Interconnect Express (PCI Express), Non-Volatile Memory Express (NVM express), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (e.g., exchange signals, instructions, and / or data) via the connection interface 121.

[0018] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of a voltage (also known as a threshold voltage). For example, the memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, and / or other memory modules having the same or similar characteristics.

[0019] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be considered the control core of the memory device 12 and is used to control the memory device 12. For example, the memory controller 123 can be used to control or manage all or part of the operation of the memory device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0020] The memory controller 123 can send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, and the present invention is not limited thereto. The memory module 122 can receive the command sequence from the memory controller 123 and access the memory cells within the memory module 122 according to the command sequence.

[0021] Figure 2 FIG is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0022] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage all or part of the operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 via the host interface 21 and access the memory module 122 via the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0023] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0024] In one embodiment, the memory controller 123 may further include a decoding circuit (also known as an error correction circuit) 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data accuracy. For example, the decoding circuit 25 may support various encoding / decoding algorithms, such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), and Exclusive OR (XOR) code.

[0025] In one embodiment, the memory controller 123 may further include an encryption circuit 26. The encryption circuit 26 is connected to the memory control circuit 23 and is used to encrypt and decrypt data to ensure data confidentiality. For example, after encryption of a certain data (also referred to as the original data) by the encryption circuit 26, a ciphertext corresponding to the original data (also referred to as the encrypted data) is generated. After decryption of this ciphertext (i.e., the encrypted data) by the encryption circuit 26, the plaintext corresponding to the ciphertext (i.e., the original data) can be restored.

[0026] In one embodiment, the encryption circuit 26 may support symmetric encryption algorithms, asymmetric encryption algorithms, or other types of encryption / decryption algorithms. For example, symmetric encryption algorithms may include AES (Advanced Encryption Standard)-256, while asymmetric encryption algorithms may include RSA (Rivest-Shamir-Adleman), but the present invention is not limited thereto. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits), but the present invention is not limited thereto.

[0027] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used for non-volatile data storage.

[0028] In one embodiment, a physical unit may include one or more physical programming units. In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit may be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit may be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0029] In one embodiment, a physical programming unit is the smallest unit to which data is written synchronously in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be programmed synchronously to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0030] In one embodiment, a physical erase unit may include multiple physical programming units. Multiple physical programming units in a physical erase unit may be erased simultaneously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to multiple physical programming units in the physical erase unit to change the threshold voltages of at least some of the memory cells in these physical programming units. By performing an erase operation on a physical erase unit, data stored in the physical erase unit may be cleared.

[0031] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also known as user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0032] In one embodiment, if a physical unit does not store valid data, the physical unit may be associated with the idle area 32. Furthermore, the physical units in the idle area 32 may be erased to clear the data in the physical units. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0033] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cells, the physical cells may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0034] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management unit. A logical unit may be mapped to one or more physical units.

[0035] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 may determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is currently not mapped by any logical unit, the memory control circuit 23 may determine that the physical unit does not currently store any valid data.

[0036] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data read, write, or erase based on the information in the management table (i.e., the logical-to-physical mapping table).

[0037] In one embodiment, the memory control circuit 23 may predetermine a plurality of physical units (also referred to as candidate physical units) in the memory module 122. For example, the plurality of candidate physical units may be dispersed across different memory regions in the memory module 122. For example, the different memory regions may include at least one of different dies, different chip-enabled (CE) regions, and different planes in the memory module 122. In one embodiment, the different memory regions may also include different physical blocks (i.e., different physical erase units) and / or different physical pages (i.e., physical programming units) in the memory module 122.

[0038] In one embodiment, the memory control circuit 23 can detect system events. The system event may include a power-on event of the storage device 12. Alternatively, in one embodiment, the system event may also include a power-on event and / or other types of custom events. For example, the custom event may include the usage status of the storage device 12 or the memory module 122 meeting a specific condition (e.g., the read count, write count, and / or erase count of the memory module 122 reaching a critical value), etc., although the present invention is not limited thereto.

[0039] In one embodiment, when the system event is detected, the memory controller 23 may select at least one of the candidate physical units as a specific physical unit (also referred to as a first physical unit) in response to the system event. For example, the first physical unit may include Figure 3 At least one of the entity units 301(1)~301(B).

[0040] In one embodiment, in response to the system event, the memory controller 23 may select one of the plurality of candidate physical units as the first physical unit based on a round-robin or other customized method. For example, the customized method may include selecting at least one physical unit from candidate physical units located in different memory regions as the first physical unit each time, although the present invention is not limited thereto.

[0041] In one embodiment, after determining the first physical unit, the memory controller 23 may send a read instruction sequence to the memory module 11. The read instruction sequence may be used to instruct the memory module 122 to read the first physical unit. Based on the read result of the memory module 122, the memory control circuit 23 may obtain the read data corresponding to the read instruction sequence from the memory module 122. For example, assuming that the first physical unit is Figure 3 The read data may reflect the reading result of the memory module 122 on the physical unit 301 (i).

[0042] In one embodiment, after obtaining the read data, the memory control circuit 23 may perform error detection on the read data. The error detection is used to obtain error rate information of the read data. The error rate information may reflect the bit error rate (BER) of the read data. For example, the error rate information (i.e., the bit error rate) may reflect the number of error bits present in a predetermined amount of read data.

[0043] It should be noted that the error detection may be performed by the memory control circuit 23 or by the memory control circuit 23 in conjunction with the decoding circuit 25. However, in one embodiment, the error detection does not include error correction of the read data by the decoding circuit 25. For example, the error correction is used to correct errors (i.e., erroneous bits) in the read data.

[0044] That is, in one embodiment, the memory control circuit 23 may perform error detection on the read data without performing error correction on the read data to obtain the error rate information, thereby saving power consumption of the memory device 12 .

[0045] In one embodiment, in response to the system event, the memory controller 23 may further disable the error correction circuit (i.e., the decoding circuit 25). While the error correction circuit (i.e., the decoding circuit 25) is in the disabled state, the memory controller 23 may perform a self-test operation to obtain the error rate information. For example, this self-test operation may be automatically initiated and performed in response to the system event to obtain the error rate information. For example, this self-test operation may include the aforementioned steps of determining a first physical unit from a plurality of candidate physical units, reading the first physical unit to obtain the read data, and obtaining the error rate information corresponding to the read data. In one embodiment, if the system event is not detected, the memory controller 23 may not perform the self-test operation to conserve system resources.

[0046] In one embodiment, based on the results of the self-test operation, the memory controller 23 may also transmit the error rate information to the host system 11 for use by the host system 11. For example, the host system 11 may encrypt data or perform other custom operations based on the error rate information. The following describes how to encrypt data based on the error rate information.

[0047] In one embodiment, after obtaining the error rate information, the memory control circuit 23 may generate cryptographic information based on the error rate information. Taking the AES-256 encryption algorithm as an example, the cryptographic information may include private key information and initialization sequence information. The private key information may include information about the key used to perform encryption in the AES-256 encryption algorithm. The initialization sequence information may include information about the initialization sequence (also known as the initialization vector) used to perform encryption in the AES-256 encryption algorithm. It should be noted that the information content of the cryptographic information may vary depending on different encryption algorithms, and the present invention is not limited thereto.

[0048] In one embodiment, after obtaining the password information, the encryption circuit 26 may encrypt the data (i.e., the original data) according to the password information to generate encrypted data corresponding to the original data. Taking the AES-256 encryption algorithm as an example, the encryption circuit 26 may encrypt the original data based on the password information and the AES-256 encryption algorithm to generate the encrypted data. It should be noted that the encryption circuit 26 may also use other encryption algorithms to encrypt the original data, and the present invention is not limited thereto.

[0049] In one embodiment, after obtaining the encrypted data, the memory control circuit 23 may send a write command sequence to the memory module 122. The write command sequence may be used to instruct the memory module 122 to store the encrypted data in at least one physical unit (also referred to as the second physical unit). For example, assuming that the first physical unit is Figure 3The entity unit 301 (i) of the second entity unit can be Figure 3 , and i is different from j. Alternatively, in one embodiment, i may be equal to j.

[0050] It should be noted that in the aforementioned embodiment, the accuracy of each data read from the first physical unit (or the bit error rate) is affected by the current operating state of the memory module 122. For example, the operating state includes the read voltage applied to the first physical unit, the length of time the read voltage is applied, the critical voltage distribution of the plurality of memory cells in the first physical unit, the ambient temperature and / or the clock frequency, etc., and the type of the operating state is not limited thereto. Therefore, at different time points, based on the current operating state of the memory module 122, the read result for the first physical unit may be different. As a result, compared to a conventional pseudo random number generator (PRNG) and / or true random number generator (TRNG), the bit error rate of the read result can be closer to a true random number (i.e., cannot be accurately predicted).

[0051] Furthermore, by distributing the multiple candidate physical units across different memory regions (e.g., different dies, different chip enable (CE) regions, different planes, different physical blocks, and / or different physical pages) within the memory module 122, it is possible to avoid a reduction in the randomness of the cryptographic information subsequently generated due to excessive data reads from a single or small portion of the memory module 122. In other words, by distributing the multiple candidate physical units across different memory regions (e.g., different dies, different chip enable (CE) regions, different planes, different physical blocks, and / or different physical pages) within the memory module 122, the randomness of the cryptographic information generated each time the first physical unit is read can be further improved.

[0052] In one embodiment, the cryptographic information is obtained based on the bit error rate of the read data and the original data is encrypted based on the cryptographic information. This can improve the defects of the pseudo-random number generator (PRNG) and / or true random number generator (TRNG), such as the random numbers generated being not random enough or even having patterns, thereby improving the efficiency of subsequent data encryption and increasing the difficulty of cracking the encrypted data. Thus, the data storage security of the storage device 12 can be effectively improved.

[0053] In one embodiment, after obtaining the error rate information, the memory control circuit 23 may perform information processing on the error rate information to obtain reference information. For example, the memory control circuit 23 may perform logarithmic transformation on the error rate information to obtain the reference information. For example, the logarithmic transformation may include taking the natural logarithm and / or performing other logical operations on the error rate information.

[0054] In one embodiment, the reference information may conform to a predetermined data format that matches the encryption algorithm used to generate the password information. For example, assuming the encryption algorithm is AES-256, the predetermined data format may match the AES-256 encryption algorithm. For example, the predetermined data format may be used to standardize the data length of the reference information to a predetermined length to meet the subsequent computational requirements of the AES-256 encryption algorithm. The memory control circuit 23 may then generate the password information based on the reference information.

[0055] In one embodiment, during the information processing, the memory control circuit 23 may first perform the logarithmic transformation on the error rate information to obtain temporary information (also referred to as first temporary information). The memory control circuit 23 may then perform at least one of taking an absolute value, extracting at least a portion of the value after the decimal point, removing at least a portion of the value after the decimal point, converting the value units, performing a polynomial operation, performing a hash operation, performing a key derivation function, and other custom processing on the first temporary information to obtain the reference information. The following description uses a hash operation as an example to obtain the reference information, but the present invention is not limited thereto. For example, the hash operation may employ SHA-256 or SHA-3, and the present invention is not limited thereto.

[0056] In one embodiment, in the information processing, after obtaining the first temporary information, the memory control circuit 23 may perform a numerical conversion on the first temporary information to obtain another temporary information (also referred to as the second temporary information). For example, the second temporary information may be in the form of a character string. After obtaining the second temporary information, the memory control circuit 23 may perform an encoding process on the second temporary information to obtain another temporary information (also referred to as the third temporary information). For example, the third temporary information may be in a byte type. After obtaining the third temporary information, the memory control circuit 23 may perform the hash operation on the third temporary information to obtain another temporary information (also referred to as the fourth temporary information). For example, the fourth temporary information may include a character string consisting of hexadecimal characters. After obtaining the fourth temporary information, the memory control circuit 23 may perform information extraction or information padding on the fourth temporary information to obtain the reference information.

[0057] In one embodiment, if the data length of the string generated by the hash operation in the fourth temporary information is longer than the data length specified by the reference information, the memory control circuit 23 may extract the first N bytes (or the last N bytes, etc., which are not limited by the present invention) from the string generated by the hash operation through the information extraction operation to obtain the reference information. Taking the AES-256 encryption algorithm as an example, N here may be 32 (i.e., 256 bits or 64 hexadecimal characters). If other encryption algorithms are used, N may also be other values. Alternatively, in one embodiment, if the data length of the string generated by the hash operation in the fourth temporary information is shorter than the data length specified by the reference information, the memory control circuit 23 may add (i.e., fill) preset data to the string generated by the hash operation through the information filling operation to obtain the reference information.

[0058] In other words, even if one or more temporary data generated during the information processing process do not conform to the preset data format, the reference information that conforms to the preset data format can still be obtained through the information extraction or information filling. Thereafter, the memory control circuit 23 can generate the password information based on the reference information.

[0059] Figure 4 This is a schematic diagram of generating password information according to an embodiment of the present invention. Figure 4 , the memory control circuit 23 may obtain error rate information 41. For example, the error rate information 41 may reflect the bit error rate of the read data read from the first physical unit. For example, the error rate information 41 may include a numerical value or a data sequence to reflect the bit error rate of the read data. After obtaining the error rate information 41, the memory control circuit 23 may perform information processing 401 on the error rate information 41 to obtain reference information 42. For example, the information processing 401 may include taking a logarithm (e.g., a natural logarithm), taking an absolute value, extracting at least a portion of the value after the decimal point, removing at least a portion of the value after the decimal point, converting the numerical unit, performing a polynomial operation, performing a hash operation, and / or other custom processing. The specific operational details of the information processing 401 may be set according to the encryption algorithm used and are not limited by the present invention. Based on the result of the information processing 401, the memory control circuit 23 may obtain the reference information 42. Similar to the error rate information 41, the reference information 42 may approach a truly random number (i.e., it cannot be accurately predicted).

[0060] In one embodiment, after obtaining the reference information 42, the memory control circuit 23 may generate the encryption information 43 according to the reference information 42. For example, taking the AES-256 encryption algorithm as an example, the encryption information 43 may include key information 431 and initialization sequence information 432.

[0061] In one embodiment, the memory control circuit 23 may perform a data transformation (also referred to as a first data transformation) 411 on the reference information 42 to obtain key information 431. For example, the key information 431 may include information about a key used for performing encryption in the encryption algorithm used by the encryption circuit 26. Furthermore, the memory control circuit 23 may perform another data transformation (also referred to as a second data transformation) 412 on the reference information 42 to obtain initialization sequence information 432. For example, the initialization sequence information 432 may include information about an initialization sequence (or initialization vector) used for performing encryption in the encryption algorithm used by the encryption circuit 26.

[0062] In one embodiment, the data format (e.g., data length) of key information 431 may differ from the data format (e.g., data length) of initialization sequence information 432. For example, using the AES-256 encryption algorithm as an example, the data lengths of key information 431 and initialization sequence information 432 used in the AES-256 encryption algorithm may be 256 bits and 128 bits, respectively. However, the data formats of key information 431 and / or initialization sequence information 432 may be adjusted according to practical needs and are not limited by the present invention.

[0063] It should be noted that in Figure 4 In the embodiment of FIG. 4 , information processing 401, first data conversion 411, and second data conversion 412 can all be set or configured according to the encryption algorithm used by encryption circuit 26. Thus, information processing 401, first data conversion 411, and second data conversion 412 can be used to generate reference information 42, key information 431, and initialization sequence information 432, respectively, that match the encryption algorithm used by encryption circuit 26.

[0064] In one embodiment, after obtaining the reference information, the memory control circuit 23 may further generate and enhance the security of the cryptographic information (e.g., key information) generated based on the reference information by adding a salt value, using more entropy sources, or using a more effective key derivation function (KDF). For example, the key derivation function may include at least one of PBKDF2 (Password-Based Key Derivation Function 2), bcrypt, and scrypt. PBKDF2 is a widely used key derivation function that is an iterative version of HMAC (Hash Message Authentication Code). Its main features are that it allows the use of a salt value to increase the randomness of the derived key, and that the computational complexity can be increased by adjusting the number of iterations, thereby improving security.

[0065] In one embodiment, the memory control circuit 23 may also convert the cryptographic information originally generated by block encryption into cryptographic information in the form of a stream cipher through a counter (CTR) mode. For example, in the counter mode, the encryption circuit 26 encrypts a series of input data blocks (referred to as counts) and generates a series of output data. Then, by performing an exclusive OR (XOR) operation on each output data and the corresponding plaintext (i.e., the original data), the encrypted data may be obtained. In this way, the data reading and writing speed of the storage device 12 and the security of data storage may be improved. Alternatively, in one embodiment, the memory control circuit 23 may also generate the encrypted data through an XTS (XOR-based Twin encryption) mode. In addition, many other types of encryption technologies may be applied to the embodiments of the present invention, which will not be described one by one here.

[0066] In one embodiment, before storing the encrypted data in the second physical unit, the memory control circuit 23 may perform error correction code (ECC) encoding on the encrypted data to generate error correction data. The error correction data may be used to correct errors (i.e., erroneous bits) in the encrypted data. For example, the error correction data may include error correction information (e.g., an error correction code) corresponding to the encrypted data.

[0067] In one embodiment, after obtaining the encrypted data and the error correction data, the memory control circuit 23 may store the encrypted data in a data area of ​​the second physical unit. In addition, the memory control circuit 23 may store the password information and the error correction data in a spare area of ​​the second physical unit.

[0068] In one embodiment, the memory controller 23 may read the encrypted data from the data area of ​​the second physical unit. Furthermore, the memory controller 23 may read the error correction data and the password information from the idle area of ​​the second physical unit. The memory controller 123 may then restore the encrypted data to the original data based on the error correction data and the password information. For example, the decoding circuit 25 may decode the encrypted data read from the data area based on the error correction data to attempt to correct errors in the read encrypted data. The encryption circuit 26 may then decrypt the corrected encrypted data based on the password information to restore the original data.

[0069] In one embodiment, after obtaining the encrypted data, the memory controller 23 may also store the encrypted data and the unencrypted data synchronously in the same physical unit (i.e., the second physical unit). For example, the unencrypted data is obtained from at least one physical unit (also referred to as the third physical unit) in the memory module 122 through a data consolidation operation, and the unencrypted data has not been encrypted by the encryption circuit 26. For example, the data consolidation operation may include a garbage collection (GC) operation. The third physical unit may include at least one physical unit that is determined to be a source unit of valid data in the data consolidation operation. For example, the third physical unit may include Figure 3 At least one of the entity units 301(1)~301(A).

[0070] Figure 5 Schematic diagram of synchronously storing encrypted data and unencrypted data in the second entity unit according to an embodiment of the present invention. Figure 5 , according to the password information (such as Figure 4 After obtaining the encrypted data 51 using the password information 43, the memory controller 23 may synchronously store the encrypted data 51 and the unencrypted data 52 into the same physical unit 501 (ie, the second physical unit).

[0071] In one embodiment, the memory controller 23 may collect (i.e., read) valid data from the third physical unit through a data consolidation operation. The memory controller 23 may then use the valid data collected (i.e., read) from the third physical unit and not encrypted by the encryption circuit 26 as the unencrypted data (e.g., unencrypted data 52).

[0072] In one embodiment, after obtaining the encrypted data, the memory controller 23 may determine whether the total data length of at least one encrypted data obtained satisfies (e.g., is the same as) the data storage capacity of one physical unit (e.g., the second physical unit). If the total data length of the encrypted data is less than the data storage capacity of one physical unit (e.g., the second physical unit), the memory controller 23 may store the encrypted data and the unencrypted data synchronously in the second physical unit. For example, the total data length of the encrypted data and the unencrypted data synchronously stored in the second physical unit may satisfy (e.g., be the same as) the data storage capacity of one physical unit (e.g., the second physical unit). However, if the total data length of the encrypted data is not less than (e.g., is greater than) the data storage capacity of one physical unit (e.g., the second physical unit), the memory controller 23 may store the encrypted data alone in the second physical unit without additionally storing the unencrypted data in the second physical unit.

[0073] In one embodiment, if the encrypted data and the unencrypted data are synchronously stored in the same physical unit (i.e., the second physical unit), when data is subsequently read from the second physical unit, the portion of the data read (i.e., the encrypted data) needs to be decrypted to restore the original data, while the other portion of the data read (i.e., the unencrypted data) does not need to be decrypted. This improves the efficiency of using a single physical unit and avoids wasting part of the physical unit's storage space due to insufficient encrypted data to be stored.

[0074] Figure 6 FIG is a flow chart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, a plurality of candidate entity units are determined from a plurality of entity units in a memory module, wherein the plurality of candidate entity units are dispersed across different memory regions in the memory module. In step S602, a system event is detected, wherein the system event comprises a power-on event of a storage device. In step S603, in response to the system event, at least one of the plurality of candidate entity units is selected as a first entity unit, and a read instruction sequence is sent to the memory module to instruct the memory module to read the first entity unit. In step S604, read data corresponding to the read instruction sequence is obtained from the memory module. In step S605, error detection is performed on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data. In step S606, cryptographic information is generated based on the error rate information. In step S607, original data is encrypted based on the cryptographic information to generate encrypted data corresponding to the original data. In step S608 , a write command sequence is sent to the memory module to instruct the memory module to store the encrypted data into a second physical unit among the plurality of physical units.

[0075] However, Figure 6 The steps have been described in detail above and will not be repeated here. Figure 6 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figure 6 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0076] In summary, the memory management method and storage device proposed in the embodiments of the present invention can generate cryptographic information for encryption based on error rate information. For example, based on the error rate information, slight changes in the current operating state of the memory module can be reflected in the cryptographic information to improve the randomness of the cryptographic information. Furthermore, by effectively distributing and / or rotating the use of physical units in different memory areas to obtain corresponding error rate information, the randomness of the cryptographic information can be further effectively improved. This effectively alleviates the problem of random numbers traditionally used for data encryption being insufficiently random, thereby improving the data encryption efficiency and data storage security of the storage device.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: determining a plurality of candidate entity units from the plurality of entity units, wherein the plurality of candidate entity units are dispersed in different memory areas in the memory module; detecting a system event, wherein the system event comprises a power-on event of the storage device; In response to the system event, selecting at least one of the plurality of candidate physical units as a first physical unit, and sending a read instruction sequence to the memory module to instruct the memory module to read the first physical unit; Obtain read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; generating password information according to the error rate information; Encrypting the original data according to the password information to generate encrypted data corresponding to the original data; and A write command sequence is sent to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the plurality of physical units. 2 . The memory management method according to claim 1 , wherein the error detection does not include error correction of the read data.

3. The memory management method according to claim 2, further comprising: In response to the system event, shutting down the error correction circuit; as well as When the error correction circuit is in the off state, a self-test operation is performed to obtain the error rate information.

4. The memory management method according to claim 3, further comprising: The error rate information is transmitted to a host system connected to the storage device according to an execution result of the self-test operation, so as to be used by the host system.

5. The memory management method according to claim 1 , wherein the step of generating the password information according to the error rate information comprises: performing a logarithmic transformation on the error rate information to obtain reference information, wherein the reference information conforms to a preset data format, and the preset data format matches an encryption algorithm used to generate the password information; as well as The password information is generated according to the reference information.

6. The memory management method according to claim 5, wherein the step of performing the logarithmic transformation on the error rate information to obtain the reference information comprises: performing the logarithmic transformation process on the error rate information to obtain first temporary information; as well as Perform at least one of taking the absolute value, extracting at least part of the value after the decimal point, removing at least part of the value after the decimal point, numerical unit conversion, polynomial operation, hash operation, key derivation function and other custom processing on the first temporary information to obtain the reference information.

7. The memory management method according to claim 6, wherein the step of performing at least one of taking the absolute value, extracting at least part of the value after the decimal point, removing at least part of the value after the decimal point, converting the value unit, performing the polynomial operation, performing the hash operation, performing the key derivation function, and performing the other custom processing on the temporary information to obtain the reference information comprises: performing a numerical conversion on the first temporary information to obtain second temporary information; performing encoding processing on the second temporary information to obtain third temporary information; performing the hash operation on the third temporary information to obtain fourth temporary information; as well as Information extraction or information filling is performed according to the fourth temporary information to obtain the reference information.

8. The memory management method according to claim 1 , wherein in response to the system event, the step of selecting the at least one of the plurality of candidate entity units as the first entity unit comprises: In response to the system event, at least one of the candidate entity units is selected as the first entity unit from the plurality of candidate entity units in a rotation or customized manner. 9 . The memory management method according to claim 1 , wherein the different memory regions comprise at least one of different dies, different chip enable regions, and different planes in the memory module.

10. The memory management method according to claim 1 , wherein the step of sending the write instruction sequence to the memory module to instruct the memory module to store the encrypted data in the second physical unit among the plurality of physical units comprises: Synchronously storing the encrypted data and the unencrypted data in the second entity unit, The unencrypted data is obtained from a third physical unit among the plurality of physical units through a data consolidation operation, and the unencrypted data has not been encrypted.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: determining a plurality of candidate entity units from the plurality of entity units, wherein the plurality of candidate entity units are dispersed in different memory areas in the memory module; detecting a system event, wherein the system event comprises a power-on event of the storage device; In response to the system event, selecting at least one of the plurality of candidate physical units as a first physical unit, and sending a read instruction sequence to the memory module to instruct the memory module to read the first physical unit; Obtain read data corresponding to the read instruction sequence from the memory module; performing error detection on the read data to obtain error rate information of the read data, wherein the error rate information reflects a bit error rate of the read data; generating password information according to the error rate information; Encrypting the original data according to the password information to generate encrypted data corresponding to the original data; as well as A write command sequence is sent to the memory module to instruct the memory module to store the encrypted data in a second physical unit among the plurality of physical units. 12 . The memory device of claim 11 , wherein the error detection does not include error correction of the read data.

13. The storage device according to claim 12, wherein the memory controller is further configured to: In response to the system event, shutting down the error correction circuit; and When the error correction circuit is in the off state, a self-test operation is performed to obtain the error rate information.

14. The storage device according to claim 13, wherein the memory controller is further configured to: The error rate information is transmitted to the host system according to the execution result of the self-test operation for use by the host system.

15. The storage device according to claim 11, wherein the operation of generating the password information according to the error rate information comprises: performing a logarithmic transformation on the error rate information to obtain reference information, wherein the reference information conforms to a preset data format, and the preset data format matches an encryption algorithm used to generate the password information; as well as The password information is generated according to the reference information.

16. The storage device according to claim 15, wherein the operation of performing the logarithmic transformation on the error rate information to obtain the reference information comprises: performing the logarithmic transformation process on the error rate information to obtain first temporary information; as well as Perform at least one of taking the absolute value, extracting at least part of the value after the decimal point, removing at least part of the value after the decimal point, numerical unit conversion, polynomial operation, hash operation, key derivation function and other custom processing on the first temporary information to obtain the reference information.

17. The storage device according to claim 16, wherein the operation of performing at least one of taking the absolute value, extracting at least part of the value after the decimal point, removing at least part of the value after the decimal point, converting the value unit, performing the polynomial operation, performing the hash operation, performing the key derivation function, and performing the other custom processing on the temporary information to obtain the reference information comprises: performing a numerical conversion on the first temporary information to obtain second temporary information; performing encoding processing on the second temporary information to obtain third temporary information; performing the hash operation on the third temporary information to obtain fourth temporary information; as well as Information extraction or information filling is performed according to the fourth temporary information to obtain the reference information.

18. The storage device according to claim 11, wherein in response to the system event, the operation of selecting the at least one of the plurality of candidate entity units as the first entity unit comprises: In response to the system event, at least one of the candidate entity units is selected as the first entity unit from the plurality of candidate entity units in a rotation or customized manner.

19. The memory device of claim 11, wherein the different memory regions comprise at least one of different dies, different chip enable regions, and different planes in the memory module.

20. The storage device according to claim 11, wherein the operation of sending the write command sequence to the memory module to instruct the memory module to store the encrypted data in the second physical unit among the plurality of physical units comprises: Synchronously storing the encrypted data and the unencrypted data in the second entity unit, The unencrypted data is obtained from a third physical unit among the plurality of physical units through a data consolidation operation, and the unencrypted data has not been encrypted.

Images