Physical unclonable function (PUF) circuit based on XOR iteration and operation method thereof

Abstract

The invention provides a physical unclonable function (PUF) circuit based on XOR iteration and an operation method, and belongs to the field of physical unclonable function design. The circuit comprises a nonvolatile transistor array, and a peripheral register circuit, an XOR circuit and a readout comparison circuit, an XOR iterative operation is utilized to continuously perform XOR and iterative operations on an initially input challenge signal R [0] and R [1] through the nonvolatile transistor array and the peripheral register circuit and the XOR circuit to obtain an nth iterative result R [n + 1], a CRP generation process of the PUF is realized; according to the method, verification of the PUF can be completed through a single challenge signal, the complexity of PUF design is remarkably improved through multiple iteration processes, the PUF design has a reconfigurable function by repeatedly carrying out erasing operation on the transistor array and changing internal fingerprints of the PUF, the safety of machine learning resisting modeling of the PUF is improved, and the method has the advantages of being high in practicability and easy to popularize. The hardware cost and the power consumption overhead of the PUF are obviously reduced through simple circuit design and working steps.

Description

Technical Field

[0001] The present invention relates to the field of physical unclonable function design, and in particular to a physical unclonable function (PUF) design based on XOR iteration with high security and resistance to modeling attacks. Background Art

[0002] The vigorous expansion of edge computing and the rapid growth of mobile devices have brought about a massive demand for cloud-edge data interaction. These large numbers and various types of edge hardware devices are connected to the cloud that stores important privacy information such as user security keys, behavioral habits, and medical health, becoming key nodes vulnerable to identity attacks, asset attacks, etc., causing important security issues such as data leakage. As a hardware-level security primitive, the physical unclonable function (PUF) uses the process fluctuations of device preparation or the physical random mechanism in the working process as an unpredictable hardware fingerprint, providing a lightweight identity security solution for devices deployed in unsupervised environments. Therefore, it is widely used in device identity authentication and various communication security protocols. As a physical entity, PUF can perform externally undetectable and mathematically unpredictable black box processing (interacting with its own random fluctuations) on a given input (Challenge signal Challenge, referred to as C), and then transform it into an output (Response signal Response, referred to as R).

[0003] Because the black box operation is essentially determined by the physical mechanism and circuit design inside the PUF, the mapping relationship of its input-output signals, namely the Challenge-Response Pair (CRP), can be used as a unique fingerprint at the hardware level for the legitimate identity authentication of the device. In the actual verification process, CRP is binary, and the PUF will first register with the cloud in a secure environment: the cloud sends enough different Cs and collects the R returned by the PUF, and establishes a CRP library of the PUF entity in the cloud. In an insecure environment, before the PUF requests to establish communication with the cloud, the cloud will randomly select a small number of Cs from the established CRP library and send it to the PUF, and compare the response result R of this PUF entity with the R in the library. If the match exceeds the judgment threshold (such as 95%), the PUF can be considered to be legitimate.

[0004] Since the "fingerprint" is only determined by the physical differences and manufacturing deviations inside the PUF, and it has the properties of anti-tampering, unmodelable, anti-collision and stable reproduction. The security of PUF is one of its most important indicators. However, the anti-modeling security of traditional CMOS PUFs such as static random access memory SRAM-PUF and delay arbiter-PUF reported so far often requires complex circuit design, which will bring significant hardware and power consumption overhead when deployed on edge devices; at the same time, traditional CMOS PUF uses random deviations in the process manufacturing process as a static entropy source (Entropy Source), and its fingerprint does not have the ability of CRP reconfiguration, facing privacy security risks when users replace it. In order to solve the above-mentioned overhead and reconstruction problems, new non-volatile NVM PUFs such as resistive random access memory RRAM-PUF and magnetic random access memory MRAM-PUF have been proposed one after another. Among them, RRAM-PUF uses IV nonlinearity or threshold switching randomness of conductive filaments as entropy source, and MRAM-PUF uses flipping randomness of free layer under the action of current magnetic field as entropy source; finally, CRP is generated by linear summation and comparison of device current in array. However, simpler spatial coupling methods such as linear operation in the CRP generation process have security problems of PUF under modeling attacks such as machine learning, such as speculation attacks based on greedy algorithm and simulated annealing. At the same time, these PUFs need to compare a large number of C and R to determine identity during verification, but these leaked parts of CRP may cause attackers to model all CRPs through modeling methods such as machine learning. Therefore, realizing reconfigurable functions, improving the CRP coupling complexity of PUF, and reducing leaked CRP information are of great significance for realizing high-security PUF circuits that are resistant to machine learning modeling. Summary of the invention

[0005] In view of the problems existing in the above prior art, the present invention proposes a physical unclonable function PUF circuit and its operation method based on XOR iterative operation to achieve high security against modeling attacks, and realizes a CRP generation method that is more difficult to model and predict at a lower hardware cost, improves the coupling complexity of CRP, and has a reconfigurable function. Compared with traditional CMOS-based or NVM-based PUF, the present invention breaks through the verification method in PUF that requires a large number of Cs and corresponding Rs to be verified at the same time, directly uses R as a new C for continuous iteration, and can complete the verification using a single C, avoiding the risk of machine learning modeling caused by CRP leakage.

[0006] The technical solution of the present invention is as follows:

[0007] A physical unclonable function (PUF) circuit based on XOR iteration is used for generating PUF challenge-response pairs CRP, characterized in that the circuit comprises: a non-volatile transistor array, and a peripheral register circuit (DFF), an XOR circuit (XOR), and a readout comparison circuit. The non-volatile transistor array is an m-row and m-column array structure formed by connecting two basic units composed of non-volatile transistors through a circuit. The two word lines WL and WL of each basic unit in the array structure are The bit line BL of each column of basic units is connected to the drive circuit, and the sense line SL is connected to the readout comparison circuit; the gates of the two non-volatile transistors in the basic unit are opposite to each other and are axially symmetrical, wherein the gate of one transistor is connected to the word line WL, and the gate of the other transistor is connected to the complementary word line WL. The drains of the two nonvolatile transistors are connected to the bit line BL, and the sources are connected to the sense line SL. In the basic unit, the storage states of the two nonvolatile transistors are complementary, and the level states of the two word lines WL connected to their gates are also complementary.

[0008] The register circuit includes a register circuit 1 and a register circuit 2, which are used for storing and updating a response R vector of a physical unclonable function PUF during an XOR iterative calculation process. The register circuit 1 stores the response R of the current iterative calculation, and inputs the binary "1" and "0" in R as high and low levels, respectively, to the word lines of the row basic units of the non-volatile transistor array by row. At the same time, the register circuit 1 outputs the response R of the previous iterative calculation to the register circuit 2.

[0009] The readout comparison circuit is used to read and compare the current of the non-volatile transistor array SL, through the sense amplifier (SA) connected to each column SL, with the threshold current I ref Compare the size and output "1" or "0" bit signal to the XOR circuit;

[0010] The XOR circuit is used to perform a bitwise XOR operation on the R vector output by the register circuit 1 and the current comparison result vector output by the readout comparison circuit, and the result is output to the register circuit 2.

[0011] Furthermore, the non-volatile transistor is a floating-gate or charge-trapping field effect transistor, that is, a storage layer is inserted into the gate stack layer, and the storage layer uses a semiconductor material composed of a floating gate / trapping layer and a tunneling dielectric layer, and the threshold voltage of the transistor is modulated by capturing / de-trapping the charge in the channel; or it is a ferroelectric field effect transistor (Ferroelectric FET, FeFET), that is, a layer of ferroelectric material is inserted into the gate stack layer, and the threshold voltage of the non-volatile modulated transistor is modulated by changing the polarization state of the ferroelectric material.

[0012] The present invention also provides an operation method of the XOR-iterative-based physical unclonable function PUF circuit, which is used for generating a PUF challenge-response pair CRP, and is characterized in that the steps include:

[0013] 1) Write the fingerprint matrix W into the basic unit of the m-row and m-column non-volatile transistor array, where W is a binary matrix of "0" and "1", and the two storage state complementary transistors of each basic unit store an element in W;

[0014] 2) Input the response R vector corresponding to the initial challenge signal C, denoted as R [0] and R [1] , respectively R [0] Stored in register circuit 1 and R [1] Stored in register circuit 2 as the initial seed for iteration;

[0015] 3) The R vector stored in register circuit 2 is used as the WL input of the non-volatile transistor array. In-memory computing will be performed in each basic unit and output as the current of SL to the readout comparison circuit to obtain the current of each column of the non-volatile transistor array and the threshold current I of the sense amplifier. ref The comparison result f(R [n] ,W), n represents the number of iteration cycles, and its value is the current number of iterations;

[0016] 4) Compare the results f(R [n] ,W) and register circuit 1 stores R [n-1] They are used as the two inputs of the XOR circuit respectively, and the bitwise XOR operation is performed to obtain the new input R for the next iteration. [n+1] ;

[0017] 5) The new input R of the next iteration [n+1] Stored in register circuit 2, and the R previously stored in register circuit 2 [n] Stored in register circuit 1 for the next XOR iteration;

[0018] 6) Continuously repeat the operations in step 3) to step 5) for a specific number of iterations until a predetermined number of iterations is reached, and output the result stored in the register circuit 2 at this time.

[0019] Furthermore, in the operation method, the threshold current I ref The value of I ref =m / 2·I on , where I on is the on-state current output by the non-volatile transistor, m is the number of rows of the non-volatile transistor array, and m is an odd number.

[0020] The present invention uses XOR iteration operation to convert an initial input challenge signal C=R [0] , R [1] Through the non-volatile transistor array and peripheral circuits, XOR and iterative operations are continuously performed to obtain the nth iteration result R [n+1] , realizing the CRP generation process of PUF. Compared with the previous PUF verification method that requires multiple Cs and multiple corresponding Rs, the present invention only needs one challenge signal C to complete the verification process, reducing the exposure of PUF information, improving the security of PUF anti-machine learning modeling, and significantly reducing the hardware cost and power consumption of PUF through simple circuit design and working steps. Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The present invention is essentially different from the existing PUF based on multiple CRPs for identity authentication. It uses an XOR iterative solution to complete the verification of the PUF through a single challenge signal, avoiding the security issues of machine learning modeling attacks caused by the need to expose multiple CRPs in traditional PUFs, while improving verification efficiency.

[0022] 2. The present invention significantly improves the complexity of PUF design through multiple iterative processes. By continuously XORing and iterating R to increase the CRP coupling complexity, the time dimension coupling scheme between the two sequences is further expanded on the spatial coupling dimension of the conventional PUF design idea, greatly improving its ability to resist modeling attacks.

[0023] 3. The PUF design of the present invention has a reconfigurable function, because the fingerprint matrix W written into the basic unit of the non-volatile transistor array can be changed arbitrarily. Whenever a user needs to be replaced or information is erased, the transistor array can be repeatedly erased and written to change the internal fingerprint of the PUF for the reconstruction of the CRP relationship. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the principle of physical unclonable function PUF;

[0025] Figure 2 The data flow chart and mathematical principle diagram of the XOR iterative PUF described in the present invention;

[0026] Figure 3 A schematic diagram of an XOR iterative PUF circuit structure design and a data flow according to an embodiment of the present invention;

[0027] Figure 4 An embodiment of the non-volatile transistor of the present invention, that is, a device structure of the non-volatile transistor; the characteristic curves on the left and right of the device transfer characteristic curve (drain-source current-gate-source voltage) represent a low threshold voltage (storing "1") and a high threshold voltage (storing "0"), respectively;

[0028] Figure 5 This is the PUF randomness simulation result obtained by the XOR iterative operation method proposed in the present invention. DETAILED DESCRIPTION

[0029] The present invention is further clearly and completely described below by specific embodiments in conjunction with the accompanying drawings. Although specific embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0030] Figure 1 This is a working diagram of a physical unclonable function. As a physical entity, it processes the input challenge signal and converts it into a response signal for output. According to the challenge-response pair CRP of the PUF, it can be used as its unique identity identification code for subsequent hardware security requirements. The complexity of PUF design ensures that it is difficult to predict and model the CRP relationship, and the CRP relationships between the same PUF are different and unique. Before most of the PUF work reported so far, it will first be registered in a secure environment. At this time, the cloud sends a large number of different Cs and collects the R returned by the PUF to establish the CRP library of the PUF. When working, the cloud will randomly select a small number of Cs from the existing CRP library and send it to the PUF to compare whether the response R returned by the PUF matches the existing R in the library.

[0031] The PUF designed by the present invention does not require multiple Cs and multiple Rs for verification, but only requires one C=R [0] , R [1] As the initial seed of the iteration, the sequence R of R can be continuously generated through XOR iteration [0] , R [1] , R [2] , …, R [n] , R [n+1]The specific operation method of the PUF is as follows Figure 2 As shown in one embodiment, namely:

[0032]

[0033] In the formula, the square brackets in the subscript of R represent the number of iteration cycles, and the numbers without square brackets represent the sequence index of the vector. R itself is a binary vector of "0" / "1"; and the W matrix is ​​the binary matrix stored in the non-volatile transistor array of PUF. The function operation f(·) is as follows Figure 2 As shown in the m×m matrix in the solid line frame of the embodiment, the function operation is mathematically equivalent to the input column vector R [n] =[R1,R2,…R m ] T Perform bit-by-bit XOR and column-by-column sum operations with each column vector of the fingerprint matrix W (i.e., the Hamming distance between two column vectors), and the result of the jth column is Where i is the index of the row. Then the HD of each column is obtained. j (From HD1 to HD m ) will be compared with m / 2 (m is a dimensionless odd number to ensure that the comparison result will not be "equal") and the output will be a bit "1" or "0" according to the size. The result of the function operation is recorded as f(R [n] ,W). Then, f(R [n] ,W) will be combined with the previous iteration result R [n-1] Perform bit-by-bit XOR operation to obtain new iterative input Complete one XOR iteration process.

[0034] exist Figure 3 An embodiment of a PUF circuit design based on the above XOR iterative operation is shown in FIG. The circuit includes a non-volatile transistor array, as well as a peripheral register circuit (DFF), an XOR circuit (XOR), and a readout comparison circuit (SA). The non-volatile transistor array is a basic unit composed of two non-volatile transistors with complementary storage states, which are connected by circuits to form a multi-row and multi-column array structure. In the array structure, two word lines WL and The first embodiment is connected to the register circuit (DFF); the bit line BL of each column of basic cells is connected to the driving circuit, and the sense line SL is connected to the readout comparison circuit (SA); the drains of the two non-volatile transistors in the basic cell are connected to the bit line BL, the sources are connected to the sense line SL, the gate of the upper transistor is connected to the word line WL, and the gate of the lower transistor is connected to the complementary word line WL. In the basic unit, the storage states of the two nonvolatile transistors are complementary, and the level states of the two word lines connected to their gates are also complementary.

[0035] The fingerprint matrix W is stored in a non-volatile transistor array, and the R of different iteration cycles is completed through the register circuit DFF and the XOR circuit XOR of the peripheral circuit. [n] The storage and output are completed by the readout comparison circuit SA and I ref =m / 2·I on Specifically, it is based on an AND-type transistor array, whose basic unit is two non-volatile transistors ( Figure 3 The two word lines WL and WL connected to the gate terminals of the two complementary non-volatile transistors The levels of the leftmost register circuit 2 are always complementary during operation, and the source terminals of the transistors in the same column are connected to the sense line SL. [n] As the level of WL is complementary to the input into the array, the i-th bit signal R [n],i The binary "1" / "0" value of the i-th row word line WL i For example, R [1],1 =1, R [1],2 =0, then the levels of the first to fourth word lines WL should be WL1 = High, And WL2=Low,

[0036] like Figure 4 The figure shows the structure and electrical characteristics of a non-volatile transistor. The extra functional layer in the gate stack can non-volatilely regulate the potential of the channel, thereby changing the threshold voltage of the device, and realizing the ability to non-volatilely store "1" or "0" data, where the low threshold state is "1" and the high threshold state is "0". Since the non-volatile transistor only inputs a voltage level V at the high gate terminal, G = High, storage data is "1" (w ij =1) can output the on-state current I only when both are met on , in other cases it is off state I off , so essentially it is V G and w ij In the analog domain, the AND operation is performed. Since the word line gate levels and weights in the same basic unit are complementary, the sum of the currents of the two transistors in the i-th row is So the sum of the SL currents of the m 2T cells in the jth column That is, the jth column SL current and the input vector R [n]and the j-th column weight vector w j The Hamming distance is proportional to each column SL. ref =m / 2·I on By comparing the currents simultaneously, m comparison results corresponding to m columns of SL can be obtained. Since the number of "1" and "0" in the matrix and vector is basically equal and evenly distributed, the current of each column of SL is consistent with the threshold current I ref The result of the comparison is either "1" or "0" with equal probability.

[0037] Then, the binary comparison result vector f(R [n] ,W) will be XORed with the previous iteration result R [n-1] Perform bitwise XOR operation to obtain a new iterative input vector R [n+1] . Figure 3 The two register circuits in the figure will update data respectively, and the register DFF circuit 2 on the left will update data from R [n] Update to R [n+1] , and the DFF circuit 1 below the register will be from R [n-1] Update to R [n] , used for the next XOR iteration process. When performing PUF authentication, the input challenge signal C is the initial iteration seed R [0] and R [1] , by comparing the output sequence R of a specific number of iterations [n] (e.g. n = 1000, 2000, etc.) and the consistency of cloud storage can authenticate the identity. This solution avoids the security issues caused by the need to expose many CRPs for authentication, and also reduces the amount of CRP data that needs to be stored in the cloud and the authentication delay. Because the cloud only needs to store the initial iteration seed R [0] and R [1] And the fingerprint matrix W can be solved by software mathematical iteration to obtain any R [n] .

[0038] Figure 5 The advantages of the XOR iterative scheme of the embodiment of the present invention are demonstrated through Monte Carlo simulation (the weight matrix W is omitted in the four formulas in the figure for convenience). Compared with other iterative operations (including R [n+1] =f(R [n] ,W), and Three different iteration methods), the R generated by iteration [n] The minimum entropy (i.e. H min =-log2 max{p0,p1}) gradually converges to S=1.0 as the array size increases, and the XOR iteration scheme proposed in the present invention The convergence speed and effect are the best. And Figure 5 The pattern diagram of the spatial arrangement of the output bits on the right directly reflects that only the solution of the present invention has a truly random and irregular distribution, while the other three solutions all have certain graphic regularities.

[0039] This embodiment fully and in detail explains the principle and method of a high-security PUF based on XOR iterative operations and a non-volatile transistor array, avoiding the potential information exposure problem that requires multiple CRPs for verification. Compared with other PUF schemes, it has significantly improved anti-machine learning modeling security, improves the CRP identity authentication speed of PUF, and realizes the reconfiguration capability of PUF at a lower hardware cost.

[0040] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A physical unclonable function PUF circuit based on XOR iteration, used for generating PUF challenge-response pairs CRP, characterized in that: The circuit comprises: a non-volatile transistor array, and a peripheral register circuit DFF, an exclusive OR circuit XOR, and a readout comparison circuit. The non-volatile transistor array is an m-row and m-column array structure formed by connecting two basic units composed of non-volatile transistors through a circuit. In the array structure, two word lines WL and The bit line BL of each column of basic units is connected to the drive circuit, and the sense line SL is connected to the readout comparison circuit; the gates of the two non-volatile transistors in the basic unit are opposite to each other and are axially symmetrical, wherein the gate of one transistor is connected to the word line WL, and the gate of the other transistor is connected to the complementary word line WL. The drains of the two nonvolatile transistors are connected to the bit line BL, and the sources are connected to the sense line SL. In the basic unit, the storage states of the two nonvolatile transistors are complementary, and the level states of the two word lines WL connected to their gates are also complementary. The register circuit includes a register circuit 1 and a register circuit 2, which are used for storing and updating a response R vector of a physical unclonable function PUF during an XOR iterative calculation process. The register circuit 2 stores the response R of the current iterative calculation, and inputs the binary "1" and "0" in R as high and low levels, respectively, to the word lines of the row basic units of the non-volatile transistor array by row. At the same time, the register circuit 2 outputs the response R of the previous iterative calculation to the register circuit 1; The readout comparison circuit is used to read and compare the current of the non-volatile transistor array SL, through the sense amplifier SA connected to each column SL and the threshold current I ref Perform size comparison and output "1" or "0" bit signal to the XOR circuit; The XOR circuit is used to perform a bitwise XOR operation on the R vector output by the register circuit 1 and the current comparison result vector output by the readout comparison circuit, and the result is output to the register circuit 2.

2. The XOR-iterative based physical unclonable function PUF circuit according to claim 1, characterized in that: The non-volatile transistor is a floating-gate or charge-trapping field effect transistor, that is, a storage layer is inserted into the gate stack layer, and the storage layer uses a semiconductor material composed of a floating gate / trapping layer and a tunneling dielectric layer, and the threshold voltage of the transistor is modulated by capturing / de-trapping the charge of the channel; or it is a ferroelectric field effect transistor, that is, a layer of ferroelectric material is inserted into the gate stack layer, and the threshold voltage of the non-volatile modulated transistor is modulated by changing the polarization state of the ferroelectric material.

3. An operation method of a physical unclonable function PUF circuit based on XOR iteration, used for generating PUF challenge-response pairs CRP, characterized in that the steps include: 1) Write the fingerprint matrix W into the basic unit of the m-row and m-column non-volatile transistor array, where W is a binary matrix of "0" and "1", and the two storage state complementary transistors of each basic unit store an element of W; 2) Input the response R vector corresponding to the initial challenge signal C, denoted as R [0] and R [1] , respectively R [0] Stored in register circuit 1 and R [1] Stored in register circuit 2 as the initial seed for iteration; 3) The R vector stored in register circuit 2 is used as the WL input of the non-volatile transistor array. In each basic unit, the in-memory calculation will be performed and output as the current of SL to the readout comparison circuit to obtain the current of each column of the non-volatile transistor array and the threshold current I of the sense amplifier. ref The comparison result f(R [n] ,W), n represents the number of iteration cycles, and its value is the current number of iterations; 4) Compare the results f(R [n] ,W) and register circuit 1 stores R [n-1] They are used as the two inputs of the XOR circuit respectively, and the bitwise XOR operation is performed to obtain the new input R for the next iteration. [n+1] ; 5) The new input R of the next iteration [n+1] Stored in register circuit 2, and the R previously stored in register circuit 2 [n] Stored in register circuit 1 for the next XOR iteration; 6) Continuously repeat the operations in step 3) to step 5) for a specific number of iterations until a predetermined number of iterations is reached, and output the result stored in the register circuit 2 at this time.

4. The method for operating a physical unclonable function PUF circuit based on XOR iteration according to claim 3, characterized in that: In the operation method, the threshold current I ref The value of I ref =m / 2·I on , where I on is the on-state current output by the non-volatile transistor, m is the number of rows of the non-volatile transistor array, and m is an odd number.

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