Layout design method for processing newly added metal level and replaced metal level

Abstract

The invention aims to provide a layout design method for processing a newly added metal level and a replaced metal level. The method comprises the following steps: acquiring a process switching demand; setting layout parameters according to the process switching requirements; and running a verification process to verify the feasibility of the layout. According to the method, various possible conditions can be considered together, process replacement is carried out at a time, and the IPtop module is rapidly and accurately completed. Power and Ground are distinguished from a signal net while efficient replacement is carried out, the power and Ground focus on not increasing EMIR, and clk and data focus on not increasing RC parasitic processing.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a layout design method for processing newly added metal layers and replaced metal layers. Background Art

[0002] In the design of integrated circuits, layout design is a very important design link. This is because if integrated circuits want to play a full role in a certain product system, they not only need professional circuit design but also good layout design to meet the needs of their installation process. At present, electronic products pay more and more attention to the layout design of integrated circuits. How to improve the level of integrated circuit layout design has become the most concerned issue for relevant technical personnel. In the process of integrated circuit design, layout design is the last design link and plays a finishing role. It is carried out on the basis of the previous system design, logic design and circuit design. The layout design of integrated circuits includes many aspects and is a necessary means to convert the circuit topology into an electrical chip. Because the previous integrated circuit designs were all completed on drawings, if these designs are to be applied to actual integrated circuit chips, it is necessary to carry out circuit layout and layout design.

[0003] In chip design, process switching often occurs due to various reasons, mainly in the following situations: switching of different metal cross-sections at the same process node in the same semiconductor manufacturer and transplantation between similar process nodes in different semiconductor manufacturers. The invention is a method applicable to the implementation of switching based on the first situation. The switching of different metal cross-sections at the same process node in the same semiconductor manufacturer includes the following situations: reduction of metal layers when the metal thickness remains unchanged; increase of metal layers when the metal thickness remains unchanged; change of metal thickness when the number of metal layers remains unchanged; and a combination of the above three situations. For the above situations, if the switching is purely done manually, it is easy to miss the processing, and then it is discovered in the verification stage, resulting in repeated iterative modifications, which greatly increases the labor cost. In order to conduct MPW or shuttle with other companies during the chip tape-out process, the completed projects are often switched in process, which makes it difficult to quickly switch the process and ensure the accuracy after the process switch, and to balance the post-simulation verification without being affected. Summary of the invention

[0004] The purpose of the present invention is to provide a layout design method for processing new metal layers and replacement metal layers, which takes various possible situations into consideration, replaces the process at one time, and completes the IPtop module quickly and accurately. While efficiently replacing, power, ground and signal net are distinguished, power and ground focus on not increasing EMIR, while clk and data focus on not increasing RC parasitics.

[0005] A layout design method for processing new metal layers and replacement metal layers, comprising: Obtain process switching requirements; Setting layout parameters according to the process switching requirements; The setting of layout parameters according to the process switching requirements includes: For the newly added PDK metal layer, determine the power, ground, and signal networks of the chip layout; Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias; The determination of the DRC condition of the newly added metal layer and the DRC condition of the newly added via hole includes: If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK; Directly use the current layer as the benchmark and copy it in PG and signal mode respectively; Directly copy the metal layer of the current layer in the power and ground networks, and then fill the vias of the newly added metal layer and the adjacent metal layer; The signal network duplicates the newly added metal layer where the original upper and lower layers are connected and overlap, and then duplicates the original via metal layer as the upper and lower holes of the newly added via layer; If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK, and determine the minimum width, maximum width, space, and newly added vias between the newly added metal layer and the adjacent metal layer; Select the adjacent upper metal layer where the maximum width is greater than the maximum width of the newly added metal layer, and filter it to become the maximum width of the newly added metal layer; The minimum space meets the requirements of the new metal layer, and the vias are filled according to the rules; Run the verification process to verify the feasibility of the layout.

[0006] Preferably, the process switching requirements include: Added PDK metal layer; Replace PDK metal; It is necessary to add a new PDK metal layer and also replace the PDK metal.

[0007] Preferably, the network for judging the power, ground and signal of the chip layout includes: Mark various networks and perform additional processing on the layout when encountering the POWER after the LDO; There is no VDD on the power or ground network, and the VSS label is signal by default.

[0008] Preferably, setting layout parameters according to the process switching requirements includes: For replacing PDK metal, determine the difference between the metal layer to be replaced and the existing metal layer; Directly replace the metal layer; When processing vias, the original vias are deleted, and then new metal layers are punched at the same location. The punching is calculated based on the number of existing holes, and the holes required by the PDK are regenerated based on the parameter information of the original holes.

[0009] Preferably, setting layout parameters according to the process switching requirements includes: If both a new PDK metal layer and a PDK metal layer need to be replaced, the PDK metal layer should be replaced first, and then the PDK metal layer should be added.

[0010] Preferably, the running verification process to verify the feasibility of the layout includes: Run DRC check to verify whether the layout design rules are correct; Run LVS verification to verify whether the layout is consistent with the circuit.

[0011] A layout system for rapidly processing new and replaced metal layers, including: Data acquisition module, used to obtain process switching requirements; A data processing module, used for setting layout parameters according to the process switching requirements; The verification module is used to run the verification process to verify the feasibility of the layout.

[0012] An electronic device includes: a chip, a processor and a memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a layout design method for processing new metal layers and replacement metal layers.

[0013] The beneficial effects of the present invention are as follows: the present invention uses a series of processes including SKILL, svrf, gdsmerge, and PV verification to quickly traverse the layout in the specified library, and finally performs PV verification of the new process on the switched layout, which mainly includes DRC and LVS verification. In the high-speed IP module, it is also necessary to distinguish between the signals clk, datanet, and Power / Ground. How these signal nets are processed when the process is switched is crucial to the performance of the IP. In order to ensure that clk and datanet are not affected by the switching process, the present invention divides non-power / ground metal routing into one category, and power and ground into another category. In this way, different logics are used for processing when superimposing, replacing, and reducing metal layers, so that the process switching is completed quickly and the performance of the high-speed IP is not affected. The time for manual modification in the later stage can be reduced to a minimum. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] Figure 1 A flow chart of a layout design method for processing newly added metal layers and replaced metal layers according to the present invention; Figure 2 A schematic diagram of the structure of a layout system for rapidly processing newly added metal layers and replaced metal layers according to the present invention; Figure 3 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0019] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0020] In chip design, process switching often occurs due to various reasons, mainly in the following situations: switching of different metal cross-sections at the same process node in the same semiconductor manufacturer and transplantation between similar process nodes in different semiconductor manufacturers. The invention is a method applicable to the implementation of switching based on the first situation. The switching of different metal cross-sections at the same process node in the same semiconductor manufacturer includes the following situations: reduction of metal layers when the metal thickness remains unchanged; increase of metal layers when the metal thickness remains unchanged; change of metal thickness when the number of metal layers remains unchanged; and a combination of the above three situations. For the above situations, if the switching is purely done manually, it is easy to miss the processing, and then it is discovered in the verification stage, resulting in repeated iterative modifications, which greatly increases the labor cost. In order to conduct MPW or shuttle with other companies during the chip tape-out process, the completed projects are often switched in process, which makes it difficult to quickly switch the process and ensure the accuracy after the process switch, and to balance the post-simulation verification without being affected.

[0021] The present invention uses a series of processes such as SKILL, svrf, gdsmerge, and PV verification to quickly traverse the layout in the specified library, and finally performs PV verification of the new process on the switched layout, which mainly includes DRC and LVS verification. In the high-speed IP module, it is also necessary to distinguish between the signals clk, datanet, and Power / Ground. How these signal nets are processed when the process is switched is crucial to the performance of the IP. In order to ensure that clk and datanet are not affected by the switching process, the present invention divides non-power / ground metal routing into one category, and power and ground into another category. In this way, different logics are used for processing when superimposing, replacing, and reducing metal layers, so that the process switching is completed quickly and the performance of the high-speed IP is not affected. The man-hours for later manual modification can be reduced to a minimum.

[0022] Example 1 A layout design method for processing new metal layers and replacement metal layers, reference Figure 1 ,include: S100, obtaining process switching requirements; Chip process switching refers to the selection and replacement of different manufacturing processes in different chip manufacturing processes according to market demand and technological development. This switching usually involves moving from one process to another to adapt to different production needs and product characteristics. The main reasons for chip process switching include changes in market demand and the need for technological development. As the market demand for chips with different processes increases, manufacturers need to adjust their production strategies according to market demand. For example, 28nm chips have gradually become the mainstream of the market due to their wide range of applications and price advantages, so manufacturers will step up the production capacity layout of 28nm chips and temporarily cancel 14nm chip technology.

[0023] S200, setting layout parameters according to process switching requirements; Setting layout parameters according to the process switching requirements includes: For the newly added PDK metal layer, determine the power, ground, and signal networks of the chip layout; Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias; Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias including: If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK; Directly use the current layer as the benchmark and copy it in PG and signal mode respectively; Directly copy the metal layer of the current layer in the power and ground networks, and then fill the vias of the newly added metal layer and the adjacent metal layer; The signal network duplicates the newly added metal layer where the original upper and lower layers are connected and overlap, and then duplicates the original via metal layer as the upper and lower holes of the newly added via layer; If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK, and determine the minimum width, maximum width, space, and newly added vias between the newly added metal layer and the adjacent metal layer; Select the adjacent upper metal layer where the maximum width is greater than the maximum width of the newly added metal layer, and filter it to become the maximum width of the newly added metal layer; The minimum space meets the requirements of the new metal layer, and the vias are filled according to the rules; Layout is a key step in converting circuit design into actual chip. Through lithography and etching technology, the geometric figures on the layout are transferred to the silicon wafer to form the actual circuit structure. During the layout design process, strict design rule checking (DRC) and circuit extraction and verification (LVS) will be carried out to ensure the correctness of the design and the feasibility of manufacturing, thereby improving the manufacturing accuracy and performance of the chip. The design process of circuit layout includes: Establishing the design environment: First, it is necessary to establish a database channel to determine the correspondence between the layout and the process. The layout diagram should be as consistent as possible with the circuit. Figure 1 To ensure the testability of the chip, EDA tools are used for layout design, including layout editing, geometry parameter adjustment, connection design, design rule checking, circuit extraction, and LVS verification.

[0024] S300, running a verification process to verify the feasibility of the layout.

[0025] ‌The main contents of verifying the layout include the following aspects‌: DRC (Design Rule Check): Geometric design rule check, used to ensure that the layout complies with specific process design rules, avoid potential open circuits, short circuits or adverse effects, and thus improve the yield of chip manufacturing‌. ‌ERC (Electrical Rule Check): Electrical rule check, check the electrical characteristics such as short circuits between power and ground, floating devices and connections, and ensure the normal operation of the circuit‌. ‌LVS (Layout vs. Schematic): Netlist consistency check, compare the netlist proposed by the layout and the netlist of the schematic diagram to ensure that the circuit connection relationship is correct, the MOS transistor size matches, and the resistance and capacitance values ​​are correct, etc. ‌LPE (Layout Parameter Extraction): Layout parasitic parameter extraction, extract parameters such as transistor size, parasitic capacitance and resistance from the layout, and generate a netlist in SPICE format for post-simulation verification‌. POSTSIM (Post-Simulation): Post-simulation checks the impact of parasitic parameters on the design, performs switch-level logic simulation or circuit simulation through actual layout parameters, and verifies the correctness of circuit functions and timing performance.

[0026] Preferably, S100, the process switching requirement includes: Added PDK metal layer; Replace PDK metal; It is necessary to add a new PDK metal layer and also replace the PDK metal.

[0027] ‌Metal layers in PDK‌ refer to multi-layer metal interconnect structures used to connect transistors and other electronic components during the design and manufacture of integrated circuits. These metal layers are usually made of copper or aluminum, isolated in insulating layers, and connected together through vertical connections (vias). Each layer of metal has specific design rules, including width, spacing, and connection methods to other layers. In integrated circuit design and manufacturing, the main role of metal layers is to provide complex interconnect schemes to meet different applications and performance requirements. Multi-layer metal stacks usually include bottom layers (such as M1, M2, etc.) for local interconnects, and upper layers (such as Mx, where x is a larger number) for longer-distance global interconnects or power / ground lines. The number and type of metal layers can be adjusted according to different processes or process variants to suit different applications and performance requirements. The number of metal layers can vary greatly in different processes. For example, a process may provide 6 layers of metal interconnects (called 6M option) or more, such as 10 layers of metal (called 10M option). Each option has its specific performance and cost trade-offs. More metal layers generally mean higher manufacturing costs, but can also provide higher performance and more design flexibility, especially in complex IC designs such as high-performance or multi-core processors.

[0028] Preferably, S200, setting layout parameters according to process switching requirements includes: For the newly added PDK metal layer, determine the power, ground, and signal networks of the chip layout; ‌PowerNet‌ refers to the power network in the circuit, which is mainly used to provide the DC power required by the circuit. In the layout, the power network is usually represented by specific layers (such as VCC or VDD layers), which are used to connect various components and modules in the circuit to ensure that they can obtain a stable power supply. The power network design must ensure that the layout of the power network is reasonable, avoid long-distance power supply, and reduce voltage drop and electromagnetic interference.

[0029] ‌GroundNet‌ refers to the ground network in the circuit, which is mainly used for signal return and electromagnetic shielding. The ground network is usually represented by the GND layer to ensure that the current in the circuit can flow back to the negative pole of the power supply smoothly, while reducing electromagnetic interference and noise. The design of the ground network is crucial to the stability and performance of the circuit. The ground network design should adopt a single-point grounding or multi-point grounding strategy to ensure the lowest impedance of the signal return path and reduce ground bounce and noise.

[0030] ‌SignalNet‌ refers to the signal network in the circuit, which is used to transmit various electrical signals. The signal network is represented by different layers, such as data lines, control lines, etc., to ensure that the signal can be transmitted correctly and stably in the circuit. The design of the signal network needs to take into account the integrity and anti-interference ability of the signal. The signal network design‌ should optimize the layout and routing of the signal line, avoid interference from long parallel lines and high-frequency signals, and ensure the integrity and transmission rate of the signal.

[0031] Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias.

[0032] Before adding a new metal layer, a design rule check (DRC) must be performed to ensure that the design rules allow the addition of the new layer and understand the usage restrictions of the new layer, such as minimum line width, spacing, Via size, etc.

[0033] When selecting a via type, you can set rules such as semi-conducting vias (blind and buried vias). Specific operations include selecting a via type, setting semi-conducting via rules, etc.

[0034] Preferably, the network for determining the power, ground, and signal of the chip layout includes: Mark various networks and perform additional processing on the layout when encountering the POWER after the LDO; ‌POWER after LDO usually refers to the output voltage or current after being adjusted by the LDO regulator. ‌LDO (Low Dropout Regulator) is a low dropout linear regulator whose main function is to subtract the excess voltage from the input voltage to generate a regulated output voltage. In the circuit, LDO is usually located between the power supply and the load to provide a stable DC power supply. The output voltage or current after LDO adjustment is called POWER, that is, power output. LDO maintains the stability of the output voltage through an internal adjustment element (usually a transistor or field effect tube). When the input voltage changes, the adjustment element will automatically adjust to keep the output voltage near the set reference voltage.

[0035] In the embodiment of the present invention, labeling can facilitate users to quickly and accurately understand the layout information and classify the layout information.

[0036] There is no VDD on the power or ground network, and the VSS label is signal by default.

[0037] VDD‌: stands for "Positive Supply Voltage". In CMOS logic circuits, VDD is often used to indicate the power supply voltage, usually the positive power supply. In field effect transistors (or CMOS devices), VDD refers to the drain voltage. ‌VSS‌: stands for "Ground" or "Negative Supply Voltage". In CMOS logic circuits, VSS usually refers to ground or negative power supply. In field effect transistors (or CMOS devices), VSS refers to the source voltage.

[0038] Preferably, judging the DRC condition of the newly added metal layer and the DRC condition of the newly added via includes: If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK; Vias are an important part of printed circuit board (PCB) design, used to connect wires between different layers. Vias are pre-drilled holes on the PCB and the pins of packaged components or connectors are soldered through the holes to achieve electrical connections between different layers. Vias include through-hole vias, blind vias, and buried vias. Each type of via has different advantages and applicability in different application scenarios.

[0039] Directly use the current layer as the benchmark and copy it in PG and signal mode respectively; Directly copy the metal layer of the current layer in the power and ground networks, and then fill the vias of the newly added metal layer and the adjacent metal layer; The signal network duplicates the newly added metal layer where the original upper and lower layers are connected and overlap, and then duplicates the original via metal layer as the upper and lower holes of the newly added via layer; If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK, and determine the minimum width, maximum width, space, and newly added vias between the newly added metal layer and the adjacent metal layer; Select the adjacent upper metal layer where the maximum width is greater than the maximum width of the newly added metal layer, and filter it to become the maximum width of the newly added metal layer; The minimum space meets the requirements of the newly added metal layer, and the vias are filled according to the rules.

[0040] Determine the DRC of the newly added layer and the DRC of the newly added VIA: If the thickness and DRC of the newly added layer are the same as those of the adjacent layer in the original PDK, replace the original via with the viadefine of the new PDK, and then directly use this layer as the benchmark and copy it in the PG and signal modes. Directly copy this metal layer in the power and groundnet areas, and then fill the newly added layer and the adjacent layer with via, which can reduce the risk of EMIR; the signal net will copy the newly added layer where the original upper and lower layers are connected and overlap, and then copy the original vialayer as the upper and lower holes of the newly added via layer, which will not increase the parasitic RC of the signal; if the thickness and DRC of the newly added layer are different from those of the adjacent layer in the original PDK, the addition method is the same as above, but at the same time, it is necessary to look at the minwidth, maxwidth, space, and newly added via of the newly added layer and the adjacent layer; usually select the adjacent upper metal, and the place where the maxwidth is greater than the maxwidth of the newly added layer is screened and becomes the maxwidth of the newly added layer. Minspace usually meets the requirements of the newly added layer. Finally, Via is filled according to the rule.

[0041] Preferably, S200, setting layout parameters according to process switching requirements includes: For replacing PDK metal, determine the difference between the metal layer to be replaced and the existing metal layer; Directly replace the metal layer; When processing vias, the original vias are deleted, and then new metal layers are punched at the same location. The punching is calculated based on the number of existing holes, and the holes required by the PDK are regenerated based on the parameter information of the original holes.

[0042] Determine the difference between the layer to be replaced and the existing layer. This is usually an operation between different metal thicknesses. The layer can be directly replaced, but the space and viawidth of the via will be different. When processing the via, you need to delete the original via first, and then punch a new layer at the same position. This hole can be converted according to the number of existing holes, and the hole required by the PDK can be regenerated according to the parameter information of the original hole.

[0043] Preferably, S200, setting layout parameters according to process switching requirements includes: If both a new PDK metal layer and a PDK metal layer need to be replaced, the PDK metal layer should be replaced first, and then the PDK metal layer should be added.

[0044] First replace the PDK metal, and then add a new PDK metal layer, so that the net connection will exist. Otherwise, it is easy to cause LVS problems after PDK switching.

[0045] Preferably, S300, running a verification process to verify the feasibility of the layout includes: Run DRC check to verify whether the layout design rules are correct; Run DRC, which has recognition capabilities and can perform complex recognition work before generating the final graphics for delivery. The program will check the file according to the rules and mark the error location and explain it when errors are found. Check for short circuits, open circuits and floating nodes. When ERC detects a short circuit error, it will limit the error prompt to the shortest connection path.

[0046] Run LVS verification to verify whether the layout is consistent with the circuit.

[0047] LVE compares the layout and schematic, reports inconsistencies between the layout connections and the schematic, and makes modifications until the layout and schematic are completely consistent.

[0048] If the layout fails the inspection, the layout needs to be modified to determine whether the label is correct, whether the selected layer is correct, whether there are any problems with the connection between power and ground, whether the obtained files are reliable, whether the naming of the device type in the netlist complies with the specifications, check the design rule, and according to the inspection report, see if there are too many foogirct nodes. If there are too many, there are open circuits. If there are too few, there are short circuits. Check the schematic diagram to see if there are any incorrect connections.

[0049] The result of the method of the present invention for processing the newly added metal layer is shown as follows: the newly added vialayer111, metal layer145, signal and Power / Ground are also processed separately from the newgds. The results of DRC and LVS verification using newgds are as follows: LVS and DRC can pass at one time, reducing the workload.

[0050] The result of the metal layer replacement processed by the method of the present invention is shown as follows: the target process is converted from the TMa process to the TMb process, and the process metal layer thickness changes from 10K to 14K, which means that the width and space of VIA will change. This step is performed using skill, and the library to be replaced is input into the specified variable, the proportion of VIA is calculated, and the holes are punched again according to the new PDK to complete the replacement of VIA. The size and space of via are different before and after replacement. Under the condition of equal overlap, VIA is replaced according to the new size, and it can be guaranteed that LVS can pass at one time, and there will be no short and OPEN situations.

[0051] Example 2 A layout system that quickly handles new and replaced metal layers, reference Figure 2 ,include: Data acquisition module, used to obtain process switching requirements; Data processing module, used to set layout parameters according to process switching requirements; The verification module is used to run the verification process to verify the feasibility of the layout.

[0052] Example 3 An electronic device includes: a chip, a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a layout design method for processing new metal layers and replacement metal layers.

[0053] refer to Figure 3, the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0054] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0055] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or portable read-only memory (ROM), which is used for related instructions and data.

[0056] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0057] The present invention uses a series of processes such as SKILL, svrf, gdsmerge, and PV verification to quickly traverse the layout in the specified library, and finally performs PV verification of the new process on the switched layout, which mainly includes DRC and LVS verification. In the high-speed IP module, it is also necessary to distinguish between the signals clk, datanet, and Power / Ground. How these signal nets are processed when the process is switched is crucial to the performance of the IP. In order to ensure that clk and datanet are not affected by the switching process, the present invention divides non-power / ground metal routing into one category, and power and ground into another category. In this way, different logics are used for processing when superimposing, replacing, and reducing metal layers, so that the process switching is completed quickly and the performance of the high-speed IP is not affected. The man-hours for later manual modification can be reduced to a minimum.

[0058] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A layout design method for processing new metal layers and replacement metal layers, characterized in that: include: Obtain process switching requirements; Setting layout parameters according to the process switching requirements; The setting of layout parameters according to the process switching requirements includes: For the newly added PDK metal layer, determine the power, ground, and signal networks of the chip layout; Determine the DRC status of the newly added metal layer and the DRC status of the newly added vias; The determination of the DRC condition of the newly added metal layer and the DRC condition of the newly added via hole includes: If the thickness and DRC of the newly added metal layer are the same as those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK; Directly use the current layer as the benchmark and copy it in PG and signal mode respectively; Directly copy the metal layer of the current layer in the power and ground networks, and then fill the vias of the newly added metal layer and the adjacent metal layer; The signal network duplicates the newly added metal layer where the original upper and lower layers are connected and overlap, and then duplicates the original via metal layer as the upper and lower holes of the newly added via layer; If the thickness and DRC of the newly added metal layer are different from those of the adjacent metal layer in the original PDK, replace the original vias with the via defines of the new PDK, and determine the minimum width, maximum width, space, and newly added vias between the newly added metal layer and the adjacent metal layer; Select the adjacent upper metal layer where the maximum width is greater than the maximum width of the newly added metal layer, and filter it to become the maximum width of the newly added metal layer; The minimum space meets the requirements of the new metal layer, and the vias are filled according to the rules; Run the verification process to verify the feasibility of the layout.

2. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The process switching requirements include: Added PDK metal layer; Replace PDK metal; It is necessary to add a new PDK metal layer and also replace the PDK metal.

3. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The power, ground, and signal networks for determining the chip layout include: Mark various networks and perform additional processing on the layout when encountering the POWER after the LDO; There is no VDD on the power or ground network, and the VSS label is signal by default.

4. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The setting of layout parameters according to the process switching requirements includes: For replacing PDK metal, determine the difference between the metal layer to be replaced and the existing metal layer; Directly replace the metal layer; When processing vias, the original vias are deleted, and then new metal layers are punched at the same location. The punching is calculated based on the number of existing holes, and the holes required by the PDK are regenerated based on the parameter information of the original holes.

5. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The setting of layout parameters according to the process switching requirements includes: If both a new PDK metal layer and a PDK metal layer need to be replaced, the PDK metal layer should be replaced first, and then the PDK metal layer should be added.

6. A layout design method for processing new metal layers and replacement metal layers according to claim 1, characterized in that: The operation verification process for verifying the feasibility of the layout includes: Run DRC check to verify whether the layout design rules are correct; Run LVS verification to verify whether the layout is consistent with the circuit.

7. A layout design system for processing new metal layers and replacement metal layers, used to implement the layout design method for processing new metal layers and replacement metal layers as described in any one of claims 1 to 6, characterized in that: include: Data acquisition module, used to obtain process switching requirements; A data processing module, used for setting layout parameters according to the process switching requirements; The verification module is used to run the verification process to verify the feasibility of the layout.

8. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions. When the chip executes the computer instructions, the electronic device executes a layout design method for processing new metal layers and replacement metal layers as described in any one of claims 1 to 6.

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