Method and System for Generating Circuit Board Design Drawings

Abstract

The present invention relates to the technical field of circuit board design, and in particular to a method and system for generating a circuit board design diagram. The method includes the following steps: obtaining an original circuit board design diagram file; vectorizing the layer data of the original circuit board design diagram to obtain vectorized layer data; constructing a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; performing overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; performing current density simulation according to the overlapping area modeling data to obtain current density simulation data; performing virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain virtual node coordinate data. The present invention solves the wiring problems of complex topological structures and overlapping areas, improves the wiring efficiency and quality, and optimizes the performance and reliability of the circuit board.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board (PCB) design, and particularly to a method and system for generating a PCB design diagram. Background Art

[0002] In the early days, PCB design relied entirely on manual work using tape and drawing tools. This method was inefficient, inaccurate, and difficult to handle complex circuits. Later, electronic design automation (EDA) software such as Altium Designer and PADS emerged. These software provide a graphical interface and some automated tools to assist engineers in PCB design, greatly improving the design efficiency. The EDA software integrates an automatic routing function that can automatically generate routing paths according to preset rules. However, the early automatic routing algorithms had limited efficiency and routing quality, especially when dealing with complex topologies and high-density routing, the effect was not good. Traditional methods are difficult to handle complex topologies and overlapping areas.

[0003] The deficiencies of traditional methods in dealing with complex topologies and overlapping areas are mainly reflected in:

[0004] Routing congestion: In areas with dense components, the routing space is limited, and traditional automatic routing algorithms are prone to cause routing congestion and difficult to find suitable routing paths.

[0005] Difficulty in optimization: For complex topologies, traditional optimization algorithms are difficult to find the global optimal solution, resulting in an increase in routing length and a decrease in signal integrity.

[0006] Difficulty in handling overlapping areas: Traditional routing algorithms usually regard the routing of each network as an independent task and do not fully consider the mutual influence between networks. Especially in overlapping areas, routing conflicts and electromagnetic interference are likely to occur. Summary of the Invention

[0007] Based on this, it is necessary to provide a method and system for generating a PCB design diagram to solve at least one of the above technical problems.

[0008] To achieve the above object, a method for generating a PCB design diagram includes the following steps:

[0009] Step S1: Obtain the original printed circuit board design drawing file; vectorize the layer data of the original printed circuit board design drawing file to obtain vectorized layer data; construct a connection matrix of component elements based on the vectorized layer data to obtain a connection matrix; perform overlapping area modeling based on the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation based on the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data;

[0010] Step S2: Generate an initial path according to the virtual node coordinate data, the connection matrix, and the vectorized layer data, and perform path optimization to obtain path optimization data; generate 3D wiring data according to the path optimization data and the virtual node coordinate data to obtain 3D wiring data;

[0011] Step S3: Determine the candidate test area according to the 3D wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; perform optimization processing on the candidate test area data to obtain test point data;

[0012] Step S4: Integrate the layer data according to the 3D wiring data and the vectorized layer data to obtain layer data integration data; create a test point layer according to the test point data to obtain test point layer data; generate a hierarchical layer according to the layer data integration data and the test point layer data to obtain hierarchical layer data, so as to implement the printed circuit board design drawing generation operation.

[0013] The present invention vectorizes the original circuit board design drawing and constructs a connection matrix, accurately extracts circuit topology information, and through overlapping area modeling and current density simulation, provides an accurate data basis for the positioning of virtual nodes. Finally, coordinate data containing complete information of virtual nodes is generated, effectively solving the testing problem brought by overlapping pads. Using the virtual node coordinate data, connection matrix, and vectorized layer data, an initial routing path is first generated, and then through a path optimization algorithm, an optimized path that meets the design rules and obstacle avoidance requirements is obtained. Finally, combining the three-dimensional coordinate information of virtual nodes, three-dimensional routing data for manufacturing and testing is generated, improving the routing quality and efficiency. By analyzing the reachability of virtual nodes and optimizing the test point positions in combination with the routing information, data containing complete information of test points is finally generated, ensuring the reachability, effectiveness, and test coverage of test points, thereby improving the efficiency and accuracy of circuit board testing. By integrating the three-dimensional routing data and vectorized layer data, and creating a dedicated test point layer, complete layer data containing all necessary information is generated. Subsequent layer optimization and format conversion further improve the manufacturability and data compatibility of the circuit board, and finally output layered layer data that can be directly used for production and testing. Therefore, the present invention provides a method for generating a circuit board design drawing, effectively solving the routing problems of complex topological structures and overlapping areas, improving the routing efficiency and quality, and optimizing the performance and reliability of the circuit board. This is particularly important for modern circuit board designs with high density and high complexity.

[0014] Preferably, step S1 includes the following steps:

[0015] Step S11: Obtain the original circuit board design drawing file; vectorize the layer data of the original circuit board design drawing file to obtain vectorized layer data;

[0016] Step S12: Extract the element connection relationship according to the vectorized layer data to obtain element connection relationship data; classify the connection types of the element connection relationship data to obtain connection type classification data;

[0017] Step S13: Construct a connection matrix according to the connection type classification data to obtain a connection matrix;

[0018] Step S14: Extract overlapping connections from the connection matrix to obtain overlapping connection data;

[0019] Step S15: Model the overlapping area according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data;

[0020] Step S16: Simulate the current density according to the overlapping area modeling data to obtain current density simulation data;

[0021] Step S17: Perform virtual node positioning on the overlapping area modeling data based on the current density simulation data and the vectorized layer data to obtain virtual node positioning data;

[0022] Step S18: Generate virtual node coordinate data based on the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data.

[0023] The present invention lays a foundation for subsequent analysis and processing by obtaining the original printed circuit board design drawing file and vectorizing the layer data, converting complex graphic information into vector data that can be processed by a computer, and improving the design efficiency. By extracting the element connection relationships and classifying the connection types from the vectorized layer data, different types of connection relationships, such as direct connections, via connections, and overlapping connections, can be accurately identified and distinguished, providing accurate data support for subsequent connection matrix construction and overlapping area processing. By constructing a connection matrix based on the connection type classification data, the connection relationships between circuit components can be clearly represented, providing a data basis for subsequent virtual node insertion and path reconstruction, and helping to improve the wiring efficiency and quality. By extracting overlapping connections from the connection matrix, all overlapping connection relationships can be quickly identified, providing the necessary input data for subsequent overlapping area modeling and virtual node positioning, thus effectively solving the testing problems brought by overlapping pads. By performing overlapping area modeling based on the vectorized layer data and the overlapping connection data, the shape, area, and center point coordinates of the overlapping area can be accurately calculated, providing an accurate geometric model for subsequent current density simulation, thereby improving the simulation accuracy. By performing current density simulation based on the overlapping area modeling data, the distribution of current in the overlapping area can be accurately predicted, providing a scientific basis for the positioning of virtual nodes, thus selecting the best test points and improving the test coverage rate. By performing virtual node positioning based on the current density simulation data and the vectorized layer data, the virtual nodes can be placed at positions with higher current density and easy probe access, thereby improving the feasibility and accuracy of testing. By generating virtual node coordinate data based on the virtual node positioning data and the overlapping connection data, various information of the virtual nodes, such as ID, coordinates, and the pad information they belong to, can be integrated into a data structure, providing complete data input for subsequent path reconstruction and test point mapping, thereby improving the efficiency and consistency of the entire design process.

[0024] Preferably, step S15 includes the following steps:

[0025] Step S151: Extract the pad shape from the vectorized layer data according to the overlapping connection data to obtain pad shape data;

[0026] Step S152: Process the irregular pad shape data to obtain processed irregular pad shape data;

[0027] Step S153: Calculate the overlapping area of the irregular pad shape processing data to obtain the overlapping area calculation data;

[0028] Step S154: Verify the overlapping area of the overlapping area calculation data according to the pad shape extraction data to obtain the overlapping area verification data;

[0029] Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain the overlapping area modeling data.

[0030] The present invention extracts the pad shape of the vectorized layer data according to the overlapping connection data, obtains accurate pad shape data, provides the necessary geometric information for subsequent overlapping area calculation and modeling, and avoids the errors caused by using a simplified model. By processing the pad shape data for irregular pad shapes, pads of various shapes can be effectively processed, including circular, rectangular, and irregular shapes, improving the accuracy and versatility of overlapping area calculation and being applicable to a wider range of PCB design scenarios. By calculating the overlapping area of the irregular pad shape processing data, information such as the area, shape, and boundary coordinates of the overlapping area can be accurately calculated, providing a reliable data basis for subsequent overlapping area verification and modeling. By verifying the overlapping area of the overlapping area calculation data according to the pad shape extraction data, the effectiveness and accuracy of the calculated overlapping area can be ensured, avoiding incorrect results caused by calculation errors or algorithm defects, and improving the reliability of the design. By generating overlapping area modeling data according to the overlapping area verification data, the overlapping area model data finally used for subsequent steps can be generated. This data has been strictly verified, ensuring the accuracy and reliability of the data, and providing high-quality input data for subsequent current density simulation and virtual node positioning.

[0031] Preferably, step S16 includes the following steps:

[0032] Step S161: Use finite element analysis technology to perform overlapping area mesh division on the overlapping area modeling data to obtain the overlapping area mesh data;

[0033] Step S162: Set boundary adjustment according to the overlapping area mesh data to obtain the overlapping area boundary condition data;

[0034] Step S163: Solve the current density field according to the overlapping area mesh data and the overlapping area boundary condition data to obtain the overlapping area current density field data;

[0035] Step S164: Calculate the current density gradient according to the overlapping area current density field data to obtain the current density gradient data;

[0036] Step S165: Generate current density simulation results based on the current density gradient data to obtain current density simulation data.

[0037] In the present invention, by using the finite element analysis technology to perform overlapping region mesh division on the overlapping region modeling data, the overlapping region is discretized, providing a necessary calculation basis for the subsequent solution of the current density field. And by controlling the mesh density, the calculation accuracy and calculation efficiency can be balanced. By performing boundary adjustment settings according to the overlapping region mesh data, the boundary conditions of the current density simulation can be accurately defined, such as the magnitude and direction of the current excitation, ensuring the accuracy and reliability of the simulation results. By solving the current density field according to the overlapping region mesh data and the overlapping region boundary condition data, the precise distribution of the current density within the overlapping region can be obtained, providing key information for the subsequent positioning of virtual nodes. By calculating the current density gradient according to the overlapping region current density field data, the change trend of the current density in space can be understood, providing guidance for the precise positioning and optimization of virtual nodes. For example, the region with the maximum current density can be found according to the current density gradient. By generating current density simulation results based on the current density gradient data, the current density field data and the gradient data can be integrated together to form a complete current density simulation result, providing necessary data support for the subsequent virtual node positioning and test point mapping.

[0038] Preferably, step S17 includes the following steps:

[0039] Step S171: Extract the current density peak point data from the current density simulation data to obtain the current density peak point data;

[0040] Step S172: Perform peak point contact analysis on the current density peak point data according to the vectorized layer data to obtain the peak point contact data;

[0041] Step S173: Adjust the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node;

[0042] Step S174: Perform local reachability analysis of the virtual node according to the initial position data of the virtual node and the preset probe contact parameters to obtain the local reachability analysis data of the virtual node;

[0043] Step S175: Optimize the test probe contact according to the local reachability analysis data of the virtual node, the initial position data of the virtual node, and the vectorized layer data to obtain the virtual node contact optimization data;

[0044] Step S176: Verify the feasibility of the virtual node according to the virtual node contact optimization data, the connection matrix, and the vectorized layer data to obtain the virtual node feasibility verification data;

[0045] Step S177: Generate virtual node positioning data based on the virtual node feasibility verification data and the virtual node contact optimization data, and obtain the virtual node positioning data.

[0046] Through extracting the peak points of the current density from the current density simulation data, the present invention can quickly find the point with the highest current density, providing a reference for the initial positioning of the virtual node and improving the efficiency of test point selection. By performing peak point contact analysis on the peak point data of the current density according to the vectorized layer data, it can be determined whether the extracted peak points are easily accessible by the probe, avoiding selecting points blocked by other components or located in difficult-to-reach areas, and improving the feasibility of the test. By adjusting the initial position of the virtual node according to the peak point contact data and the current density simulation data, the initial position of the virtual node can be adjusted according to the accessibility of the peak point, ensuring that the virtual node is located at an accessible position with a relatively high current density, and improving the accuracy and reliability of the test. By performing local reachability analysis of the virtual node according to the virtual node initial position data and the preset probe contact parameters, the reachability of the virtual node can be evaluated more precisely, considering factors such as the size, shape and maximum tilt angle of the probe, so as to more accurately judge whether the probe can effectively contact the virtual node. By optimizing the contact of the test probe according to the virtual node local reachability analysis data, the virtual node initial position data and the vectorized layer data, the contact position and angle of the test probe can be optimized to find the best probe contact method, improving the stability and accuracy of the test. By performing virtual node feasibility verification according to the virtual node contact optimization data, the connection matrix and the vectorized layer data, it can be ensured that the selected virtual node position meets the requirements of circuit connection and does not conflict with other components or wiring, guaranteeing the integrity and correctness of the design. By generating virtual node positioning data based on the virtual node feasibility verification data and the virtual node contact optimization data, the final virtual node positioning data can be generated, which contains the precise position of the virtual node, the pad information it belongs to and the recommended probe contact method, providing a reliable data basis for subsequent path reconstruction and test point mapping.

[0047] Preferably, step S2 includes the following steps:

[0048] Step S21: Add the virtual nodes of the virtual node coordinate data to the connection matrix, update the connection relationship, and obtain the updated connection relationship data;

[0049] Step S22: Generate an initial path based on the updated connection relationship data and the vectorized layer data, and obtain the initial path data;

[0050] Step S23: Optimize the path based on the initial path data and the vectorized layer data to obtain path optimization data;

[0051] Step S24: Generate a 3D path based on the path optimization data and the virtual node coordinate data to obtain 3D path data;

[0052] Step S25: Convert the format of the 3D path data into 3D wiring data format to obtain 3D wiring data.

[0053] In the present invention, by adding the virtual nodes of the virtual node coordinate data to the connection matrix and updating the connection relationship, the virtual nodes can be seamlessly incorporated into the circuit topology structure, providing the correct connection relationship for subsequent path generation and optimization, and effectively solving the problem that overlapping pads cannot be independently tested. By generating the initial path based on the updated data of the connection relationship and the vectorized layer data, the initial path connecting all nodes can be quickly generated, laying the foundation for subsequent path optimization and improving the efficiency of the wiring design. By optimizing the path based on the initial path data and the vectorized layer data, the initial path can be optimized according to the preset wiring rules and obstacle information, such as shortening the path length, reducing the number of corners, and avoiding overlapping with obstacles, thereby improving the performance and manufacturability of the circuit board. By generating the 3D path based on the path optimization data and the virtual node coordinate data, the 2D path can be converted into a 3D path, considering the cross-layer connection and the 3D coordinates of the virtual nodes, generating 3D wiring data that is more in line with the actual production environment, providing more accurate information for subsequent layer generation and circuit testing. By converting the format of the 3D path data into the 3D wiring data format, the 3D path data can be converted into a standard 3D wiring data format, such as the IPC-2581 format, so as to be compatible with other PCB design software and manufacturing equipment, improving the efficiency of data exchange and the generality of the design.

[0054] Preferably, step S23 includes the following steps:

[0055] Step S231: Segment the initial path data to obtain path segment data;

[0056] Step S232: Identify obstacles in the vectorized layer data to obtain obstacle identification data;

[0057] Step S233: Extract the topological relationship from the path segment data to obtain topological relationship data;

[0058] Step S234: Perform topology-aware path optimization on the path segment data according to the obstacle identification data and the topological relationship data to obtain topology-aware path optimization data;

[0059] Step S235: Perform path merging based on the topology-aware path optimization data to obtain path merging data;

[0060] Step S236: Convert the path merging data into a standard data format to obtain path optimization data.

[0061] In the present invention, by segmenting the initial path data, the path is decomposed into smaller line segments, which can more finely control and optimize each segment of the path, improve the flexibility and efficiency of path optimization, and provide basic data for subsequent topology-aware optimization. By identifying obstacles in the vectorized layer data, obstacles that need to be avoided during the wiring process, such as components, existing traces, and no-wire zones, can be accurately identified, providing necessary constraint conditions for path optimization and avoiding wiring errors. By extracting the topological relationships from the path segment data, the connection relationships between the line segments in the path and the connection relationships between the line segments and the virtual nodes can be clearly understood, providing necessary topological information for topology-aware path optimization and ensuring that the optimized path still meets the requirements of circuit connection. By performing topology-aware path optimization on the path segment data according to the obstacle identification data and topological relationship data, while optimizing the path, the topological structure of the circuit can be kept unchanged, avoiding the introduction of new crossings or loops, thereby improving the signal integrity and reliability of the circuit board. By performing path merging according to the topology-aware path optimization data, the optimized line segments can be recombined into a complete path, removing redundant points, simplifying the path representation, and improving the efficiency of subsequent processing. By converting the path merging data into a standard data format, the path data can be converted into a standard format, such as Gerber format or ODB++ format, to be compatible with other PCB design software and manufacturing equipment, improving the efficiency of data exchange and the universality of the design.

[0062] Preferably, step S3 includes the following steps:

[0063] Step S31: Perform reachability analysis based on the 3D wiring data, vectorized layer data, and virtual node coordinate data to obtain reachability analysis data;

[0064] Step S32: Construct a reachability matrix for the reachability analysis data to obtain a reachability matrix;

[0065] Step S33: Determine the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data;

[0066] Step S34: Optimize the test point positions for the candidate test area data according to the 3D wiring data to obtain optimized test point position data;

[0067] Step S35: Generate test point data based on the optimized data of the test point positions and the virtual node coordinate data to obtain the test point data.

[0068] Through reachability analysis based on the three-dimensional wiring data, vectorized layer data, and virtual node coordinate data, the present invention can comprehensively evaluate the reachability of each virtual node, consider factors such as probe parameters, component layout, and wiring conditions, provide a reliable basis for subsequent test point selection, and effectively avoid selecting unreachable test points. By constructing a reachability matrix for the reachability analysis data, the reachability relationship between virtual nodes can be clearly represented, such as whether there are spatial conflicts or mutual interferences, providing more comprehensive information for determining the candidate areas of test points in the subsequent process, and helping to optimize the test point layout. By determining the candidate areas of test points based on the reachability matrix for the virtual node coordinate data, appropriate candidate areas of test points can be screened out according to the reachability scores of virtual nodes and the spatial relationships between them, improving the efficiency and accuracy of test point selection. By optimizing the test point positions based on the three-dimensional wiring data for the candidate test area data, the positions of the test points can be further optimized, such as maximizing the distance from the corresponding network wiring to reduce the interference of the probe on signal transmission, or minimizing the probe movement distance to improve the test efficiency. By generating test point data based on the optimized data of the test point positions and the virtual node coordinate data, test point data containing complete test point information can be generated, including coordinates, the affiliated network, the corresponding virtual node ID, and the recommended probe contact method, etc., providing clear guidance for subsequent printed circuit board testing.

[0069] Preferably, step S4 includes the following steps:

[0070] Step S41: Project the three-dimensional wiring data onto the corresponding two-dimensional plane and integrate it with the vectorized layer data to obtain the integrated layer data;

[0071] Step S42: Create a test point layer based on the test point data to obtain the test point layer data;

[0072] Step S43: Optimize the integrated layer data and the test point layer data to obtain the optimized layer data;

[0073] Step S44: Convert the format of the optimized layer data to obtain the converted layer data in terms of format;

[0074] Step S45: Generate hierarchical layer data based on the converted layer data in terms of format to obtain the hierarchical layer data.

[0075] By projecting the three-dimensional wiring data onto the corresponding two-dimensional plane and integrating it with the vectorized layer data, the three-dimensional wiring information can be converted into two-dimensional layer data, which is then merged with the original layer data to generate complete and manufacturable layer data, ensuring the consistency and integrity of the design. By creating a test point layer based on the test point data, the test point information can be added to an independent layer, facilitating subsequent testing and fault diagnosis and improving the testing efficiency. The clear test point layer information also makes it easier for PCB manufacturers and testers to understand the design intent. By optimizing the layer data of the integrated data and the test point layer data, the manufacturability and reliability of the circuit board can be further improved. For example, by adjusting the trace spacing, adding teardrops, etc., potential manufacturing problems can be avoided and the electrical performance of the circuit board can be enhanced. By converting the layer data format of the optimized layer data, the layer data can be converted into the standard Gerber file format, ensuring that the data can be correctly recognized and used by PCB manufacturers, improving the manufacturability of the design and avoiding data compatibility issues. By generating hierarchical layer data based on the converted layer data format, all Gerber files can be organized according to their levels to generate the final hierarchical layer data, facilitating PCB manufacturers' production and ensuring the integrity and orderliness of the data, thus simplifying the production process.

[0076] Preferably, the present invention further provides a generation system for a circuit board design diagram for performing the generation method for a circuit board design diagram as described above. The generation system for a circuit board design diagram includes:

[0077] A topology decomposition and virtual node insertion module for obtaining the original circuit board design diagram file; vectorizing the layer data of the original circuit board design diagram file to obtain vectorized layer data; constructing a connection matrix of component elements based on the vectorized layer data to obtain a connection matrix; performing overlapping area modeling based on the vectorized layer data and the connection matrix to obtain overlapping area modeling data; performing current density simulation based on the overlapping area modeling data to obtain current density simulation data; performing virtual node positioning on the overlapping area modeling data based on the current density simulation data and the vectorized layer data, and generating virtual node coordinate data to obtain virtual node coordinate data;

[0078] A path reconstruction module for generating an initial path based on the virtual node coordinate data, the connection matrix, and the vectorized layer data, and performing path optimization to obtain path optimization data; generating three-dimensional wiring data based on the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data;

[0079] A test point mapping module, which is used to determine candidate areas of test points based on three-dimensional wiring data, vectorized layer data, and virtual node coordinate data to obtain candidate test area data; perform optimization processing on the candidate test area data to obtain test point data;

[0080] A layer generation module, which is used to integrate layer data according to three-dimensional wiring data and vectorized layer data to obtain integrated layer data; create a test point layer according to the test point data to obtain test point layer data; generate a hierarchical layer according to the integrated layer data and the test point layer data to obtain hierarchical layer data. Description of the Drawings

[0081] Figure 1 It is a schematic flow chart of the steps of a method for generating a circuit board design drawing;

[0082] Figure 2 It is Figure 1 a detailed implementation step flow chart of step S1 in

[0083] Figure 3 It is Figure 1 a detailed implementation step flow chart of step S2 in

[0084] The realization of the purpose, functional characteristics, and advantages of the present invention will be further described in conjunction with the embodiments with reference to the drawings. Detailed Embodiments

[0085] The technical method of the present invention will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0086] In addition, the drawings are only schematic diagrams of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus the repeated description of them will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0087] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly, the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed related items.

[0088] To achieve the above object, please refer to Figures 1 to 3 , a method for generating a circuit board design diagram, comprising the following steps:

[0089] Step S1: Obtain the original circuit board design diagram file; vectorize the layer data of the original circuit board design diagram to obtain vectorized layer data; construct a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data;

[0090] Step S2: Generate an initial path according to the virtual node coordinate data, the connection matrix, and the vectorized layer data, and perform path optimization to obtain path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data;

[0091] Step S3: Determine a candidate test area according to the three-dimensional wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; perform optimization processing on the candidate test area data to obtain test point data;

[0092] Step S4: Integrate the layer data according to the three-dimensional wiring data and the vectorized layer data to obtain layer data integration data; create a test point layer according to the test point data to obtain test point layer data; generate a hierarchical layer according to the layer data integration data and the test point layer data to obtain hierarchical layer data, so as to implement the circuit board design diagram generation operation.

[0093] In the embodiments of the present invention, referring to Figure 1 shown, it is a schematic flow chart of the steps of the method for generating a circuit board design diagram of the present invention. In this example, the method for generating a circuit board design diagram comprises the following steps:

[0094] Step S1: Obtain the original circuit board design drawing file; perform vectorization on the layer data of the original circuit board design drawing file to obtain vectorized layer data; construct a connection matrix for component elements based on the vectorized layer data to obtain a connection matrix; perform overlapping area modeling based on the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation based on the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data;

[0095] In the embodiment of the present invention, first, obtain the original circuit board design drawing file (such as a Gerber file), and convert it into vectorized layer data, and extract information such as the coordinates and line widths of graphic elements. Then, construct a connection matrix based on the vectorized layer data to record the connection relationships and types between component elements, including the levels and degrees of overlapping connections. Next, perform modeling on the overlapping area according to the vectorized layer data and the connection matrix, and calculate information such as the shape, area, and center point coordinates of the overlapping area. Then, use finite element analysis software to perform current density simulation on the overlapping area to obtain current density distribution data. Finally, according to the current density simulation data and the vectorized layer data, locate virtual nodes in the overlapping area, and generate virtual node coordinate data including virtual node IDs, coordinates, and the information of the pads to which they belong.

[0096] Step S2: Generate an initial path according to the virtual node coordinate data, the connection matrix, and the vectorized layer data, and perform path optimization to obtain path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data;

[0097] In the embodiment of the present invention, based on the virtual node coordinate data, the connection matrix, and the vectorized layer data, generate an initial path connecting all nodes, including direct connections, cross-layer connections, and connections through virtual nodes. Then, according to preset wiring rules (such as minimum corners, minimum line lengths, obstacle avoidance, etc.) and the hierarchical relationships of virtual nodes, optimize the initial path, for example, use the A* algorithm or the Dijkstra algorithm for path search and optimization. Finally, convert the optimized two-dimensional path into a three-dimensional path, consider the vertical transition of cross-layer connections and the three-dimensional coordinates of virtual nodes, and generate three-dimensional wiring data including the start point, end point, width, and hierarchical information of each path segment.

[0098] Step S3: Determine a candidate test area according to the three-dimensional wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; perform optimization processing on the candidate test area data to obtain test point data;

[0099] In the embodiments of the present invention, according to the three-dimensional wiring data, vectorized layer data, and virtual node coordinate data, the reachability of each virtual node is analyzed, taking into account the probe parameters and the obstacles in the surrounding environment. The reachability analysis results are stored in a reachability matrix, which is used to guide the determination of the candidate area for test points. Then, based on the reachability matrix, virtual nodes with higher reachability are selected, and candidate test areas are defined centered on them. Finally, the position of the test points is optimized within the candidate test areas, considering the distance from the wiring path and the uniformity of the distribution of test points, to generate test point data including information such as the coordinates of the test points, the networks to which they belong, the corresponding virtual node IDs, and the recommended probe contact directions.

[0100] Step S4: Integrate the layer data according to the three-dimensional wiring data and the vectorized layer data to obtain integrated layer data; create a test point layer according to the test point data to obtain test point layer data; generate a hierarchical layer according to the integrated layer data and the test point layer data to obtain hierarchical layer data, so as to implement the operation of generating a printed circuit board design drawing;

[0101] In the embodiments of the present invention, the three-dimensional wiring data is projected onto the corresponding two-dimensional plane and integrated with the original vectorized layer data to generate integrated layer data containing all layer information. Then, a new test point layer is created according to the test point data, including information such as the positions of the test points, network names, test methods, and parameters. Next, all layer data is optimized, such as removing redundant data, repairing graphic defects, and optimizing graphic arrangements, to improve the manufacturability and reliability of the printed circuit board. Finally, the optimized layer data is converted into the standard Gerber file format and organized hierarchically to generate hierarchical layer data, containing all information for manufacturing and testing.

[0102] Preferably, step S1 includes the following steps:

[0103] Step S11: Obtain the original printed circuit board design drawing file; vectorize the layer data of the original printed circuit board design drawing file to obtain vectorized layer data;

[0104] Step S12: Extract the element connection relationship according to the vectorized layer data to obtain element connection relationship data; classify the connection types of the element connection relationship data to obtain connection type classification data;

[0105] Step S13: Construct a connection matrix according to the connection type classification data to obtain a connection matrix;

[0106] Step S14: Extract the overlapping connections from the connection matrix to obtain overlapping connection data;

[0107] Step S15: Model the overlapping area according to the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data;

[0108] Step S16: Perform current density simulation based on the overlapping region modeling data to obtain current density simulation data;

[0109] Step S17: Locate virtual nodes for the overlapping region modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node location data;

[0110] Step S18: Generate virtual node coordinate data according to the virtual node location data and the overlapping connection data to obtain virtual node coordinate data.

[0111] As an example of the present invention, refer to Figure 2 As shown, in this example, step S1 includes:

[0112] Step S11: Obtain the original printed circuit board design drawing file; perform vectorization of the layer data of the original printed circuit board design drawing file to obtain vectorized layer data;

[0113] In the embodiment of the present invention, obtaining the original printed circuit board design drawing file and performing vectorization of the layer data: First, read the original printed circuit board design drawing file, such as Gerber file, ODB++ file, etc. Use software such as CAM350 to convert the graphic information of each layer (such as copper layer, solder mask layer, silk screen layer, etc.) in the Gerber file into vector data. The specific operation is to import the Gerber file in the CAM350 software, select the layer to be vectorized, execute the vectorization command, and convert the graphic into a vector graphic composed of line segments and arcs. Then, extract the coordinate data, line width, layer level and other information of the vector graphic and store it in a specific data structure, such as DXF format or a custom vector data format. This step outputs vectorized layer data, including the vector representation of graphic elements in all layers.

[0114] Step S12: Extract element connection relationship data according to the vectorized layer data; classify the connection types of the element connection relationship data to obtain connection type classification data;

[0115] In the embodiments of the present invention, element connection relationship extraction and connection type classification are performed based on vectorized layer data: all elements in the vectorized layer data are traversed, and the distance and overlapping area between elements are calculated. If there is an overlapping area between two pads and they belong to the same network, the overlapping connection relationship between them is recorded, and the overlapping degree is calculated, that is, the ratio of the overlapping area to the total area of the pads. If the center coordinates of a pad and a via are completely coincident and they are on adjacent layers, the cross-layer connection relationship between them is recorded. If there is a wire connection between two pads, the direct connection relationship between them is recorded. All connection relationships are classified into direct connections, cross-layer connections, and overlapping connections, and information such as the classification results and overlapping degrees is stored in the connection type classification data.

[0116] Step S13: Construct a connection matrix based on the connection type classification data to obtain the connection matrix;

[0117] In the embodiments of the present invention, a connection matrix is constructed based on the connection type classification data: a two-dimensional matrix is created, and the rows and columns of the matrix represent all nodes in the circuit (including pads, vias, etc.). According to the connection type classification data, the values of the matrix elements are filled. If there is a direct connection relationship between two nodes, the value of the corresponding matrix element is 1; if there is a cross-layer connection relationship between two nodes, the value of the corresponding matrix element is the layer difference; if there is an overlapping connection relationship between two nodes, the value of the corresponding matrix element is the overlapping degree. The finally generated connection matrix completely describes the connection relationship and connection type between circuit nodes.

[0118] Step S14: Extract overlapping connection data from the connection matrix;

[0119] In the embodiments of the present invention, overlapping connection data is extracted from the connection matrix: the connection matrix is traversed to find all elements whose values are greater than 0 and less than 1, and these elements represent overlapping connection relationships. The row and column indices corresponding to these elements are extracted, that is, the IDs of the overlapping pads. The IDs of the overlapping pads, the corresponding overlapping degrees, and the hierarchical relationships are stored in the overlapping connection data.

[0120] Step S15: Perform overlapping area modeling based on the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data;

[0121] In the embodiments of the present invention, overlapping area modeling is performed based on the vectorized layer data and the overlapping connection data: according to the pad IDs provided by the overlapping connection data, the vector graphic data of the corresponding pads is extracted from the vectorized layer data. Boolean operations are used to perform intersection operations on the vector graphics of the overlapping pads to obtain the exact shape of the overlapping area. Geometric information such as the area and center point coordinates of the overlapping area is calculated and stored in the overlapping area modeling data.

[0122] Step S16: Perform current density simulation based on the overlapping region modeling data to obtain current density simulation data;

[0123] In the embodiment of the present invention, the current density simulation is performed based on the overlapping region modeling data: The finite element analysis software such as COMSOL is used to perform current density simulation on the overlapping region. First, import the overlapping region modeling data into the COMSOL software, and set the material properties according to the material of the pad. Then, apply current excitation on the boundary of the overlapping region, for example, set the magnitude and direction of the current. Next, perform mesh generation on the overlapping region, and input the mesh data and boundary conditions into the COMSOL solver. Finally, solve the current density field, extract the current density distribution data, and store it as current density simulation data.

[0124] Step S17: Perform virtual node positioning on the overlapping region modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data;

[0125] In the embodiment of the present invention, the virtual node positioning is performed on the overlapping region modeling data according to the current density simulation data and the vectorized layer data: Extract the point with the maximum current density from the current density simulation data as the initial position of the virtual node. Then, judge whether the initial position is located in the accessible region according to the vectorized layer data, for example, whether it is blocked by other components or located in a narrow gap. If the initial position is not accessible, search for the nearby accessible region along the current density gradient direction, and take the first accessible point found as the position of the virtual node. Store the position information of the virtual node in the virtual node positioning data.

[0126] Step S18: Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data;

[0127] Generate virtual node coordinate data according to the virtual node positioning data and the overlapping connection data: Integrate the position coordinates of each virtual node, the corresponding overlapping pad ID, and the hierarchical relationship and other information in the virtual node positioning data to generate virtual node coordinate data. This data includes the unique identifier of each virtual node, the three-dimensional coordinates, and the original pad information to which it belongs.

[0128] Preferably, step S15 includes the following steps:

[0129] Step S151: Extract the pad shape from the vectorized layer data according to the overlapping connection data to obtain pad shape data;

[0130] Step S152: Process the irregular pad shape data to obtain irregular pad shape processed data;

[0131] Step S153: Calculate the overlapping area of the irregular pad shape processing data to obtain the overlapping area calculation data;

[0132] Step S154: Verify the overlapping area of the overlapping area calculation data according to the pad shape extraction data to obtain the overlapping area verification data;

[0133] Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain the overlapping area modeling data.

[0134] In the embodiment of the present invention, the pad shape is extracted from the vectorized layer data according to the overlapping connection data: read the pad IDs whose shapes need to be extracted from the overlapping connection data. Then, search for the pad graphic elements corresponding to these IDs in the vectorized layer data. Extract the vector contour data of these pad graphic elements, including the coordinates and endpoint information of the line segments and arcs that make up the pad shape. Store the extracted pad shape data as a data structure of a polygon or a curve. For example, use a series of ordered coordinate points to represent the boundary of the pad. The shape data of each pad is stored in association with its corresponding ID.

[0135] Process the pad shape data for irregular pad shapes: Analyze the extracted pad shape data. If the pad shape is a regular shape, such as a circle or a rectangle, directly record its geometric parameters, such as the radius of the circle or the length and width of the rectangle. If the pad shape is an irregular shape, use methods such as polygon approximation or spline curve fitting to process the irregular shape. For example, for polygon approximation, decompose the irregular shape into multiple small line segments and use the set of these line segments to approximately represent the original shape. Store the processed shape data, including the geometric parameters of the regular shape or the approximation curve parameters of the irregular shape, as the irregular pad shape processing data.

[0136] Calculate the overlapping area of the irregular pad shape processing data: Read two sets of irregular pad shape processing data for which the overlapping area needs to be calculated. If the pad shape is a regular shape, calculate the area and shape of the overlapping area according to its geometric parameters using geometric formulas. For example, to calculate the overlapping area of two circular pads, first calculate the distance between the centers, and then calculate the area and shape of the overlapping area according to the distance between the centers and the radius. If the pad shape is an irregular shape, use a polygon clipping algorithm or a curve intersection calculation method to calculate the overlapping area of the two irregular shapes. Store the information such as the area, shape, and boundary coordinates of the calculated overlapping area as the overlapping area calculation data.

[0137] Extract data according to the pad shape and verify the overlapping area calculation data for the overlapping area: Compare the calculated overlapping area in the overlapping area calculation data with the original pad shape extraction data. Verify whether the overlapping area is completely within the shapes of the two pads and does not exceed the boundaries of the pads. For example, after calculating the overlapping area of two polygonal pads, verify whether the polygon vertices of the overlapping area are all inside the two original pad polygons. Store the verification results, such as information about the validity of the overlapping area and the matching degree between the overlapping area and the original pad shape, as overlapping area verification data.

[0138] Generate overlapping area modeling data based on the overlapping area verification data: If the overlapping area verification result indicates that the overlapping area is valid, extract information such as the shape, area, and center point coordinates of the overlapping area in the overlapping area calculation data to generate overlapping area modeling data. If the overlapping area verification result indicates that the overlapping area is invalid, such as incorrect calculation of the overlapping area or exceeding the pad boundary, re-execute the overlapping area calculation step or make corrections according to the specific situation until a valid overlapping area is obtained, and finally generate overlapping area modeling data.

[0139] Preferably, step S16 includes the following steps:

[0140] Step S161: Use finite element analysis technology to perform overlapping area mesh generation on the overlapping area modeling data to obtain overlapping area mesh data;

[0141] Step S162: Set boundary adjustment according to the overlapping area mesh data to obtain overlapping area boundary condition data;

[0142] Step S163: Solve the current density field according to the overlapping area mesh data and the overlapping area boundary condition data to obtain overlapping area current density field data;

[0143] Step S164: Calculate the current density gradient according to the overlapping area current density field data to obtain current density gradient data;

[0144] Step S165: Generate a current density simulation result according to the current density gradient data to obtain current density simulation data.

[0145] In the embodiments of the present invention, finite element analysis technology is used to perform mesh generation for the overlapping region modeling data: import the overlapping region modeling data into a finite element analysis software, such as ANSYS or COMSOL. According to the geometric shape and size of the overlapping region, set the mesh generation parameters, such as the maximum element size, the minimum element size, and the mesh growth rate, etc. Perform mesh generation for the overlapping region to generate a mesh composed of basic elements such as triangles or quadrilaterals. Store the generated mesh data, including information such as the node coordinates of each element, the element type, and the connection relationship between elements, as the overlapping region mesh data. Ensure that the mesh density is fine enough to accurately capture the details of the current density distribution. For example, in the edge of the overlapping region or the region where the current density changes drastically, a smaller mesh size can be used.

[0146] Perform boundary adjustment settings according to the overlapping region mesh data: Based on the overlapping region mesh data, define the boundary conditions for the current density simulation. Apply a current excitation on the boundary of the overlapping region. For example, set the magnitude and direction of the input current. The specific method for setting the current excitation can be selected according to the actual situation. For example, the boundary of the overlapping region can be defined as a constant current density boundary or a constant electric potential boundary. Store the set boundary conditions, including information such as the boundary type, the boundary value, and which mesh nodes the boundary conditions act on, as the overlapping region boundary condition data.

[0147] Solve for the current density field according to the overlapping region mesh data and the overlapping region boundary condition data: Input the overlapping region mesh data and the overlapping region boundary condition data into the solver of the finite element analysis software. The solver calculates the current density distribution in the overlapping region based on Maxwell's equations and the relevant material properties. The solving process usually adopts numerical iteration methods, such as the finite element method or the finite difference method. Store the obtained current density field data, including the current density values at each mesh node, as the overlapping region current density field data.

[0148] Calculate the current density gradient according to the overlapping region current density field data: Calculate the gradient of the current density according to the overlapping region current density field data. The current density gradient represents the rate of change and direction of the current density in space. Numerical differentiation methods, such as the finite difference method, can be used to calculate the current density gradient at each mesh node. Store the calculated current density gradient data, including the gradient values and directions at each mesh node, as the current density gradient data.

[0149] Generation of current density simulation results based on current density gradient data: Integrate information such as current density field data in the overlapping region, current density gradient data, and grid data in the overlapping region to generate current density simulation data. The current density simulation data includes the current density distribution, gradient information, and grid information in the overlapping region, which can be used for subsequent virtual node positioning. For example, the current density data can be visualized to more intuitively observe the current density distribution.

[0150] Preferably, step S17 includes the following steps:

[0151] Step S171: Extract the current density peak points from the current density simulation data to obtain the current density peak point data;

[0152] Step S172: Perform peak point contact analysis on the current density peak point data according to the vectorized layer data to obtain the peak point contact data;

[0153] Step S173: Adjust the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node;

[0154] Step S174: Perform local reachability analysis of the virtual node according to the initial position data of the virtual node and the preset probe contact parameters to obtain the local reachability analysis data of the virtual node;

[0155] Step S175: Optimize the test probe contact according to the local reachability analysis data of the virtual node, the initial position data of the virtual node, and the vectorized layer data to obtain the virtual node contact optimization data;

[0156] Step S176: Verify the feasibility of the virtual node according to the virtual node contact optimization data, the connection matrix, and the vectorized layer data to obtain the virtual node feasibility verification data;

[0157] Step S177: Generate virtual node positioning data according to the virtual node feasibility verification data and the virtual node contact optimization data to obtain the virtual node positioning data.

[0158] In the embodiment of the present invention, the current density peak points are extracted from the current density simulation data: Analyze the current density simulation data to find the point with the largest current density. A search algorithm can be used, such as traversing all grid nodes to find the node with the largest current density value. Extract the coordinates of the node and the corresponding current density value. If there are multiple maximum points with the same current density, extract the coordinates and current density values of all these points. Store the extracted peak point coordinates and current density values as the current density peak point data.

[0159] Perform peak point contact analysis on the peak point data of current density based on the vectorized layer data: Compare the coordinates in the peak point data of current density with the vectorized layer data. Check whether the peak points are located in any areas that hinder the contact of the test probes, such as the component body, pad edge, or other non-contactable areas. For example, calculate the distance between the peak points and the surrounding components to determine whether the peak points are blocked by other components. Store the analysis results, such as whether the peak points are contactable, and if not, the specific reasons for non-contact, such as being blocked by which component, as peak point contact data.

[0160] Adjust the initial position of the virtual node according to the peak point contact data and the current density simulation data: If the peak point contact analysis result indicates that the peak point is contactable, use the coordinates of the peak point as the initial position of the virtual node. If the peak point is not contactable, search for a nearby contactable area along the opposite direction of the gradient according to the current density gradient information in the current density simulation data. During the search process, continuously check whether the new position is contactable until the first contactable point is found. Use the coordinates of this point as the initial position of the virtual node and store it as the virtual node initial position data.

[0161] Perform local reachability analysis of the virtual node according to the virtual node initial position data and the preset probe contact parameters: According to the preset probe contact parameters, such as the diameter of the probe, the shape of the probe, and the maximum tilt angle of the probe, perform local reachability analysis around the virtual node initial position. Simulate the contact situation of the test probe in different directions and angles at the virtual node initial position. Determine whether the probe can contact the virtual node initial position under the condition of meeting the preset parameters. Store the analysis results, such as the reachability scores of the probe in different directions and angles, as the virtual node local reachability analysis data.

[0162] Optimize the test probe contact according to the virtual node local reachability analysis data, the virtual node initial position data, and the vectorized layer data: According to the virtual node local reachability analysis data, select the direction and angle with the highest reachability score as the best contact direction and angle of the test probe. If the reachability score is lower than the preset threshold, search for a better test point position near the virtual node initial position according to the vectorized layer data and the current density simulation data, and re-perform the local reachability analysis until a test point position that meets the reachability requirements is found. Store the coordinates of the optimized test point position and the best contact direction and angle of the probe as the virtual node contact optimization data.

[0163] Verify the feasibility of virtual nodes based on the virtual node contact optimization data, connection matrix, and vectorized layer data: Check whether the positions of the test points in the virtual node contact optimization data meet the requirements of circuit connection. For example, check the connectivity between the test points and the corresponding pads in the connection matrix, and whether the test points are located in the correct network. At the same time, according to the vectorized layer data, check whether the positions of the test points conflict with other components or wirings. Store the verification results, such as whether the test points meet the circuit connection requirements and whether they conflict with other elements, as virtual node feasibility verification data.

[0164] Generate virtual node positioning data based on the virtual node feasibility verification data and the virtual node contact optimization data: If the virtual node feasibility verification result shows that the test point position is feasible, integrate information such as the coordinate positions of the test points in the virtual node contact optimization data, the corresponding pad IDs, hierarchical relationships, and the optimal contact directions and angles of the probes to generate virtual node positioning data. If the virtual node feasibility verification result shows that the test point position is not feasible, re-execute the steps of adjusting the initial position of the virtual node and optimizing the test probe contact until a feasible test point position is found, and finally generate virtual node positioning data.

[0165] Preferably, step S2 includes the following steps:

[0166] Step S21: Add the virtual nodes of the virtual node coordinate data to the connection matrix, update the connection relationship, and obtain connection relationship update data;

[0167] Step S22: Generate an initial path based on the connection relationship update data and the vectorized layer data to obtain initial path data;

[0168] Step S23: Optimize the path based on the initial path data and the vectorized layer data to obtain path optimization data;

[0169] Step S24: Generate a three-dimensional path based on the path optimization data and the virtual node coordinate data to obtain three-dimensional path data;

[0170] Step S25: Convert the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data.

[0171] As an example of the present invention, refer to Figure 3 As shown, in this example, step S2 includes:

[0172] Step S21: Add the virtual nodes of the virtual node coordinate data to the connection matrix, update the connection relationship, and obtain connection relationship update data;

[0173] In an embodiment of the present invention, virtual nodes of virtual node coordinate data are added to a connection matrix for connection relationship update: read the virtual node coordinate data to obtain the ID of each virtual node and the ID of the original pad it is connected to. Modify the connection matrix to change the nodes originally connected to the overlapping pads to be connected to the corresponding virtual nodes. The specific operations are as follows: add rows and columns representing virtual nodes to the connection matrix, and update the connection relationship between the virtual nodes and the corresponding original pads into the matrix. For example, if there is an overlap between pad A and pad B, insert virtual node V, then delete the connection relationship between A and B in the connection matrix, and establish new connection relationships between A and V, and B and V. Store the updated connection matrix as connection relationship update data.

[0174] Step S22: Generate an initial path based on the connection relationship update data and the vectorized layer data to obtain initial path data;

[0175] In an embodiment of the present invention, an initial path is generated based on the connection relationship update data and the vectorized layer data: read the connection relationship update data to obtain the connection relationships between all nodes. For each connection relationship, obtain the coordinates of the connected nodes according to the vectorized layer data. If the relationship between two nodes is a direct connection or a cross-layer connection, directly connect the coordinates of these two nodes with a straight line segment to generate an initial path. If the connection relationship involves a virtual node, use the coordinates of the virtual node as an intermediate point, and connect the coordinates of the virtual node and the two original pads with two straight line segments respectively to generate an initial path. Store the generated initial path data as a series of line segments, and each line segment contains information such as the starting point coordinates, ending point coordinates, and the layer it belongs to.

[0176] Step S23: Optimize the path based on the initial path data and the vectorized layer data to obtain path optimization data;

[0177] In an embodiment of the present invention, the path is optimized based on the initial path data and the vectorized layer data: read the initial path data and the vectorized layer data. Optimize the initial path to meet the preset wiring rules, such as minimum corners, minimum line length, and obstacle avoidance. Path search algorithms, such as the A* algorithm or Dijkstra algorithm, can be used, combined with the obstacle information marked in the vectorized layer data, to optimize the initial path. During the optimization process, the shape, position, and layer of the path can be adjusted to reduce the path length, the number of corners, and the overlap with obstacles. Store the optimized path data, including information such as the starting point coordinates, ending point coordinates, line width, and the layer it belongs to for each segment of the path, as path optimization data.

[0178] Step S24: Generate a 3D path based on the path optimization data and the virtual node coordinate data to obtain 3D path data;

[0179] In the embodiment of the present invention, three-dimensional path generation is performed according to path optimization data and virtual node coordinate data: Read the path optimization data and virtual node coordinate data. According to the hierarchical information of each segment of the path in the path optimization data and the three-dimensional coordinates of the virtual nodes in the virtual node coordinate data, convert the two-dimensional path into a three-dimensional path. For cross-layer connections, according to the starting layer and the ending layer of the connection, and the position of the via, generate vertical path segments connecting different layers. For connections involving virtual nodes, according to the three-dimensional coordinates of the virtual nodes and the layer of the connection pads, generate three-dimensional path segments connecting the virtual nodes and the pads. Store the generated three-dimensional path data as a series of three-dimensional line segments, and each line segment contains information such as the starting three-dimensional coordinates, the ending three-dimensional coordinates, the line width, and the belonging layer, etc.

[0180] Step S25: Convert the three-dimensional path data into a three-dimensional wiring data format to obtain three-dimensional wiring data;

[0181] In the embodiment of the present invention, convert the three-dimensional path data into a three-dimensional wiring data format: Read the three-dimensional path data. Convert the three-dimensional path data into a standard three-dimensional wiring data format, such as the IPC-2581 format. During the conversion process, it is necessary to convert the line segment information, hierarchical information, line width information, etc. in the three-dimensional path data into the corresponding data structures in the target format. For example, convert each three-dimensional line segment into a wiring element in the target format and set its attributes, such as the starting coordinates, ending coordinates, line width, and the belonging network, etc. Store the converted data as three-dimensional wiring data.

[0182] Preferably, step S23 includes the following steps:

[0183] Step S231: Segment the initial path data to obtain path segment data;

[0184] Step S232: Identify obstacles in the vectorized layer data to obtain obstacle identification data;

[0185] Step S233: Extract the topological relationship from the path segment data to obtain topological relationship data;

[0186] Step S234: Perform topology-aware path optimization on the path segment data according to the obstacle identification data and the topological relationship data to obtain topology-aware path optimization data;

[0187] Step S235: Merge the paths according to the topology-aware path optimization data to obtain path merge data;

[0188] Step S236: Convert the path merge data into a standard data format to obtain path optimization data.

[0189] In an embodiment of the present invention, initial path data is read, and each path is segmented according to inflection points and vias. For example, if a path contains two inflection points and one via, it is divided into four segments: from the starting point to the first inflection point, from the first inflection point to the via, from the via to the second inflection point, and from the second inflection point to the end point. Each segment of the path is stored as an independent line segment, including information such as the starting point coordinates, end point coordinates, line width, and the layer to which it belongs. All the segmented path data is stored as path segmentation data.

[0190] Perform obstacle recognition on the vectorized layer data: Analyze the vectorized layer data to identify all possible obstacles that may hinder routing, such as component outlines, existing traces, and prohibited routing areas. Extract the geometric shapes and location information of these obstacles. For example, use polygons to represent the boundaries of the obstacles. Store all the identified obstacle information, including the type, geometric shape, location, and the layer to which it belongs, as obstacle recognition data.

[0191] Extract topological relationships from the path segmentation data: Analyze the connection relationships between the line segments in the path segmentation data and the connection relationships between the line segments and virtual nodes. For example, record which line segments share the same end points and which line segments are connected to the same virtual node. Store these connection relationships as topological relationship data, and a graph data structure can be used to represent the connection relationships between nodes and edges.

[0192] Perform topology-aware path optimization on the path segmentation data based on the obstacle recognition data and the topological relationship data: Use a topology-aware path optimization algorithm, such as an improved algorithm based on the A* algorithm or Dijkstra algorithm, to optimize the path segmentation data. During the optimization process, consider the obstacle information in the obstacle recognition data and the connection relationships between the line segments in the topological relationship data. For example, when searching for the shortest path, avoid obstacle areas and keep the topological relationships between the line segments unchanged to avoid generating new crossings or loops. Store the optimized path segmentation data, including the starting point coordinates, end point coordinates, line width, and the layer to which each line segment belongs, as topology-aware path optimization data.

[0193] Perform path merging according to the topology-aware path optimization data: Read the topology-aware path optimization data. Merge the line segments belonging to the same path into a complete path. During the merging process, remove redundant points between the line segments. For example, if two line segments share an end point and are on the same straight line, merge these two line segments into one line segment. Store the merged path data, including the starting point coordinates, end point coordinates, all intermediate inflection point coordinates, line width, and the layer to which it belongs, as path merging data.

[0194] Perform standard data format conversion on path merged data: Read the path merged data. Convert the path merged data into a standard path data format. For example, convert the coordinate information, line width information, layer information, etc. of each path into the corresponding data structure in the target format. Ensure that the converted data format meets the requirements of the PCB design software. For example, the path data can be converted into Gerber format or ODB++ format. Store the converted data as path optimized data.

[0195] Preferably, step S3 includes the following steps:

[0196] Step S31: Perform reachability analysis based on the 3D routing data, vectorized layer data, and virtual node coordinate data to obtain reachability analysis data;

[0197] Step S32: Construct a reachability matrix for the reachability analysis data to obtain a reachability matrix;

[0198] Step S33: Determine the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data;

[0199] Step S34: Optimize the test point positions for the candidate test area data according to the 3D routing data to obtain optimized test point position data;

[0200] Step S35: Generate test point data according to the optimized test point position data and the virtual node coordinate data to obtain test point data.

[0201] In the embodiment of the present invention, perform reachability analysis based on the 3D routing data, vectorized layer data, and virtual node coordinate data: Read the 3D routing data, vectorized layer data, and virtual node coordinate data. For each virtual node, simulate the process of the probe approaching the virtual node from different directions and angles according to the preset probe parameters (such as probe diameter, probe shape, maximum tilt angle). The collision detection algorithm is used to detect whether the probe collides with other components, routing, or the board edge during movement. According to the collision detection results, calculate the reachability score of the virtual node. For example, the number of reachable directions, the maximum reachable angle, or the minimum collision distance. Store the reachability score and related information (such as reachable directions, angles) of each virtual node as reachability analysis data.

[0202] Construct a reachability matrix for reachability analysis data: Based on the reachability analysis data, create a matrix where the rows and columns represent virtual nodes respectively. Each element of the matrix represents the reachability relationship between the corresponding two virtual nodes. For example, the element value can indicate whether two virtual nodes can be accessed by the probe simultaneously, or whether there is a spatial conflict between them, such as the reach direction of one node being blocked by another node. Store the constructed reachability matrix as reachability matrix data.

[0203] Determine the candidate area of test points for virtual node coordinate data according to the reachability matrix: Analyze the reachability matrix and virtual node coordinate data. According to the reachability score and the spatial conflict information in the reachability matrix, filter out the virtual nodes with higher reachability as the center points of the candidate area of test points. For example, select the virtual nodes with reachability scores higher than the preset threshold, and exclude the nodes with spatial conflicts with other high-reachability nodes. Define a rectangular or circular area centered on each selected virtual node as the candidate area of test points. Store the information such as the center point coordinates, area shape, and size of the candidate area as candidate test area data.

[0204] Optimize the test point positions for the candidate test area data according to the 3D wiring data: Read the 3D wiring data and candidate test area data. In each candidate test area, find the best test point positions. The optimization goal can be to maximize the distance from the corresponding network wiring to avoid probe interference with signal transmission, or to minimize the probe movement distance. Optimization algorithms such as the gradient descent method or genetic algorithm can be used to search for the best test point positions within the candidate area. Store the optimized test point position coordinates as test point position optimization data.

[0205] Generate test point data according to the test point position optimization data and virtual node coordinate data: Combine the test point position optimization data and virtual node coordinate data to generate the final test point data. The test point data includes information such as the coordinates of each test point, the network it belongs to, the corresponding virtual node ID, the recommended probe contact direction and angle, etc. This information will be used to guide the subsequent circuit test process, such as generating test programs and controlling test equipment.

[0206] Preferably, step S4 includes the following steps:

[0207] Step S41: Project the 3D wiring data onto the corresponding 2D plane and integrate it with the vectorized layer data to obtain the integrated layer data;

[0208] Step S42: Create a test point layer according to the test point data to obtain the test point layer data;

[0209] Step S43: Optimize the layer data integration data and the test point layer data to obtain optimized layer data integration data;

[0210] Step S44: Convert the format of the optimized layer data integration data to obtain format-converted layer data;

[0211] Step S45: Generate hierarchical layer data based on the format-converted layer data to obtain hierarchical layer data.

[0212] In the embodiment of the present invention, project the three-dimensional wiring data onto the corresponding two-dimensional plane and integrate it with the vectorized layer data: Read the three-dimensional wiring data and project it onto the corresponding two-dimensional plane according to the hierarchical information of each wiring segment. For example, project the top-layer wiring onto the top-layer plane and the bottom-layer wiring onto the bottom-layer plane. Merge the projected two-dimensional wiring data with the original vectorized layer data. For example, add the wiring data projected onto the top layer to the top-layer vectorized layer data, and add the wiring data projected onto the bottom layer to the bottom-layer vectorized layer data. Store the integrated layer data as layer data integration data, which contains the vector representations of graphic elements in all layers, including the original graphic elements and the projected wiring.

[0213] Create a test point layer based on the test point data: Create a new layer named the test point layer. Read the test point data and add the position information of each test point to the test point layer. Specific graphic symbols can be used to represent the test points, such as circles or crosses. At the same time, add the attribute information of the test points, such as the affiliated network, test method, test parameters, etc., to the test point layer as the attributes of the graphic symbols. Store the created test point layer data as test point layer data, which contains the graphic symbols, position information, and attribute information of all test points.

[0214] Optimize the layer data integration data and the test point layer data: Read the layer data integration data and the test point layer data. Optimize all layer data, such as removing redundant data, repairing graphic defects, and optimizing graphic layout. A rule-based optimization algorithm can be used to optimize the layer data according to the preset design rules and manufacturing process requirements. For example, adjust the trace spacing, add teardrops, and check the minimum line width and line spacing. Store the optimized layer data as optimized layer data integration data, which contains the optimized graphic elements in all layers.

[0215] Perform layer data format conversion on the optimized layer data: Read the optimized layer data. Convert the optimized layer data into the standard Gerber file format. During the conversion process, it is necessary to convert the data of each layer into the corresponding Gerber file and set the parameters of the Gerber file, such as coordinate unit, data format, graphic precision, etc. Ensure that the generated Gerber file meets the requirements of the PCB manufacturer. Store the converted Gerber file as the layer data format conversion data.

[0216] Generate hierarchical layer data based on the layer data format conversion data: Read all Gerber files in the layer data format conversion data. Organize the Gerber files into a hierarchical data structure according to the hierarchy to which each Gerber file belongs. For example, store the top-layer Gerber file, bottom-layer Gerber file, solder mask layer Gerber file, etc. in the corresponding hierarchical directories respectively. Store the organized hierarchical layer data as the hierarchical layer data, which contains all Gerber files used for manufacturing and testing and is organized according to the hierarchy so that the PCB manufacturer can directly use it.

[0217] Preferably, the present invention also provides a generation system for a circuit board design drawing, which is used to execute the generation method for a circuit board design drawing as described above. The generation system for a circuit board design drawing includes:

[0218] A topology decomposition and virtual node insertion module, which is used to obtain the original circuit board design drawing file; perform vectorization of layer data on the original circuit board design drawing file to obtain vectorized layer data; construct a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data;

[0219] A path reconstruction module, which is used to generate an initial path according to the virtual node coordinate data, the connection matrix, and the vectorized layer data, and perform path optimization to obtain path optimization data; generate three-dimensional wiring data according to the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data;

[0220] A test point mapping module, which is used to determine a candidate test area according to the three-dimensional wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; perform test point optimization processing on the candidate test area data to obtain test point data;

[0221] A layer generation module is configured to integrate layer data according to three-dimensional wiring data and vectorized layer data to obtain integrated layer data; create a test point layer according to test point data to obtain test point layer data; and generate a hierarchical layer according to the integrated layer data and the test point layer data to obtain hierarchical layer data.

[0222] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Accordingly, all changes falling within the meaning and scope of the equivalent elements of the application documents are intended to be embraced by the present invention.

[0223] The above description is only a specific implementation manner of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for generating a circuit board design diagram, characterized in that, It includes the following steps: Step S1: Obtain the original printed circuit board design drawing file; Perform vectorization on the layer data of the original printed circuit board design drawing file to obtain vectorized layer data; Construct a connection matrix for component elements based on the vectorized layer data to obtain a connection matrix; perform overlapping area modeling based on the vectorized layer data and the connection matrix to obtain overlapping area modeling data; Perform current density simulation based on the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; Step S2: Generate an initial path based on the virtual node coordinate data, the connection matrix, and the vectorized layer data, and perform path optimization to obtain path optimization data; Generate three-dimensional wiring data based on the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; Step S3: Determine the candidate test area based on the three-dimensional wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; Perform optimization processing on the candidate test area data to obtain test point data; Step S4: Integrate the layer data based on the three-dimensional wiring data and the vectorized layer data to obtain integrated layer data; Create a test point layer based on the test point data to obtain test point layer data; Generate a layered layer based on the integrated layer data and the test point layer data to obtain layered layer data, so as to realize the printed circuit board design drawing generation operation.

2. The method for generating a circuit board design drawing according to claim 1, wherein Step S1 includes the following steps: Step S11: Obtain the original printed circuit board design drawing file; perform vectorization on the layer data of the original printed circuit board design drawing file to obtain vectorized layer data; Step S12: Extract the element connection relationship based on the vectorized layer data to obtain element connection relationship data; classify the connection types of the element connection relationship data to obtain connection type classification data; Step S13: Construct a connection matrix based on the connection type classification data to obtain a connection matrix; Step S14: Extract overlapping connections from the connection matrix to obtain overlapping connection data; Step S15: Perform overlapping area modeling based on the vectorized layer data and the overlapping connection data to obtain overlapping area modeling data; Step S16: Perform current density simulation based on the overlapping area modeling data to obtain current density simulation data; Step S17: Perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data to obtain virtual node positioning data; Step S18: Generate virtual node coordinate data based on the virtual node positioning data and the overlapping connection data to obtain virtual node coordinate data.

3. The generation method for a circuit board design drawing according to claim 2, characterized in that, Step S15 includes the following steps: Step S151: Extract the pad shape from the vectorized layer data according to the overlapping connection data to obtain pad shape data; Step S152: Process the irregular pad shape of the pad shape data to obtain irregular pad shape processing data; Step S153: Calculate the overlapping area of the irregular pad shape processing data to obtain the overlapping area calculation data; Step S154: Verify the overlapping area of the overlapping area calculation data according to the pad shape extraction data to obtain the overlapping area verification data; Step S155: Generate overlapping area modeling data according to the overlapping area verification data to obtain the overlapping area modeling data.

4. The generating method for the circuit board design drawing according to claim 2, wherein Step S16 includes the following steps: Step S161: Use finite element analysis technology to perform overlapping area mesh division on the overlapping area modeling data to obtain the overlapping area mesh data; Step S162: Set boundary adjustment according to the overlapping area mesh data to obtain the overlapping area boundary condition data; Step S163: Solve the current density field according to the overlapping area mesh data and the overlapping area boundary condition data to obtain the overlapping area current density field data; Step S164: Calculate the current density gradient according to the overlapping area current density field data to obtain the current density gradient data; Step S165: Generate the current density simulation result according to the current density gradient data to obtain the current density simulation data.

5. The generation method for a circuit board design diagram according to claim 2, wherein Step S17 includes the following steps: Step S171: Extract the current density peak point from the current density simulation data to obtain the current density peak point data; Step S172: Analyze the peak point contact of the current density peak point data according to the vectorized layer data to obtain the peak point contact data; Step S173: Adjust the initial position of the virtual node according to the peak point contact data and the current density simulation data to obtain the initial position data of the virtual node; Step S174: Analyze the local reachability of the virtual node according to the initial position data of the virtual node and the preset probe contact parameters to obtain the local reachability analysis data of the virtual node; Step S175: Optimize the test probe contact according to the local reachability analysis data of the virtual node, the initial position data of the virtual node and the vectorized layer data to obtain the virtual node contact optimization data; Step S176: Verify the feasibility of the virtual node according to the virtual node contact optimization data, the connection matrix and the vectorized layer data to obtain the virtual node feasibility verification data; Step S177: Generate virtual node positioning data according to the virtual node feasibility verification data and the virtual node contact optimization data to obtain the virtual node positioning data.

6. The method for generating a circuit board design diagram according to claim 1, characterized in that, Step S2 includes the following steps: Step S21: Add the virtual node of the virtual node coordinate data to the connection matrix and update the connection relationship to obtain the connection relationship update data; Step S22: Generate the initial path according to the connection relationship update data and the vectorized layer data to obtain the initial path data; Step S23: Optimize the path according to the initial path data and the vectorized layer data to obtain the path optimization data; Step S24: Generate a three-dimensional path according to the path optimization data and the virtual node coordinate data to obtain the three-dimensional path data; Step S25: Convert the three-dimensional path data into a three-dimensional wiring data format to obtain the three-dimensional wiring data.

7. The method for generating a circuit board design diagram according to claim 6, wherein Step S23 includes the following steps: Step S231: Segment the initial path data to obtain path segment data; Step S232: Identify obstacles in the vectorized layer data to obtain obstacle identification data; Step S233: Extract the topological relationship from the path segment data to obtain topological relationship data; Step S234: Optimize the path segment data based on topology perception according to the obstacle identification data and the topological relationship data to obtain path optimization data based on topology perception; Step S235: Merge the paths according to the path optimization data based on topology perception to obtain path merge data; Step S236: Convert the path merge data into a standard data format to obtain path optimization data.

8. The method for generating a circuit board design drawing according to claim 1, wherein Step S3 includes the following steps: Step S31: Perform reachability analysis based on the 3D wiring data, vectorized layer data, and virtual node coordinate data to obtain reachability analysis data; Step S32: Construct a reachability matrix from the reachability analysis data to obtain a reachability matrix; Step S33: Determine the candidate test area for the virtual node coordinate data according to the reachability matrix to obtain candidate test area data; Step S34: Optimize the test point positions for the candidate test area data based on the 3D wiring data to obtain optimized test point position data; Step S35: Generate test point data according to the optimized test point position data and the virtual node coordinate data to obtain test point data.

9. The method for generating a circuit board design diagram according to claim 1, wherein Step S4 includes the following steps: Step S41: Project the 3D wiring data onto the corresponding 2D plane and integrate it with the vectorized layer data to obtain integrated layer data; Step S42: Create a test point layer according to the test point data to obtain test point layer data; Step S43: Optimize the layer data for the integrated layer data and the test point layer data to obtain optimized layer data; Step S44: Convert the format of the optimized layer data to obtain format-converted layer data; Step S45: Generate hierarchical layer data according to the format-converted layer data to obtain hierarchical layer data.

10. A generation system for a circuit board design diagram, characterized in that, A system for generating a circuit board design diagram for implementing the method for generating a circuit board design diagram according to claim 1, the system for generating a circuit board design diagram includes: A topology decomposition and virtual node insertion module, configured to obtain an original circuit board design diagram file; vectorize the layer data of the original circuit board design diagram file to obtain vectorized layer data; construct a connection matrix of component elements according to the vectorized layer data to obtain a connection matrix; perform overlapping area modeling according to the vectorized layer data and the connection matrix to obtain overlapping area modeling data; perform current density simulation according to the overlapping area modeling data to obtain current density simulation data; perform virtual node positioning on the overlapping area modeling data according to the current density simulation data and the vectorized layer data, and generate virtual node coordinate data to obtain virtual node coordinate data; A path reconstruction module, which is used to generate an initial path based on virtual node coordinate data, a connection matrix, and vectorized layer data, and optimize the path to obtain path optimization data; generate three-dimensional wiring data based on the path optimization data and the virtual node coordinate data to obtain three-dimensional wiring data; A test point mapping module, which is used to determine a candidate test area based on the three-dimensional wiring data, the vectorized layer data, and the virtual node coordinate data to obtain candidate test area data; perform test point optimization processing on the candidate test area data to obtain test point data; A layer generation module, which is used to integrate layer data based on the three-dimensional wiring data and the vectorized layer data to obtain integrated layer data; create a test point layer based on the test point data to obtain test point layer data; generate a hierarchical layer based on the integrated layer data and the test point layer data to obtain hierarchical layer data.

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