Geometric processing pipeline, graphics processing core, processor and vertex caching method

Abstract

The invention discloses a geometric processing pipeline, a graphic processing core, a processor and a vertex caching method, and belongs to the field of chips. The geometric processing pipeline comprises a vertex cache unit with a vertex index cache, a vertex processing pipeline, and a vertex storage and primitive pipeline unit. According to the geometric processing assembly line disclosed by the invention, the vertex cache test of the vertex granularity is realized, the primitives obtained by primitive assembly do not need to be relied on any more, and the geometric processing assembly line of a distributed architecture for delaying primitive assembly is favorably realized.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a geometry processing pipeline, a graphics processing core, a processor and a vertex cache method. Background Art

[0002] Primitive assembly and vertex shading are two different stages of the GPU (Graphics Processing Unit) in the graphics rendering process. Primitive assembly is used to convert vertices into complete geometric primitives, while vertex shading is to calculate vertices. Before vertex shading, the GPU needs to perform a hit test on each vertex to determine whether each vertex needs to start a vertex processing program for processing or use the previous processing result.

[0003] In the related art, hit testing requires taking a complete primitive as the basic unit and performing hit testing on all vertices in the primitive at the same time to ensure that when the primitives are subsequently assembled, the vertex shading results of the assembled primitives can be output simultaneously by the GPU.

[0004] This method is not conducive to the separation of various stages in the rendering process, and it is easy to cause dependencies between various stages such as primitive assembly, hit testing and vertex shading mentioned above. Summary of the invention

[0005] The present application provides a geometry processing pipeline, a graphics processing core, a processor, and a vertex cache method, and the technical solution is as follows:

[0006] According to one aspect of the present application, a geometry processing pipeline is provided, the geometry processing pipeline comprising: a vertex cache unit having a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit;

[0007] The vertex cache unit and the primitive pipeline unit are used to receive a plurality of vertex indexes arranged in order, the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond to the plurality of vertices one by one;

[0008] The vertex cache unit is used to add the vertex index of the first vertex that is not hit in the vertex index cache among the multiple vertex indexes to the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and send a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit;

[0009] The vertex storage is used to store the vertex processing result of the first vertex based on the pipeline index;

[0010] The primitive pipeline unit is used to perform primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on the split initial state information, the multiple vertex indexes and the mapping relationship, and the split initial state information is used to indicate the splitting method of splitting the multiple vertices into at least one primitive.

[0011] According to one aspect of the present application, a graphics processing core is provided, the graphics processing core comprising: a geometry processing pipeline, the geometry processing pipeline being the above-mentioned geometry processing pipeline.

[0012] According to one aspect of the present application, a graphics processor is provided, the graphics processor comprising: N graphics processing cores, a system configuration unit, a system bus and a storage unit, where N is a positive integer;

[0013] The N graphics processing cores are respectively connected to the system bus, and the system bus is connected to the storage unit;

[0014] The system configuration unit is respectively connected to each of the N graphics processing cores;

[0015] Each of the graphics processing cores includes the geometry processing pipeline.

[0016] According to one aspect of the present application, a vertex caching method is provided, the method being performed by the above-mentioned geometry processing pipeline, the geometry processing pipeline comprising: a vertex cache unit having a vertex index cache, a vertex processing pipeline, a vertex storage, and a primitive pipeline unit;

[0017] The method comprises:

[0018] The vertex cache unit and the primitive pipeline unit receive a plurality of vertex indexes arranged in order, the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond one-to-one to the plurality of vertices;

[0019] The vertex cache unit adds the vertex index of the first vertex among the multiple vertex indices that is not hit in the vertex index cache to the vertex index cache; generates a vertex shader task to which the first vertex belongs; generates a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and sends a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit;

[0020] The vertex storage stores a vertex processing result of the first vertex based on the pipeline index;

[0021] The primitive pipeline unit performs primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on split initial state information, the multiple vertex indexes and the mapping relationship, and the split initial state information is used to indicate a splitting method for splitting the multiple vertices into at least one primitive.

[0022] The beneficial effects of the technical solution provided by this application include at least:

[0023] The processing of vertices is realized without the need for primitive assembly, and the hit test of vertex granularity is realized. Specifically, by generating a pipeline index used inside a geometry pipeline by the vertex cache unit, the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shading program, which makes it unnecessary for the vertex shading program to confirm the primitive where the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, so that the geometry processing pipeline shown in the embodiment of the present application can be applied to processors with distributed structures. Moreover, the geometry processing pipeline provided in the embodiment of the present application improves the processing efficiency of the geometry processing pipeline compared to the geometry processing pipeline with primitives as the hit test granularity in the related art. That is, it is realized that the vertex cache unit can perform hit testing without obtaining primitive assembly information, so that hit testing and vertex shading can be performed in parallel, thereby improving the processing performance of the geometry processing pipeline. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a geometric pipeline provided by an exemplary embodiment of the present application is shown;

[0026] Figure 2 A schematic diagram of a vertex cache unit provided by an exemplary embodiment of the present application is shown;

[0027] Figure 3 A schematic diagram of a processing flow of a hit test control subunit provided by an exemplary embodiment of the present application is shown;

[0028] Figure 4A schematic diagram of a processing flow of a vertex pipeline unit provided by an exemplary embodiment of the present application is shown;

[0029] Figure 5 A schematic diagram showing a processing process of a geometry processing pipeline provided by an exemplary embodiment of the present application is shown;

[0030] Figure 6 A schematic diagram showing a processing process of a geometry processing pipeline provided by an exemplary embodiment of the present application is shown;

[0031] Figure 7 A schematic diagram showing a processing process of a geometry processing pipeline provided by an exemplary embodiment of the present application is shown;

[0032] Figure 8 A schematic diagram of a geometry processing pipeline provided by an exemplary embodiment of the present application is shown;

[0033] Fig. 9 A schematic diagram showing a processing process of a geometry processing pipeline provided by an exemplary embodiment of the present application is shown;

[0034] Fig.10 A schematic diagram of an image processing core provided by an exemplary embodiment of the present application is shown;

[0035] Fig.11 A schematic diagram of an image processor provided by an exemplary embodiment of the present application is shown;

[0036] Fig.12 A flowchart of a vertex cache method provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0039] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0040] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the information such as setting operations involved in this application is obtained with full authorization.

[0041] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0042] First, the relevant terms involved in this application are introduced:

[0043] The rendering pipeline of the GPU (Graphics Processing Unit) is a key concept in computer graphics. It is a stage in the GPU that is responsible for processing and converting graphics data for rendering.

[0044] The main task of the rendering pipeline is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. It consists of multiple stages, each of which performs specific geometric calculations and transformations.

[0045] The following are typical geometry pipeline stages:

[0046] (1) Vertex Input: This stage passes vertex data from the application to the geometry pipeline. Vertex data includes attributes such as position, color, and normal.

[0047] (2) Vertex Shader: At this stage, the vertex shader calculates each input vertex and can perform various transformations and operations, such as model transformation, view transformation, projection transformation, etc. It can also calculate the lighting and texture coordinates of the vertex.

[0048] (3) Primitive Assembly: In this stage, the primitive assembler converts vertices into complete geometric primitives, such as points, line segments, triangles, etc.

[0049] (4) Geometry Shader: In the geometry shading stage, the geometry shader can operate and generate geometric primitives. It can create new primitives and change the shape, size, position, etc. of the primitives.

[0050] (5) Clipping: In this stage, the clipper compares the primitives with the screen boundaries and discards the parts outside the viewing volume.

[0051] (6) Screen Mapping: This stage maps the cropped primitives to pixel coordinates in screen space.

[0052] (7) Rasterization: The rasterization stage converts geometric primitives into pixels on the screen and determines the position, color and other attributes of each pixel.

[0053] (8) Fragment Shader: In the fragment shading stage, the fragment shader performs calculations on each rasterized pixel. It can perform pixel-level lighting calculations, texture sampling, depth testing, and other operations.

[0054] (9) Pixel Operations: The last stage is pixel operations, which performs final pixel processing such as blending, dithering, anti-aliasing, etc.

[0055] The goal of the rendering pipeline is to process geometry and generate the final image in an efficient manner. Through parallel processing and specialized hardware support, the GPU is able to perform these calculations quickly to achieve real-time graphics rendering.

[0056] The rendering pipeline can generally be divided into two parts: the geometry processing part (i.e., the geometry pipeline) and the pixel processing part (also called the fragment pipeline). The geometry processing part includes vertex input, vertex shading, primitive assembly, set shading, clipping, and screen mapping. The geometry pipeline mainly focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and converts them into pixels on the screen after a series of stages. The geometry pipeline is responsible for performing geometric calculations such as model transformation, view transformation, projection transformation, as well as generating new geometric primitives and changing the shape, size, position, etc. of the primitives.

[0057] The pixel processing part generally includes rasterization, fragment shading and pixel operation parts. The fragment pipeline focuses on pixel-level processing. It receives the pixels on the screen generated by the rasterization stage and processes each pixel through a series of stages. The main stages include fragment shading, depth testing, template testing, transparency blending, etc. The fragment pipeline is responsible for performing pixel-level lighting calculations, texture sampling, depth testing and other operations to determine the final color and attributes of each pixel.

[0058] These two pipelines are consecutive stages in the rendering pipeline, which are interdependent and work closely together to ultimately generate a visual image. The geometry pipeline converts geometric data into pixel data, while the fragment pipeline performs the final processing and calculations for each pixel. Through parallel processing and specialized hardware support, the GPU is able to efficiently execute these pipeline stages to achieve real-time graphics rendering.

[0059] Vertex Cache: A cache used in a graphics processing unit (GPU) to store processed vertex data. In GPU geometry processing, vertex cache is generally required to reduce the number of vertices that the GPU needs to process. In graphics rendering, vertices are the basic components of a three-dimensional model, and each vertex contains information such as position, normal, and texture coordinates. During the rendering process, the vertices of the model need to be used multiple times, and the vertex cache is used to temporarily store these vertex data.

[0060] The role of the vertex cache is to reduce the repeated calculation of vertex data during the rendering process. When a vertex is processed, its result will be stored in the vertex cache. The next time the vertex is needed, it can be directly read from the cache without recalculation. This can improve rendering efficiency, especially when processing large 3D models, it can significantly reduce the amount of calculation required for rendering and improve rendering performance.

[0061] Vertex buffers are usually implemented by the GPU's internal hardware. After the vertex is input and before vertex shading begins, the GPU needs to perform a hit test on the input vertex. If the input vertex hits a vertex in the cache, the GPU does not need to start the vertex shading program for the newly input vertex, but uses the processing result of the previously existing vertex. If the input vertex does not hit any vertex in the cache, the GPU needs to start the vertex shading program for the newly input vertex, and the GPU also inserts the vertex into the vertex cache for subsequent vertices to hit test. Vertex hit testing is generally not performed on a single vertex, but on a complete primitive as the basic unit. All vertices in this primitive are hit tested at the same time to ensure that when the primitives are assembled later, the vertex shading results of the assembled primitives can be output by the GPU at the same time.

[0062] Wave / warp: A group of continuous threads in the process of shading program processing. In GPU programming, "wave" / "warp" is a common concept in GPU architecture. The embodiment of the present application uses wave as an example. Wave represents a group of continuous threads in the process of shading program processing, and these threads can execute the same instructions together. Waves usually also contain a certain number of threads, but this number may vary depending on the GPU architecture. Different GPU architectures can use the SIMD (Single Instruction Multiple Data) execution model, in which the threads in a wave execute the same instruction, but the data operated on may be different, or they can use the "SIMT (Single Instruction Multiple Threads)" execution model. Waves are very important for optimizing GPU program performance. Maximizing the parallel execution capabilities of warps can improve program efficiency.

[0063] Figure 1 A schematic diagram of a geometry pipeline provided by an exemplary embodiment of the present application is shown. The geometry processing pipeline 100 includes: a vertex cache unit 110 having a vertex index cache, a vertex processing pipeline 120, a vertex storage 130 and a primitive pipeline unit 140;

[0064] Optionally, the vertex cache unit 110 and the primitive pipeline unit 140 are used to receive a plurality of vertex indexes arranged in order, where the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond one-to-one to the plurality of vertices.

[0065] Optionally, multiple vertex indices arranged in sequence refer to that the multiple vertex indices are arranged according to the arrangement order of the multiple vertices in the primitive, such as the vertex indices corresponding to the multiple vertices in each primitive are continuous, and the vertex indices corresponding to the multiple vertices in each primitive are arranged in clockwise order or counterclockwise order according to the multiple vertices in the primitive.

[0066] Optionally, the vertex cache unit 110 is used to add the vertex index of the first vertex among multiple vertex indexes that is not hit in the vertex index cache to the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index for the first vertex, and the pipeline index is used to identify the first vertex in the geometry processing pipeline 100; send the vertex shader task and the pipeline index to which the first vertex belongs to the vertex processing pipeline 120 to perform vertex processing; and send the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit 140.

[0067] Optionally, a hit in the vertex cache means that the vertex index of the vertex has been stored in the vertex index cache; a miss in the vertex cache means that the vertex index of the vertex does not exist in the vertex index cache.

[0068] Optionally, a vertex shader task includes the vertices processed each time a vertex shader is started. That is, in order to improve hardware performance and efficiency, the vertex shader is not started immediately for each vertex input. Instead, the vertex shader is started for these vertices after a certain number of vertices are collected. Such a batch of started vertices is a vertex shader task (referred to as a shader task).

[0069] Optionally, the pipeline index is used to identify the first vertex in the geometry processing pipeline 100 . In other words, the pipeline index is used to identify the first vertex in the vertex storage 130 .

[0070] Optionally, the vertex storage 130 is used to store the vertex processing result of the first vertex based on the pipeline index.

[0071] Exemplarily, the vertex processing result of the first vertex refers to the vertex processing result of the first vertex after the vertex is processed by the vertex shading program, or the calculation result of the vertex shading program on the first vertex. The vertex shading program is used to calculate the first vertex, such as calculating the lighting and texture coordinates of the first vertex.

[0072] Optionally, the primitive pipeline unit 140 is used to perform primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on split initial state information, multiple vertex indexes and mapping relationships, and the split initial state information is used to indicate a splitting method for splitting multiple vertices into at least one primitive.

[0073] Optionally, primitive assembly refers to determining each vertex belonging to the first primitive from a plurality of vertices; or, primitive assembly refers to determining each vertex index belonging to the first primitive from a plurality of vertex indexes; or, primitive assembly refers to determining each vertex belonging to the first primitive from a plurality of vertices, and assembling each vertex into the first primitive; or, primitive assembly refers to determining each vertex index belonging to the first primitive from a plurality of vertex indexes, and assembling each vertex index to obtain the first primitive. Each vertex includes the first vertex; each vertex index includes the vertex index of the first vertex.

[0074] Optionally, primitive processing refers to performing primitive-related processing on the first primitive. Primitive processing includes but is not limited to: rasterization; primitive shading; surface tessellation. Surface tessellation is a method of further dividing a primitive to obtain a smooth surface.

[0075] Optionally, the split initial state information is used to indicate a splitting method for splitting multiple vertices into at least one primitive; or, the split initial state information is used to indicate a vertex among multiple vertices that needs to be assembled into primitives; or, the split initial state information is used to indicate a vertex among multiple vertices that needs to be processed by the primitive pipeline unit 140; or, the split initial state information is used to indicate a splitting method for processing multiple vertices by the primitive pipeline unit 140. Splitting methods include, but are not limited to: vertices to be processed; the number of vertices included in each primitive; primitive type; and the ordering method of vertices corresponding to the primitive among multiple vertices.

[0076] Exemplarily, if the vertices to be processed are, for example, 16 vertices, the split initial state information is used to indicate that the vertices to be processed are the second to the fifteenth vertices among the multiple vertices. If the number of vertices included in each primitive is a triangle, the number of vertices included in each primitive is 3. The primitive type is used to indicate the shape of the primitive or the arrangement of multiple primitives, such as indicating that the shape of the primitive is a triangle, a quadrilateral, indicating the arrangement of multiple primitives such as a line strip, a triangle strip, and so on. A line strip is that except for the first vertex, each vertex will form a line segment primitive with the previous vertex, and all line segment primitives form a continuous strip structure in space. A triangle strip means that except for the first triangle primitive, each new vertex will form a triangle primitive together with the first two vertices, and all triangle primitives form a continuous strip structure in space. The ordering of the vertices corresponding to the primitive among multiple vertices, such as whether each vertex is arranged in clockwise order, or arranged in counterclockwise order, and so on.

[0077] Optionally, the primitive pipeline unit 140 performs primitive assembly based on the split initial state information and multiple vertex indices to determine the first primitive to which the first vertex belongs; obtains the vertex processing result of the first vertex from the vertex storage 130 based on the mapping relationship; and performs primitive processing based on the vertex processing result of the first vertex to obtain the first primitive to which the first vertex belongs. Alternatively, the primitive pipeline unit 140 performs primitive assembly based on the split initial state information and multiple vertex indices to determine the first primitive to which the first vertex belongs, and the first primitive includes multiple vertices; obtains the vertex processing result of each vertex in the multiple vertices from the vertex storage 130 based on the mapping relationship between the vertex indices of the multiple vertices and the pipeline index; and performs primitive processing based on the vertex processing results of each vertex to obtain the first primitive to which the first vertex belongs.

[0078] In summary, the geometry processing pipeline provided in the embodiment of the present application realizes the processing of vertices without the need for primitive assembly, and realizes the hit test of vertex granularity. Specifically, by generating a pipeline index used inside the geometry pipeline by the vertex cache unit, the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shading program, which makes it unnecessary for the vertex shading program to confirm the primitive where the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, so that the geometry processing pipeline shown in the embodiment of the present application can be applied to processors with distributed structures. And the geometry processing pipeline provided in the embodiment of the present application improves the processing efficiency of the geometry processing pipeline compared to the geometry processing pipeline with primitives as the hit test granularity in the related art. That is, it is realized that the vertex cache unit can perform hit testing without obtaining primitive assembly information, so that hit testing and vertex shading can be performed in parallel, improving the processing performance of the geometry processing pipeline.

[0079] Next, the generation method of the pipeline index is shown.

[0080] Optionally, the vertex cache unit 110 is used to generate a pipeline index based on a shader identifier and a vertex cache index corresponding to the first vertex; wherein the shader identifier is used to identify the vertex shader task to which the first vertex belongs; and the vertex cache index is used to identify the cache position of the first vertex in the vertex index cache.

[0081] Optionally, the pipeline index is obtained by splicing the shader identifier and the vertex cache index; or, the pipeline index is a shader identifier and a vertex cache index combined in an agreed format. For example, the shader identifier of the first vertex is 1, and the vertex cache index of the first vertex is 5; if the pipeline index is obtained by splicing the shader identifier and the vertex cache index, the pipeline index of the first vertex is 15. In this scheme, the number of bits of the vertex cache index is fixed. For example, the number of bits of the vertex cache index shown above is 1 bit. If the number of bits of the vertex cache index is 2 bits, the pipeline index of the first vertex can be 105, that is, the pipeline index of the first vertex is considered to be 05; similarly, the number of bits of the shader identifier can also be fixed or not. Or, if the pipeline index is a shader identifier and a vertex cache index combined in an agreed format, such as the agreed format is "shader identifier-vertex cache index", if the shader identifier of the first vertex is 1, and the vertex cache index of the first vertex is 5, then the pipeline index of the first vertex is 1-5.

[0082] In other embodiments, the pipeline identifier of the first vertex may also be a unique identifier generated by the vertex cache unit, such as using the current timestamp as the pipeline identifier of the first vertex, or, if the first vertex is the i-th vertex processed by the vertex cache unit, setting the pipeline identifier of the first vertex to i; or, the pipeline identifier of the first vertex may also be an identifier generated by the vertex cache unit based on the storage position of the first vertex in the vertex index cache.

[0083] In summary, the geometry processing pipeline provided by the embodiment of the present application obtains the pipeline identifier through the shader identifier and the vertex cache index, that is, using an identifier inside the geometry processing pipeline instead of the vertex index, which can reduce the geometry processing pipeline's dependence on external information, making the geometry processing pipeline more independent, and reducing the coupling between the geometry processing pipeline and other modules. In addition, by identifying with the shader identifier and the vertex cache index, the geometry processing pipeline can also directly determine the vertex shader task corresponding to the vertex processing based on the identifier, which can achieve fast query in the vertex storage compared to directly generating a unique identifier.

[0084] Next, the specific structure of the vertex cache unit 110 is shown, as shown in FIG. Figure 2 shown.

[0085] In addition to the above-mentioned vertex index cache 111, the vertex cache unit 110 also includes: a hit test control subunit 112, a shader task assembly subunit 113 and a shader task mapping subunit 114;

[0086] Optionally, the hit test control subunit 112 is used to perform a vertex hit test on each vertex index in multiple vertex indexes; add the vertex index of the first vertex in the multiple vertex indexes that has not hit the vertex index cache 111 to the vertex index cache 111; generate a vertex shader task to which the first vertex belongs; generate a pipeline index for the first vertex; and send the pipeline index for the first vertex to the shader task assembly unit 113.

[0087] Optionally, the shader task assembly subunit 113 is used to send the vertex shader task and pipeline index to which the first vertex belongs to the vertex processing pipeline 120 to perform vertex processing;

[0088] Optionally, the hit test control subunit 112 sends the pipeline index of the first vertex to the shader task assembly unit 113, and the shader task assembly subunit 113 sends the vertex shader task and the pipeline index to which the first vertex belongs to the vertex processing pipeline 120 to perform vertex processing.

[0089] Optionally, the vertex shader task to which the first vertex belongs includes a vertex index of the first vertex, and the vertex processing pipeline 120 reads the vertex data of the first vertex from the storage unit based on the vertex index included in the vertex shader task to perform vertex processing, and the vertex data includes at least one of the following: the three-dimensional coordinates of the vertex, the normal vector of the vertex, the texture coordinates, and the vertex tangent. Or, the hit test control subunit 112 also sends the mapping relationship to the shader task assembly subunit 113, and the shader task assembly subunit 113 sends the mapping relationship to the vertex processing pipeline 120, and the vertex processing pipeline 120 obtains the vertex index based on the mapping relationship and the pipeline index, and reads the vertex data of the first vertex from the storage unit based on the vertex index. Or, the hit test control subunit 112 also sends the vertex index of the first vertex to the shader task assembly subunit 113, and the shader task assembly subunit 113 sends the vertex index to the vertex processing pipeline 120, and the vertex processing pipeline 120 reads the vertex data of the first vertex from the storage unit based on the vertex index.

[0090] Optionally, the shader task mapping subunit 114 is used to send the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit 140 .

[0091] Optionally, the vertex cache unit 110 receives a plurality of vertex indexes and sends them to the hit test control subunit 112. The hit test control subunit 112 performs a vertex hit test on each vertex index in the plurality of vertex indexes in turn, and compares it with the vertex index cached in the vertex index cache 111. If it hits (i.e., the vertex index in the vertex index cache 111 includes the vertex index to be tested), then the next vertex is tested. If it misses, the hit test control subunit 112 adds the vertex to the vertex index cache 111, and sends the vertex to the shader task assembly subunit 113, so as to prepare to start the corresponding vertex shader task. In addition, for the vertex that misses, after being added to the vertex index cache 111, the hit test control subunit 112 also needs to generate a pipeline index for the newly inserted vertex and determine the mapping relationship between the vertex index and the pipeline index of the vertex, and then send the mapping relationship to the shader task mapping subunit 114, and the shader task mapping subunit 114 saves the mapping relationship.

[0092] Optionally, the shader task assembly subunit 113 receives and saves the pipeline index sent by the hit test control subunit 112. When the number of vertices saved in the shader task assembly subunit 113 reaches the task requirement number (i.e., the number of waves / warps) for starting the vertex shader task, the pipeline indexes of the vertices belonging to the vertex shader task are sent to the vertex processing pipeline 120, and the vertex processing pipeline 120 executes the corresponding vertex shading program for these vertices.

[0093] Optionally, the shader task mapping subunit 114 saves the mapping relationship of each missed vertex, and these mapping relationships will be sent by the shader task mapping subunit 114 to the primitive pipeline unit 140 for the primitive pipeline unit 140 to perform primitive assembly.

[0094] In addition to performing a hit test on the vertices, the hit test control subunit 112 also needs to send control information to force the shader task assembly subunit 113 to start.

[0095] In summary, the geometry processing pipeline provided by the embodiment of the present application shows the specific structure of the vertex cache unit. In addition to the vertex index cache, the vertex cache unit also includes a shader task assembly subunit for sending vertex shader tasks and a shader task mapping subunit for storing the mapping relationship between vertex indices and pipeline identifiers, as well as a hit test control subunit for performing hit tests. The clear division of different functions of the vertex cache unit is conducive to improving the maintainability and scalability of the vertex cache unit.

[0096] There are the following three situations when the vertex shader task to which the first vertex belongs is started by the vertex cache unit 110 .

[0097] Case 1: The number of vertices reaches the trigger threshold.

[0098] Case 2: The vertex index buffer is full.

[0099] Case 3: There are no unprocessed vertices.

[0100] Next, we will introduce three scenarios of shader task startup in turn. It should be noted that the order of introduction does not represent the advantages or disadvantages of the shader task startup method.

[0101] Case 1: The number of vertices reaches the trigger threshold.

[0102] In some embodiments, the vertex cache unit 110 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertices to the vertex processing pipeline 120 to perform vertex processing based on the unsent vertices when the number of unsent vertices reaches a trigger threshold; wherein the unsent vertices include the first vertex.

[0103] Optionally, the trigger threshold is pre-set.

[0104] Exemplarily, the trigger threshold is less than the number of vertices that can be stored in the vertex index cache 111. The above can be understood as sending the vertex shader task to which the first vertex belongs based on the unsent vertices when the number of unsent vertices reaches the trigger threshold. The vertex shader task is used to indicate that the unsent vertices are vertices that need to perform vertex processing.

[0105] Exemplarily, the trigger threshold is equal to the number of vertices that can be stored in the vertex index cache 111. This is similar to the second scenario and will not be described in detail here.

[0106] Exemplarily, if the trigger threshold is greater than the number of vertices that can be stored in the vertex index cache 111, then when the vertex index cache 111 is full but the number of vertices that have not been sent does not reach the trigger threshold, the vertex index cache 111 is cleared, and the vertex cache index in the pipeline index at this time can be cumulative; for example, if the number of vertices that can be stored in the vertex index cache 111 is 8, and the trigger threshold is 16, then when the vertex index cache 111 is full for the first time, that is, 8 vertices are stored in the vertex index cache and their corresponding vertex cache indexes are 0-7, the vertex index cache 111 is cleared, but when generating pipeline identifiers for subsequent vertices, the corresponding vertex cache indexes are numbered starting from 8, that is, the vertex index cache 111 is cleared but the accumulator corresponding to the vertex cache index is not initialized; or, different shader identifiers are set for vertices in the vertex index cache 111 belonging to different batches, that is, a vertex shader task includes multiple shader identifiers.

[0107] Optionally, when the vertex cache unit 110 includes a vertex index cache 111, a hit test control subunit 112, a shader task assembly subunit 113 and a shader task mapping subunit 114, the shader task assembly subunit 113 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertices when the number of unsent vertices reaches a trigger threshold; wherein the unsent vertices include the first vertex.

[0108] In summary, the geometry processing pipeline provided by the embodiment supports expanding the hit detection range of new vertices when the trigger threshold is less than the number of vertices that can be stored in the vertex index cache, thereby searching for duplicate vertices in a larger range, reducing the number of duplicate vertex shading, and reducing the number of repeated processing times of the vertex shading program, indirectly improving the processing efficiency of the geometry processing pipeline, improving shading performance, and reducing the power consumption of the geometry processing pipeline. When the trigger threshold is greater than the number of vertices that can be stored in the vertex index cache 111, the decoupling of primitive assembly and vertex processing can also be achieved, thereby reducing the hardware requirements for the vertex index cache.

[0109] Case 2: The vertex index buffer is full.

[0110] In some embodiments, the vertex cache unit 110 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline 120 to perform vertex processing based on the unsent vertices when the vertex index cache 111 is full; wherein the unsent vertices include the first vertex.

[0111] Optionally, one vertex shader task corresponds to a batch of vertices in the vertex index buffer 111 .

[0112] Exemplarily, when the vertex index cache 111 is full, it is determined that the currently unsent vertex sends a vertex shader task, and the vertex shader task is the vertex shader task to which the first vertex belongs. After the vertex shader task is formed, the vertex shader task and the pipeline index corresponding to the vertex in the vertex shader task are sent to the vertex processing pipeline 120 to perform vertex processing.

[0113] Optionally, the method can also be designed based on the above situation 1, that is, when the number of unsent vertices reaches the trigger threshold, the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex are sent to the vertex processing pipeline to perform vertex processing based on the unsent vertices, and the preset threshold at this time is equal to the number of vertices that can be stored in the vertex index cache 111. It is also possible to make a judgment based on the vertex index cache instead of the number of unsent vertices.

[0114] Optionally, when the vertex cache unit 110 includes a vertex index cache 111, a hit test control subunit 112, a shader task assembly subunit 113, and a shader task mapping subunit 114, the shader task assembly subunit 113 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline for vertex processing based on the unsent vertices when the number of unsent vertices reaches the number of vertices that can be stored in the vertex index cache 111, wherein the unsent vertices include the first vertex. Or, when the vertex index cache 111 is full, send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline for vertex processing based on the unsent vertices.

[0115] In summary, the geometry processing pipeline provided by the embodiment of the present application sends the vertex shader task when the vertex index cache is full, thereby improving the space utilization rate of the vertex index cache. Since the vertex shader task is sent when the vertex index cache is full, compared with sending the vertex shader task when the vertex index cache is not full, the number of vertices processed by a vertex shader task is greater, thereby ensuring that more vertices can be detected, and when there are multiple repeated vertices close to each other, the probability of repeated processing of vertices can be reduced, thereby improving the effectiveness of vertex processing.

[0116] Case 3: There are no unprocessed vertices.

[0117] In some embodiments, the vertex cache unit 110 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertices when there are no unprocessed remaining vertices among multiple vertices; wherein the unsent vertices include the first vertex.

[0118] Exemplarily, when there are no unprocessed remaining vertices among the multiple vertices, it is determined that the vertices that are not currently sent form a vertex shader task, and the vertex shader task is the vertex shader task to which the first vertex belongs. After the vertex shader task is formed, the vertex shader task and the pipeline index corresponding to the vertex in the vertex shader task are sent to the vertex processing pipeline 120 to perform vertex processing.

[0119] Optionally, when the vertex cache unit 110 includes a vertex index cache 111, a hit test control subunit 112, a shader task assembly subunit 113 and a shader task mapping subunit 114, the shader task assembly subunit 113 is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform vertex processing based on the unsent vertices when there are no remaining unprocessed vertices among multiple vertices; wherein the unsent vertices include the first vertex.

[0120] To sum up, the geometry processing pipeline provided in the embodiment of the present application directly sends the vertex shader task instead of waiting for the next batch of vertices when multiple vertices have been processed. This can avoid the geometry processing pipeline being in a standby state due to waiting for the next batch of vertices, release the geometry processing pipeline as soon as possible, so that the GPU can assign tasks to the idle geometry processing pipeline again, thereby improving the operating efficiency of the geometry processing pipeline.

[0121] It should be noted that the above-mentioned scenarios 1, 2 and 3 can be implemented independently or in combination. For example, scenarios 1 and 3 can be implemented in combination. When there are unprocessed remaining vertices among multiple vertices, scenario 1 is executed; when there are no unprocessed remaining vertices among multiple vertices, scenario 3 is executed. Situation 2 and 3 can be implemented in combination. When there are unprocessed remaining vertices among multiple vertices, scenario 1 is executed; when there are no unprocessed remaining vertices among multiple vertices, scenario 3 is executed. Situation 1 and 2 can be implemented in combination. Regarding the quantitative relationship between the number of vertices for forming a vertex shader task and the number of vertices that can be stored in the vertex index cache, scenario 2 is executed when the number of vertices for forming a vertex shader task is equal to the number of vertices that can be stored in the vertex index cache; scenario 1 is executed when the number of vertices for forming a vertex shader task is not equal to the number of vertices that can be stored in the vertex index cache. Case 1, Case 2 and Case 3 can be implemented in combination. When there are unprocessed remaining vertices among multiple vertices, and the number of vertices that form the vertex shader task is not equal to the number of vertices that can be stored in the vertex index cache, Case 1 is executed; when there are unprocessed remaining vertices among multiple vertices, and the number of vertices that form the vertex shader task is equal to the number of vertices that can be stored in the vertex index cache, Case 2 is executed; when there are no unprocessed remaining vertices among multiple vertices, Case 3 is executed.

[0122] In addition, the above only shows the situation when the vertex index of the first vertex does not hit in the vertex index cache. When the vertex index of the first vertex hits in the vertex index cache, in some embodiments, the vertex cache unit 110 is used to ignore the second vertex among multiple vertices that hits in the vertex index cache.

[0123] Here, a hit means that the vertex index of the vertex exists in the vertex index cache 111 .

[0124] Optionally, when the vertex index of the second vertex hits, the processing of the second vertex is ignored, that is, the pipeline index is not generated for the second vertex; the vertex processing is not performed on the second vertex, that is, the vertex index of the second vertex is not sent to the vertex processing pipeline 120; and the mapping relationship between the vertex index of the second vertex and the pipeline index is not sent to the primitive pipeline unit 140. In this way, unnecessary calculations are avoided, the power consumption of the geometry processing pipeline is reduced, and the processing efficiency of the geometry processing pipeline is improved.

[0125] For example, taking the second scenario as an example, the process of the hit control subunit 112 performing the hit test is further described. Figure 3 shown.

[0126] Step 1, initialize the shader identifier and vertex buffer index.

[0127] The hit test control subunit 112 needs to initialize data, including a shader identifier and a vertex buffer index, for example, the shader identifier is initialized to 0, and the vertex buffer index is initialized to 0.

[0128] Step 2: Receive vertex index.

[0129] The hit test control subunit 112 receives multiple vertex indexes, and obtains a vertex index that currently needs to be processed from the multiple vertex indexes.

[0130] Step 3, hit test.

[0131] The hit test control subunit 112 performs a hit test on the acquired vertex index to obtain a hit test result of the vertex corresponding to the vertex index.

[0132] Step 4, determine whether it is a hit.

[0133] The hit test control subunit 112 determines whether a hit occurs.

[0134] If the hit test result of the vertex is a hit, it means that the vertex index of this vertex already exists in the vertex shader task to be sent / sent, and there is no need to send the vertex shader task again for this vertex. At this time, you can start processing the next vertex, that is, jump to step 12.

[0135] If the hit test result of the vertex is a miss, it means that the vertex index of this vertex does not exist in the vertex shader task to be sent / sent, but it is also possible that it has been processed, but due to the limited storage range of the vertex index cache 111, it cannot provide more information, resulting in a miss. However, a miss means that it is necessary to process this vertex or the vertex index corresponding to this vertex, that is, execute step 5 sequentially.

[0136] Step 5: Test whether the vertex index cache can accommodate the new vertex index.

[0137] The hit test control subunit 112 needs to check whether the vertex index cache 111 has enough space to store the missed vertex index.

[0138] Step 6: Determine whether the vertex index cache is full.

[0139] The hit test control subunit 112 determines whether the vertex index buffer 111 is full.

[0140] If the vertex index cache 111 does not have enough space to store, that is, the vertex index cache is full, then the hit test control subunit 112 needs to send control information to drive the downstream shader task assembly subunit 113 to send the previously accumulated vertices to the vertex shading program and officially start the vertex shader task, that is, execute step 7 sequentially.

[0141] If the vertex index cache 111 is not full, the hit vertex index is saved in the vertex index cache 111 , and the process jumps to step 10 .

[0142] Step 7: Send the buffer content to the vertex processing pipeline to execute the vertex shader task.

[0143] The cache content refers to the unsent vertices stored in the vertex index cache 111. The vertex index cache 111 caches vertices or vertex indices of each vertex, but each vertex index corresponds to a vertex cache index in the vertex index cache 111. The hit test control subunit 112 stores the shader identifier, and the hit test control subunit 112 is responsible for the generation and accumulation of the shader identifier.

[0144] The hit test control subunit 112 sends control information to the shader task assembly subunit 113, and the control information is used to instruct the shader task assembly subunit to send the pipeline indexes of the stored multiple vertices to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shading program to perform the vertex shader task. Or, the control information is used to instruct the shader task assembly subunit 113 to send the pipeline indexes and mapping relationships of the stored multiple vertices to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shading program to perform the vertex shading task. Or, the control information is used to instruct the shader task assembly subunit 113 to send the pipeline indexes of the stored multiple vertices and the multiple vertex indexes to the vertex processing pipeline 120, so that the vertex processing pipeline 120 starts the vertex shading program to perform the vertex shading task.

[0145] Optionally, what is stored in the shader task assembly subunit 113 are the pipeline indexes of each vertex, and the control information is only used to instruct the shader task assembly subunit 113 to send the pipeline index of each vertex to the vertex processing pipeline 120; or, what is stored in the shader task assembly subunit 113 are the pipeline indexes of each vertex, and the control information, in addition to instructing the shader task assembly subunit 113 to send the pipeline index of each vertex to the vertex processing pipeline 120, also includes a shader identifier, and the shader identifier is used for the shader task assembly subunit 113 to generate the pipeline index of each vertex based on the vertex cache index and the shader identifier of each vertex.

[0146] Step 8, accumulate shader flags.

[0147] While sending the control information, that is, while sending the buffer content to the vertex processing pipeline 120, the hit test control subunit 112 accumulates the shader identifier, that is, starts the next vertex shader task.

[0148] In some embodiments, the above steps 7 and 8 may be performed in an interchangeable order or simultaneously.

[0149] Step 9: Mark the cached content as invalid.

[0150] Since the vertices in the vertex index cache 111 have been sent at this time, the vertex indexes cached in the vertex index cache 111 can be safely cleared, such as the hit test control subunit 112 directly marking all the contents in the vertex index cache 111 as invalid.

[0151] Step 10: Add the vertex index to the vertex index cache to generate a vertex cache index.

[0152] If the vertex index cache 111 has enough space to store the missed vertex index, the hit test control subunit 112 adds the missed vertex index to the vertex index cache 111 and generates a vertex cache index corresponding to the vertex index based on the position of the vertex index in the vertex index cache 111.

[0153] Step 11, fill in the shader identifier and vertex cache index and the current vertex index into the mapping table.

[0154] The hit test control subunit 112 obtains the pipeline identifier according to the shader identifier and the vertex cache index, and saves the pipeline identifier and the currently processed vertex index into a mapping table. The mapping table is used to indicate the mapping relationship between the pipeline identifiers and vertex indices of multiple vertices. Among them, the mapping table is located in the shader task mapping subunit 114, that is, the hit test control subunit 112 sends the mapping relationship between the shader identifier and the vertex cache index (or the pipeline index) and the vertex index, that is, the pipeline index and the vertex index to the shader task mapping subunit 114, and the shader task mapping subunit 114 is responsible for saving and sending the mapping relationship to the primitive pipeline unit 140.

[0155] Step 12, determine whether there is a new vertex.

[0156] That is, the hit test control subunit 112 determines whether all of the multiple vertices have been processed. If there is no new vertex, that is, there is no unprocessed vertex among the multiple vertices, step 13 is executed sequentially.

[0157] If there is a new vertex, that is, there is an unprocessed vertex among the multiple vertices, then continue to obtain an unprocessed vertex to continue vertex processing, that is, jump to execute step 2.

[0158] Step 13, sending the cache content to the shader to perform the shading task.

[0159] If there are no more vertices to be processed, the hit test control subunit 112 needs to force the vertex shading program to be started for the vertices that are not full in the vertex index cache 111 to execute the vertex shader task according to the scene flow of processing the full vertex index cache 111, that is, to send control information to the shader task assembly subunit 113.

[0160] Step 14, accumulate shader flags.

[0161] The hit test control subunit 112 accumulates the shader flag, that is, starts the next vertex shader task to prepare for the subsequent input of multiple vertex indexes.

[0162] Step 15: Mark the cached content as invalid.

[0163] Since the vertex indices in the vertex index cache 111 have been sent at this time, the vertex indices cached in the vertex index cache 111 can be safely cleared, such as the hit test control subunit 112 directly marking all the contents in the vertex index cache 111 as invalid.

[0164] Next, the primitive assembly process of the primitive pipeline unit 140 is shown.

[0165] In some embodiments, the primitive pipeline unit 140 includes a primitive assembly pipeline and a primitive processing pipeline;

[0166] Optionally, the primitive assembly pipeline is used to perform primitive assembly based on the split initial state information, multiple vertex indexes and mapping relationships to obtain primitive assembly information of the first primitive to which the first vertex belongs. The primitive processing pipeline is used to perform primitive processing on the first primitive based on the primitive assembly information of the first primitive. Or, the primitive assembly pipeline is used to perform primitive assembly based on the split initial state information and multiple vertex indexes to obtain primitive assembly information of the first primitive to which the first vertex belongs. The primitive processing pipeline is used to perform primitive processing on the first primitive based on the primitive assembly information and mapping relationships of the first primitive.

[0167] Optionally, the primitive assembly information includes at least one of a pipeline index of each vertex of the first primitive, a vertex index of each vertex, and a mapping relationship between the vertex index of each vertex and the pipeline index.

[0168] Optionally, the primitive assembly information of the first primitive includes pipeline indexes of each vertex of the first primitive, and each vertex of the first primitive includes the first vertex. The primitive processing pipeline is used to receive the primitive assembly information sent by the primitive assembly pipeline; obtain the vertex processing results of each vertex from the vertex storage based on the pipeline index of each vertex carried by the primitive assembly information; and perform primitive processing on the first primitive based on the vertex processing results of each vertex.

[0169] Exemplarily, the primitive processing pipeline accesses the vertex storage according to the primitive assembly information sent by the primitive assembly pipeline, obtains the vertex processing results of the vertices indicated in the primitive assembly information, and assembles primitives based on the results. It also supports further primitive processing, including but not limited to rasterization, starting a geometry shader, or starting a tessellation function.

[0170] Optionally, the primitive assembly information of the first primitive includes vertex indexes of each vertex of the first primitive, and each vertex of the first primitive includes the first vertex. The primitive processing pipeline is used to receive the primitive assembly information sent by the primitive assembly pipeline; determine the pipeline index of each vertex based on the mapping relationship and the vertex index of each vertex carried by the primitive assembly information; obtain the vertex processing result of each vertex from the vertex storage based on the pipeline index of each vertex; and perform primitive processing on the first primitive based on the vertex processing result of each vertex.

[0171] Optionally, the mapping relationship is sent by the primitive assembly pipeline to the primitive processing pipeline; or, the mapping relationship is carried in the primitive assembly information and sent by the primitive assembly pipeline to the primitive processing pipeline, that is, the primitive assembly information includes the vertex index and mapping relationship of each vertex of the first primitive; or, the mapping relationship is sent by the vertex cache unit (or the shader task mapping subunit) to the vertex processing pipeline.

[0172] That is, optionally, the shader task mapping subunit is used to send the mapping relationship between the vertex index and the pipeline index to the primitive assembly pipeline or the primitive processing pipeline.

[0173] Optionally, primitive assembly pipeline 141 performs primitive assembly based on the split initial state information, multiple vertex indexes and mapping relationships to obtain primitive assembly information of the first primitive to which the first vertex belongs; determines whether each vertex of the first primitive has completed vertex processing; and when each vertex of the first primitive has completed vertex processing, sends the primitive assembly information to primitive processing pipeline 142, so that primitive processing pipeline 142 performs primitive processing based on the primitive assembly information.

[0174] Optionally, the primitive assembly pipeline 141 performs primitive assembly to obtain primitive assembly information of the first primitive to which the first vertex belongs based on the split initial state information, multiple vertex indexes and mapping relationships; sends the primitive assembly information to the primitive processing pipeline 142; after receiving the primitive assembly information, the primitive processing pipeline 142 determines whether each vertex has completed vertex processing based on the primitive assembly information; when each vertex of the first primitive has completed vertex processing, primitive processing is performed on the first primitive according to the primitive assembly information and the vertex processing results of each vertex.

[0175] Optionally, the method for determining whether each vertex of the first primitive has completed vertex processing may be to query whether the vertex storage 130 includes the vertex processing results of each vertex. In the case where the vertex storage 130 includes the vertex processing results of each vertex, it is determined that each vertex of the first primitive has completed vertex processing; in the case where the vertex storage 130 does not include the vertex processing results of each vertex of the first primitive, it is determined that each vertex of the first primitive has not yet completed vertex processing. Alternatively, the method for determining whether each vertex of the first primitive has completed vertex processing may be to confirm whether the vertex shader task corresponding to each vertex has been executed through the vertex processing pipeline 120. In the case where the vertex processing pipeline 120 indicates that the vertex shader task corresponding to each vertex has been executed, it is determined that each vertex of the first primitive has completed vertex processing; in the case where the vertex processing pipeline 120 indicates that the vertex shader task corresponding to each vertex has not been executed, it is determined that each vertex of the first primitive has not completed vertex processing. Optionally, the vertex processing pipeline 120 sends the shader identifier of the vertex shader task to the primitive processing pipeline 142 each time the vertex processing pipeline 120 completes the execution of a vertex shader task; or, the primitive processing pipeline 142 sends the shader identifier to the vertex processing pipeline 120, and after receiving the shader identifier, the vertex processing pipeline 120 sends an indication message to the primitive processing pipeline 142 to indicate whether the vertex shader task corresponding to the shader identifier has been completed.

[0176] Exemplarily, the primitive assembly information includes the pipeline index of each vertex of the first primitive; the primitive assembly pipeline 141 determines the vertex index of each vertex belonging to the first primitive from multiple vertex indexes based on the split initial state information, such as the first primitive is ABC, that is, the first primitive includes 3 vertices, and the vertex indexes of these 3 vertices are A, B, and C respectively; the primitive assembly pipeline 141 determines the pipeline index of each vertex of the first primitive based on the vertex indexes and mapping relationship of the first primitive, such as the first primitive after mapping is wave0-3, wave1-4, wave0-5, wherein for waveX-Y, waveX represents the shader identifier, X is a positive integer, Y represents the vertex cache index, and waveX-Y can also be understood as the Xth wave (i.e. Vertex shader task 0); then primitive assembly pipeline 141 obtains primitive assembly information based on the pipeline index of each vertex of the first primitive and sends the primitive assembly information to primitive processing pipeline 142; primitive processing pipeline 142 determines the vertex shader task (wave0 and wave1) related to the first primitive according to the pipeline index of each vertex of the first primitive indicated in the primitive assembly information; primitive processing pipeline 142 determines from vertex processing pipeline 120 whether the above two vertex shader tasks are completed; when the above two vertex shader tasks are completed, the vertex processing results of each vertex are read from the vertex storage according to the pipeline index of each vertex, and then primitive processing is performed based on the vertex shading results of each vertex.

[0177] In some embodiments, the split initial state information includes: at least one vertex that needs to be skipped among multiple vertices; a primitive assembly pipeline for skipping the first vertex if the first vertex belongs to at least one vertex that needs to be skipped; and determining the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the arrangement position of the first vertex among multiple vertices, the vertex index, and the mapping relationship if the first vertex does not belong to at least one vertex that needs to be skipped.

[0178] Exemplarily, if the primitive assembly information of the first primitive includes the pipeline index of each vertex of the first primitive; when the first vertex does not belong to at least one vertex that needs to be skipped, the primitive assembly pipeline determines the primitive assembly information of the first primitive to which the first vertex belongs based on the arrangement position of the first vertex among multiple vertices, multiple vertex indexes, and mapping relationships. For example, the primitive assembly pipeline first determines the vertex index of the first primitive to which the first vertex belongs and each vertex of the first primitive based on the arrangement position of the first vertex among multiple vertices and multiple vertex indexes, each vertex including the first vertex; and determines the pipeline index of each vertex based on the vertex index and mapping relationship of each vertex.

[0179] Exemplarily, if the primitive assembly information of the first primitive includes vertex indexes of each vertex of the first primitive; when the first vertex does not belong to at least one vertex that needs to be skipped, the primitive assembly pipeline determines the primitive assembly information of the first primitive to which the first vertex belongs based on the arrangement position of the first vertex among multiple vertices and multiple vertex indexes. For example, the primitive assembly pipeline first determines the first primitive to which the first vertex belongs and the vertex indexes of each vertex of the first primitive based on the arrangement position of the first vertex among multiple vertices and multiple vertex indexes, and each vertex includes the first vertex.

[0180] Exemplarily, the split initial state information indicates the index of the vertices to be processed among the multiple vertices. For example, if the multiple vertices are 16 vertices, the split initial state information indicates that the starting offset of the valid vertices is 2, that is, the valid vertices to be processed start from the second vertex.

[0181] In some embodiments, the geometry processing pipeline is located in the first graphics processing core, the split initial state information comes from the second graphics processing core, and the second graphics processing core is the previous graphics processing core connected to the first graphics processing core; or, the second graphics processing core is the central graphics processing core of the first graphics processing core.

[0182] Exemplarily, the second graphics processing core is the previous graphics processing core connected to the first graphics processing core, which means that an output end of the second graphics processing core is connected to an input end of the first graphics processing core, and the second graphics processing core will generate the split initial state information and send it to the primitive pipeline unit 140 of the first graphics processing core.

[0183] Exemplarily, the second graphics processing core is the central graphics processing core of the first graphics processing core, which means that there are multiple graphics processing cores in the graphics processor, and the multiple graphics processing cores include a central graphics processing core, and the central graphics processing core is used to generate the split initial state information required by each graphics processing core. The second graphics processing core is the central graphics processing core of the first graphics processing core.

[0184] To summarize, the geometry processing pipeline provided in the embodiment of the present application further illustrates the specific structure of the primitive pipeline unit, where the primitive assembly pipeline splits multiple vertex indexes to obtain vertex indexes corresponding to at least one primitive, and then obtains primitive assembly information of at least one primitive. The primitive processing pipeline then assembles and calculates the primitives based on the primitive assembly information, thereby achieving the decoupling of primitive assembly and primitive processing.

[0185] When the primitive assembly information includes the pipeline index of each vertex, the primitive processing pipeline is supported to obtain the vertex processing results of each vertex directly from the vertex storage based on the pipeline index, thereby realizing the decoupling of vertex shading and primitive assembly in the geometry processing pipeline from the external vertex index, and improving the flexibility of the combined processing pipeline.

[0186] In addition, the process of assembling primitives based on the split initial state information is also shown, that is, supporting invalid vertex indexes that do not need to be processed in multiple vertex indexes. These vertex indexes will be set before and after multiple vertex indexes, thereby improving the anti-interference ability of multiple vertex indexes during the sending process.

[0187] In addition, the split initial state information may be from the previous graphics processing core or the central graphics processing core, that is, the geometry processing pipeline shown in the embodiment of the present application supports both distributed graphics processors and centralized graphics processors, thus expanding the application scenarios of the geometry processing pipeline.

[0188] The primitive pipeline unit 140 receives multiple vertex indices on one hand, and on the other hand receives the mapping relationship between the vertex indices and pipeline identifiers sent by the vertex cache unit 110. When the primitive pipeline unit 140 receives the split initial state information, it can start assembling primitives.

[0189] For example, the processing of the primitive pipeline unit 140 is further described as follows. Figure 4 shown.

[0190] Step 1, receive vertex index.

[0191] The primitive pipeline unit 140 receives multiple vertex indices, and obtains a vertex index that currently needs to be processed from the multiple vertex indices.

[0192] Step 2: Determine whether it is a vertex that needs to be skipped.

[0193] Determine whether this vertex is a vertex that needs to be skipped based on the split initial state information. If yes, skip this vertex and jump to step 3. If not, jump to step 4 to start assembling the primitive.

[0194] Step 3, skip and do not assemble the primitives.

[0195] After skipping, execute step 8 to determine whether there are new vertices to be processed.

[0196] Step 4: Start assembling the graphics elements.

[0197] The primitive pipeline unit 140 determines the primitive to which the current vertex belongs or the primitive assembly information of the primitive to which the unit vertex belongs based on the vertex index currently processed, the position of the vertex index currently processed in the multiple vertex indices, and the split initial state information. The primitive assembly information includes the vertex index of the current vertex.

[0198] Step 5: Determine the pipeline index based on the vertex index and the mapping relationship.

[0199] The primitive pipeline unit 140 determines the pipeline index of the vertex, that is, the shader identifier and the vertex cache index of the vertex, based on the vertex index and the mapping relationship sent by the vertex cache unit.

[0200] Optionally, based on the vertex index currently being processed, the position of the vertex index currently being processed in the plurality of vertex indexes, the split initial state information and the mapping relationship, the primitive assembly information of the primitive to which the current vertex belongs is determined. The primitive assembly information includes the pipeline index of the current vertex.

[0201] Step 6, obtaining vertex processing results of the vertices constituting the primitive from the vertex storage.

[0202] The primitive pipeline unit 140 queries the vertex processing result of the vertex from the vertex storage according to the pipeline index of the vertex, determines whether the vertex processing results of all vertices of the current primitive have been queried, and waits until all vertex shading results constituting the primitive are queried from the vertex storage before formally processing the primitive.

[0203] Step 7: Process the graphics primitives.

[0204] The processing of primitives includes but is not limited to starting a primitive shader, starting a tessellation pipeline, or performing a rasterization operation.

[0205] Step 8: Determine whether there is a new vertex.

[0206] That is, it is determined whether all of the multiple vertices have been processed. If there is no new vertex, that is, there is no vertex among the multiple vertices that has not been processed by the primitive, the processing of the primitive pipeline unit 140 ends.

[0207] If there is a new vertex, that is, there is an unprocessed vertex among the multiple vertices, then continue to obtain an unprocessed vertex to continue the primitive processing, that is, jump to execute step 1.

[0208] In the case where the primitive pipeline unit 140 includes a primitive assembly pipeline and a primitive processing pipeline, the above steps 1 to 4 are executed by the primitive assembly pipeline, and the above steps 5 to 7 are executed by the primitive processing pipeline. Both the primitive assembly pipeline and the primitive processing pipeline need to execute step 8. At this time, for the primitive assembly pipeline, step 8 should be executed between step 4 and step 5; or, the above steps 1 to 5 are executed by the primitive assembly pipeline, and the above steps 6 and 7 are executed by the primitive processing pipeline. Both the primitive assembly pipeline and the primitive processing pipeline need to execute step 8 or neither of them executes step 8. At this time, for the primitive assembly pipeline, step 8 should be executed between step 5 and step 6.

[0209] Next, refer to Figures 5 to 7 , showing the specific processing process of the geometry processing pipeline shown in the embodiment of the present application.

[0210] like Figure 5 As shown, the multiple vertex indexes are A, B, C, D, B, C, A, E, F, C, G, B, C, H, C, I, J, K, A, B, C, that is, each vertex uses an uppercase letter to represent its corresponding vertex index. If the vertex processing pipeline 120 shades according to the granularity of 8 vertices when calling the vertex shading program, then after these vertices are hit tested in turn, a total of two vertex shader tasks will be started, namely vertex shader task 0 and vertex shader task 1. Vertex shader task 0 processes vertices A, B, C, D, E, F, G, H, and vertex shader task 1 processes I, J, K, A, B, C. Among them, vertex shader task 1 has to be forced to start the vertex shader task because there are no unprocessed vertices, so it does not fully organize 8 vertices. When forming vertex shader task 0, the mapping relationship is as follows Figure 5 As shown in the mapping relationship table 60, vertex A is mapped to 0-0, that is, the 0th vertex of vertex shader task 0, and so on. The mapping relationship when forming vertex shader task 1 is as follows Figure 5 As shown in the mapping relationship table 61, vertex I is mapped to 1-0, that is, the 0th vertex of vertex shader task 1, vertex J is mapped to 1-1, that is, the 1st vertex of vertex shader task 1, vertex K is mapped to 1-2, that is, the 2nd vertex of vertex shader task 1, vertex A is mapped to 1-3, that is, the 3rd vertex of vertex shader task 1, vertex B is mapped to 1-4, that is, the 4th vertex of the vertex shader task, and vertex C is mapped to 1-5, that is, the 5th vertex of the vertex shader task. It should be noted that although the above Figure 5 In the diagram, two mapping tables are shown (one for each vertex shader task), but in reality these two mapping tables are a unified mapping table.

[0211] Among them, the original input stream provides a total of 21 vertices. After passing through the vertex cache unit 110, only 2 shader tasks are run, and a total of 8+6=14 vertices are sent, that is, the vertex shading program processes a total of 14 vertices. This is because the embodiment of the present application fully utilizes the characteristics of sharing vertices between primitives and reduces the number of times repeated vertices are processed. Since the last A, B, C vertices are separated from the previous A, B, C vertices by more other vertices, the last A, B, C need to be run again in vertex shader task 1.

[0212] Vertex shader task 0 and vertex shader task 1 are sent to the vertex processing pipeline 120, and after being processed, the results are output to the vertex storage 130. Next, the primitive pipeline unit 140 starts primitive assembly.

[0213] In addition to receiving the input vertex stream data and the mapping relationship table sent by the vertex cache unit 110, the primitive pipeline unit 140 also needs to perform splitting according to the splitting initial state information.

[0214] Next, the primitive assembly process of the primitive pipeline unit 140 according to different split initial state information is shown.

[0215] Example 1:

[0216] If the primitive topology is a triangle list, and the split initial state information sent indicates that the primitive needs to be assembled starting from the third vertex (that is, skipping the first two vertices A and B).

[0217] like Figure 6 As shown, after skipping the first two vertices AB, the primitive pipeline unit 140 forms the primitives CDB, CAE, FCG, BCH, CIJ, and KAB according to the rules of the triangle list. Among them, the last single vertex C cannot form a complete primitive and is therefore directly discarded. During the primitive assembly process, the vertex processing results of the vertices that constitute each triangle are searched in the vertex storage 130 according to the mapping relationship table sent over. For example, for triangle CDB, vertex C is mapped to 0-2, D is mapped to 0-3, and B is mapped to 0-1, which means that this triangle needs to obtain the vertex processing results of the vertex shading program from the 2nd, 3rd, and 1st vertices in vertex shader task 0 to form the primitive.

[0218] Example 2:

[0219] If the initial state information of the split indicates that the primitive needs to be assembled from the second vertex (i.e. skipping the first vertex A), then Figure 7 shown.

[0220] The triangles decomposed by the primitive pipeline unit 140 are BCD, BCA, EFC, GBC, HCI, and JKA. At this time, the primitive pipeline unit 140 can still find the shader identifier-vertex cache index of each vertex from the provided mapping relationship table, thereby finding the vertex processing result of the corresponding vertex from the vertex storage 130 and assembling the primitives for further processing.

[0221] The existence of clipping points does not affect the process of this application. When doing hit testing, the clipping points are skipped. When doing primitive assembly, the clipping points provide more information to assemble the primitives.

[0222] In addition, although the shader and cache have the same number (8) in this example, in practice, the two numbers may not be equal. For example, a shader task can have 32 threads, and the vertex cache can have 128 positions for testing (to search for duplicate vertices in a larger range and reduce the number of vertex shading). At this time, when each cache is full (that is, all 128 positions are filled), it corresponds to 4 corresponding shader tasks. The mapping table can also provide this mapping relationship. On the contrary, if the shader task is 128 threads, but the vertex cache has only 32, the present application can also achieve the same purpose.

[0223] In some embodiments, Figure 8 As shown, the geometry processing pipeline 100 includes a vertex cache module 110, a vertex processing pipeline 120, a vertex storage 130, and a primitive pipeline unit 140, wherein the vertex cache module 110 is connected to the vertex processing pipeline 120, the vertex processing pipeline 120 is connected to the vertex storage 130, the vertex storage 130 is connected to the primitive pipeline unit 140, and the vertex cache unit 110 is connected to the primitive processing pipeline. Optionally, the primitive pipeline unit 140 includes a primitive assembly pipeline 141 and a primitive processing pipeline 142, the primitive assembly pipeline 141 is connected to the primitive processing pipeline 142, the primitive assembly pipeline 141 is connected to the vertex cache unit 110, and the primitive processing pipeline 142 is connected to the vertex storage 130. Optionally, Figure 8Only a typical geometry processing pipeline 100 shown in the embodiment of the present application is shown, but the connection relationship between the various units inside the geometry pipeline 100 may also be different according to different implementation methods, such as supporting the connection between the vertex storage 130 and the primitive assembly pipeline 141, so that the primitive assembly pipeline 141 can read the vertex processing result from the vertex storage 130; it can also support the primitive processing pipeline 142 and the vertex cache unit 110, so that the vertex cache unit 110 directly sends the mapping relationship to the primitive processing pipeline 142, and so on, that is, there can be a circuit connection between the various units for sending and receiving the existence information (such as split initial state information, multiple vertex indexes, pipeline indexes, mapping relationships, etc.) shown in the embodiment of the present application. The embodiment of the present application does not limit this, but the protection scope of the embodiment of the present application is not limited to this.

[0224] The functions of each unit in the entire geometry processing pipeline 100 are further introduced.

[0225] First, the geometry processing pipeline 100 will receive a plurality of vertex indices.

[0226] Exemplarily, multiple vertex indexes are sent from the vertex splitting unit to the geometry processing pipeline 100 in the form of a vertex stream. The vertex splitting unit is a unit in the image processing core connected to the geometry pipeline 100. The vertex splitting unit is used to receive drawing instructions from an application or a driver; obtain vertex index data required for the drawing instructions from a storage unit, or generate vertex index data by itself. The vertex splitting unit splits these vertex index data into segments with the same number of vertex indexes (i.e., multiple vertex indexes are obtained as mentioned in the embodiment of the present application) according to the splitting method specified by the drawing instructions or the driver or the system configuration module, and sends these vertex fragments to the geometry processing pipeline.

[0227] On the one hand, multiple vertex indexes are directly sent to the vertex cache unit 110 and the subsequent vertex processing pipeline 120. After the vertex shader task is started, the result of vertex processing is input into the vertex storage 130. On the other hand, multiple vertex indexes are directly sent to the primitive assembly pipeline 141. When the primitive assembly pipeline 141 receives the split initial state information, combined with the mapping relationship sent from the vertex cache unit 110, it can start primitive assembly, obtain primitive assembly information, and send it to the primitive processing pipeline 142.

[0228] The primitive processing pipeline 142 accesses the vertex storage 130 according to the primitive assembly information sent by the primitive assembly pipeline 141, so that the vertex processing results calculated by the vertex shading program can be used to assemble primitives for further primitive processing, including but not limited to rasterization, starting the geometry shader, or starting the tessellation function.

[0229] Among them, the vertex cache unit 110 is designed to reduce the number of times the vertex shading program is run. By designing a cache structure, the vertices sent within a period of time are recorded. If a new vertex is found in this cache, it means that the vertex shading program has been sent for the corresponding vertex, and there is no need to send it again.

[0230] In the geometry processing pipeline, the vertex processing pipeline 120 needs to process the vertices corresponding to the pipeline index sent by the vertex cache unit 110. The vertex processing pipeline 120 starts the user-defined vertex shading program for these vertices, and outputs the vertex processing results corresponding to these vertices to the vertex storage 130, so that the subsequent pipelines can use the vertex processing results after these vertex shading. For the vertex processing pipeline 120, the actual processing is carried out in a mode of inputting one vertex and outputting one vertex result. Therefore, the vertex processing pipeline 120 will not increase or decrease the number of vertices, nor will it change the order of the input vertices, and will output the vertex processing results of each vertex to the vertex storage 130 in the order of input. Since the work done by the vertex processing pipeline 120 is actually vertex shading, the vertex processing result can also be called the vertex shading result.

[0231] However, for the vertex processing pipeline 120, when running the vertex shading program, in order to improve hardware performance and efficiency, the vertex shading program is not started immediately for each vertex input. Instead, based on the design concept of wave / warp, the vertex shading program is started for these vertices after a certain number of vertices are collected. In the embodiment of the present application, this batch of started vertices is referred to as a vertex shader task (referred to as shader task).

[0232] For example, Fig. 9 As shown, a scenario of starting a vertex shader with 8 threads is shown. It should be noted that modern GPU shaders usually have 16 or 32 threads. Here, 8 threads are used as an example for illustration. In practice, the number of threads in each graphics processing core or shader in a graphics processor is not limited, but the protection scope of the embodiments of the present application is not limited thereto. Fig. 9 The vertex processing pipeline 120 starts the multiple vertices of the input shown in FIG. 1 according to two vertex shader tasks, each of which includes 8 vertices. The vertices corresponding to vertex shader task 0 are A, B, C, D, E, F, G, H, and the vertices corresponding to vertex shader task 1 are I, J, K, A, L, G, H, M. A vertex may appear in multiple vertex shader tasks, such as points A, G, and H appear in vertex shader task 0 and vertex shader task 1, respectively.

[0233] Fig.10 The schematic diagram of the graphics processing core provided by the embodiment of the present application is shown. The graphics processing core 10 includes: a geometry processing pipeline 100, which is the geometry processing pipeline mentioned above, including: a vertex cache unit with a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit, which will not be repeated here. Optionally, the primitive pipeline unit includes a primitive assembly pipeline and a primitive processing pipeline.

[0234] Optionally, the graphics processing core 10 further includes a vertex splitting unit 200. A first end of the vertex splitting unit 200 is connected to the vertex cache unit 110, and a second end of the vertex splitting unit 200 is connected to the primitive assembly pipeline 141; the vertex splitting unit 200 is used to split at least one vertex index to obtain multiple vertex indexes; and send the multiple vertex indexes to the vertex cache unit 110 and the primitive assembly pipeline 141.

[0235] Exemplarily, the vertex splitting unit 200 receives a drawing instruction specified by an application or a driver, and then obtains the vertex indexes required for the drawing command from the storage unit, or generates the vertex indexes by itself. The vertex splitting unit 200 splits the vertex indexes into segments with the same number of vertex indexes, i.e., the multiple vertex indexes mentioned above, according to the splitting method specified by the drawing instruction or the driver or the system configuration module.

[0236] Optionally, the graphics processing core 10 also includes: a storage access arbitrator 300 and a pixel processing pipeline 400; a first end of the storage access arbitrator 300 is connected to the output end of the primitive processing pipeline 142, and a second end of the storage access arbitrator 300 is connected to the pixel processing pipeline 400; a third end of the storage access arbitrator 300 is used to connect to a system bus, and the system bus is connected to a storage unit; the storage access arbitrator 300 is used to arbitrate one of the primitive processing pipeline 142 and the pixel processing pipeline 400 to access the storage unit.

[0237] In summary, the image processing core provided in the embodiment of the present application realizes the processing of vertices without the need for primitive assembly, and realizes the hit test of vertex granularity. Specifically, by generating a pipeline index used inside a geometry pipeline by the vertex cache unit, the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shading program, which makes it unnecessary for the vertex shading program to confirm the primitive where the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, so that the geometry processing pipeline shown in the embodiment of the present application can be applied to processors with distributed structures. And the geometry processing pipeline provided in the embodiment of the present application improves the processing efficiency of the geometry processing pipeline compared to the geometry processing pipeline with primitives as the hit test granularity in the related art. That is, it is realized that the vertex cache unit can perform hit testing without obtaining primitive assembly information, so that hit testing and vertex shading can be performed in parallel, improving the processing performance of the geometry processing pipeline.

[0238] Fig.11 A schematic diagram of a graphics processor provided by an exemplary embodiment of the present application is shown.

[0239] In some embodiments, the graphics processor includes: N graphics processing cores 10, a system configuration unit 20, a system bus 30 and a storage unit 40, where N is a positive integer; the N graphics processing cores 10 are respectively connected to the system bus 30, and the system bus 30 is connected to the storage unit 40; the system configuration unit 20 is respectively connected to each of the N graphics processing cores 10; wherein each graphics processing core 10 includes the above-mentioned geometry processing pipeline 100.

[0240] Optionally, the N graphics processing cores 10 are homogeneous, that is, the performance of the graphics processor can be adjusted by simply increasing or decreasing the number of graphics processing cores 10 to meet the requirements of throughput, performance and power consumption of the graphics processor in different application scenarios, thereby reducing the complexity of design and verification.

[0241] In summary, the graphics processor provided in the embodiment of the present application realizes the processing of vertices without the need for primitive assembly, and realizes the hit test of vertex granularity. Specifically, by generating a pipeline index used inside a geometry pipeline by the vertex cache unit, the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shading program, which makes it unnecessary for the vertex shading program to confirm the primitive where the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, so that the geometry processing pipeline shown in the embodiment of the present application can be applied to processors with distributed structures. And the geometry processing pipeline provided in the embodiment of the present application improves the processing efficiency of the geometry processing pipeline compared to the geometry processing pipeline with primitives as the hit test granularity in the related art. That is, it is realized that the vertex cache unit can perform hit testing without obtaining primitive assembly information, so that hit testing and vertex shading can be performed in parallel, improving the processing performance of the geometry processing pipeline.

[0242] Fig.12 A flowchart of a vertex cache method provided by an exemplary embodiment of the present application is shown. The method is executed by the geometry processing pipeline 100 shown above. The geometry processing pipeline 100 includes: a vertex cache unit with a vertex index cache, a vertex processing pipeline, a vertex storage, and a primitive pipeline unit; the method includes:

[0243] Step 510: The vertex cache unit and the primitive pipeline unit receive a plurality of vertex indices arranged in order, the plurality of vertex indices are used to indicate a plurality of vertices, and the plurality of vertex indices correspond one-to-one to the plurality of vertices.

[0244] Optionally, multiple vertex indices arranged in sequence refer to that the multiple vertex indices are arranged according to the arrangement order of the multiple vertices in the primitive, such as the vertex indices corresponding to the multiple vertices in each primitive are continuous, and the vertex indices corresponding to the multiple vertices in each primitive are arranged in clockwise order or counterclockwise order according to the multiple vertices in the primitive.

[0245] Step 520: The vertex cache unit adds the vertex index of the first vertex that is not hit in the vertex index cache among multiple vertex indices to the vertex index cache; generates a vertex shader task to which the first vertex belongs; generates a pipeline index for the first vertex, and the pipeline index is used to identify the first vertex in the geometry processing pipeline; sends the vertex shader task and the pipeline index to which the first vertex belongs to the vertex processing pipeline to perform vertex processing; and sends the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0246] Optionally, a hit in the vertex cache means that the vertex index of the vertex has been stored in the vertex index cache; a miss in the vertex cache means that the vertex index of the vertex does not exist in the vertex index cache.

[0247] Optionally, a vertex shader task includes the vertices processed each time a vertex shader is started. That is, in order to improve hardware performance and efficiency, the vertex shader is not started immediately for each vertex input. Instead, the vertex shader is started for these vertices after a certain number of vertices are collected. Such a batch of started vertices is a vertex shader task (referred to as a shader task).

[0248] Optionally, the pipeline index is used to identify the first vertex in the geometry processing pipeline. In other words, the pipeline index is used to identify the first vertex in the vertex cache.

[0249] In some embodiments, the vertex cache unit generates a pipeline index based on a shader identifier and a vertex cache index corresponding to the first vertex; wherein the shader identifier is used to identify the vertex shader task to which the first vertex belongs; and the vertex cache index is used to identify the cache position of the vertex index of the first vertex in the vertex index cache.

[0250] In some embodiments, when the number of unsent vertices reaches a trigger threshold, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline for vertex processing based on the unsent vertices, wherein the unsent vertices include the first vertex. For details, please refer to the above scenario 1.

[0251] In some embodiments, when the vertex index cache is full, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline for vertex processing based on the unsent vertices, wherein the unsent vertices include the first vertex. For details, please refer to the above scenario 2.

[0252] In some embodiments, when there are no unprocessed remaining vertices among the plurality of vertices, the vertex cache unit sends the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline for vertex processing based on the unsent vertices, wherein the unsent vertices include the first vertex. For details, please refer to the above scenario 3.

[0253] In some embodiments, the vertex cache unit ignores a second vertex among the plurality of vertices that hits the vertex index cache.

[0254] In some embodiments, the vertex cache unit includes: a vertex index cache, a hit test control subunit, a shader task assembly subunit and a shader task mapping subunit, such as Figure 2 As shown; the hit test control subunit performs a vertex hit test on each vertex index in a plurality of vertex indexes; adds the vertex index of the first vertex in the plurality of vertex indexes that is not hit in the vertex index cache to the vertex index cache; generates a vertex shader task to which the first vertex belongs; generates a pipeline index for the first vertex; and sends the pipeline index for the first vertex to the shader task assembly subunit; the shader task assembly subunit sends the vertex shader task and the pipeline index to which the first vertex belongs to the vertex processing pipeline to perform vertex processing; the shader task mapping subunit sends the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

[0255] Step 530: The vertex storage saves the vertex processing result of the first vertex based on the pipeline index.

[0256] Exemplarily, the vertex processing result of the first vertex refers to the vertex processing result of the first vertex after the vertex is processed by the vertex shading program, or the calculation result of the vertex shading program on the first vertex. The vertex shading program is used to calculate the first vertex, such as calculating the lighting and texture coordinates of the first vertex.

[0257] Step 540: The primitive pipeline unit performs primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on the split initial state information, multiple vertex indexes and mapping relationships, and the split initial state information is used to indicate a splitting method for splitting multiple vertices into at least one primitive.

[0258] Optionally, primitive assembly refers to determining each vertex belonging to the first primitive from a plurality of vertices; or, primitive assembly refers to determining each vertex index belonging to the first primitive from a plurality of vertex indexes; or, primitive assembly refers to determining each vertex belonging to the first primitive from a plurality of vertices, and assembling each vertex into the first primitive; or, primitive assembly refers to determining each vertex index belonging to the first primitive from a plurality of vertex indexes, and assembling each vertex index to obtain the first primitive. Each vertex includes the first vertex; each vertex index includes the vertex index of the first vertex.

[0259] Optionally, primitive processing refers to performing primitive-related processing on the first primitive. Primitive processing includes but is not limited to: rasterization; primitive shading; surface tessellation. Surface tessellation is a method of further dividing a primitive to obtain a smooth surface.

[0260] Optionally, the split initial state information is used to indicate a splitting method for splitting multiple vertices into at least one primitive; or, the split initial state information is used to indicate a vertex among multiple vertices that needs to be assembled into primitives; or, the split initial state information is used to indicate a vertex among multiple vertices that needs to be processed by a primitive pipeline unit; or, the split initial state information is used to indicate a splitting method for a primitive pipeline unit to process multiple vertices. Splitting methods include but are not limited to: vertices to be processed; the number of vertices included in each primitive; primitive type; and the ordering method of vertices corresponding to a primitive among multiple vertices.

[0261] Exemplarily, if the vertices to be processed are, for example, 16 vertices, the split initial state information is used to indicate that the vertices to be processed are the second to the fifteenth vertices among the multiple vertices. If the number of vertices included in each primitive is a triangle, the number of vertices included in each primitive is 3. The primitive type is used to indicate the shape of the primitive or the arrangement of multiple primitives, such as indicating that the shape of the primitive is a triangle, a quadrilateral, indicating the arrangement of multiple primitives such as a line strip, a triangle strip, and so on. A line strip is that except for the first vertex, each vertex will form a line segment primitive with the previous vertex, and all line segment primitives form a continuous strip structure in space. A triangle strip means that except for the first triangle primitive, each new vertex will form a triangle primitive together with the first two vertices, and all triangle primitives form a continuous strip structure in space. The ordering of the vertices corresponding to the primitive among multiple vertices, such as whether each vertex is arranged in clockwise order, or arranged in counterclockwise order, and so on.

[0262] Optionally, the primitive pipeline unit performs primitive assembly based on the split initial state information and multiple vertex indices to determine the first primitive to which the first vertex belongs; obtains the vertex processing result of the first vertex from the vertex storage based on the mapping relationship; and performs primitive processing based on the vertex processing result of the first vertex to obtain the first primitive to which the first vertex belongs. Or, the primitive pipeline unit performs primitive assembly based on the split initial state information and multiple vertex indices to determine the first primitive to which the first vertex belongs, and the first primitive includes multiple vertices; obtains the vertex processing result of each vertex in the multiple vertices from the vertex storage based on the mapping relationship between the vertex indices of the multiple vertices and the pipeline index; and performs primitive processing based on the vertex processing results of each vertex to obtain the first primitive to which the first vertex belongs.

[0263] In some embodiments, the primitive pipeline unit includes: a primitive assembly pipeline and a primitive processing pipeline; the primitive assembly pipeline performs primitive assembly based on the split initial state information, multiple vertex indexes and mapping relationships to obtain primitive assembly information of the first primitive to which the first vertex belongs; the primitive processing pipeline performs primitive processing based on the primitive assembly information of the first primitive to obtain the first primitive;

[0264] Or, a primitive assembly pipeline is used to perform primitive assembly based on the split initial state information and multiple vertex indexes to obtain primitive assembly information of a first primitive to which a first vertex belongs; a primitive processing pipeline is used to perform primitive processing based on the primitive assembly information and a mapping relationship of the first primitive to obtain the first primitive.

[0265] In some embodiments, primitive assembly information of a first primitive includes pipeline indexes of each vertex of the first primitive, and each vertex of the first primitive includes a first vertex; a primitive processing pipeline receives primitive assembly information sent by a primitive assembly pipeline; vertex processing results of each vertex are obtained from a vertex storage based on the pipeline indexes of each vertex carried by the primitive assembly information; and primitive processing is performed based on the vertex processing results of each vertex to obtain a first primitive.

[0266] In some embodiments, the primitive assembly information of the first primitive includes vertex indices of each vertex of the first primitive, and each vertex of the first primitive includes a first vertex; a primitive processing pipeline is used to receive primitive assembly line information sent by the primitive assembly pipeline; based on the mapping relationship and the vertex indices of each vertex carried by the primitive assembly information, the pipeline index of each vertex is determined; based on the pipeline index of each vertex, the vertex processing result of each vertex is obtained from the vertex storage; based on the vertex processing result of each vertex, primitive processing is performed to obtain the first primitive.

[0267] In some embodiments, the splitting initial state information includes: at least one vertex that needs to be skipped among multiple vertices; the primitive assembly pipeline skips the first vertex when the first vertex belongs to at least one vertex that needs to be skipped; and when the first vertex does not belong to at least one vertex that needs to be skipped, determines the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the arrangement position of the first vertex among multiple vertices, multiple vertex indexes and mapping relationships.

[0268] In some embodiments, the geometry processing pipeline is located in the first graphics processing core, the split initial state information comes from the second graphics processing core, and the second graphics processing core is the previous graphics processing core connected to the first graphics processing core; or, the second graphics processing core is the central graphics processing core of the first graphics processing core.

[0269] In summary, the method provided in the embodiment of the present application realizes the processing of vertices without the need for primitive assembly, and realizes the hit test of vertex granularity. Specifically, by generating a pipeline index used inside a geometry pipeline by the vertex cache unit, the vertex processing result and the pipeline index corresponding to the vertex are stored in the vertex storage after the processing of the vertex shading program, which makes it unnecessary for the vertex shading program to confirm the primitive where the vertex is located during processing, that is, the decoupling of vertex shading and hit testing and the decoupling between different geometry processing pipelines are realized, so that the geometry processing pipeline shown in the embodiment of the present application can be applied to processors with distributed structures. And the geometry processing pipeline provided in the embodiment of the present application improves the processing efficiency of the geometry processing pipeline compared to the geometry processing pipeline with primitives as the hit test granularity in the related art. That is, it is realized that the vertex cache unit can perform hit testing without obtaining primitive assembly information, so that hit testing and vertex shading can be performed in parallel, improving the processing performance of the geometry processing pipeline.

[0270] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0271] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A geometry processing pipeline, characterized in that: The geometry processing pipeline includes: a vertex cache unit having a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit; The vertex cache unit and the primitive pipeline unit are used to receive a plurality of vertex indexes arranged in order, the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond to the plurality of vertices one by one; The vertex cache unit is used to add the vertex index of the first vertex that is not hit in the vertex index cache among the multiple vertex indexes to the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and send a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit; The vertex storage is used to store the vertex processing result of the first vertex based on the pipeline index; The primitive pipeline unit is used to perform primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on the split initial state information, the multiple vertex indexes and the mapping relationship, and the split initial state information is used to indicate the splitting method of splitting the multiple vertices into at least one primitive.

2. The geometry processing pipeline according to claim 1, characterized in that: The vertex cache unit is used to generate the pipeline index based on the shader identifier and the vertex cache index corresponding to the first vertex; The shader identifier is used to identify the vertex shader task to which the first vertex belongs; and the vertex cache index is used to identify the cache position of the vertex index of the first vertex in the vertex index cache.

3. The geometry processing pipeline according to claim 1, characterized in that: The vertex cache unit is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform the vertex processing based on the unsent vertices when the number of unsent vertices reaches a trigger threshold; The unsent vertices include the first vertex.

4. The geometry processing pipeline according to claim 1, characterized in that: The vertex cache unit is used to send the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform the vertex processing based on the unsent vertex when the vertex index cache is full; The unsent vertices include the first vertex.

5. The geometry processing pipeline according to claim 1, characterized in that: The vertex cache unit is used for sending the vertex shader task to which the first vertex belongs and the pipeline index of the unsent vertex to the vertex processing pipeline to perform the vertex processing based on the unsent vertex when there are no unprocessed remaining vertices among the plurality of vertices; The unsent vertices include the first vertex.

6. The geometry processing pipeline according to any one of claims 1 to 5, characterized in that: The vertex cache unit is used to ignore the second vertex among the multiple vertices that hits the vertex index cache.

7. The geometry processing pipeline according to any one of claims 1 to 5, characterized in that: The vertex cache unit also includes: a hit test control subunit, a shader task assembly subunit and a shader task mapping subunit; The hit test control subunit is used to perform a vertex hit test on each vertex index of the multiple vertex indexes; add the vertex index of the first vertex that is not hit in the vertex index cache among the multiple vertex indexes to the vertex index cache; generate a vertex shader task to which the first vertex belongs; generate a pipeline index of the first vertex; and send the pipeline index of the first vertex to the shader task assembly subunit; The shader task assembly subunit is used to send the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; The shader task mapping subunit is used to send the mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit.

8. The geometry processing pipeline according to any one of claims 1 to 5, characterized in that: The primitive pipeline unit includes: a primitive assembly pipeline and a primitive processing pipeline; The primitive assembly pipeline is used to perform the primitive assembly based on the split initial state information, the multiple vertex indexes and the mapping relationship to obtain the primitive assembly information of the first primitive to which the first vertex belongs; the primitive processing pipeline is used to perform the primitive processing on the first primitive based on the primitive assembly information of the first primitive; Or, the primitive assembly pipeline is used to perform the primitive assembly based on the split initial state information and the multiple vertex indexes to obtain the primitive assembly information of the first primitive to which the first vertex belongs; the primitive processing pipeline is used to perform the primitive processing on the first primitive based on the primitive assembly information of the first primitive and the mapping relationship.

9. The geometry processing pipeline according to claim 8, characterized in that: The primitive assembly information of the first primitive includes pipeline indexes of respective vertices of the first primitive, and the respective vertices of the first primitive include the first vertex; The primitive processing pipeline is used to receive the primitive assembly information sent by the primitive assembly pipeline; Acquire vertex processing results of each vertex from the vertex storage based on the pipeline index of each vertex carried by the primitive assembly information; The primitive processing is performed on the first primitive based on the vertex processing results of the respective vertices.

10. The geometry processing pipeline according to claim 8, characterized in that: The primitive assembly information of the first primitive includes vertex indexes of respective vertices of the first primitive, and the respective vertices of the first primitive include the first vertex; The primitive processing pipeline is used to receive the primitive assembly line information sent by the primitive assembly pipeline; Determine a pipeline index of each vertex based on the mapping relationship and the vertex index of each vertex carried by the primitive assembly information; Based on the pipeline index of each vertex, the vertex processing result of each vertex is obtained from the vertex storage; based on the vertex processing result of each vertex, the primitive processing is performed on the first primitive.

11. The geometry processing pipeline according to claim 8, characterized in that: The split initial state information includes: at least one vertex that needs to be skipped among the multiple vertices; The primitive assembly pipeline is used to skip the first vertex when the first vertex belongs to at least one vertex that needs to be skipped; when the first vertex does not belong to at least one vertex that needs to be skipped, determine the primitive assembly information of the first primitive to which the first vertex belongs based on at least two of the arrangement position of the first vertex among the multiple vertices, multiple vertex indexes and mapping relationships.

12. The geometry processing pipeline according to any one of claims 1 to 5, characterized in that: The geometry processing pipeline is located in the first graphics processing core, the split initial state information comes from the second graphics processing core, the second graphics processing core is the previous graphics processing core connected to the first graphics processing core; or, the second graphics processing core is the central graphics processing core of the first graphics processing core.

13. A graphics processing core, characterized in that: The graphics processing core comprises: a geometry processing pipeline, wherein the geometry processing pipeline is the geometry processing pipeline as claimed in any one of claims 1 to 12.

14. The graphics processing core according to claim 13, characterized in that: The graphics processing core also includes: a storage access arbitrator and a pixel processing pipeline; The first end of the storage access arbitrator is connected to the output end of the primitive processing pipeline, and the second end of the storage access arbitrator is connected to the pixel processing pipeline; the third end of the storage access arbitrator is used to connect to the system bus, and the system bus is connected to the storage unit; The storage access arbiter is used to arbitrate access to the storage unit by one of the primitive processing pipeline and the pixel processing pipeline.

15. The graphics processing core according to claim 13 or 14, characterized in that: The graphics processing core further includes: a vertex splitting unit; a first end of the vertex splitting unit is connected to the vertex cache unit, and a second end of the vertex splitting unit is connected to the primitive assembly pipeline; The vertex splitting unit is used to split at least one vertex index to obtain the multiple vertex indexes; and send the multiple vertex indexes to the vertex cache unit and the primitive assembly pipeline.

16. A graphics processor, characterized in that: The graphics processor includes: N graphics processing cores, a system configuration unit, a system bus and a storage unit, where N is a positive integer; The N graphics processing cores are respectively connected to the system bus, and the system bus is connected to the storage unit; The system configuration unit is respectively connected to each of the N graphics processing cores; Each of the graphics processing cores comprises a geometry processing pipeline as described in any one of claims 1 to 12.

17. A vertex caching method, characterized in that: The method is performed by a geometry processing pipeline according to any one of claims 1 to 12, the geometry processing pipeline comprising: a vertex cache unit having a vertex index cache, a vertex processing pipeline, a vertex storage and a primitive pipeline unit; The method comprises: The vertex cache unit and the primitive pipeline unit receive a plurality of vertex indexes arranged in order, the plurality of vertex indexes are used to indicate a plurality of vertices, and the plurality of vertex indexes correspond one-to-one to the plurality of vertices; The vertex cache unit adds the vertex index of the first vertex among the multiple vertex indices that is not hit in the vertex index cache to the vertex index cache; generates a vertex shader task to which the first vertex belongs; generates a pipeline index of the first vertex, the pipeline index being used to identify the first vertex in the geometry processing pipeline; sends the vertex shader task to which the first vertex belongs and the pipeline index to the vertex processing pipeline to perform vertex processing; and sends a mapping relationship between the vertex index of the first vertex and the pipeline index to the primitive pipeline unit; The vertex storage stores a vertex processing result of the first vertex based on the pipeline index; The primitive pipeline unit performs primitive assembly and primitive processing on the first primitive to which the first vertex belongs based on split initial state information, the multiple vertex indexes and the mapping relationship, and the split initial state information is used to indicate a splitting method for splitting the multiple vertices into at least one primitive.

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