Source electrode driving circuit, source electrode driving chip and display driving method

Abstract

The invention provides a source electrode driving circuit, a source electrode driving chip and a display driving method. The source electrode driving circuit comprises a control circuit used for generating K starting signals; each driving unit is used for latching N paths of data according to an input signal of the input signal end, generating a cascade signal at the cascade signal output end, and outputting the latched N paths of data through the N data signal output ends under the control of an enable signal of the enable signal end, and N is an integer greater than 1. The plurality of driving units are divided into K groups, and the driving units in each group are in cascade connection, so that the cascade signal output end of each stage of driving unit in the group is connected with the input signal end of the next stage of driving unit. The input signal end of the first-stage driving unit in the kth group of driving units is connected with the control circuit, the first-stage driving unit is used for receiving the kth starting signal from the control circuit as an input signal, K is an integer greater than 1, and k = 1, 2,..., K.

Description

Technical Field

[0001] The present disclosure relates to the field of display driving, and in particular to a source driving circuit, a source driving chip and a display driving method. Background Art

[0002] In the field of display technology, the source driver circuit plays a vital role as a driver circuit that provides data signals to sub-pixels. However, the source driver circuit latches data slowly, and often the transmission path of the carry signal in data latching is too long, resulting in a large line resistance. A long line is prone to cause a delay in the carry signal, and if the signal pulse time is short, the large line resistance may even cause the carry signal to disappear, thereby affecting the latching of the data. Summary of the invention

[0003] An embodiment of the present disclosure provides a source driver circuit, comprising: a control circuit for generating K start signals; a plurality of driver units, each of which has an input signal terminal, an enable signal terminal, a cascade signal output terminal and N data signal output terminals, and is used to latch N data according to an input signal of the input signal terminal and generate a cascade signal at the cascade signal output terminal, and output the latched N data through the N data signal output terminals respectively under the control of an enable signal of the enable signal terminal, wherein N is an integer greater than 1; wherein the plurality of driver units are divided into K groups, and the driver units in the group are cascaded so that the cascade signal output terminal of each level of the driver units in the group is connected to the input signal terminal of the next level of the driver unit; wherein the input signal terminal of the first level of the driver unit in the kth group of the driver units is connected to the control circuit, and the first level of the driver unit is used to receive the kth start signal from the control circuit as an input signal, wherein K is an integer greater than 1, k=1, 2, …, K.

[0004] In some examples, the driving unit includes: a shift register having an input end, a first output end, and a second output end, the input end of the shift register serving as an input signal end of the driving unit, the first output end of the shift register serving as a cascade signal output end of the driving unit, the shift register being used to generate a cascade signal and a control signal according to an input signal received at the input end of the shift register, outputting the generated cascade signal through the first output end of the shift register, and outputting the generated control signal through the second output end of the shift register; a latch circuit having an input end, an enable end, and N output ends, the input end of the latch circuit being connected to the second output end of the shift register, the enable end of the latch circuit serving as an enable signal end of the driving unit, the N output ends of the latch circuit serving as N data signal output ends of the driving unit, the latch circuit being used to latch N data according to a control signal received at the input end of the latch circuit, and outputting the latched N data respectively through the N output ends of the latch circuit according to an enable signal received at the enable end of the latch circuit.

[0005] In some examples, the shift register also has a clock terminal, and the shift register is used to generate a cascade signal and a control signal based on a clock signal at the clock terminal in response to receiving an input signal at the input terminal of the shift register, and output the generated cascade signal through a first output terminal of the shift register, and output the generated control signal through a second output terminal of the shift register; wherein the data latch period of the source driver circuit is an integer multiple of the period of the clock signal, and the data latch period is the length of time required for all driver units in each group of driver units to receive the input signal.

[0006] In some examples, the latch circuit includes N channels, each channel having a first input terminal, a second input terminal, an enable terminal and an output terminal, wherein the first input terminal of the nth channel serves as the input terminal of the latch circuit, the second input terminal of the nth channel is configured to collect nth data among N data, the enable terminal of the nth channel serves as the enable terminal of the latch circuit, and the output terminal of the nth channel serves as the nth output terminal among N output terminals of the latch circuit; the nth channel is configured to collect and latch the nth data among the N data at the second input terminal of the nth channel under the control of a control signal received at the first input terminal of the nth channel, and output the latched nth data through the output terminal of the nth channel under the control of an enable signal received at the enable terminal of the nth channel, wherein n=1, 2, …, N.

[0007] In some examples, the channel includes: a latch, a first input terminal of the latch serving as a first input terminal of the channel, a second input terminal of the latch serving as a second input terminal of the channel, an enable terminal of the latch serving as an enable terminal of the channel, an output terminal of the latch connected to an output terminal of the channel, the latch being configured to collect and latch single-channel data from the second input terminal of the latch under the control of the first input terminal of the latch, and to provide the latched single-channel data to the output terminal of the latch under the control of the enable terminal of the latch.

[0008] In some examples, the channel also includes: a digital-to-analog converter, the output end of the latch is connected to the output end of the channel via the digital-to-analog converter, the digital-to-analog converter is used to perform digital-to-analog conversion on the data provided by the latch, and provide the digital-to-analog converted data to the output end of the channel.

[0009] In some examples, the channel further includes: an amplifier, the digital-to-analog converter is connected to the output end of the channel via the amplifier, and the amplifier is used to amplify data from the digital-to-analog converter and provide the amplified data to the output end of the channel.

[0010] In some examples, the latch is an M-bit latch, where M is an integer greater than or equal to one.

[0011] In some examples, where K=2, the plurality of drive units are divided into a first group of drive units and a second group of drive units, the control circuit is located in a region between the first group of drive units and the second group of drive units, an input signal end of a first-stage drive unit in the first group of drive units is configured to receive a first start signal from the control circuit as an input signal, and an input signal end of a first-stage drive unit in the second group of drive units receives a second start signal from the control circuit as an input signal.

[0012] In some examples, K=4, the plurality of drive units are divided into a first group of drive units, a second group of drive units, a third group of drive units, and a fourth group of drive units, the control circuit is located between the second group of drive units and the third group of drive units, the first group of drive units is located on a side of the second group of drive units away from the control circuit, and the fourth group of drive units is located on a side of the third group of drive units away from the control circuit; the input signal end of the first-stage drive unit in the first group of drive units is configured to receive a first start signal from the control circuit as an input signal; the input signal end of the first-stage drive unit in the second group of drive units is configured to receive a second start signal from the control circuit as an input signal; the input signal end of the first-stage drive unit in the third group of drive units is configured to receive a third start signal from the control circuit as an input signal; the input signal end of the first-stage drive unit in the fourth group of drive units is configured to receive a fourth start signal from the control circuit as an input signal.

[0013] In some examples, the number of driving units in each group of driving units is equal, and the K start signals are the same.

[0014] In some examples, the driving unit is configured to generate a cascade signal based on a clock signal, and the data latch period of the source driving circuit is T times the period of the clock signal, and the data latch period is the length of time required for all driving units in each group of driving units to receive the input signal, where T=S / K, S represents the total number of multiple driving units, and T is an integer greater than 1.

[0015] In some examples, N is an integer multiple of 3.

[0016] The embodiments of the present disclosure further provide a source driver chip, including the source driver circuit of the embodiments of the present disclosure.

[0017] An embodiment of the present disclosure also provides a display device, comprising: a plurality of sub-pixels arranged in an array; a gate driving circuit, connecting each sub-pixel in the array through a plurality of gate lines, the gate driving circuit being used to provide a scanning signal to each sub-pixel to turn on each sub-pixel; a source driving chip of an embodiment of the present disclosure, connecting each sub-pixel in the array through a plurality of data lines, the source driving chip being used to provide a data signal to each sub-pixel so that the turned-on sub-pixel performs display based on the received data signal.

[0018] In some examples, multiple sub-pixels are arranged into an array of pixel units, each pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel; the N data signal output terminals of each driving unit are connected to H columns of pixel units through N data lines, where N=3×H, and H is an integer greater than or equal to 1.

[0019] The embodiment of the present disclosure also provides a display driving method, which is performed by the source driving circuit of the embodiment of the present disclosure, and the method includes: the control circuit generates K start signals and provides them to K groups of driving units respectively; in the kth group of driving units, the first-level driving unit receives the kth start signal from the control circuit as an input signal, latches N-way data according to the input signal and generates a cascade signal; each level of driving unit except the first-level driving unit receives the cascade signal generated by the previous level of driving unit as an input signal, latches the corresponding N-way data according to the input signal and generates a cascade signal, wherein k=1, 2,…, K; each driving unit provides the latched N-way data to its own N data signal output terminals respectively under the control of the enable signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic block diagram of a display device according to an embodiment of the present disclosure is shown.

[0021] Figure 2 A schematic block diagram of a source driving circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 3 The connection between the driving unit and the sub-pixel in the source driving circuit according to the embodiment of the present disclosure is shown.

[0023] Figure 4 An example structure of a driving unit in a source driving circuit according to an embodiment of the present disclosure is shown.

[0024] Figure 5 Another exemplary structure of a driving unit in a source driving circuit according to an embodiment of the present disclosure is shown.

[0025] Figure 6 A flow chart of a driving method performed by a source driving circuit according to an embodiment of the present disclosure is shown.

[0026] FIG. 7A to FIG. 7B Shows Figure 2 Schematic diagram of a driving method performed by a source driving circuit.

[0027] Figure 8 Shows Figure 2 Signal timing diagram of the source driver circuit.

[0028] Fig. 9A schematic block diagram of a source driving circuit according to another embodiment of the present disclosure is shown.

[0029] FIG. 10A to FIG. 10D Shows Fig. 9 Schematic diagram of a driving method performed by a source driving circuit.

[0030] Fig.11 Shows Fig. 9 Signal timing diagram of the source driver circuit. DETAILED DESCRIPTION

[0031] Although the present disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments of the present disclosure, it should be understood before this description that a person of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the above description is a broad disclosure to a person of ordinary skill in the art, and its content is not intended to limit the exemplary embodiments described in the present disclosure.

[0032] In addition, in the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments may be implemented without these specific details. In other cases, known structures and devices are embodied in a schematic manner to simplify the accompanying drawings.

[0033] Figure 1 A schematic block diagram of a display device according to an embodiment of the present disclosure is shown.

[0034] like Figure 1 As shown, the display device includes a source driver 10, a gate driver 20, and a plurality of sub-pixels 30 arranged in an array. The source driver 10 connects the sub-pixels 30 in the array through a plurality of data lines S, and the gate driver 20 connects the sub-pixels 30 in the array through a plurality of gate lines G. As an example, each gate line G connects a row of sub-pixels 30, and each data line S connects a column of sub-pixels 30. However, the embodiments of the present disclosure are not limited thereto, and each gate line G may also connect two or more rows of sub-pixels, and each data line S may connect two or more columns of sub-pixels.

[0035] In some embodiments, a plurality of sub-pixels 30, gate lines G, and data lines S may be disposed in a display panel, and a source driver 10 may be implemented in the form of a chip (hereinafter referred to as a source driver chip), for example, connected to a data line S in a display panel through a pin on the display panel. The gate driver 20 may be implemented as a gate drive circuit (hereinafter referred to as a gate drive circuit 20), which may be disposed in the display panel and connected to the gate line G in the display panel. However, the embodiments of the present disclosure are not limited thereto, and the gate drive circuit 20 may also be disposed outside the display panel, which is not limited here.

[0036] In some embodiments, the sub-pixels 30 may be arranged into an array of pixel units, where the pixel unit includes a group of sub-pixels of multiple colors, such as red sub-pixels, green sub-pixels, and blue sub-pixels, which will be described in detail below.

[0037] The gate drive circuit 20 can provide a scan signal to each sub-pixel 30 to turn on each sub-pixel. For example, the gate drive circuit 20 can apply a scan signal to multiple gate lines G in sequence, and the scan signal on each gate line G is provided to the corresponding row of sub-pixels 30 connected to the gate line G, so as to turn on this row of sub-pixels 30. In this way, each row of sub-pixels can be turned on in sequence. The order of turning on can be set as needed, for example, the first row of sub-pixels can be turned on first, then the second row of sub-pixels, until the last row of sub-pixels; each row of sub-pixels can also be turned on in order from the last row to the first row; two or more rows of sub-pixels can also be turned on each time, or odd rows of sub-pixels can be turned on in sequence first, and then even rows of sub-pixels can be turned on in sequence, and so on, which is not limited here.

[0038] The source driver chip 10 can provide data signals to each sub-pixel 30, so that the turned-on sub-pixels 30 display based on the received data signals. For example, after the gate driver circuit 20 turns on the first row of sub-pixels, the source driver chip 10 can apply data signals to each data line S, so that the turned-on row of sub-pixels receives corresponding data signals through each data line S and displays based on the received data signals.

[0039] In some embodiments, the display device may further include a timing controller 40. The timing controller may provide the required signals to the gate drive circuit 20 and the source drive chip 10. The signals provided by the timing controller 40 to the source drive chip 10 include image data signals and various control signals, such as but not limited to a line start signal (Start Horizontal, STH), a clock signal (also referred to as a line clock pulse signal (Clock Pulse Horizontal, CPH)), a data transmission control signal Load, and a data polarity inversion signal POL. The signals provided by the timing controller 40 to the gate drive circuit 20 include but are not limited to a frame start signal (Start Vertical, STV) representing the start of a frame scan, a scan clock pulse signal (Clock Pulse Vertical, CPV), and the like.

[0040] The embodiment of the present disclosure provides a source driving circuit, which may be included in a source driving chip, such as the one described above. Figure 1 In the source driver chip described above, the data signal generated by the source driver circuit is provided to each data line. Figure 2To describe an example structure of a source driver circuit.

[0041] Figure 2 A schematic block diagram of a source driving circuit according to an embodiment of the present disclosure is shown.

[0042] like Figure 2 As shown, the source driving circuit includes a control circuit 110 and a plurality of driving units DR1 to DR320. Each driving unit has an input signal terminal In, an enable signal terminal OE, a cascade signal output terminal C and N data signal output terminals O1, O2, ..., O6, where N is an integer greater than 1 (N=6 is used for schematic illustration here). Each driving unit can latch N data according to the input signal of the input signal terminal In and generate a cascade signal at the cascade signal output terminal C, and output the latched N data respectively through the N data signal output terminals O1, O2, ..., O6 under the control of the enable signal of the enable signal terminal OE.

[0043] The N data signal output terminals of each driving unit are respectively connected to N data lines. Figure 2 The data signal output terminals O1 to O6 of the driving unit DR1 are connected to the data lines S1 to S6 in a one-to-one correspondence, the data signal output terminals O1 to O6 of the driving unit DR2 are connected to the data lines S7 to S12 in a one-to-one correspondence, and so on.

[0044] In some embodiments, N may be an integer multiple of 3, because in most display devices, a pixel unit uses red, green, and blue sub-pixels as a pixel unit. By setting N to a multiple of 3, each driving unit can drive one or more pixel units. Figure 3 As shown, a plurality of sub-pixels are arranged into an array of pixel units, each pixel unit includes a red sub-pixel, a green sub-pixel and a blue sub-pixel. For example, the first pixel unit includes a red sub-pixel R1, a green sub-pixel G1 and a blue sub-pixel B1, the second pixel unit includes a red sub-pixel R2, a green sub-pixel G2 and a blue sub-pixel B2, the third pixel unit includes a red sub-pixel R3, a green sub-pixel G3 and a blue sub-pixel B3, and so on. The N data signal output terminals of each driving unit can be connected to H columns of pixel units through N data lines, where N=3×H, and H is an integer greater than or equal to 1. Also, taking N=6 as an example, assuming H=2, then the 6 data signal output terminals of each driving unit will be connected to two columns of pixel units through six data lines. For example, see Figure 3, the driving unit DR1 is connected to the sub-pixels R1, G1, B1, R2, G2, B2 one-to-one through the data lines S1 to S6, that is, the first and second pixel units are connected; the driving unit DR2 is connected to the sub-pixels R3, G3, B3, R4, G4, B4 one-to-one through the data lines S7 to S12, that is, the third and fourth pixel units are connected, and so on. In this way, each driving unit can provide data signals to two columns of pixel units (for example, each pixel unit in the two columns of pixel units includes three RGB sub-pixels) through six data lines. It should be noted that Figure 3 For the sake of simplicity, Figure 3 A row of sub-pixels is taken as an example for schematic illustration, and other rows of sub-pixels are arranged in a similar manner, which will not be repeated here.

[0045] According to an embodiment of the present disclosure, the plurality of driving units DR1 to DR320 can be divided into K groups, and the driving units in the group are cascaded so that the cascade signal output terminal C of each level of driving unit in the group is connected to the input signal terminal In of the next level of driving unit. For example, K can be 2. In this case, the driving units DR1 to DR320 can be divided into two groups. Figure 2 In the example of , the first group includes driving units DR1 to DR160, and the second group includes driving units DR161 to DR320. In the first group of driving units DR1 to DR160, the cascade signal output terminal C of the first-stage driving unit DR1 is connected to the input signal terminal In of the second-stage driving unit DR2, and the cascade signal output terminal C of the second-stage driving unit DR2 is connected to the input signal terminal In of the third-stage driving unit DR3, and so on, until the last-stage driving unit DR160. The cascade signal output terminal C of the last-stage driving unit DR160 can be floated. In this way, the cascade of the first group of driving units DR1 to DR160 is realized. In the same way, in the second group of driving units DR161 to DR320, the cascade signal output terminal C of the first-stage driving unit DR161 is connected to the input signal terminal In of the second-stage driving unit DR162, and the cascade signal output terminal C of the second-stage driving unit DR162 is connected to the input signal terminal In of the third-stage driving unit DR163, and so on, until the last-stage driving unit DR320. In this way, the cascade connection of the second group of driving units DR161 to DR320 is achieved.

[0046] According to an embodiment of the present disclosure, the control circuit 110 may generate K start signals, which are provided to K groups of driving units respectively, wherein the input signal terminal of the first-stage driving unit in the k-th group of driving units is connected to the control circuit, and the first-stage driving unit is used to receive the k-th start signal from the control circuit 110 as an input signal, wherein K is an integer greater than 1, k=1, 2,…, K. For example, in Figure 2In the example, the driving units are divided into two groups, and the control circuit 110 can generate two start signals, namely, a first start signal LSR_1 and a second start signal RSR_1. The first start signal LSR_1 is provided to the first-stage driving unit DR1 in the first group of driving units DR1 to DR160, and the second start signal RSR_1 is provided to the first-stage driving unit DR161 in the second group of driving units DR161 to DR320.

[0047] like Figure 2 As shown, in the first group of driving units DR1 to DR160, the input signal terminal In of the first-stage driving unit DR1 receives the first start signal LSR_1 as an input signal, the second-stage driving unit DR2 receives the cascade signal output by the cascade signal output terminal C of the first-stage driving unit DR1 as an input signal at the input signal terminal In, and the third-stage driving unit DR3 receives the cascade signal of the cascade signal output terminal C of the second-stage driving unit DR2 as an input signal at the input signal terminal In, and so on. The first-stage driving unit DR1 can latch the first to sixth paths of data according to the received input signal LSR_1, and the second-stage driving unit DR2 can latch the seventh to twelfth paths of data according to the received input signal LSR_2, and so on. In this way, the first group of driving units DR1 to DR160 completes their respective data latching step by step under the control of the first start signal LSR_1. The second group of driving units DR161 to DR320 are cascaded in a manner similar to the first group, so that data latching can be completed step by step under the control of the second start signal RSR_1, which will not be repeated here.

[0048] When the effective level of the enable signal of the enable signal terminal OE arrives, the driving unit DR1 can output the latched first to sixth data through the data signal output terminals O1, O2, ..., O6, respectively, so as to be applied to the data lines S1 to S6; the driving unit DR2 can output the latched seventh to twelfth data through the data signal output terminals O1, O2, ..., O6 of the second-level driving unit DR2, respectively, so as to be applied to the data lines S7 to S12, and so on. In this way, the driving units DR1 to DR320 apply the multiple data latched by each of them to the corresponding data lines under the control of the enable signal, thereby completing the data output to the data lines S1 to S1920.

[0049] In some embodiments, Figure 2 As shown, the control circuit 110 can be arranged between two groups of driving units, that is, between the first group of driving units DR1 to DR160 and the second group of driving units DR161 to DR320. The driving units DR1 to DR320 can be arranged in this order along one direction. Figure 2The horizontal direction is shown in FIG. 1 , and the control unit 110 is located in the gap between the driving units 160 and 161. With this arrangement, the difference in distances from the control unit 110 to the two groups of driving units can be reduced, thereby minimizing the difference in wiring resistances to the two groups of driving units.

[0050] In the above embodiment, 320 driving units, each of which has 6 output signal terminals, are used as an example for description, so that the output terminal of each driving unit is connected to 6 data lines, and the 320 driving units can apply data signals to 1920 data lines S1 to S1920 in total. However, the embodiments of the present disclosure are not limited thereto, and the number of driving units and the number of output signal terminals of the driving units can be set as needed.

[0051] In the above embodiment, the number of driving units in each group is equal, however, the embodiments of the present disclosure are not limited thereto, and for any two groups of driving units, the number of driving units in each group may be equal or unequal.

[0052] The embodiment of the present disclosure shortens the transmission path of the carry signal (the cascade signal of each level of the drive unit) by driving the drive units in groups, for example, from passing through 320 drive units to only passing through 160 drive units, so that the time required for data latching of the source drive circuit can be reduced and the driving speed can be improved. At the same time, due to the shortening of the transmission path, the resistance and signal delay on the path are also reduced accordingly, which is conducive to improving the quality of data latching.

[0053] Figure 4 An example structure of a driving unit in a source driving circuit according to an embodiment of the present disclosure is shown.

[0054] like Figure 4 As shown, the driving unit includes a shift register 1101 and a latch circuit 1102 .

[0055] The shift register 1101 has an input terminal, a first output terminal, and a second output terminal. The input terminal of the shift register 1101 serves as the input signal terminal In of the driving unit, and the first output terminal of the shift register 1101 serves as the cascade signal output terminal C of the driving unit. The second output terminal of the shift register 1101 is connected to the latch circuit 1102. The shift register 1101 can generate a cascade signal and a control signal according to the input signal received at its input terminal (i.e., the input signal terminal In of the driving unit), output the generated cascade signal through the first output terminal of the shift register (i.e., the cascade signal output terminal C of the driving unit), and output the generated control signal Ctr to the latch circuit 1102 through the second output terminal of the shift register.

[0056] The latch circuit 1102 has an input terminal, an enable terminal and N output terminals. The input terminal of the latch circuit is connected to the second output terminal of the shift register to receive the control signal Ctr provided by the shift register 1101. The enable terminal of the latch circuit 1102 serves as the enable signal terminal OE of the driving unit, and the N output terminals of the latch circuit serve as the N data signal output terminals O1 to O6 of the driving unit. The latch circuit can latch N-channel data according to the control signal Ctr received by the input terminal of the latch circuit, and output the latched N-channel data through the N output terminals of the latch circuit (i.e., the N data signal output terminals O1 to O6 of the driving unit) according to the enable signal received by the enable terminal of the latch circuit (i.e., the enable signal terminal OE of the driving unit). The embodiment of the present disclosure realizes a driving unit that can be driven in groups with a simple circuit structure by means of a shift register and a latch circuit.

[0057] like Figure 4 As shown, the latch circuit includes N channels CH1 to CH6, each channel latches one data path among the N data paths, and outputs it to a corresponding one of the N data signal output terminals O1 to O6. For example, channel CH1 latches the first data path and outputs it through the data signal output terminal O1, channel CH2 latches the second data path and outputs it through the data signal output terminal O2, channel CH3 latches the second data path and outputs it through the data signal output terminal O3, and so on.

[0058] According to an embodiment of the present disclosure, each channel CH1 to CH6 may have a first input terminal, a second input terminal, an enable terminal and an output terminal. For the nth channel, its first input terminal serves as an input terminal of the latch circuit 1102 to receive the control signal Ctr from the shift register 1101, the second input terminal collects the nth data DATA in the N-channel data, the enable terminal serves as an enable terminal OE of the latch circuit to receive the enable signal, and the output terminal serves as the nth output terminal On of the N output terminals of the latch circuit, where n=1,2, …, N. Reference Figure 4 , channel CH1 can collect and latch the first data DATA among N data at the second input terminal under the control of the control signal Ctr received at the first input terminal, and output the latched first data DATA through the output terminal O1 under the control of the enable signal received at the enable terminal OE. In a similar manner, channel CH2 can collect and latch the second data among N data at the second input terminal under the control of the control signal Ctr, and output the latched second data through the output terminal O2 under the control of the enable signal received at the enable terminal OE, and so on. Figure 4 For the sake of simplicity, only the enable terminal (as the enable terminal OE of the driving unit) and the second input terminal (collecting the first data DATA) of channel CH1 are shown. By setting multiple channels, each channel works independently without affecting each other.

[0059] In some embodiments, Figure 4 As shown, the channel may include a latch, for example, the channel CH1 includes a latch LAT1, the channel CH2 includes a latch CH2, and so on. Taking the channel CH1 as an example, the first input end of the latch LAT1 can be used as the first input end of the channel to receive the control signal Ctr from the shift register 1101. The second input end of the latch LAT1 can be used as the second input end of the channel to receive the first data signal DATA. The enable end of the latch LAT1 can be used as the enable end of the channel (i.e., the enable end OE of the driving unit) to receive the enable signal. The output end of the latch LAT1 can be connected to the output end of the channel (i.e., the output end O1 of the driving unit). The latch LAT1 can collect and latch the single-channel data DATA from the second input end of the latch LAT1 under the control of the control signal Ctr received at the first input end of the latch LAT1, and provide the latched single-channel data DATA to the output end of the latch LAT1 under the control of the enable end OE of the latch LAT1, and then provide it to the output end O1. Channels CH2 to CH6 have the same structure and operate in a similar manner, which will not be described in detail here.

[0060] In some embodiments, the channel may further include a digital-to-analog converter, for example, channel CH1 also includes a digital-to-analog converter DAC1, channel CH2 also includes a digital-to-analog converter DAC2, and so on. Also taking channel CH1 as an example, the output end of latch LAT1 is connected to the output end O1 of the channel via the digital-to-analog converter DAC1, and the digital-to-analog converter DAC may perform digital-to-analog conversion on the data provided by latch LAT1, and provide the digital-to-analog converted data to the output end O1 of the channel. Channels CH2 to CH6 have the same structure and work in a similar manner, which will not be described in detail here. By setting a digital-to-analog converter, the source drive circuit can output an analog signal, adapt to pixels that require analog drive, and simplify the panel side structure.

[0061] In some embodiments, the channel may further include an amplifier, for example, channel CH1 may further include an amplifier AMP1, channel CH2 may further include an amplifier AMP2, and so on. Also taking channel CH1 as an example, the digital-to-analog converter DAC1 is connected to the output terminal O1 of channel CH1 via the amplifier AMP1, and the amplifier AMP1 is used to amplify the data from the digital-to-analog converter DAC1 and provide the amplified data to the output terminal O1 of channel CH1. Channels CH2 to CH6 have the same structure and are not described here. By setting an amplifier, the analog signal output by the digital-to-analog converter can be amplified to improve the driving capability.

[0062] In some embodiments, the latches LAT1 to LAT6 in the channel may be M-bit latches, where M is an integer greater than or equal to 1. In this way, the latch circuit 1102 has N channels, each channel latches M-bit data, so that the latch circuit 1102 can latch M×N image data, greatly improving the latching efficiency.

[0063] Figure 5 Another exemplary structure of a driving unit in a source driving circuit according to an embodiment of the present disclosure is shown.

[0064] like Figure 5 As shown, the shift register 1101 has a clock terminal CLK in addition to an input signal terminal In and a cascade signal output terminal C. The shift register 1101 can generate a cascade signal and a control signal based on a clock signal of the clock terminal CLK in response to receiving an input signal at the input terminal In, and output the generated cascade signal through the first output terminal of the shift register 1101 (i.e., the cascade signal output terminal C of the driving unit), and output the generated control signal Ctr through the second output terminal of the shift register 1101.

[0065] In some embodiments, the display device may further include a reference signal generating circuit 50, and the digital-to-analog converters DAC1 to DAC6 in each driving unit in the source driving circuit are connected to the reference signal generating circuit 50 to receive the reference voltage signal provided by it. For example, the reference signal generating circuit 50 can provide multiple reference voltage signals, such as grayscale voltages, and each digital-to-analog converter DAC1 to DAC6 converts the digital signal provided by the corresponding latch into an analog voltage signal according to the received multiple reference voltage signals. The reference signal generating circuit can be a gamma voltage generating circuit (also referred to as a gamma circuit) to generate multiple grayscale voltages as multiple input signals respectively. The gamma voltage generating circuit, for example, includes one or more resistor strings to generate, for example, multiple reference voltage signals with equal voltage differences for generating grayscale voltage signals. Figure 5 For the sake of simplicity, only the connection between the digital-to-analog converter DAC1 and the reference signal generating circuit 50 is shown, and other digital-to-analog converters are connected in the same way, which will not be repeated here.

[0066] Figure 6 The flowchart of the driving method performed by the source driving circuit according to the embodiment of the present disclosure is shown. The method is applicable to the source driving circuit of any of the above embodiments.

[0067] like Figure 6 As shown, in operation s110, the control circuit generates K start signals and provides them to K groups of driving units respectively.

[0068] In operation s120, in the kth group of driving units, the first-stage driving unit receives the kth start signal from the control circuit as an input signal, latches N-way data according to the input signal and generates a cascade signal; each stage of driving unit except the first-stage driving unit receives the cascade signal generated by the previous stage of driving unit as an input signal, latches corresponding N-way data according to the input signal and generates a cascade signal, where k=1, 2, …, K.

[0069] In operation s130 , each driving unit provides the latched N-channel data to its own N data signal output terminals respectively under the control of the enable signal.

[0070] FIG. 7A to FIG. 7B Shows Figure 2 Schematic diagram of the driving method performed by the source driving circuit of FIG. Figure 2 and Figure 3 The circuit structure of Fig. 7A and Figure 7B The driving method is schematically described. The data signals to be latched are divided into odd-numbered column data signals and even-numbered column data signals. Figures 7A to 7B "ODD" in represents odd-numbered columns, "EVEN" represents even-numbered columns, R represents red sub-pixels, G represents green sub-pixels, and B represents blue sub-pixels.

[0071] Combination Figure 2 , Figure 3 , Fig. 7A and Figure 7B In the first stage, the control circuit generates start signals LSR_1 and RSR_1, which are respectively provided to the first-stage driving unit DR1 in the first group and the first-stage driving unit DR161 in the second group.

[0072] In the second phase, the first group of driving units DR1 to DR160 completes the step-by-step data latching based on the start signal LSR_1 , and the second group of driving units DR161 to DR320 completes the step-by-step data latching based on the start signal RSR_1 .

[0073] In the first group of driving units DR1 to DR160, the driving unit DR1 latches 6 data based on the received start signal LSR_1, and the 6 data are respectively used to drive the two columns of pixel units connected thereto, see Figure 3The driving unit DR1 also generates a cascade signal as an input signal LSR_2 of the driving unit DR2 based on the received start signal LSR_1. The driving unit DR2 latches 6 data for sub-pixels R3, G3, B3, R4, G4, and B4 based on the received input signal LSR_2. In a similar manner, the driving unit DR3 latches 6 data for sub-pixels R5, G5, B5, R6, G6, and B6 based on the input signal LSR_3 provided by the driving unit DR2, and so on, until the last driving unit DR160 in the first group latches 6 data for sub-pixels R319, G319, B319, R320, G320, and B320 based on the input signal LSR_160 provided by the previous driving unit 159. In this way, the first group of driving units DR1 to DR160 completes data latching.

[0074] The second group of driving units DR161 to DR320 completes data latching step by step in a similar manner. Figures 7A to 7B As shown, the driving unit DR161 latches 6 data for sub-pixels R321, G321, B321, R322, G322, and B322 based on the received start signal RSR_1, and generates a cascade signal as the input signal RSR_2 of the driving unit DR162. The driving unit DR162 latches 6 data for sub-pixels R323, G323, B323, R324, G324, and B324 based on the input signal RSR_2, and so on, until the driving unit DR320 latches 6 data for sub-pixels R639, G639, B639, R640, G640, and B640. In this way, the second group of driving units DR161 to DR320 completes data latching.

[0075] Next, each driving unit can output the 6-way data latched by each driving unit to its six data signal output terminals under the control of the enable signal, so as to provide the corresponding sub-pixels through the corresponding data lines. Figure 3 , Fig. 7A and Figure 7B , the driving unit DR1 outputs the latched six-way data to the data lines S1 to S6 respectively, so that the six-way data is provided to the corresponding sub-pixels R1, G1, B1, R2, G2, and B2. In a similar manner, the driving unit DR2 provides the latched six-way data to the sub-pixels R3, G3, B3, R4, G4, and B4 through the data lines S7 to S12, and the driving unit DR3 provides the latched six-way data to the sub-pixels R5, G5, B5, R6, G6, and B6 through the data lines S13 to S18, and so on.

[0076] Figure 8 Shows Figure 2Signal timing diagram of the source driver circuit.

[0077] like Figure 8 As shown, in the first stage, the control circuit generates start signals LSR_1 and RSR_1, which are respectively provided to the first-stage driving unit DR1 in the first group and the first-stage driving unit DR161 in the second group. In the following second stage, the start signals LSR_1 and RSR_1 enable the first group of driving units DR1 to DR160 and the second group of driving units DR161 to DR320 to start data latching stage by stage at the same time.

[0078] exist Figure 2 In the example of FIG. 1 , the number of driving units in each group of driving units is equal. In this case, the K start signals generated by the control circuit may be the same, such as Figure 8 As shown, the start signals LSR_1 and RSR_1 can be implemented as the same signal. By making the number of driving units equal, the latching time can be shortened by multiples, which is conducive to flexible control of the data latching cycle.

[0079] According to an embodiment of the present disclosure, the data latch period of the source driver circuit may be an integer multiple of the period of the clock signal. The so-called data latch period here may be the length of time required for all the drive units in each group of drive units to receive the input signal. Figure 8 In the example, since the number of driving units in each group is equal, the time length required for each group of driving units is the same, and the data latch period can be defined as the time length between the rising edge of the input signal of the first-level driving unit and the rising edge of the input signal of the last-level driving unit in the group. For example, T times the period of the clock signal, where T=S / K, S represents the total number of the plurality of driving units, and T is an integer greater than 1. Figure 2 For example, S=320, K=2, so T=160, the data latch period of the source drive circuit is 160 times the clock signal period. In this way, the data latch period can be flexibly adjusted. For example, the data latch period can be adjusted by adjusting the clock period. The data latch period can also be adjusted by adjusting the number of drive units and the number of drive unit groups.

[0080] Compared with not grouping the driving units and latching data step by step from the first level to the last level, the driving method of the embodiment of the present disclosure can greatly save the latching time by grouping the driving units. Figure 2 By dividing into two groups as shown, the latching time can be halved.

[0081] Fig. 9 A schematic block diagram of a source driving circuit according to another embodiment of the present disclosure is shown. Fig. 9 The source drive circuit and Figure 2Similar, the difference is that K=4, that is, the drive units are divided into four groups. For the sake of simplicity, the following will mainly explain the differences in detail.

[0082] like Fig. 9 As shown in FIG. 1 , 320 drive units are also used as an example, each of which has 6 channels. Figure 2 The difference is that K=4, and the multiple drive units are divided into the first group of drive units DR1 to DR80, the second group of drive units DR81 to DR160, the third group of drive units DR161 to DR240 and the fourth group of drive units DR241-DR320. Each group of drive units is cascaded, and the cascade method is as shown in the reference above. Figure 2 The first group of driving units DR1 to DR80 is located on the side of the second group of driving units DR81 to DR160 away from the control circuit 110, and the fourth group of driving units DR241-DR320 is located on the side of the third group of driving units DR161 to DR240 away from the control circuit 110. The control circuit 110 may be located between the second group of driving units DR81 to DR160 and the third group of driving units DR161 to DR240. Figure 2 , the drive units DR1 to DR320 can be arranged along one direction, so that the first to fourth groups of drive units are arranged in this order along one direction ( Figure 2 The control circuit 110 is located between the driving units 160 and 161.

[0083] The control circuit 110 generates four start signals LSR1_1 , LSR2_1 , RSR1_1 , and RSR2_1 .

[0084] The input signal terminal In of the first-stage driving unit DR1 in the first group of driving units receives the first start signal LSR1_1 from the control circuit 110 as an input signal. The input signal terminal In of the first-stage driving unit DR81 in the second group of driving units receives the second start signal LSR2_1 from the control circuit 110 as an input signal. The input signal terminal In of the first-stage driving unit DR161 in the third group of driving units receives the third start signal RSR1_1 from the control circuit 110 as an input signal. The input signal terminal In of the first-stage driving unit DR241 in the fourth group of driving units receives the fourth start signal RSR1_1 from the control circuit 110 as an input signal. In this way, the four start signals LSR1_1, LSR2_1, RSR1_1 and RSR2_1 can enable the four groups of driving units to start data latching at the same time, and the latching method is the same as Figure 2Similarly, in response to the enable signal of the enable signal terminal OE, each driving unit DR1 to DR320 can provide the 6 data signals latched by each driving unit DR1 to DR320 to the respective output signal terminals O1 to O6, thereby realizing data output to the data signal lines S1 to S1920.

[0085] References Figure 6 The described drive method also applies to Fig. 9 The following will refer to FIG. 10A to FIG. 11 Let me explain this.

[0086] FIG. 10A to FIG. 10D Shows Fig. 9 Schematic diagram of a driving method performed by a source driving circuit. Fig.11 Shows Fig. 9 Signal timing diagram of the source driver circuit.

[0087] See also FIG. 10A to FIG. 10D , Fig. 9 The working mode of each drive unit is similar to Figure 2 Similarly, the difference lies in the different grouping methods of the driving units. The first group of driving units DR1 to DR80 responds to the first start signal LSR1_1 to latch data step by step, thereby completing the data latching of the 1st to 160th column pixel units (providing 480 sub-pixels) for output to the data lines S1 to S480; in a similar manner, the second group of driving units DR81 to DR160 responds to the second start signal LSR2_1 to latch data step by step, thereby completing the data latching of the 161st to 320th column pixel units for output to the data lines S481 to S960, and so on.

[0088] See also Fig.11 , it can be seen that compared with Figure 8 In the case of two groups, when the drive units are divided into four groups, the data latching period is reduced to 80 times the clock signal period; if the drive units are not grouped and latched step by step from the first stage to the last stage, the data latching period will be 320 times the clock period. Fig.11 In the embodiment, the data latch period is reduced to 1 / 4 of the original period.

[0089] Those skilled in the art can understand that the embodiments described above are exemplary and can be improved by those skilled in the art. The structures described in various embodiments can be freely combined without causing conflicts in structure or principle.

[0090] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation methods of the exemplary embodiments listed in the specification.

Claims

1. A source driving circuit, comprising: A control circuit, used for generating K start signals; A plurality of driving units, each of which has an input signal terminal, an enable signal terminal, a cascade signal output terminal and N data signal output terminals, and is used to latch N data according to an input signal of the input signal terminal and generate a cascade signal at the cascade signal output terminal, and output the latched N data through the N data signal output terminals respectively under the control of the enable signal of the enable signal terminal, wherein N is an integer greater than 1; The plurality of driving units are divided into K groups, and the driving units in the group are connected in cascade, so that the cascade signal output end of each level of driving unit in the group is connected to the input signal end of the next level of driving unit; Among them, the input signal end of the first-stage driving unit in the k-th group of driving units is connected to the control circuit, and the first-stage driving unit is used to receive the k-th start signal from the control circuit as an input signal, where K is an integer greater than 1, k=1, 2, …, K.

2. The source driving circuit according to claim 1, wherein: The driving unit comprises: A shift register having an input end, a first output end, and a second output end, wherein the input end of the shift register serves as an input signal end of the driving unit, and the first output end of the shift register serves as a cascade signal output end of the driving unit. The shift register is used to generate a cascade signal and a control signal according to an input signal received by the input end of the shift register, output the generated cascade signal through the first output end of the shift register, and output the generated control signal through the second output end of the shift register; A latch circuit comprises an input terminal, an enable terminal and N output terminals, wherein the input terminal of the latch circuit is connected to the second output terminal of the shift register, the enable terminal of the latch circuit serves as the enable signal terminal of the driving unit, and the N output terminals of the latch circuit serve as the N data signal output terminals of the driving unit. The latch circuit is used to latch N data according to a control signal received at the input terminal of the latch circuit, and to output the latched N data respectively through the N output terminals of the latch circuit according to the enable signal received at the enable terminal of the latch circuit.

3. The source driving circuit according to claim 2, wherein: The shift register further has a clock terminal, and the shift register is used to generate a cascade signal and a control signal based on a clock signal at the clock terminal in response to receiving an input signal at the input terminal of the shift register, and output the generated cascade signal through the first output terminal of the shift register, and output the generated control signal through the second output terminal of the shift register; The data latching period of the source driving circuit is an integral multiple of the period of the clock signal, and the data latching period is the length of time required for all driving units in each group of driving units to receive the input signal.

4. The source driving circuit according to any one of claims 2 or 3, wherein: The latch circuit includes N channels, each channel having a first input terminal, a second input terminal, an enable terminal and an output terminal, wherein the first input terminal of the nth channel serves as the input terminal of the latch circuit, the second input terminal of the nth channel is configured to collect the nth data among the N data, the enable terminal of the nth channel serves as the enable terminal of the latch circuit, and the output terminal of the nth channel serves as the nth output terminal among the N output terminals of the latch circuit; The nth channel is configured to collect and latch the nth data among N data at the second input end of the n channel under the control of the control signal received at the first input end of the n channel, and output the latched nth data through the output end of the n channel under the control of the enable signal received at the enable end of the n channel, where n=1,2, …,N.

5. The source driving circuit according to claim 4, wherein: The channel comprises: A latch, wherein the first input end of the latch serves as the first input end of the channel, the second input end of the latch serves as the second input end of the channel, the enable end of the latch serves as the enable end of the channel, and the output end of the latch is connected to the output end of the channel, The latch is configured to collect and latch single-channel data from the second input terminal of the latch under the control of the first input terminal of the latch, and provide the latched single-channel data to the output terminal of the latch under the control of the enable terminal of the latch.

6. The source driving circuit according to claim 5, wherein: The channel also includes: a digital-to-analog converter, the output end of the latch is connected to the output end of the channel via the digital-to-analog converter, and the digital-to-analog converter is used to perform digital-to-analog conversion on the data provided by the latch and provide the converted data to the output end of the channel.

7. The source driving circuit according to claim 6, wherein: The channel further includes an amplifier, the digital-to-analog converter is connected to the output end of the channel via the amplifier, and the amplifier is used to amplify data from the digital-to-analog converter and provide the amplified data to the output end of the channel.

8. The source driving circuit according to any one of claims 5 to 7, wherein: The latch is an M-bit latch, where M is an integer greater than or equal to 1.

9. The source driving circuit according to any one of claims 1 to 8, wherein K=2, the plurality of driving units are divided into a first group of driving units and a second group of driving units, and the control circuit is located in a region between the first group of driving units and the second group of driving units, The input signal end of the first stage driving unit in the first group of driving units is configured to receive a first start signal from the control circuit as an input signal, and the input signal end of the first stage driving unit in the second group of driving units receives a second start signal from the control circuit as an input signal.

10. The source driving circuit according to any one of claims 1 to 8, wherein K=4, the plurality of driving units are divided into a first group of driving units, a second group of driving units, a third group of driving units and a fourth group of driving units, the control circuit is located between the second group of driving units and the third group of driving units, the first group of driving units is located on a side of the second group of driving units away from the control circuit, and the fourth group of driving units is located on a side of the third group of driving units away from the control circuit; The input signal terminal of the first stage driving unit in the first group of driving units is configured to receive a first start signal from the control circuit as an input signal; The input signal terminal of the first stage driving unit in the second group of driving units is configured to receive a second start signal from the control circuit as an input signal; The input signal terminal of the first stage driving unit in the third group of driving units is configured to receive a third start signal from the control circuit as an input signal; The input signal terminal of the first stage driving unit in the fourth group of driving units is configured to receive a fourth start signal from the control circuit as an input signal.

11. The source driving circuit according to any one of claims 1 to 10, wherein: The number of driving units in each group of driving units is equal, and the K starting signals are the same.

12. The source driving circuit according to claim 11, wherein: The driving unit is configured to generate a cascade signal based on a clock signal, and the data latch period of the source driving circuit is T times the period of the clock signal. The data latch period is the length of time required for all driving units in each group of driving units to receive the input signal, wherein T=S / K, S represents the total number of the multiple driving units, and T is an integer greater than 1.

13. The source driving circuit according to any one of claims 1 to 12, wherein: N is an integer multiple of 3.

14. A source driver chip, comprising the source driver circuit according to any one of claims 1 to 13.

15. A display device, comprising: a plurality of sub-pixels arranged in an array; A gate driving circuit, connected to each sub-pixel in the array through a plurality of gate lines, the gate driving circuit is used to provide a scanning signal to each sub-pixel to turn on each sub-pixel; The source driver chip as claimed in claim 14 is connected to each sub-pixel in the array through a plurality of data lines, and the source driver chip is used to provide a data signal to each sub-pixel so that the turned-on sub-pixel performs display based on the received data signal.

16. The display device according to claim 15, wherein: The plurality of sub-pixels are arranged into an array of pixel units, each pixel unit comprising a red sub-pixel, a green sub-pixel and a blue sub-pixel; The N data signal output terminals of each driving unit are connected to H columns of pixel units through N data lines, where N=3×H, and H is an integer greater than or equal to 1.

17. A display driving method, performed by the source driving circuit according to any one of claims 1 to 13, the method comprising: The control circuit generates K start signals and provides them to K groups of driving units respectively; In the kth group of driving units, the first-stage driving unit receives the kth start signal from the control circuit as an input signal, latches N channels of data according to the input signal and generates a cascade signal; Each driving unit except the first driving unit receives the cascade signal generated by the previous driving unit as an input signal, latches the corresponding N-channel data according to the input signal and generates a cascade signal, where k=1, 2, …, K; Under the control of the enable signal, each driving unit provides the latched N channels of data to its own N data signal output terminals.

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