Gate line driver

Abstract

A gate line driver includes first to second transistors and first to third switches. The first transistor and the second transistor are coupled in series between a first voltage terminal and a second voltage terminal. The first switch has a first terminal coupled to a first node between the first transistor and the second transistor. The second switch has a first terminal coupled to a third voltage terminal, the second switch having a second terminal, the second terminal of the second switch being coupled to the second terminal of the first switch on a second node. A third switch has a first terminal coupled to a third voltage terminal, a second terminal coupled to the first node, and a third terminal coupled to the second node. The configuration of the scheme can reduce power consumption and improve the operation speed of charging and discharging.

Description

Technical Field

[0001] The present invention relates to a gate line driver of a display panel, and more particularly to a gate line driver including diode-connected transistors to facilitate the generation of gate line signals. Background Art

[0002] Thin film transistor (TFT) liquid crystal display (LCD) devices have been widely used in a variety of information products, such as monitors, notebook computers, mobile devices, etc. In some embodiments, LCD includes control circuits, such as a timing controller, one or more gate line drivers, one or more source drivers, and a display panel. In operation, the gate line driver provides gate line signal pulses to scan the lines that cooperate with the timing controller to sequentially turn on or off the TFT gate and further control the on / off of multiple TFTs. However, the charging and discharging operations that generate the pulses in the gate line signal consume power and lead to the complexity of the design of the control signal of the gate line driver. Summary of the invention

[0003] Some aspects of the present invention provide a gate line driver, characterized by comprising: a first transistor to a second transistor and a first switch to a third switch. The first transistor and the second transistor are coupled in series between a first voltage terminal and a second voltage terminal. The first switch has a first terminal coupled to a first node between the first transistor and the second transistor. The second switch has a first terminal coupled to a third voltage terminal. The second switch has a second terminal, and the second terminal of the second switch is coupled to the second terminal of the first switch at a second node. The third switch has a first terminal coupled to the third voltage terminal, a second terminal coupled to the first node, and a third terminal coupled to the second node.

[0004] In some embodiments, the first transistor and the third switch are a plurality of P-type transistors, and the second transistor is an N-type transistor.

[0005] In some embodiments, the second switch is a P-type transistor.

[0006] In some embodiments, the gate line driver further includes an N-type third transistor and a P-type fourth transistor and a fifth transistor. The N-type third transistor has a first terminal and a second terminal. The first terminal of the third transistor and the second terminal of the third transistor are coupled to the first terminal of the third switch and the second terminal of the third switch, respectively. The P-type fourth transistor and the fifth transistor are coupled between the first node and the third voltage terminal. The gate terminal of the third transistor is coupled to a third node between the fourth transistor and the fifth transistor.

[0007] In some embodiments, the gate line driver further includes an N-type third transistor, a fourth switch, and a fifth switch. The N-type third transistor has a first terminal and a second terminal. The first terminal of the third transistor and the second terminal of the third transistor are coupled to the first node and the third voltage terminal, respectively. The fourth switch has a first terminal coupled to the third voltage terminal and a second terminal coupled to the gate terminal of the third transistor at the third node. The fifth switch has a first terminal coupled to the first node and a second terminal coupled to the third node.

[0008] In some embodiments, the fourth switch and the fifth switch are a plurality of P-type transistors.

[0009] In some embodiments, the first transistor is a P-type transistor, and the second transistor and the third switch are a plurality of N-type transistors.

[0010] In some embodiments, the third switch is a P-type metal oxide semiconductor transistor, and the third terminal of the third switch is a gate terminal.

[0011] In some embodiments, the first switch and the second switch are a plurality of P-type metal oxide semiconductor transistors, and the second terminal of the first switch and the second terminal of the second switch are drain / source terminals.

[0012] In some embodiments, the third switch is an N-type metal oxide semiconductor, and the third terminal of the third switch is a gate terminal.

[0013] In some embodiments, the first switch and the second switch are a plurality of N-type metal oxide semiconductor transistors, and the second terminal of the first switch and the second terminal of the second switch are drain / source terminals.

[0014] In some embodiments, the first to third switches are a plurality of P-type transistors, the first terminals of the first to third switches are drain / source terminals, the second terminals of the first to third switches are source / drain terminals, and the third terminal of the third switch is a gate terminal.

[0015] In some embodiments, the voltage at the third voltage terminal is between the voltage at the first voltage terminal and the voltage at the second voltage terminal.

[0016] In some embodiments, when the second transistor and the second switch are turned off, the first transistor and the first switch are turned on, and the first node is electrically connected to the third voltage terminal through a diode-connected third switch.

[0017] In some embodiments, when the first transistor and the first switch are turned off, the second transistor and the second switch are turned on, and the first terminal of the third switch and the second terminal of the third switch are electrically connected to each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the above and other purposes, features, advantages and embodiments of the present invention more clearly understood, the attached drawings are described as follows:

[0019] Figure 1 is a schematic diagram of a gate line driver according to some embodiments of the present invention;

[0020] Figure 2 is a schematic diagram of a signal generator according to some embodiments of the present invention;

[0021] Figure 3 is a schematic diagram of a gate line driver according to some embodiments of the present invention;

[0022] Figure 4A and Figure 4B The operation of some embodiments of the present invention is shown in FIG. Figure 3 A schematic diagram of a gate line driver;

[0023] Figure 4C According to some embodiments of the present invention, Figure 3 A schematic waveform diagram of a gate line signal output by a gate line driver;

[0024] Figure 5A and Figure 5B The operation of some embodiments of the present invention is shown in FIG. Figure 3 A schematic diagram of a gate line driver;

[0025] Figure 5C According to some embodiments of the present invention, Figure 3 A schematic waveform diagram of a gate line signal output by a gate line driver;

[0026] Figure 6 is a schematic diagram of a gate line driver according to another embodiment of the present invention;

[0027] Figure 7 is a schematic diagram of a gate line driver according to another embodiment of the present invention;

[0028] Figure 8 is a schematic diagram of a gate line driver according to another embodiment of the present invention;

[0029] Fig. 9 is a schematic diagram of a gate line driver according to another embodiment of the present invention; and

[0030] Fig.10 is a schematic diagram of a gate line driver according to another embodiment of the present invention.

[0031]

Explanation of symbols

[0032] 100: Gate line driver

[0033] 110:Signal generator

[0034] 111,112,113,114: Inverter

[0035] 300: Gate line driver

[0036] 600: Gate line driver

[0037] 700: Gate line driver

[0038] 800: Gate line driver

[0039] 900: Gate line driver

[0040] 1000: Gate line driver

[0041] CK1a, CK2a, CK1b, CK2b, CK1c, CK2c: control signals

[0042] I AUX : Auxiliary current

[0043] I CHG :Charging current

[0044] M1, M2: transistors

[0045] n1,n2,n3: nodes

[0046] PWR1,PWR2,PWR3: terminals

[0047] SW1, SW2, SW3, SW5, SW6: switches

[0048] SW1_MP,SW2_MP,SW3_MP,SW5_MP,SW6_MP: Transistors

[0049] SW1_MN,SW2_MN,SW3_MN,SW4_MN: transistors

[0050] VC: Voltage

[0051] VC1,VC2: voltage

[0052] VGATE: Gate line signal

[0053] V PWR1 ,V PWR2 ,V PWR3 :Voltage

[0054] VSG: Voltage

[0055] Vth: threshold voltage

[0056] t1,t2,t3: time DETAILED DESCRIPTION

[0057] Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and detailed description to refer to the same or like parts.

[0058] As used herein, the term “coupled” may also refer to “electrically coupled”, and the term “connected” may also refer to “electrically connected.” “Coupled” and “connected” may also refer to two or more elements cooperating or interacting with each other.

[0059] In some embodiments, a gate line driver for generating a pulse as a gate line signal is provided. For example, a pull-up circuit including a P-type metal-oxide semiconductor (PMOS) transistor and a switch are turned on to output a charging current and an auxiliary current for generating a rising edge of a pulse, wherein the switch is coupled between the output of the gate line signal and a voltage terminal other than two supply voltage terminals. For generating a falling edge of a pulse, a pull-down circuit including an N-type metal-oxide semiconductor (NMOS) transistor and the aforementioned switch are turned on to discharge a node of the output gate line signal through a discharge current and an auxiliary current flowing to an additional voltage terminal. Using the configuration of the present case, the gate line driver consumes less power and operates faster. Thus, the performance of the gate line driver is improved.

[0060] Please refer to Figure 1 . Figure 1 is a schematic diagram of a gate line driver 100 according to some embodiments of the present invention. For illustration, the gate line driver 100 includes transistors M1-M2 and switches SW1-SW3. Transistor M1 and transistor M2 are coupled in series between a voltage terminal PWR1 and a voltage terminal PWR2. Switch SW1 has a terminal coupled to a node n1 between transistors M1-M2 and another terminal coupled to a node n2. Switch SW2 has a terminal coupled to a node n2 and another terminal coupled to a voltage terminal PWR3. Switch SW3 is coupled between node n1 and voltage terminal PWR3. Specifically, switch SW3 has a terminal coupled to a terminal of switch SW1 at node n1, another terminal coupled to voltage terminal PWR3 and switch SW2, and a control terminal coupled to node n2.

[0061] In some embodiments, transistor M1 is a P-type transistor and transistor M2 is an N-type transistor. In some embodiments, transistors M1-M2 are metal oxide semiconductor (MOS) transistors.

[0062] In some embodiments, transistors M1-M2 and switches SW1-SW3 cooperate to generate a gate line signal VGATE at node n1 according to the voltages at voltage terminals PWR1-PWR3. PWR3 Between the voltage V at the voltage terminal PWR1 PWR1 The voltage V of the voltage terminal PWR2 PWR2 Between, and voltage V PWR1 Greater than voltage V PWR2 In some embodiments, the voltage V PWR1 is a positive voltage, voltage V PWR2 is a negative voltage and the voltage V PWR3 Ground (ie zero volts).

[0063] Specifically, transistors M1-M2 operate in response to control signals CK1a, CK2a, respectively. Switches SW1-SW2 operate in response to control signals CK1b, CK2b, respectively, and switch SW3 is controlled by voltage VC of node n2 in response to the operation of switches SW1-SW2. In some embodiments, control signal CK1b is a coupled signal of control signal CK1a, and switch SW1 switches in response to transistor M1 being switched. Control signal CK2b is a coupled signal of control signal CK2a, and switch SW2 switches in response to transistor M2 being switched.

[0064] For example, when the transistor M2 and the switch SW2 are turned off, the transistor M1 and the switch SW1 are turned on and the node n1 is electrically connected to the voltage terminal PWR3 through the switch SW3, wherein the switch SW3 is turned on in response to the voltage VC and is diode-connected. Similarly, when the transistor M1 and the switch SW1 are turned off, the transistor M2 and the switch SW2 are turned on and the node n1 is electrically connected to the voltage terminal PWR3 through the switch SW3.

[0065] Please refer to Figure 2 . Figure 2 is a schematic diagram of a signal generator 110 according to some embodiments of the present invention. In some embodiments, the signal generator 110 is used to generate control signals CK1b and CK2b according to control signals CK1a and CK2a. The control signals CK1b and CK2b are different from the control signals CK1a and CK2a. For example, the control signals CK1b and CK2b are delayed signals relative to the control signals CK1a and CK2a, and include delay and / or phase difference.

[0066] like Figure 2 As shown, the signal generator 110 includes inverters 111-114. The inverter 111 receives the control signal CK1a and outputs an inverted signal to the inverter 112, and the inverter 112 inverts the received signal to generate the control signal CK1b. Similarly, the inverter 113 receives the control signal CK2a and outputs an inverted signal to the inverter 114, and the inverter 114 inverts the received signal to generate the control signal CK2b.

[0067] Figure 1 to Figure 2 The configuration is provided for illustrative purposes. Various implementations are within the contemplated scope of the present invention. For example, in some embodiments, the control signals CK1b and CK2b are not generated by the signal generator 110 but are any other suitable circuits that output coupled signals.

[0068] Please refer to Figure 3 . Figure 3 is a schematic diagram of a gate line driver 300 according to some embodiments of the present invention. Figure 1 to Figure 2 In the embodiment of the present invention, similar elements in the following figures are represented by the same element symbols for ease of understanding. For the sake of simplicity, the specific operations of similar elements that have been discussed in detail in the previous paragraphs are omitted here.

[0069] Compared to Figure 1 In the embodiment, the switch SW3 is implemented by a P-type metal oxide semiconductor (PMOS) transistor SW3_MP and has a gate terminal coupled to the node n2, a drain / source terminal coupled to the node n1, and a source / drain terminal coupled to the voltage terminal PWR3.

[0070] Please refer to Figure 4A , Figure 4B ,and Figure 4C . Figure 4A and Figure 4B Shows the charging operation Figure 3 A schematic diagram of a gate line driver 300, and Figure 4C According to some embodiments of the present invention, Figure 3 Schematic waveform diagram of the gate line signal VGATE output by the gate line driver 300.

[0071] In some embodiments, during the charging operation, the transistor M2 is turned off in response to the control signal CK2a having a low logic state and the transistor M1 is turned on in response to the control signal CK1a having a low logic state to charge the transistor M2 based on the voltage V PWR1 , by the charging current I flowing from the voltage terminal PWR1 to the node n1 CHG The node n1 is charged.

[0072] In response to the control signal CK1b, the switch SW1 is turned on to couple the node n1 to the node n2, while the switch SW2 is turned off. Figure 4B As shown, the transistor SW3_MP is diode-connected because its gate terminal and drain / source terminals are connected to each other via the switch SW1.

[0073] Please refer to Figure 4B and Figure 4C At the beginning of the charging operation, the gate line signal VGATE has a voltage less than V PWR3 The voltage V PWR2 , and the voltage VSG across the gate terminal and the drain / source terminal of the transistor SW3_MP is greater than the threshold voltage Vth of the transistor SW3_MP. Then, the transistor SW3_MP is turned on to generate the auxiliary current I AUX To the node n1 to charge the gate line signal VGATE.

[0074] like Figure 4C As shown, at time t1, the gate line signal VGATE at node n1 is charged by the charging current I generated by transistor M1. CHG and the auxiliary current I generated by transistor SW3_MP AUX Flows to the node n1 and charges the node n1, thereby increasing.

[0075] During the period from time t1 to time t2, the gate line signal VGATE is charged to have a value equal to (V PWR3 -Vth) voltage level, and the auxiliary current I AUX At time t2, the voltage V PWR3 The voltage difference between the gate line signal VGATE (ie, the voltage VSG of the transistor SW3_MP) is less than the threshold voltage Vth of the transistor SW3_MP. Thus, the transistor SW3_MP is turned off and the auxiliary current I AUX =0. Compared to the period between time t1 and time t2, when node n1 is completely charged by the charging current I CHG The gate line signal VGATE is charged and increases with a gentle slope.

[0076] At time t3, the voltage level of the gate line signal VGATE is pulled up to the voltage V PWR1 And the charging operation is completed.

[0077] In some embodiments, the rising edge of the pulse in the gate signal is generated only by the charging current from the positive voltage terminal. This results in high power consumption. Using the configuration of the present case, the voltage terminal PWR3 provides additional current for charging. This reduces the power consumption of the voltage terminal PWR1. Furthermore, when the voltage terminal PWR3 is grounded, no additional power is required to generate the additional current. In other words, the total energy consumption of the charging operation is reduced. Benefiting from the additional charging capability of the gate line driver 300, the charging operation time is shortened and the performance of the gate line driver 300 is improved.

[0078] Furthermore, compared to some other methods of implementing multiple logic signals for controlling the auxiliary current in the charging operation, the present invention utilizes a diode-connected transistor to spontaneously turn on or off to generate the auxiliary current I AUX , and are assisted by controlling two switches in response to control signals CK1b and CK2b. Since the control signals CK1b and CK2b are coupled signals of the original control signals CK1a and CK2a, the present invention reduces the number of control signals and simplifies the configuration of the auxiliary current.

[0079] For the discharge operation of the gate line driver 300, please refer to Figure 5A , Figure 5B and Figure 5C . Figure 5A and Figure 5B The operation of some embodiments of the present invention is shown in FIG. Figure 3 A schematic diagram of a gate line driver 300, and Figure 5C It is illustrated according to some embodiments of the present case Figure 3 Schematic waveform diagram of a gate line signal VGATE of the gate line driver 300.

[0080] In some embodiments, during the discharge period, the transistor M1 is turned off in response to the control signal CK1a having a high logic state and the transistor M2 is turned on in response to the control signal CK2a having a high logic state to generate a voltage V PWR2 , through the discharge current I flowing from the node n1 to the voltage terminal PWR2 DIS The node n1 is discharged.

[0081] The switch SW2 is turned on in response to the control signal CK2b to couple the node n2 to the voltage terminal PWR3 while the switch SW1 is turned off. Figure 5B As shown, the transistor SW3_MP is diode-connected because its gate terminal and source / drain terminals are connected to each other via the switch SW2.

[0082] Please refer to Figure 5B and Figure 5C At the beginning of the discharge operation, the gate line signal VGATE has a voltage greater than V PWR3The voltage V PWR1 And the voltage VSG across the gate terminal and the source / drain terminal of the transistor SW3_MP is greater than the threshold voltage Vth of the transistor SW3_MP. Then, the transistor SW3_MP is turned on to generate the auxiliary current I AUX To the voltage terminal PWR3 to discharge the gate line signal VGATE.

[0083] like Figure 5C As shown, at time t1, the gate line signal VGATE of node n1 generates a discharge current I DIS The voltage of node n1 is connected to transistor M2 and generates auxiliary current I AUX The diode-connected transistor SW3_MP pulls down and decreases with a large slope.

[0084] During the period from time t1 to time t2, the gate line signal VGATE is discharged to have a value equal to (V PWR3 +Vth) voltage level and the auxiliary current I AUX At time t2, the voltage V PWR3 The voltage difference between the gate line signal VGATE and the gate line signal VGATE is less than the threshold voltage Vth of the transistor SW3_MP. Therefore, the transistor SW3_MP is turned off and the auxiliary current I AUX =0. Compared to the period between time t1 and time t2, the node n1 is completely charged by the discharge current I DIS The gate line signal VGATE is discharged and decreases with a gentle slope.

[0085] At time t3, the voltage level of the gate line signal VGATE is pulled down to the voltage V PWR2 And the discharge operation is completed.

[0086] Similar to the charging operation, in some embodiments, the falling edge of the pulse in the gate line signal is generated only by the discharge current from the negative voltage terminal. This causes high power consumption. Using the configuration of the present case, for discharge, the voltage terminal PWR3 provides additional current. This reduces the power consumption of the voltage terminal PWR2 without requiring additional power to generate the additional current. In other words, the total energy consumption of the discharge operation is reduced. Benefiting from the additional discharge capability of the gate line driver 300, the discharge operation time is shortened and the performance of the gate line driver 300 is improved.

[0087] Please refer to Figure 6 . Figure 6 FIG. 4 is a schematic diagram of a gate line driver 600 according to another embodiment of the present invention.

[0088] Compared to Figure 3 In the embodiment, switches SW1-SW2 are composed of Figure 6The gate line driver 600 is implemented by two PMOS transistors SW1_MP and SW2_MP in the embodiment. In some embodiments, the transistor SW2_MP is used to operate in response to the control signal CK2c, wherein the control signal CK2c has a different logic state from the control signal CK2a. In some embodiments, the control signal CK2c is responsive to the control signal CK2a by Figure 2 The inverter 113 in generates.

[0089] Please refer to Figure 7 . Figure 7 is a schematic diagram of a gate line driver 700 according to another embodiment of the present invention.

[0090] Compared to Figure 3 In the embodiment, transistor SW3_MP is composed of Figure 7 The gate line driver 700 is implemented by the (NMOS) transistor SW3_MN. Figure 7 As shown, instead of operating in response to control signal CK1b, switch SW1 is controlled by control signal CK2b. Instead of operating in response to control signal CK2b, switch SW2 is controlled by control signal CK1b.

[0091] In the charging operation, according to some embodiments, transistor M1 is turned on to provide a charging current I CHG to the node n1, and when the switch SW1 is off, the switch SW2 is turned on to couple the voltage terminal PWR3 to the node n2. The transistor SW3_MN is thus diode-connected and provides an auxiliary current I AUX to node n1 to change the gate line signal VGATE from the voltage V PWR2 Charged to a voltage V PWR1 .

[0092] In the discharge operation, according to some embodiments, transistor M2 is turned on to allow the discharge current I DIS From node n1 to voltage terminal PWR2. When switch SW2 is off, switch SW1 is turned on to couple node n1 to node n2. Transistor SW3_MN is thus diode-connected and passes auxiliary current I flowing to voltage terminal PWR3. AUX The gate line signal VGATE is discharged through the auxiliary current I AUX And the discharge current I DIS is pulled to a voltage V PWR2 .

[0093] Please refer to Figure 8 . Figure 8 is a schematic diagram of a gate line driver 800 according to another embodiment of the present invention.

[0094] Compared to Figure 7In the embodiment, switches SW1-SW2 are composed of Figure 8 The gate line driver 800 is implemented by two NMOS transistors SW1_MN and SW2_MN in FIG. In some embodiments, the transistor SW2_MN is used to operate in response to a control signal CK1c, wherein the control signal CK1c has a different logic state from the control signal CK1a. In some embodiments, the control signal CK1c is generated by Figure 2 The inverter 111 in responds to the control signal CK1a to generate.

[0095] Please refer to Fig. 9 . Fig. 9 is a schematic diagram of a gate line driver 900 according to another embodiment of the present invention.

[0096] Compared to Figure 3 In the embodiment of the present invention, the gate line driver 900 further includes switches SW5-SW6 and an NMOS transistor SW4_MN to form a complementary MOS of the PMOS transistor SW3_MP. Fig. 9 As shown, transistor SW4_MN has a gate terminal coupled to node n3 and a drain terminal and a source terminal coupled to voltage terminal PWR3 and node n1, respectively. Node n3 is between switches SW5-SW6. Switch SW5 has one terminal coupled to voltage terminal PWR3 and another terminal coupled to one terminal of switch SW6 at node n3. The other terminal of switch SW6 is coupled to node n1.

[0097] In some embodiments, the switch SW5 is operable to respond to the control signal Ck1b and the switch SW6 is operable to respond to the control signal Ck2b.

[0098] In the charging operation, according to some embodiments, transistors SW3_MP and SW4_MN are diode-connected in response to the conduction of switches SW1 and SW5. The voltage VC1 at node n2 is initially equal to the voltage of gate line signal VGATE (for example, equal to voltage V PWR2 ) and the voltage VC2 at the node n3 is initially equal to the voltage V PWR3 Therefore, in order to charge, the auxiliary current I AUX The voltage is generated by transistors SW3_MP and SW4_MN and flows from the voltage terminal PWR3 to the node n1.

[0099] In the discharge operation, according to some embodiments, transistors SW3_MP and SW4_MN are diode-connected in response to the on-state switches SW2 and SW6. Voltage VC1 is initially equal to voltage V PWR3 and the voltage VC2 is initially equal to the voltage of the gate line signal VGATE (for example, equal to the voltage V PWR1 ). Therefore, for charging, the auxiliary current IAUX The voltage is generated by transistors SW3_MP and SW4_MN and flows from the voltage terminal PWR3 to the node n1.

[0100] Please refer to Fig.10 . Fig.10 is a schematic diagram of a gate line driver 1000 according to another embodiment of the present invention.

[0101] Compared to Fig. 9 In the embodiment, switches SW1-SW2, SW5-SW6 are composed of Fig.10 The gate line driver 1000 is implemented by four transistors SW1_MP, SW2_MP, SW5_MP, and SW6_MP. In some embodiments, the transistors SW2_MP and SW6_MP are used to operate in response to the control signal CK2c.

[0102] In summary, in the present case, the gate line driver utilizes a switch between an output coupled to the gate line signal and a voltage terminal other than the two positive and negative supply voltage terminals to provide an auxiliary charging current and an auxiliary discharging current for generating the gate line signal. In such a configuration, less power consumption of the positive and negative supply voltage terminals and improved operation speed of the charging and discharging operations are provided. Furthermore, due to the diode connection characteristics of the transistors that implement the switch, fewer control signals are required, reducing the design complexity of the control signals in the gate line driver.

[0103] Although the present disclosure has been specifically described in detail according to certain embodiments, other embodiments are also feasible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein. It should also be understood by those skilled in the art that various modifications and variations made to the present disclosure are feasible without departing from the spirit and scope of the present disclosure. Based on the foregoing, the present disclosure is intended to cover various modifications and variations in the present disclosure that may fall within the scope of the subsequent claims.

Claims

1. A gate line driver, characterized in that: Include: A first transistor and a second transistor are coupled in series between a first voltage terminal and a second voltage terminal; a first switch having a first terminal coupled to a first node between the first transistor and the second transistor; a second switch having a first terminal coupled to a third voltage terminal, the second switch having a second terminal, the second terminal of the second switch coupled to a second terminal of the first switch at a second node; as well as A third switch has a first terminal coupled to the third voltage terminal, a second terminal coupled to the first node, and a third terminal coupled to the second node.

2. The gate line driver according to claim 1, wherein: The first transistor and the third switch are a plurality of P-type transistors, and the second transistor is an N-type transistor.

3. The gate line driver according to claim 2, wherein: The second switch is a P-type transistor.

4. The gate line driver according to claim 3, wherein: Also includes: A third N-type transistor having a first terminal and a second terminal, wherein the first terminal of the third transistor and the second terminal of the third transistor are respectively coupled to the first terminal of the third switch and the second terminal of the third switch; as well as A fourth transistor and a fifth transistor of P type are coupled between the first node and the third voltage terminal, wherein a gate terminal of the third transistor is coupled to a third node between the fourth transistor and the fifth transistor.

5. The gate line driver according to claim 2, wherein: Also includes: A third N-type transistor having a first terminal and a second terminal, wherein the first terminal of the third transistor and the second terminal of the third transistor are coupled to the first node and the third voltage terminal respectively; a fourth switch having a first terminal coupled to the third voltage terminal and a second terminal coupled to a gate terminal of the third transistor at a third node; as well as A fifth switch has a first terminal coupled to the first node and a second terminal coupled to the third node.

6. The gate line driver according to claim 5, wherein: The fourth switch and the fifth switch are a plurality of P-type transistors.

7. The gate line driver according to claim 1, wherein: The first transistor is a P-type transistor, and the second transistor and the third switch are a plurality of N-type transistors.

8. The gate line driver according to claim 1, wherein: The third switch is a P-type metal oxide semiconductor transistor, and the third terminal of the third switch is a gate terminal.

9. The gate line driver according to claim 8, wherein: The first switch and the second switch are a plurality of P-type metal oxide semiconductor transistors, and the second terminal of the first switch and the second terminal of the second switch are drain / source terminals.

10. The gate line driver according to claim 1, wherein: The third switch is an N-type metal oxide semiconductor, and the third terminal of the third switch is a gate terminal.

11. The gate line driver according to claim 10, wherein: The first switch and the second switch are a plurality of N-type metal oxide semiconductor transistors, and the second terminal of the first switch and the second terminal of the second switch are drain / source terminals.

12. The gate line driver according to claim 1, wherein: The first switch to the third switch are a plurality of P-type transistors. The first terminal from the first switch to the third switch is a drain / source terminal, the second terminal from the first switch to the third switch is a source / drain terminal, and the third terminal of the third switch is a gate terminal.

13. The gate line driver according to claim 1, wherein: A voltage on the third voltage terminal is between a voltage on the first voltage terminal and a voltage on the second voltage terminal.

14. The gate line driver according to claim 1, wherein: When the second transistor and the second switch are turned off, the first transistor and the first switch are turned on, and the first node is electrically connected to the third voltage terminal through the diode-connected third switch.

15. The gate line driver according to claim 14, wherein: When the first transistor and the first switch are turned off, the second transistor and the second switch are turned on, and the first terminal of the third switch and the second terminal of the third switch are electrically connected to each other.

Images