Control circuit and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a control circuit and a memory, and the control circuit comprises a first signal conditioning circuit which is used for receiving a first identification signal and a second identification signal output by a mode register based on the memory; the first identification signal is used for indicating whether the memory starts a terminal data strobe (TDQS) function or not, and the memory executes the terminal data strobe function based on the valid first identification signal; the second identification signal is used for indicating whether the memory starts a data mask (DM) function or not, and the memory executes the data mask function based on the valid second identification signal; the first signal adjusting circuit is configured to shield the effective second identification signal based on the effective first identification signal, and adjust the indication signal output by the mode register to avoid the starting conflict of the TDQS function and the DM function of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a control circuit and a memory. Background Art

[0002] With the development of integrated circuits, the density of integrated circuits is getting higher and higher, and the speed is getting faster and faster; for dynamic random access memory (DRAM), the circuit complexity is rapidly increasing and the capacity of the memory is getting larger and larger.

[0003] For DRAM, DRAM contains a large number of memory particles, and the data bit widths of different memory particles (data bit widths include x16bit, x8bit, x4bit, etc.) may be different. The terminal data selection function (TDQS function) of DRAM can realize the termination of memory particles with different bit widths, thereby ensuring the load balance of the data selection signal line.

[0004] However, in DDR3 or DDR4, the TDQS function of the memory can only be enabled in x8bit mode, and in DDR3 or DDR4, the TDQS function and the DM function [input data mask when writing to the memory, when the DM accompanying the writing to the memory is high, the corresponding data will be masked or blocked and not written] share the same pin, and there may be a conflict in enabling the TDQS function and the DM function of the memory. Summary of the invention

[0005] The embodiments of the present disclosure provide a control circuit and a memory, which adjust an indication signal output by a mode register to avoid the conflict between enabling a TDQS function and a DM function of the memory.

[0006] An embodiment of the present disclosure provides a control circuit, including: a first signal conditioning circuit, used to receive a first identification signal and a second identification signal output based on a mode register of a memory; the first identification signal is used to indicate whether the memory starts a terminal data selection (TDQS) function, and the memory performs the terminal data selection function based on the valid first identification signal; the second identification signal is used to indicate whether the memory starts a data mask (DM) function, and the memory performs the data mask function based on the valid second identification signal; the first signal conditioning circuit is configured to mask the valid second identification signal based on the valid first identification signal.

[0007] The control circuit provided in this embodiment adjusts the first identification signal and the second identification signal output by the mode register to avoid the first identification signal and the second identification signal being valid at the same time, thereby avoiding the enabling conflict between the TDQS function and the DM function of the memory.

[0008] Optionally, the control circuit also includes: a second signal adjustment circuit for receiving a first bit width identification signal and a second bit width identification signal of the memory; the second signal adjustment circuit is configured to shield the first identification signal based on an invalid first bit width identification signal, and to shield the second identification signal based on an invalid second bit width identification signal.

[0009] Optionally, the first bit width identification signal includes an x4 identification signal and an x16 identification signal, the second bit width identification signal includes an x4 identification signal, and the second signal adjustment circuit includes: a first inverter, whose input end is used to receive the x4 identification signal; a second inverter, whose input end is used to receive the x16 identification signal; a first AND logic circuit, whose first input end is connected to the output end of the first inverter, whose second input end is connected to the output end of the second inverter, whose third input end is used to receive the first identification signal, and whose output end is used to output the adjusted first identification signal; a third inverter, whose input end is used to receive the x4 identification signal; and a second AND logic circuit, whose first input end is connected to the output end of the third inverter, whose second input end is used to receive the second identification signal, and whose output end is used to output the adjusted second identification signal.

[0010] Optionally, the first signal conditioning circuit includes: a fourth inverter, whose input end is used to receive the second identification signal; a first OR-NOT logic circuit, whose first input end is connected to the output end of the fourth inverter, and whose second input end is used to receive the first identification signal; and a third AND logic circuit, whose first input end is connected to the output end of the first OR-NOT logic circuit, whose second input end is used to receive a write enable signal, and whose output end is used to output the adjusted second identification signal.

[0011] Optionally, the output end of the first signal conditioning circuit is connected to the input end of the second signal conditioning circuit.

[0012] Optionally, the output end of the second signal conditioning circuit is connected to the input end of the first signal conditioning circuit.

[0013] Optionally, the control circuit also includes: a signal generating circuit, configured to generate a selection signal, a configuration signal and a clock signal based on a control command; a mode control circuit, receiving the selection signal, the configuration signal and the clock signal, and configured to select a target mode register from multiple mode registers based on the selection signal, and the target mode register completes signal configuration based on the configuration signal and the clock signal.

[0014] Optionally, the mode control circuit includes: multiple mode registers, and a selection decoder; the selection decoder is configured to generate a selected enable signal based on a selection signal decoding, and the selected enable signal corresponds one-to-one to the mode register; the mode register selected by the selected enable signal completes signal configuration based on the configuration signal and the clock signal.

[0015] Optionally, the mode control circuit also includes: a fourth AND logic circuit, a first input end for receiving a selected enable signal, a second input end for receiving a clock signal, and an output end for outputting a selected clock signal; a first D flip-flop, an input end for receiving a configuration value of a mode register, a clock end for receiving a selected clock signal, and an output end connected to the mode register.

[0016] Optionally, the signal generating circuit includes: a command decoding circuit configured to decode a control command to obtain a configuration control signal, an initial configuration signal and an initial selection signal; a configuration control circuit configured to generate a clock signal based on the configuration control signal, and sample the initial configuration signal based on the clock signal to obtain the configuration signal, and sample the initial selection signal based on the clock signal to obtain the selection signal.

[0017] Optionally, the command decoding circuit is further configured to decode the control command to obtain a configuration shielding signal, where the configuration shielding signal is used to shield the configuration control signal.

[0018] Optionally, the configuration control circuit includes: a first delay unit, whose input end is used to receive a configuration control signal; a fifth inverter, whose input end is used to receive a configuration shielding signal; a non-AND logic circuit, whose first input end is used to receive a configuration control signal, and whose second input end is connected to the output end of the fifth inverter; a sixth inverter, whose input end is connected to the output end of the non-AND logic circuit; a second D flip-flop, whose input end is connected to the output end of the fifth inverter, whose inverted clock end is connected to the output end of the first delay unit, and whose output end is used to output a clock signal; a second delay unit, whose input end is connected to the output end of the second D flip-flop; a seventh inverter, whose input end is connected to the output end of the second delay unit; a third D flip-flop, whose input end is used to receive an initial selection signal, whose clock end is connected to The output end of the NAND logic circuit and the inverted clock end are connected to the output end of the sixth inverter; the fourth D flip-flop, the input end is connected to the inverted output end of the third D flip-flop, the clock end is connected to the output end of the sixth inverter, the inverted clock end is connected to the output end of the NAND logic circuit, and the inverted output end is used to output a selection signal; the fifth D flip-flop, the input end is used to receive an initial configuration signal, the input end is used to receive an initial configuration signal, the clock end is connected to the output end of the second delay unit, the inverted clock end is connected to the output end of the seventh inverter, the sixth D flip-flop, the input end is connected to the inverted output end of the fifth D flip-flop, the clock end is connected to the output end of the seventh inverter, the inverted clock end is connected to the output end of the second delay unit, and the inverted output end is used to output a configuration signal.

[0019] Another embodiment of the present disclosure further provides a memory, including the control circuit provided in the above embodiment, which adjusts the indication signal output by the mode register to avoid the enabling conflict between the TDQS function and the DM function of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the structure of a control circuit for performing priority shielding provided in one embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of a timing control principle for priority shielding provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of the structure of a second signal conditioning circuit provided in one embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of the structure of another second signal conditioning circuit provided in an embodiment of the present disclosure;

[0025] Figure 5 A schematic diagram of the structure of a first signal conditioning circuit provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the principle of shielding application scenarios provided by an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of a control circuit that first performs application scenario shielding and then performs priority shielding, provided in an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of the principle of first performing application scenario shielding and then performing priority shielding provided in an embodiment of the present disclosure;

[0029] Fig. 9 A schematic diagram of the structure of a control circuit that first performs priority shielding and then performs application scenario shielding, provided in an embodiment of the present disclosure;

[0030] Fig.10 A schematic diagram of the principle of first performing priority shielding and then performing application scenario shielding provided in an embodiment of the present disclosure;

[0031] Fig.11 A schematic diagram of a control circuit structure including a signal generating circuit and a mode control circuit provided in an embodiment of the present disclosure;

[0032] Fig.12 A schematic diagram of the structure of a signal generating circuit provided by an embodiment of the present disclosure;

[0033] Fig.13 A schematic diagram of the structure of a mode control circuit provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] As known from the background technology, in DDR3 or DDR4, the TDQS function and the DM function share a pin, and there may be a conflict in enabling the TDQS function and the DM function in the memory.

[0035] An embodiment of the present disclosure provides a control circuit, which adjusts an indication signal output by a mode register to avoid the enabling conflict between a TDQS function and a DM function of a memory.

[0036] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0037] Figure 1 A schematic diagram of a control circuit for performing priority shielding according to an embodiment of the present disclosure is provided. Figure 2 A schematic diagram of a timing control principle for priority shielding provided by an embodiment of the present disclosure, Figure 3 A schematic diagram of the structure of a second signal conditioning circuit provided in an embodiment of the present disclosure is shown in FIG. Figure 4 A schematic diagram of the structure of another second signal conditioning circuit provided in an embodiment of the present disclosure, Figure 5 A schematic diagram of the structure of a first signal conditioning circuit provided in an embodiment of the present disclosure, Figure 6 A schematic diagram of the principle of shielding application scenarios provided by an embodiment of the present disclosure, Figure 7 A schematic diagram of the structure of a control circuit that first performs application scenario shielding and then performs priority shielding provided in this embodiment, Figure 8 A schematic diagram of the principle of first performing application scenario shielding and then performing priority shielding provided by an embodiment of the present disclosure, Fig. 9 A schematic diagram of the structure of a control circuit that first performs priority shielding and then performs application scenario shielding provided in this embodiment, Fig.10 A schematic diagram of the principle of first performing priority shielding and then performing application scenario shielding provided in an embodiment of the present disclosure, Fig.11A schematic diagram of a control circuit structure including a signal generating circuit and a mode control circuit provided in an embodiment of the present disclosure, Fig.12 A schematic diagram of the structure of a signal generating circuit provided in an embodiment of the present disclosure is shown in FIG. Fig.13 This is a schematic diagram of the structure of a mode control circuit provided in an embodiment of the present disclosure. The control circuit provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0038] It should be noted that in the introduction of various signals in this disclosure, the description of the signal as "valid" or "invalid" is adopted. In the description of this embodiment, "valid" means that the corresponding signal is at a high level, that is, data "1"; "invalid" means that the corresponding signal is at a low level, that is, data "0". In specific applications, an inverter can be introduced at the corresponding position of the control circuit so that "valid" means that the corresponding signal is at a low level, and "invalid" means that the corresponding signal is at a high level; in addition, since "invalid" means that the corresponding signal is at a low level, in the description of this embodiment, outputting an invalid signal can be regarded as not outputting the corresponding signal.

[0039] For the memory, the control of the TDQS function and the DM function of the memory is realized through the relevant parameters of the mode register. Specifically, the memory changes the MR5_OP by encoding the MRW command. <4> The value of TDQS is controlled by the MRW command to change MR5_OP <5> The value of controls the opening or closing of the DM function. Of course, the above-mentioned coded command MRW can also be configured to control the implementation of DM and TDQS by changing the value of other specific mode registers.

[0040] In one example, if the mode register MR5_OP <4> = "1", the mode register outputs a relevant and valid indication signal to instruct the memory to enable the TDQS function; if MR5_OP <4> = "0", the mode register outputs a relevant and invalid indication signal to instruct the memory to turn off the TDQS function.

[0041] It should be noted that in the subsequent description of this embodiment, unless otherwise indicated, the first identification signal output by the mode register is used to instruct the memory to turn on or off the TDQS function; specifically, the memory performs the TDQS function based on the valid first identification signal.

[0042] In one example, if the mode register MR5_OP <5> = "1", the mode register outputs a relevant and valid indication signal to instruct the memory to enable the DM function; if MR5_OP <5> = "0", the mode register outputs a relevant and invalid indication signal to instruct the memory to turn off the DM function.

[0043] It should be noted that, in the subsequent description of this embodiment, unless otherwise indicated, the second identification signal output by the mode register is used to instruct the memory to turn on or off the DM function; specifically, the memory performs the DM function based on the valid second identification signal.

[0044] However, based on the foregoing, it can be known that the TDQS function and the DM function of the memory share a pin, that is, the TDQS function and the DM function of the memory cannot be enabled at the same time. When the first identification signal and the second identification signal output by the mode register are valid at the same time, the enabling of the TDQS function and the DM function of the memory conflicts.

[0045] The control circuit provided in this embodiment adjusts the first identification signal and the second identification signal output by the mode register to avoid the first identification signal and the second identification signal being valid at the same time, thereby avoiding the enabling conflict of the TDQS function and the DM function of the memory; in addition, the adjustment logic of the first identification signal and the second identification signal of the control circuit provided in this embodiment is consistent with the enabling logic of the mode register for the TDQS function and the DM function.

[0046] As for the enabling logic of the mode register for the TDQS function and the DM function, based on the foregoing, it can be known that the mode register MR5 controls whether the TDQS function is enabled through the value of OP4, and controls whether the DM function is enabled through the value of OP5, and under normal operation, only when OP4 = "0" can OP5 = "1" be configured, that is, the memory can enable the DM function without enabling the TDQS function, that is, the priority of the memory TDQS function is higher than the priority of the DM function.

[0047] In this regard, refer to Figure 1 The control circuit provided in this embodiment includes: a first signal conditioning circuit 101, which is used to receive a first identification signal and a second identification signal, and the first signal conditioning circuit 101 is configured to shield the valid second identification signal based on the valid first identification signal.

[0048] For the adjustment logic of the control circuit for the first identification signal and the second identification signal, refer to Figure 2When the effective time of the first identification signal and the second identification signal partially overlap or completely overlap, the activation of the TDQS function and the DM function of the memory conflict. At this time, the memory shields the effective second identification signal through the effective first identification signal, so that the memory performs the TDQS function, and only when the first identification signal is invalid, the effective second identification signal is enabled. When the effective time of the first identification signal and the second identification signal do not affect each other, that is, when the effective time of the first identification signal and the effective time of the second identification signal are staggered, the activation of the TDQS function and the DM function of the memory does not conflict, and the effective time of the first identification signal and the second identification signal do not affect each other. The memory performs work, that is, by adjusting the first identification signal and the second identification signal through the control circuit, on the basis of ensuring the normal operation of the memory, the scenario of the activation conflict of the TDQS function and the DM function of the memory is avoided.

[0049] In some embodiments, the control circuit further includes: a second signal conditioning circuit 102, configured to receive a first bit width identification signal and a second bit width identification signal of the memory. The second signal conditioning circuit 102 is configured to shield the first identification signal based on an invalid first bit width identification signal, and shield the second identification signal based on an invalid second bit width identification signal.

[0050] Specifically, refer to Figure 3 The second signal conditioning circuit 102 receives the first identification signal and the first bit-width identification signal through the first AND gate 201, thereby shielding the first identification signal based on the first bit-width identification signal; similarly, the second signal conditioning circuit 102 receives the second identification signal and the second bit-width identification signal through the second AND gate 202, thereby shielding the second identification signal based on the second bit-width identification signal.

[0051] In other words, when the first bit width identification signal is valid, the second signal adjustment circuit 102 outputs the first identification signal normally, and when the second bit width identification signal is valid, the second signal adjustment circuit 102 outputs the second identification signal normally. The valid time of the first identification signal is limited by the first bit width identification signal, and the valid time of the second identification signal is limited by the second bit width identification signal, thereby avoiding the incorrect activation of the DM function of the TDQS function of the memory.

[0052] In some embodiments, the first bit width identification signal and the second bit width identification signal may include the same identification signal; for example, the TDQS function and the DM function of the memory can both be started in the x8bit mode, that is, the first bit width identification signal and the second bit width identification signal can both include the identification signal corresponding to the x8bit mode. In addition, in some embodiments, the first bit width identification signal and the second bit width identification signal may include different identification signals; for example, the TDQS function of the memory can be started in the x8bit mode, and the DM function of the memory can be started in the x16bit mode, that is, the first bit width identification signal includes the identification signal corresponding to the x8bit mode, and the second bit width identification signal includes the identification signal corresponding to the x16bit mode, that is, the identification signals included in the first bit width identification signal and the second bit width identification signal are different. Similarly, in some embodiments, the first bit width identification signal or the second bit width identification signal may include multiple identification signals; for example, the DM function of the memory can be started in the x8bit mode and the x16bit mode, that is, the second bit width identification signal includes the identification signals corresponding to the x8bit mode and the x16bit mode.

[0053] It should be noted that the purpose of introducing the first bit-width identification signal and the second bit-width identification signal in this embodiment is to shield the effective enabling of the TDQS function or the DM function. As for the specific content of the first bit-width identification signal and the second bit-width identification signal, this embodiment does not limit it. Those skilled in the art can obtain the signal content of the first bit-width identification signal and the second bit-width identification signal based on the driving mode of the TDQS function and the DM function in the memory to which they are applied.

[0054] In some embodiments, the bit width identification signal may be received through an inverter, and in this case, the second signal conditioning circuit 102 is configured to shield the first identification signal and the second identification signal in the corresponding bit width output mode.

[0055] Based on the background technology, it can be known that in DDR3 or DDR4, the TDQS function of the memory can only be enabled in the x8bit mode; accordingly, in DDR3 or DDR4, the DM function of the memory can only be enabled in the x8bit mode and the x16bit mode. In other words, the memory needs to shield the first identification signal in the x4bit mode and the x16bit mode to avoid the TDQS function of the memory from being erroneously enabled, and the memory needs to shield the second identification signal in the x4bit mode to avoid the DM function of the memory from being erroneously enabled.

[0056] refer to Figure 4 and Figure 5, the first bit width identification signal includes an x4 identification signal and an x16 identification signal, the second bit width identification signal includes an x4 identification signal, wherein the x4 identification signal is used to indicate that the memory is in x4bit mode, the x8 identification signal is used to indicate that the memory is in x8bit mode, and the x16 identification signal is used to indicate that the memory is in x16bit mode, the second signal conditioning circuit 102, includes: a first inverter 310, whose input end is used to receive the x4 identification signal; a second inverter 320, whose input end is used to receive the x16 identification signal; a first AND logic circuit 301, whose first input end is connected to the output end of the first inverter 310, whose second input end is connected to the output end of the second inverter, whose third input end is used to receive the first identification signal, and whose output end is used to output the adjusted first identification signal; a third inverter 330, whose input end is used to receive the x4 identification signal; a second AND logic circuit 302, whose first input end is connected to the output end of the third inverter 330, whose second input end is used to receive the second identification signal, and whose output end is used to output the adjusted second identification signal.

[0057] Specifically, when the memory is in the x4bit mode, the x4 identification signal is valid. After being inverted by the first inverter 310 or the third inverter 330, the output of the first inverter 310 and the third inverter 330 is a low level. For the first AND logic circuit 301 and the second AND logic circuit 302, their output is a low level, so that the valid first identification signal and the second identification signal are not enabled; when the memory is in the x16bit mode, the x16 identification signal is valid. After being inverted by the second inverter 320, the output of the second inverter 320 is a low level. For the first AND logic circuit 301, its output is a low level, so that the valid first identification signal is not enabled.

[0058] It should be noted that Figure 4 In the circuit structure of the second signal conditioning circuit 102 shown, the first inverter 310 and the third inverter 330 have the same function. In some embodiments, the first inverter 310 and the third inverter 330 can be implemented based on the same inverter.

[0059] In some embodiments, reference Figure 5 The first signal conditioning circuit 101 includes: a fourth inverter 403, whose input end is used to receive the second identification signal; a first OR logic circuit 401, whose first input end is connected to the output end of the fourth inverter 403, and whose second input end is used to receive the first identification signal; a third AND logic circuit 402, whose first input end is connected to the output end of the first OR logic circuit 401, whose second input end is used to receive the output enable signal DQ_Enable, and whose output end is used to output the adjusted second identification signal.

[0060] Specifically, based on the background technology, it can be known that the DM function of the memory is the input data mask (Input Data Mask) when writing to the memory. When the DM accompanying the writing to the memory is at a high level, the corresponding data will be masked or blocked and not written. Therefore, the DM function of the memory needs to be implemented in combination with the write function. In this embodiment, the write enable signal DQ_Enable is used to control the write function of the memory. The third AND logic circuit 402 combines the effective write enable signal DQ_Enable and the high level output of the first OR logic circuit 401 to generate a valid second identification signal to turn on the DM function of the memory. For the first OR logic circuit 401, the output is high only when all the inputs are low. At this time, the first identification signal is low and the second identification signal is high. When the first identification signal is high, the output of the first OR logic circuit 401 is low, and the first signal adjustment circuit 102 cannot generate a valid second identification signal, thereby realizing the shielding of the second identification signal based on the effective first identification signal.

[0061] As can be seen from the foregoing, the first signal conditioning circuit 101 sets the shielding logic according to the priorities of the first identification signal and the second identification signal, and the second signal conditioning circuit 102 sets the shielding logic according to the usage scenarios of the first identification signal and the second identification signal. Different connection relationships between the first signal conditioning circuit 101 and the second signal conditioning circuit 102 may result in different output results.

[0062] In some embodiments, reference Figure 7 and Figure 8 , the output end of the second signal conditioning circuit 102 is connected to the input end of the first signal conditioning circuit 101, that is, the control circuit first performs application scenario shielding and then performs priority shielding; in some embodiments, reference Fig. 9 and Fig.10 , the output end of the first signal conditioning circuit 101 is connected to the input end of the second signal conditioning circuit 102, that is, the control circuit first performs priority shielding and then performs application scenario shielding.

[0063] refer to Figure 7 and Figure 8 The first identification signal and the second identification signal are indication signals output by the mode register, the first identification signal-1 and the second identification signal-1 are output results adjusted based on the second signal adjustment circuit 102, the second identification signal-2 is the output result adjusted based on the first signal adjustment circuit 101, and the first identification signal-1 and the second identification signal-2 are used to indicate whether the memory turns on the TDQS function and the DM function.

[0064] Specifically, ideally, assuming that the memory operates in x4bit mode, that is, when the x4 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory neither turns on the TDQS function nor the DM function, and when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the application scenario shielding of the second signal conditioning circuit 102, the first identification signal and the second identification signal output by the second signal conditioning circuit 102 are invalid, which is in line with expectations. Assuming that the memory operates in x8bit mode, that is, when the x8 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory only turns on the TDQS function, and when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the application scenario shielding of the second signal conditioning circuit 102, the first identification signal and the second identification signal output by the second signal conditioning circuit 102 are valid, and after the priority shielding of the first signal conditioning circuit 101, the second identification signal output by the first signal conditioning circuit 101 is invalid, which is in line with expectations. Assume that the memory operates in x16bit mode, that is, when the x16 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory only turns on the DM function; when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the application scenario shielding of the second signal conditioning circuit 102, the first identification signal output by the second signal conditioning circuit 102 is invalid; after the priority shielding of the first signal conditioning circuit 101, the second identification signal output by the first signal conditioning circuit 101 is valid, which is as expected.

[0065] refer to Fig. 9 and Fig.10 The first identification signal and the second identification signal are indication signals output by the mode register, the second identification signal -3 is the output result after adjustment based on the first signal adjustment circuit 101, the first identification signal -4 and the second identification signal -4 are the output results after adjustment based on the second signal adjustment circuit 102, and the first identification signal -4 and the second identification signal -4 are used to indicate whether the memory turns on the TDQS function and the DM function.

[0066] Specifically, ideally, assuming that the memory operates in the x4bit mode, that is, when the x4 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory neither turns on the TDQS function nor the DM function, and when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the priority shielding of the first signal conditioning circuit 101, the second identification signal output by the first signal conditioning circuit 101 is invalid, and then after the application scenario shielding of the second signal conditioning circuit 102, the first identification signal output by the second signal conditioning circuit 102 is invalid, which is in line with expectations. Assuming that the memory operates in the x8bit mode, that is, when the x8 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory only turns on the TDQS function, and when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the priority shielding of the first signal conditioning circuit 101, the second identification signal output by the first signal conditioning circuit 101 is invalid, and then after the application scenario shielding of the second signal conditioning circuit 102, the first identification signal output by the second signal conditioning circuit 102 is valid, which is in line with expectations. Assume that the memory operates in x16bit mode, that is, when the x16 identification signal is valid, when the first identification signal and the second identification signal are valid at the same time, the memory only turns on the DM function, and when the first identification signal and the second identification signal output by the mode register are valid at the same time, after the priority shielding of the first signal adjustment circuit 101, the second identification signal output by the first signal adjustment circuit 101 is invalid, and then after the application scenario shielding of the second signal adjustment circuit 101, the second identification signal output by the second signal adjustment circuit 102 is invalid, which is not as expected.

[0067] Through the above analysis, it can be seen that no matter whether the priority shielding logic is executed first or the application scenario shielding logic is executed, both circuits have certain applicability, but the logic of executing application scenario shielding first and then priority shielding has a wider scope of application.

[0068] In some embodiments, reference Fig.11 , the control circuit also includes: a signal generating circuit 501 and a mode control circuit 502.

[0069] Specifically, the signal generating circuit 501 is configured to generate a selection signal, a configuration signal and a clock signal based on the control command MRW. The control command is issued based on the storage controller, including signals such as PCLK_E / O, CS_n and CA. The selection signal MRAB<7:0> generated by the signal generating circuit 501 is used to select a target mode register from multiple mode registers in the memory, and the configuration signal OPB<7:0> and the clock signal MRW_CLK are used to perform signal configuration on the selected target mode register. For example, the specific values ​​of OP0 to OP7 in the configuration mode register MR5. The mode control circuit 502 is used to receive the selection signal, the configuration signal and the clock signal, and is configured to select the target mode register from multiple mode registers based on the selection signal, and the target mode register completes the signal configuration based on the configuration signal and the clock signal.

[0070] Continue to refer Fig.11 In some embodiments, the signal generating circuit 501 includes a command decoding circuit 511 and a configuration control circuit 521, wherein the command decoding circuit 511 is configured to decode the control command to obtain the configuration control signal MRW_CMD, the initial configuration signal OP<7:0> and the initial selection signal MRA<7:0>; the configuration control circuit 521 is configured to generate a clock signal MRW_CLK based on the configuration control signal MRW_CMD, and sample the initial configuration signal OP<7:0> based on the clock signal MRW_CLK to obtain the configuration signal OPB<7:0>, and sample the initial selection signal based on the clock signal MRW_CLK to obtain the selection signal MRAB<7:0>.

[0071] In some embodiments, the command decoding circuit 511 is further configured to decode the control command to obtain a configuration shielding signal CW, where the configuration shielding signal CW is used to shield the configuration control signal MRW_CMD; specifically, when the configuration shielding signal CW is valid, the configuration control signal MRW_CMD is shielded.

[0072] refer to Fig.12In some embodiments, the configuration control circuit 521 includes: a first delay unit 701, whose input end is used to receive the configuration control signal MRW_CMD; a fifth inverter 801, whose input end is used to receive the configuration shielding signal CW; a non-AND logic circuit 702, whose first input end is used to receive the configuration control signal MRW_CMD, and whose second input end is connected to the output end of the fifth inverter 801; a sixth inverter 802, whose input end is connected to the output end of the non-AND logic circuit; a second D flip-flop 703, whose input end is connected to the output end of the fifth inverter 801, whose inverted clock end is connected to the output end of the first delay unit 801, and whose output end is used to output the clock signal MRW_CLK; a second delay unit 704, whose input end is connected to the output end of the second D flip-flop 703; a seventh inverter 808, whose input end is connected to the output end of the second delay unit 704; a third D flip-flop 705, whose input end is used to receive the initial selection signal signal MRA<7:0>, the clock end is connected to the output end of the NAND logic circuit 702, and the inverted clock end is connected to the output end of the sixth inverter 802; the fourth D flip-flop 706, the input end is connected to the inverted output end of the third D flip-flop 705, the clock end is connected to the output end of the sixth inverter 802, the inverted clock end is connected to the output end of the NAND logic circuit 702, and the inverted output end is used to output the selection signal MRAB<7:0>; the fifth D flip-flop 707, the input end is used to receive the initial configuration signal OP<7:0>, the clock end is connected to the output end of the second delay unit 704, and the inverted clock end is connected to the output end of the seventh inverter 803; the sixth D flip-flop 708, the input end is connected to the inverted output end of the fifth D flip-flop 707, the clock end is connected to the output end of the seventh inverter 803, the inverted clock end is connected to the output end of the second delay unit 704, and the inverted output end is used to output the configuration signal OPAB<7:0>;

[0073] Among them, the first delay unit 701 is used to delay the effective level of the configuration control signal MRW_CMD, the fifth inverter 801 is used to generate the inverted configuration shielding signal CWB, the input end of the NAND logic circuit 702 is used to receive the configuration signal control MRW_CMD and the inverted configuration shielding signal CWB, and the output end is connected to the clock end CK and the inverted clock end CKB of the third D flip-flop 705 and the fourth D flip-flop 706. When the configuration control signal MRW_CMD is valid and the configuration shielding signal CW is invalid, the NAND logic circuit 702 outputs a low level based on the valid configuration control signal MRW_CMD and the inverted configuration shielding signal CWB. At this time, MRSB is low and MRSD is high. The third D flip-flop 705 and the fourth D flip-flop 706 sample the initial selection signal MRA<7:0> based on MRSB and MRSD to obtain the selection signal MRAB<7:0>. Similarly, the second D flip-flop 703 generates a clock signal MRW_CLK based on the inverted configuration shielding signal CWB and the configuration control signal MRW_CMD, and generates MRWB and MRWD after delaying and inverting the clock signal MRW_CLK. When the configuration control signal MRW_CMD is valid and the configuration shielding signal CW is invalid, the clock signal MRW_CLK sampled and obtained by the second D flip-flop 703 is valid. At this time, MRWB is high and MRWD is low. The fifth D flip-flop 707 and the sixth D flip-flop 708 sample the initial configuration signal OP<7:0> based on MRWB and MRWD to configure the signal OPB<7:0>.

[0074] In some embodiments, reference Fig.11 The mode control circuit 502 includes: multiple mode registers 522 (MR0~MRn), and a selection decoder 512. The selection decoder 512 is configured to generate a selected enable signal based on the selection signal MRAB<7:0>. The selected enable signal corresponds to the mode register one by one and is used to select the target mode register 522 in the multiple mode registers 522 to be turned on. The mode register 522 selected by the selected enable signal completes the signal configuration based on the configuration signal OPB<7:0> and the clock signal MRW_CLK.

[0075] In some embodiments, reference Fig.13 , the mode control circuit 502 also includes: a fourth AND logic circuit 601, whose first input end is used to receive the selected enable signal, whose second input end is used to receive the clock signal MRW_CLK, and whose output end is used to output the selected enable signal; a first D flip-flop 602, whose input end is used to receive the configuration value of the mode register, the clock end is used to receive the selected clock signal, and the output end is used to connect the mode register.

[0076] Specifically, for the mode register MR5, the configuration signal OPB<7:0> includes the configuration value OP <0> ~OP <7> , OP <0> ~OP <7> MR5_OP is used to configure the mode register MR5. <0> ~MR5_OP <7> , for example, when OP <4> = 1, used to set MR5_OP in mode register MR5 <4> Set to 1.

[0077] The control circuit provided in this embodiment adjusts the first identification signal and the second identification signal output by the mode register to avoid the first identification signal and the second identification signal being valid at the same time, thereby avoiding the enabling conflict between the TDQS function and the DM function of the memory.

[0078] It should be noted that the features disclosed in the control circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new control circuit embodiments.

[0079] Another embodiment of the present disclosure provides a memory, including the control circuit provided in the above embodiment, and adjusting the indication signal output by the mode register to avoid the enabling conflict between the TDQS function and the DM function of the memory.

[0080] For the adjustment logic of the control circuit for the first identification signal and the second identification signal, refer to Figure 2 When the effective time of the first identification signal and the second identification signal partially overlap or completely overlap, the activation of the TDQS function and the DM function of the memory conflict. At this time, the memory shields the effective second identification signal through the effective first identification signal, so that the memory performs the TDQS function, and only when the first identification signal is invalid, the effective second identification signal is enabled. When the effective time of the first identification signal and the second identification signal do not affect each other, that is, when the effective time of the first identification signal and the effective time of the second identification signal are staggered, the activation of the TDQS function and the DM function of the memory does not conflict, and the effective time of the first identification signal and the second identification signal do not affect each other. The memory performs work, that is, by adjusting the first identification signal and the second identification signal through the control circuit, on the basis of ensuring the normal operation of the memory, the scenario of the activation conflict of the TDQS function and the DM function of the memory is avoided.

[0081] In some examples, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0082] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A control circuit, characterized in that: include: A first signal conditioning circuit, configured to receive a first identification signal and a second identification signal outputted by a mode register based on a memory; The first identification signal is used to indicate whether the memory starts a terminal data strobe (TDQS) function, and the memory performs the terminal data strobe function based on the valid first identification signal; The second identification signal is used to indicate whether the memory starts a data mask (DM) function, and the memory performs the data mask function based on the valid second identification signal; The first signal conditioning circuit is configured to mask the valid second identification signal based on the valid first identification signal.

2. The control circuit according to claim 1, characterized in that: Also includes: The second signal conditioning circuit is used to receive the first bit width identification signal and the second bit width identification signal of the memory, wherein; The second signal conditioning circuit is configured to mask the first identification signal based on the invalid first bit width identification signal, and mask the second identification signal based on the invalid second bit width identification signal.

3. The control circuit according to claim 2, characterized in that: The first bit width identification signal includes a x4 identification signal and a x16 identification signal, the second bit width identification signal includes the x4 identification signal, and the second signal conditioning circuit includes: A first inverter, an input end of which is used to receive the x4 identification signal; A second inverter, an input end of which is used to receive the x16 identification signal; a first AND logic circuit, wherein the first input terminal is connected to the output terminal of the first inverter, the second input terminal is connected to the output terminal of the second inverter, the third input terminal is used to receive the first identification signal, and the output terminal is used to output the adjusted first identification signal; A third inverter, an input end of which is used to receive the x4 identification signal; The second AND logic circuit has a first input terminal connected to the output terminal of the third inverter, a second input terminal for receiving the second identification signal, and an output terminal for outputting the adjusted second identification signal.

4. The control circuit according to claim 1, characterized in that: The first signal conditioning circuit comprises: a fourth inverter, an input end of which is used to receive the second identification signal; A first NOR logic circuit, wherein the first input terminal is connected to the output terminal of the fourth inverter, and the second input terminal is used to receive the first identification signal; The third AND logic circuit has a first input terminal connected to the output terminal of the first OR logic circuit, a second input terminal for receiving a write enable signal, and an output terminal for outputting the adjusted second identification signal.

5. The control circuit according to any one of claims 2 to 4, characterized in that: The output end of the first signal conditioning circuit is connected to the input end of the second signal conditioning circuit.

6. The control circuit according to any one of claims 2 to 4, characterized in that: The output end of the second signal conditioning circuit is connected to the input end of the first signal conditioning circuit.

7. The control circuit according to claim 1, characterized in that: Also includes: A signal generating circuit configured to generate a selection signal, a configuration signal and a clock signal based on the control command; The mode control circuit receives the selection signal, the configuration signal and the clock signal, and is configured to select a target mode register from a plurality of mode registers based on the selection signal, wherein the target mode register completes signal configuration based on the configuration signal and the clock signal.

8. The control circuit according to claim 7, characterized in that: The mode control circuit comprises: a plurality of said mode registers, and a selection decoder; The selection decoder is configured to generate a selected enable signal based on the selection signal by decoding, and the selected enable signal corresponds to the mode register one by one; The mode register selected by the selection enable signal completes signal configuration based on the configuration signal and the clock signal.

9. The control circuit according to claim 7, characterized in that: The mode control circuit further includes: A fourth AND logic circuit, wherein the first input terminal is used to receive the selected enable signal, the second input terminal is used to receive the clock signal, and the output terminal is used to output the selected clock signal; The first D flip-flop has an input end for receiving the configuration value of the mode register, a clock end for receiving the selected clock signal, and an output end connected to the mode register.

10. The control circuit according to claim 7, characterized in that: The signal generating circuit comprises: A command decoding circuit is configured to decode the control command to obtain a configuration control signal, an initial configuration signal and an initial selection signal; The configuration control circuit is configured to generate the clock signal based on the configuration control signal, sample the initial configuration signal based on the clock signal to obtain the configuration signal, and sample the initial selection signal based on the clock signal to obtain the selection signal.

11. The control circuit according to claim 10, characterized in that: The command decoding circuit is further configured to decode the control command to obtain a configuration masking signal, where the configuration masking signal is used to mask the configuration control signal.

12. The control circuit according to claim 11, characterized in that: The configuration control circuit comprises: A first delay unit, whose input end is used to receive the configuration control signal; a fifth inverter, an input end of which is used to receive the configuration shielding signal; A NAND logic circuit, wherein the first input terminal is used to receive the configuration control signal, and the second input terminal is connected to the output terminal of the fifth inverter; A sixth inverter, an input end of which is connected to the output end of the NAND logic circuit; A second D flip-flop, whose input end is connected to the output end of the fifth inverter, whose inverted clock end is connected to the output end of the first delay unit, and whose output end is used to output a clock signal; A second delay unit, an input end of which is connected to an output end of a second D flip-flop; a seventh inverter, an input end of which is connected to the output end of the second delay unit; A third D flip-flop, whose input terminal is used to receive the initial selection signal, whose clock terminal is connected to the output terminal of the NAND logic circuit, and whose inverted clock terminal is connected to the output terminal of the sixth inverter; A fourth D flip-flop, whose input end is connected to the inverting output end of the third D flip-flop, whose clock end is connected to the output end of the sixth inverter, whose inverting clock end is connected to the output end of the NAND logic circuit, and whose inverting output end is used to output the selection signal; a fifth D flip-flop, whose input end is used to receive the initial configuration signal, whose clock end is connected to the output end of the second delay unit, and whose inverted clock end is connected to the output end of the seventh inverter, The sixth D flip-flop has an input end connected to the inverting output end of the fifth D flip-flop, a clock end connected to the output end of the seventh inverter, an inverted clock end connected to the output end of the second delay unit, and an inverting output end for outputting the configuration signal.

13. A memory, characterized in that: The control circuit comprises the control circuit according to any one of claims 1 to 12.

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