Memory control circuit and memory control method

Abstract

The invention provides a memory control circuit and a memory control method.The memory control circuit comprises a first state machine, a second state machine, an erasing and writing process identification unit and an erasing and writing execution circuit, the erasing and writing process identification unit is used for responding to erasing and writing operation executed by a processor and sending a target request to the first state machine, an erasing request corresponding to the erasing instruction is sent to a second state machine, and the received erasing data is transmitted to an erasing execution circuit; the first state machine is used for responding to the target request, switching from a first state to a second state, and sending a first mark signal to the second state machine; the second state machine is used for responding to the erasing and writing request under the condition that the first mark signal is received, and skipping to a working state corresponding to the erasing and writing operation from an idle state; and the erasing execution circuit is used for executing corresponding erasing operation on the memory according to the erasing data under the condition that the first state machine is in the second state and the second state machine is in the working state corresponding to the erasing operation.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of memory reading and writing technology, and more specifically, to a memory control circuit and a memory control method. Background Art

[0002] In the prior art, when programming a NAND flash memory (FLASH), it is unavoidable to generate an erase process due to abnormal program jumps, which affects the security of data in the memory. Summary of the invention

[0003] One purpose of the embodiments of the present disclosure is to provide a new technical solution for improving the security of memory programming.

[0004] According to a first aspect of an embodiment of the present disclosure, a memory control circuit is provided, including a first state machine, a second state machine, an erase process identification unit, and an erase execution circuit.

[0005] The erase process identification unit is used to send a target request to the first state machine in response to the erase operation executed by the processor, send an erase request corresponding to the erase instruction to the second state machine, and transmit the received erase data to the erase execution circuit;

[0006] The first state machine is used to switch from the first state to the second state in response to the target request, and send a first flag signal to the second state machine;

[0007] The second state machine is used for jumping from an idle state to a working state corresponding to the erase operation in response to the erase request when the first flag signal is received;

[0008] The erase execution circuit is used to execute a corresponding erase operation on the memory according to the erase data when the first state machine is in the second state and the second state machine is in a working state corresponding to the erase operation.

[0009] Optionally, in the case where the erase operation is a programming operation, the erase request corresponding to the erase operation is a programming request, and the working state corresponding to the erase operation is a programming state;

[0010] In the case where the erase operation is a page erase operation, the erase request corresponding to the erase operation is a page erase request, and the working state corresponding to the erase operation is a page erase state;

[0011] In the case where the erase operation is a sector erase operation, the erase request corresponding to the erase operation is a sector erase request, and the working state corresponding to the erase operation is a sector erase state;

[0012] In the case that the erase operation is a block erase operation, the erase request corresponding to the erase operation is a block erase request, and the working state corresponding to the erase operation is a block erase state.

[0013] Optionally, the second state machine is used to jump back to the idle state and send a second flag signal to the first state machine when the erase execution circuit completes the corresponding erase operation on the memory;

[0014] The first state machine is used for switching from the second state to the first state according to the second flag signal.

[0015] Optionally, the first flag signal and the second flag signal are indicated by a 1-bit signal.

[0016] Optionally, the memory control circuit also includes a read execution circuit, which is used to respond to a read operation performed by the processor when the first state machine is in the first state, perform a read operation on the memory according to read configuration information issued by the processor, and return the read data to the processor.

[0017] Optionally, the memory control circuit further includes a first clock generator and a second clock generator.

[0018] The first clock generator is used to output a first clock signal to the read execution circuit when the memory control circuit is powered on;

[0019] The read execution circuit is used to execute the read operation according to the first clock signal;

[0020] The second clock generator is used to respond to the first instruction issued by the processor before executing the erase and write operation, send a second clock signal to the erase and write execution circuit; when the erase and write execution circuit completes the corresponding erase and write operation on the memory, stop sending the second clock signal to the erase and write execution circuit;

[0021] The erase / write execution circuit is used to execute the erase / write operation according to the second clock signal.

[0022] Optionally, the memory control circuit further includes a second reset signal generator;

[0023] The second reset signal generator is used to respond to the second instruction issued by the processor before executing the erase operation, output an invalid second reset signal to the erase process identification unit, so that the erase process identification unit works; when the erase execution circuit completes the corresponding erase operation on the memory, output a valid second reset signal to the erase process identification unit, so that the erase process identification unit is reset.

[0024] Optionally, the erase process identification unit is used to output a valid first enable signal when sending an erase request corresponding to the erase instruction to the second state machine;

[0025] The memory control circuit further includes a first AND gate, wherein the first AND gate is used to perform an AND logic operation on the first enable signal and the second reset signal to obtain a third reset signal.

[0026] The second state machine is used to operate when the third reset signal is valid, and reset when the third reset signal is invalid.

[0027] Optionally, the second state machine is used to output a valid second enable signal when jumping from an idle state to a corresponding working state;

[0028] The memory control circuit further includes a second AND gate, wherein the second AND gate is used to perform an AND logic operation on the second enable signal and the third reset signal to obtain a fourth reset signal;

[0029] The erase execution circuit is used to work when the fourth reset signal is valid, and reset when the fourth reset signal is invalid.

[0030] Optionally, the erase process identification unit is used to respond to the erase operation, obtain the erase configuration information selected by the processor, and perform the erase configuration operation according to the erase configuration information; and configure the startup enable corresponding to the erase operation; determine whether the startup enable and the erase configuration operation match, and send the target request to the first state machine if they match; and report an error to the processor if they do not match.

[0031] According to a second aspect of the present disclosure, there is provided a memory control method, comprising:

[0032] In response to the erase / write operation performed by the processor, the first state machine is controlled to switch from the first state to the second state, and the second state machine is controlled to jump from the idle state to the working state corresponding to the erase / write operation;

[0033] When the first state machine is in the second state and the second state machine is in the working state corresponding to the erase operation, the corresponding erase operation is performed on the memory according to the received erase data.

[0034] Optionally, the memory control method further includes:

[0035] When the corresponding erase and write operation on the memory is completed, the second state machine is controlled to jump back to the idle state, and the first state machine is controlled to switch from the second state to the first state.

[0036] Optionally, the memory control method further includes:

[0037] When the first state machine is in the first state, in response to a read operation performed by the processor, a read operation is performed on the memory according to read configuration information issued by the processor, and the read data is returned to the processor.

[0038] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the memory control method as described in the second aspect of the present disclosure is implemented.

[0039] The memory control circuit of this embodiment uses two state machines, the first state machine is used for read operation, and the second state machine is used for erase operation. If a single state machine jumps due to external environment such as electromagnetic pulse or cosmic ray, the erase execution circuit will not generate an erase operation. Only when the two state machines jump at the same time, the erase execution circuit may generate an erase operation, which can improve the security of the memory.

[0040] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0042] Figure 1 is a structural schematic diagram of a memory control circuit according to an embodiment of the present disclosure;

[0043] Figure 2 is a structural schematic diagram of a memory control circuit according to an embodiment of the present disclosure;

[0044] Figure 3 is a schematic diagram of an erasure identification process according to an embodiment of the present disclosure;

[0045] Figure 4 is a state switching schematic diagram of a second state machine according to an embodiment of the present disclosure;

[0046] Figure 5 is a timing diagram of a memory control circuit according to an embodiment of the present disclosure;

[0047] Figure 6is a flowchart of a memory control method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0049] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0050] Technologies, methods and equipment known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods and equipment should be considered part of the specification.

[0051] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0052] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0053] This embodiment provides a memory control circuit, through which a processor can read, erase, and program data from a memory.

[0054] The memory may be, for example, any type of read-write memory, such as a flash memory.

[0055] Figure 1 FIG. 1 is a schematic diagram of a memory control circuit according to an embodiment of the present disclosure. Figure 1 As shown, the memory control circuit 100 may include a first state machine 101 , a second state machine 102 , an erase process identification unit 103 and an erase execution circuit 104 .

[0056] The erase process identification unit 103 is used to respond to the erase operation executed by the processor 200, send a target request to the first state machine 101, send an erase request corresponding to the erase instruction to the second state machine 102, and transmit the received erase data to the erase execution circuit 104.

[0057] The first state machine 101 is used to switch from the first state to the second state in response to the target request, and send a first flag signal to the second state machine 102 to enable the second state machine 102 to start state transition.

[0058] The second state machine 102 is used to jump from an idle state to a working state corresponding to the erase operation in response to an erase request when the first flag signal is received.

[0059] The erase execution circuit 104 is used to execute a corresponding erase operation on the memory 300 according to the erase data when the first state machine 101 is in the second state and the second state machine 102 is in the working state corresponding to the erase operation.

[0060] In this embodiment, the first state machine 101 may have only the first state and the second state, which can improve the utilization of the first state machine 101 and prevent other states from reducing the reading efficiency of the memory control circuit 100 .

[0061] In this embodiment, the second state machine 102 may have an idle state and multiple working states, and the multiple working states may include a programming state, a page erase state, a sector erase state, and a block erase state. The second state machine 102 may be in an idle state by default. In the case where the second state machine 102 does not receive the first flag signal sent by the first state machine 101, that is, when the first state machine 101 is in the first state, the second state machine 102 will remain in an idle state and cannot jump to any working state. In the case where the second state machine 102 receives the first flag signal sent by the first state machine 101, that is, when the first state machine 101 is in the second state, the state jump is enabled, that is, it can jump from the idle state to the working state corresponding to the erase operation according to the erase request sent by the erase process identification unit 103.

[0062] In this embodiment, the erase operation may be any one of a programming operation, a page erase operation, a sector erase operation, and a block erase operation. When the erase operation is a programming operation, the erase request corresponding to the erase operation is a programming request, and the working state corresponding to the erase operation is a programming state; when the erase operation is a page erase operation, the erase request corresponding to the erase operation is a page erase request, and the working state corresponding to the erase operation is a page erase state; when the erase operation is a sector erase operation, the erase request corresponding to the erase operation is a sector erase request, and the working state corresponding to the erase operation is a sector erase state; when the erase operation is a block erase operation, the erase request corresponding to the erase operation is a block erase request, and the working state corresponding to the erase operation is a block erase state.

[0063] The memory control circuit 100 of this embodiment may be communicatively connected to the processor 200 via a bus.

[0064] When the first state machine 101 is in the second state, the read execution circuit 105 can suspend the read operation of the bus and delay the read operation until the erase and write operation of the erase and write execution circuit 104 is completed.

[0065] The memory control circuit of this embodiment uses two state machines, the first state machine is used for read operation, and the second state machine is used for erase operation. If a single state machine jumps due to external environment such as electromagnetic pulse or cosmic ray, the erase execution circuit will not generate an erase operation. Only when the two state machines jump at the same time, the erase execution circuit may generate an erase operation, which can improve the security of the memory.

[0066] In one embodiment of the present disclosure, when the erase process identification unit 103 receives an erase operation executed by the processor 200, it sends a target request to the first state machine 101, sends an erase request corresponding to the erase instruction to the second state machine 102, and transmits the received erase data to the erase execution circuit 104.

[0067] In another embodiment of the present disclosure, in order to reduce the possibility of the first state machine 101 abnormally entering the second state, the erase process identification unit 103 can be used to respond to the erase operation, obtain the erase configuration information selected by the processor 200, and perform the erase configuration operation according to the erase configuration information; and configure the startup enable corresponding to the erase operation; determine whether the startup enable and the erase configuration operation match, and if they match, send a target request to the first state machine 101, send an erase request corresponding to the erase instruction to the second state machine 102, and transmit the received erase data to the erase execution circuit 104, and output a valid first enable signal; if there is no match, report an error to the processor, and do not send a target request to the first state machine 101, do not send an erase request corresponding to the erase instruction to the second state machine 102, and do not transmit the received erase data to the erase execution circuit 104.

[0068] In this embodiment, performing the erase configuration operation according to the erase configuration information may include configuring the address to be processed and configuring the erase parameters.

[0069] Specifically, the erase process identification unit 103 may be responsive to the erase operation and execute the following steps: Figure 3 The erase and write identification process is shown.

[0070] The erase process identification unit 103 can receive an erase operation selected by the processor 200 to be executed, including any one of a programming operation, a page erase operation, a sector erase operation, and a block erase operation.

[0071] Further, the erase process identification unit 103 performs the erase configuration operation according to the erase configuration information, which may include configuring the address to be processed according to the address requirement required by the erase operation selected by the processor 200. In the case where the erase operation selected to be performed is a programming operation, the programming address may be configured as required; in the case where the erase operation selected to be performed is a page erase operation, the page erase address may be configured as required; in the case where the erase operation selected to be performed is a sector erase operation, the sector erase address may be configured as required; in the case where the erase operation selected to be performed is a block erase operation, the block erase address may be configured as required.

[0072] Furthermore, the erase process identification unit 103 performs the erase configuration operation according to the erase configuration information, and may also include configuring the erase parameters according to the requirements of the processor 200. When the erase operation selected to be performed is a programming operation, the data to be written may be configured according to the requirements; when the erase operation selected to be performed is a page erase operation, a sector erase operation, or a block erase operation, the erase time may be configured according to the requirements.

[0073] In this embodiment, the order in which the erasing and writing process identification unit 103 configures the erasing and writing parameters and the addresses to be processed is not limited.

[0074] Furthermore, the erase process identification unit 103 can configure the corresponding start enable according to the erase operation selected for execution. When the erase operation selected for execution is a programming operation, the programming start enable can be configured; when the erase operation selected for execution is a page erase operation, the page erase start enable can be configured; when the erase operation selected for execution is a sector erase operation, the sector erase start enable can be configured; when the erase operation selected for execution is a block erase operation, the block erase start enable can be configured.

[0075] On this basis, the erase process identification unit 103 can determine whether the configured startup enable matches the executed erase configuration operation (including the operation of configuring the address to be processed and the operation of configuring the erase parameters).

[0076] In an embodiment where the erase operation to be performed is selected as a programming operation, when the erase configuration operation to be performed includes configuring a programming address, configuring data to be written, and the configured start enable is a programming start enable, it can be determined that the configured start enable matches the erase configuration operation performed. In an embodiment where the erase operation to be performed is selected as a page erase operation, when the erase configuration operation to be performed includes configuring a page erase address, configuring a page erase time, and the configured start enable is a page erase start enable, it can be determined that the configured start enable matches the erase configuration operation performed. In an embodiment where the erase operation to be performed is selected as a sector erase operation, when the erase configuration operation to be performed includes configuring a sector erase address, configuring a sector erase time, and the configured start enable is a sector erase start enable, it can be determined that the configured start enable matches the erase configuration operation performed. In an embodiment where the erase operation selected for execution is a block erase operation, when the erase configuration operation executed includes configuring a block erase address, configuring a block erase time, and the configured start enable is a block erase start enable, it can be determined that the configured start enable matches the erase configuration operation executed. Through this embodiment, the complexity of the erase identification process can be increased, thereby reducing the possibility of the first state machine abnormally entering the second state, and improving the data security of the memory.

[0077] In one embodiment of the present disclosure, Figure 2 As shown, the memory control circuit 100 also includes a read execution circuit 105, which is used to respond to a read operation performed by the processor 200 when the first state machine 101 is in the first state, perform a read operation on the memory 300 according to the read configuration information issued by the processor, and return the read data to the processor 200.

[0078] In this embodiment, the first state machine 101, the second state machine 102, the erase and write execution circuit 104, and the read execution circuit 105 can all be implemented by hardware logic circuits that can implement corresponding functions.

[0079] In one embodiment of the present disclosure, Figure 2 As shown, the memory control circuit 100 further includes a first clock generator 106 and a second clock generator 107 .

[0080] The first clock generator 106 may also be configured to output a first clock signal CLK1 to the read execution circuit 105 and the first state machine 101 when the memory control circuit is powered on.

[0081] In an example, the second clock generator 107 is used to respond to the first instruction issued by the processor before executing the erase operation, and send the second clock signal CLK2 to the erase execution circuit 104, the second state machine 102, and the erase process identification unit 103; when the erase execution circuit completes the corresponding erase operation on the memory, stop sending the second clock signal CLK2 to the erase execution circuit 104, the second state machine 102, and the erase process identification unit 103.

[0082] In this embodiment, the processor can issue a first instruction to the second clock generator 107 before executing the erase operation, so that the second clock generator 107 first outputs the second clock signal CLK2 to the erase execution circuit 104, the second state machine 102, and the erase process identification unit 103, so as to prepare for the memory control circuit 100 to respond to the erase operation.

[0083] In another example, the second clock generator 107 may also be used to send the second clock signal CLK2 to the erase execution circuit 104 when the memory control circuit is powered on.

[0084] The read execution circuit 105 is used to execute a read operation according to the first clock signal CLK1, and the erase execution circuit 104 executes an erase operation according to the second clock signal CLK2. The first state machine 101, the second state machine 102, and the erase process identification unit 103 all operate according to the first clock signal.

[0085] In this embodiment, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 may be the same or different, which is not limited herein.

[0086] In one embodiment of the present disclosure, Figure 2 As shown, the memory control circuit 100 further includes a first reset signal generator 108, which can output an invalid first reset signal RESET1 to the read execution circuit 105 and the first state machine 101 when the memory control circuit 100 is powered on, so that the read execution circuit 105 and the first state machine 101 work. The invalid first reset signal RESET1 can be a high level signal.

[0087] In one embodiment of the present disclosure, Figure 2 As shown, the memory control circuit 100 further includes a second reset signal generator 109 .

[0088] In an example, the second reset signal generator 109 is used to output an invalid second reset signal RESET2 to the erase process identification unit 103 when the memory control circuit is powered on, so that the erase process identification unit works.

[0089] In another example, the second reset signal generator 109 is used to respond to the second instruction issued by the processor before executing the erase operation, output an invalid second reset signal RESET2 to the erase process identification unit 103, so that the erase process identification unit 103 works and executes the erase identification process; when the erase execution circuit completes the corresponding erase operation on the memory, output a valid second reset signal RESET2 to the erase process identification unit 103, so that the erase process identification unit 103 is reset and the erase identification process is not executed. The invalid second reset signal RESET2 can be a high level signal. The valid second reset signal RESET2 can be a low level signal.

[0090] In this embodiment, the processor may send a second instruction to the second reset signal generator 109 before executing the erase operation, so that the second reset signal generator 109 outputs an invalid second reset signal RESET2 to the erase process identification unit 103, so as to prepare for the memory control circuit 100 to respond to the erase operation. At the same time, it can also prevent the memory control circuit 100 from generating an erase process due to abnormal program jump, thereby improving the security of the memory.

[0091] Furthermore, the erase process identification unit 103 is used to output a valid first enable signal EN1 when the configured startup enable matches the executed erase configuration operation. Figure 2 As shown, the memory control circuit 100 further includes a first AND gate 110, which is used to perform an AND logic operation on the first enable signal EN1 and the second reset signal RESET2 to obtain a third reset signal RESET3. The second state machine 102 is used to operate when the third reset signal RESET is invalid, and reset when the third reset signal RESET is valid.

[0092] In this embodiment, the valid first enable signal EN1 may be a high level signal.

[0093] When the second reset signal RESET2 is at a high level and the erase process identification unit 103 outputs a high level first enable signal EN1, the first AND gate 110 outputs a high level third reset signal RESET3; when the second reset signal RESET2 is at a low level or the erase process identification unit 103 does not output a high level first enable signal EN1, the first AND gate 110 outputs a low level third reset signal RESET3.

[0094] The second state machine 102 may operate when the third reset signal RESET3 is at a high level, and reset when the third reset signal RESET3 is at a low level without executing the corresponding working process.

[0095] Furthermore, the second state machine 102 is used to output a valid second enable signal EN2 when the second state machine 102 jumps from the idle state to the working state corresponding to the erase operation. Figure 2 As shown, the memory control circuit 100 further includes a second AND gate 111, which is used to perform an AND logic operation on the second enable signal EN2 and the third reset signal RESET3 to obtain a fourth reset signal RESET4, which is used to control the working state of the erase execution circuit 104.

[0096] In this embodiment, the effective second enable signal EN2 may be a high level signal.

[0097] When the third reset signal RESET3 is at a high level and the second state machine 102 outputs a high level second enable signal EN2, the second AND gate 111 outputs a high level fourth reset signal RESET4; when the third reset signal RESET3 is at a low level, or the second state machine 102 does not output a high level second enable signal EN2, the second AND gate 111 outputs a low level fourth reset signal RESET4.

[0098] The erase execution circuit 104 may operate when the fourth reset signal RESET4 is at a high level, and reset when the fourth reset signal RESET4 is at a low level without executing the corresponding working process.

[0099] In this embodiment, the erase and write operations and read operations of the memory control circuit use different clock and reset domains respectively. When the memory control circuit works normally, only the first clock signal and the first reset signal are used. At this time, the second state machine is in a clockless and reset state. If the first state machine abnormally jumps to the second state, it will immediately return to the normal first state because the second state machine is in a reset state. The second state machine itself is in a reset state and will not jump abnormally due to the influence of the external environment, which can avoid the problem of accidental erase and write of the memory.

[0100] In one embodiment of the present disclosure, the second state machine 102 is used to jump back to the idle state when the erase execution circuit 104 completes the corresponding erase operation on the memory 300, and sends a second flag signal to the first state machine 101. The first state machine 101 is used to switch from the second state to the first state according to the second flag signal.

[0101] In this embodiment, the multiple working states of the second state machine 102 cannot be directly switched, and each working state and the idle state can be switched to each other. The state switching method of the second state machine 102 can be as follows: Figure 4 shown.

[0102] Specifically, when the erase operation selected by the processor 200 to be executed is a programming operation, the erase process identification unit 103 sends an erase request corresponding to the erase instruction to the second state machine 102, which may be a programming request. When the second state machine 102 receives the first flag signal, it responds to the programming request and jumps from the idle state to the programming state; when the erase execution circuit 104 completes the programming operation on the memory, the second state machine 102 jumps from the programming state to the idle state again, and sends a second flag signal to the first state machine 101, so that the first state machine 101 switches from the second state back to the first state.

[0103] When the erase operation selected by the processor 200 to be executed is a page erase operation, the erase process identification unit 103 sends an erase request corresponding to the erase instruction to the second state machine 102, which may be a page erase request. When the second state machine 102 receives the first flag signal, it responds to the page erase request and jumps from the idle state to the page erase state; when the erase execution circuit 104 completes the page erase operation on the memory, the second state machine 102 jumps from the page erase state to the idle state again, and sends a second flag signal to the first state machine 101, so that the first state machine 101 switches from the second state back to the first state.

[0104] When the erase operation selected by the processor 200 to be executed is a sector erase operation, the erase process identification unit 103 sends an erase request corresponding to the erase instruction to the second state machine 102, which may be a sector erase request. When the second state machine 102 receives the first flag signal, it responds to the sector erase request and jumps from the idle state to the sector erase state; when the erase execution circuit 104 completes the sector erase operation on the memory, the second state machine 102 jumps from the sector erase state to the idle state again, and sends a second flag signal to the first state machine 101, so that the first state machine 101 switches from the second state back to the first state.

[0105] When the erase operation selected by the processor 200 to be executed is a block erase operation, the erase process identification unit 103 sends an erase request corresponding to the erase instruction to the second state machine 102, which may be a block erase request. When the second state machine 102 receives the first flag signal, it responds to the block erase request and jumps from the idle state to the block erase state; when the erase execution circuit 104 completes the block erase operation on the memory, the second state machine 102 jumps from the block erase state to the idle state again, and sends a second flag signal to the first state machine 101, so that the first state machine 101 switches from the second state back to the first state.

[0106] Through this embodiment, the complexity of the erase and write process can be increased, thereby improving the data security of the memory.

[0107] In one embodiment of the present disclosure, the first flag signal and the second flag signal may be indicated by 1 bit.

[0108] Specifically, when the 1-bit signal is 0, it indicates the first flag signal, and when the 1-bit signal is 1, it indicates the second flag signal; or, when the 1-bit signal is 1, it indicates the first flag signal, and when the 1-bit signal is 0, it indicates the second flag signal.

[0109] like Figure 5 As shown, when the 1-bit flag signal indicates the first flag signal when it is 1 and indicates the second flag signal when it is 0, the flag signal has an abnormal flip at time 1, and the original state is restored at time 2. The first state machine 101 switches the first state machine to the second state (B) at time 3, and then switches from the second state (B) to the first state. In this way, the memory control circuit can automatically recover from the abnormal state in time. Since the second state machine 102 does not receive the erase request sent by the erase process identification unit 103, it remains in an idle state. Then, the erase execution circuit 104 will not perform an erase operation on the memory, which can prevent the data stored in the memory from being accidentally lost and improve the security of the memory.

[0110] Through this embodiment, the problem that the state of the first state machine abnormally enters the second state and cannot be restored due to the burr of the flag signal can be prevented from occurring.

[0111] <Method>

[0112] The present disclosure also provides a memory control method. Figure 6 is a flowchart of a memory control method according to an embodiment of the present disclosure.

[0113] according to Figure 6 As shown, the memory control method may include steps S610 to S620 as shown below:

[0114] Step S610, in response to the erase operation performed by the processor, controlling the first state machine to switch from the first state to the second state, and controlling the second state machine to jump from the idle state to the working state corresponding to the erase operation.

[0115] Step S620: When the first state machine is in the second state and the second state machine is in the working state corresponding to the erase operation, perform a corresponding erase operation on the memory according to the received erase data.

[0116] In one embodiment of the present disclosure, the memory control method further includes: when the corresponding erase and write operation on the memory is completed, controlling the second state machine to jump back to the idle state, and controlling the first state machine to switch from the second state to the first state.

[0117] In one embodiment of the present disclosure, the memory control method also includes: when the first state machine is in the first state, in response to a read operation performed by the processor, performing a read operation on the memory according to read configuration information issued by the processor, and returning the read data to the processor.

[0118] <Computer Readable Storage Medium>

[0119] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the memory control method as described in any embodiment of the present disclosure is implemented.

[0120] The same or similar steps among the above embodiments may be referred to each other.

[0121] The present disclosure may be a system, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0122] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0123] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0124] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0125] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0126] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0127] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0128] The flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of an instruction, and the module, a program segment or a part of an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of the boxes in the block diagram and / or the flowchart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0129] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present disclosure is defined by the appended claims.

Claims

1. A memory control circuit, characterized in that: It includes a first state machine, a second state machine, an erase process identification unit, and an erase execution circuit. The erase process identification unit is used to send a target request to the first state machine in response to the erase operation executed by the processor, send an erase request corresponding to the erase instruction to the second state machine, and transmit the received erase data to the erase execution circuit; The first state machine is used to switch from the first state to the second state in response to the target request, and send a first flag signal to the second state machine; The second state machine is used for jumping from an idle state to a working state corresponding to the erase operation in response to the erase request when the first flag signal is received; The erase execution circuit is used to execute a corresponding erase operation on the memory according to the erase data when the first state machine is in the second state and the second state machine is in a working state corresponding to the erase operation.

2. The memory control circuit according to claim 1, characterized in that: In the case where the erase operation is a programming operation, the erase request corresponding to the erase operation is a programming request, and the working state corresponding to the erase operation is a programming state; In the case where the erase operation is a page erase operation, the erase request corresponding to the erase operation is a page erase request, and the working state corresponding to the erase operation is a page erase state; In the case where the erase operation is a sector erase operation, the erase request corresponding to the erase operation is a sector erase request, and the working state corresponding to the erase operation is a sector erase state; In the case that the erase operation is a block erase operation, the erase request corresponding to the erase operation is a block erase request, and the working state corresponding to the erase operation is a block erase state.

3. The memory control circuit according to claim 1, wherein: The second state machine is used for jumping back to the idle state and sending a second flag signal to the first state machine when the erase execution circuit completes the corresponding erase operation on the memory; The first state machine is used for switching from the second state to the first state according to the second flag signal.

4. The memory control circuit according to claim 3, characterized in that: The first flag signal and the second flag signal are indicated by 1-bit signals.

5. The memory control circuit according to claim 3, characterized in that: The memory control circuit also includes a read execution circuit, which is used to respond to a read operation performed by the processor when the first state machine is in the first state, perform a read operation on the memory according to read configuration information issued by the processor, and return the read data to the processor.

6. The memory control circuit according to claim 5, characterized in that: The memory control circuit further includes a first clock generator and a second clock generator, The first clock generator is used to output a first clock signal to the read execution circuit when the memory control circuit is powered on; The read execution circuit is used to execute the read operation according to the first clock signal; The second clock generator is used to respond to the first instruction issued by the processor before executing the erase and write operation, send a second clock signal to the erase and write execution circuit; when the erase and write execution circuit completes the corresponding erase and write operation on the memory, stop sending the second clock signal to the erase and write execution circuit; The erase / write execution circuit is used to execute the erase / write operation according to the second clock signal.

7. The memory control circuit according to claim 1, characterized in that: The memory control circuit also includes a second reset signal generator; The second reset signal generator is used to output an invalid second reset signal to the erase process identification unit in response to the second instruction issued by the processor before executing the erase process identification unit, so that the erase process identification unit works; When the erase execution circuit completes the corresponding erase operation on the memory, a valid second reset signal is output to the erase process identification unit to reset the erase process identification unit.

8. The memory control circuit according to claim 7, characterized in that: The erase process identification unit is used for outputting a valid first enable signal when sending an erase request corresponding to the erase instruction to the second state machine; The memory control circuit further includes a first AND gate, wherein the first AND gate is used to perform an AND logic operation on the first enable signal and the second reset signal to obtain a third reset signal. The second state machine is used to operate when the third reset signal is valid, and reset when the third reset signal is invalid.

9. The memory control circuit according to claim 8, characterized in that: The second state machine is used to output a valid second enable signal when jumping from an idle state to a corresponding working state; The memory control circuit further includes a second AND gate, wherein the second AND gate is used to perform an AND logic operation on the second enable signal and the third reset signal to obtain a fourth reset signal; The erase execution circuit is used to work when the fourth reset signal is valid, and reset when the fourth reset signal is invalid.

10. The memory control circuit according to any one of claims 1 to 9, characterized in that: The erase process identification unit is used to respond to the erase operation, obtain the erase configuration information selected by the processor, and perform the erase configuration operation according to the erase configuration information; and configure the startup enable corresponding to the erase operation; determine whether the startup enable and the erase configuration operation match, and send the target request to the first state machine if they match; and report an error to the processor if they do not match.

11. A memory control method, characterized in that: include: In response to the erase / write operation performed by the processor, the first state machine is controlled to switch from the first state to the second state, and the second state machine is controlled to jump from the idle state to the working state corresponding to the erase / write operation; When the first state machine is in the second state and the second state machine is in the working state corresponding to the erase operation, the corresponding erase operation is performed on the memory according to the received erase data.

12. The memory control method according to claim 11, characterized in that: The memory control method further includes: When the corresponding erase and write operation on the memory is completed, the second state machine is controlled to jump back to the idle state, and the first state machine is controlled to switch from the second state to the first state.

13. The memory control method according to claim 11, characterized in that: The memory control method further includes: When the first state machine is in the first state, in response to a read operation performed by the processor, a read operation is performed on the memory according to read configuration information issued by the processor, and the read data is returned to the processor.

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