Memory, operating method thereof, and memory system

By introducing a gating circuit and multiple page buffers in the X-NAND memory, ensuring that the first bit line is independently controlled and continuously pre-charged during the programming operation, the problem of adjacent plane bit line coupling is solved and data loading efficiency is improved.

CN119851726AActive Publication Date: 2025-04-18YANGTZE MEMORY TECH CO LTD
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Patent Information

Application Number
CN202311339152.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-10-16
Publication Date
2025-04-18
Estimated Expiration
2043-10-16

AI Technical Summary

Technical Problem

During programming operations of X-NAND memory, bit lines of two adjacent planes are prone to coupling problems.

Method used

By introducing a gating circuit and multiple page buffers in the memory array, it is ensured that the first bit line at the first end of the plane can be controlled independently and pre-charged continuously during the data loading phase, thereby solving the coupling problem of adjacent bit lines.

Benefits of technology

It effectively solves the coupling problem of adjacent plane bit lines in X-NAND memory during programming operations, improves data loading efficiency and reduces the number of page buffer usage.

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Abstract

The invention provides a memory, an operation method of the memory and a memory system. The memory includes a memory array and a peripheral circuit coupled to the memory array. The memory array includes a plurality of planes, each plane including a plurality of bit lines. The peripheral circuit includes a gate circuit and a plurality of page buffers, and the gate circuit is coupled to the plurality of page buffers. A first bit line at a first end of the plane is coupled with a first page buffer of the plurality of page buffers through a gate circuit. The bit lines other than the first bit line are coupled to at least one of the plurality of page buffers other than the first page buffer through the gate circuit, and at least two of the bit lines other than the first bit line are coupled to the same page buffer through the gate circuit. The first bit line located at the first end of the plane can be independently controlled during programming, so that pre-charging is continuously carried out in the pre-charging process, and the coupling problem between adjacent bit lines in an adjacent bit plane can be solved.
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Citation Information

Patent Citations

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