Flash memory device and erasing method thereof

Abstract

The invention provides a flash memory device and an erasing method thereof. The erasing method comprises the following steps: during an erasing operation, applying an erasing voltage to a target memory block, and judging whether the target memory block passes erasing verification or not; when the erase verification is not passed, judging whether the target memory block meets a degradation condition or not; when the degradation condition is met, judging whether the target memory block passes the soft programming verification, and returning to the step of applying the erasing voltage after the target memory block passes the soft programming verification; when the target memory block does not meet the degradation condition, returning to the step of applying the erasing voltage; and when the target memory block passes the erase verification, judging whether the target memory block passes the soft programming verification, and applying a soft programming voltage to the target memory block after the target memory block does not pass the soft programming verification.

Description

Technical Field

[0001] The present invention relates to a memory device, and more particularly to a flash memory device and an erasing method thereof for reducing the erasing time spent in an erasing operation. Background Art

[0002] Flash memory devices can perform write operations, erase operations, and read operations, among which the erase operation takes the longest time. Therefore, the length of time required for the erase operation can be said to dominate the performance of the flash memory. Generally speaking, during the erase operation of a flash memory device, steps such as applying a pre-program voltage, executing an erase procedure, and executing a soft-program procedure (also known as a post-program procedure) are included. The erase procedure includes sequentially applying an erase voltage and performing an erase verification, and applying the erase voltage again after determining that the erase verification has not passed, and executing the soft programming procedure after determining that the erase verification has passed. The soft programming procedure includes executing a soft programming verification, and applying a soft programming voltage after determining that the soft programming verification has not passed, and returning to the soft programming verification again, and ending the erase operation after determining that the soft programming verification has passed. Although the soft programming process can improve the over-erase problem, the soft programming process takes up a high proportion of time (for example, more than half of the time of the erase operation). Especially after the flash memory device performs multiple cycling operations, the over-erase phenomenon is more serious, resulting in the soft programming process taking a longer time, which becomes a bottleneck for reducing the erase time. Summary of the invention

[0003] The invention provides a flash memory device and an erasing method thereof, which can dynamically adjust the process of the erasing operation to improve the overall efficiency of the erasing operation.

[0004] The erasing method of the flash memory device of the present invention comprises the following steps: during the erasing operation, applying an erasing voltage to a target memory block, and judging whether the target memory block passes the erasing verification; when the target memory block fails the erasing verification, judging whether the target memory block meets the degradation condition; when the target memory block meets the degradation condition, judging whether the target memory block passes the soft programming verification, and returning to the step of applying the erasing voltage to the target memory block after the target memory block passes the soft programming verification; when the target memory block does not meet the degradation condition, returning to the step of applying the erasing voltage to the target memory block; when the target memory block passes the erasing verification, judging whether the target memory block passes the soft programming verification, and applying the soft programming voltage to the target memory block after the target memory block fails the soft programming verification; and when the target memory block passes the erasing verification and the soft programming verification, ending the erasing operation.

[0005] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array includes a plurality of memory blocks. The memory control circuit is coupled to the memory array and includes an erase verification circuit, a degradation judgment circuit, and a soft programming verification circuit. The erase verification circuit is configured to determine whether the target memory block passes the erase verification after applying an erase voltage to the target memory block during an erase operation. The degradation judgment circuit is coupled to the erase verification circuit. The degradation judgment circuit includes a comparator, which is configured to determine whether the target memory block meets the degradation condition when the target memory block does not pass the erase verification. The soft programming verification circuit is coupled to the erase verification circuit and the degradation judgment circuit. The soft programming verification circuit is configured to: determine whether the target memory block passes the soft programming verification when the target memory block meets the degradation condition; and determine whether the target memory block passes the soft programming verification when the target memory block passes the erase verification. The memory control circuit is also configured to: apply an erase voltage to the target memory block again after the target memory block meets the degradation condition and passes the soft programming verification; apply an erase voltage to the target memory block again when the target memory block does not meet the degradation condition; apply a soft programming voltage to the target memory block after the target memory block passes the erase verification and fails the soft programming verification; and end the erase operation when the target memory block passes the erase verification and the soft programming verification.

[0006] Based on the above, the flash memory device and the erasing method of the present invention can dynamically adjust the process of the erasing operation according to whether the target memory block meets the degradation condition. In this way, even after executing multiple cycles, it can be ensured that the erasing time will not increase significantly, thereby improving the erasing efficiency.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram showing a flash memory device according to an embodiment of the present invention;

[0009] Figure 2 A flowchart showing a method for erasing a flash memory device according to an embodiment of the present invention;

[0010] Figure 3 A flowchart showing a method for erasing a flash memory device according to another embodiment of the present invention;

[0011] Figure 4 FIG. 1 shows the distribution range of the threshold voltage of the memory cells in the target memory block during each stage of the erase operation according to an embodiment of the present invention;

[0012] Figure 5FIG. 1 is a graph showing the relationship between the erase time and the number of executions of the loop operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Please refer to Figure 1 A flash memory device 100 according to an embodiment of the present invention includes a memory array 110 and a memory control circuit 120. The memory array 110 includes a plurality of memory blocks 112. Each memory block 112 includes a plurality of memory cells. In the embodiment of the present invention, the number of memory blocks 112 and memory cells is not limited.

[0015] The memory control circuit 120 is coupled to the memory array 110. The memory control circuit 120 can be used to select a target memory block 114 from a plurality of memory blocks 112 in the memory array 110 according to a selection command to perform a specified operation (such as an erase or program operation). Figure 1 The memory control circuit 120 is shown to be located in the flash memory device 100 . However, the memory control circuit 120 may also be a device independent of the flash memory device 100 .

[0016] like Figure 1 As shown, the memory control circuit 120 includes an erase verification circuit 121, a degradation judgment circuit 122, a soft programming verification circuit 123, a voltage generation circuit 124, and a control signal generation circuit 125. The erase verification circuit 121 can be configured to determine whether the target memory block 114 passes the erase verification after applying the erase voltage to the target memory block 114 during the erase operation, and provide a first signal EN1. When the first signal EN1 is a first logic level, it indicates that the erase verification passes. When the first signal EN1 is a second logic level, it indicates that the erase verification fails.

[0017] The degradation judgment circuit 122 is coupled to the erase verification circuit 121 and receives the first signal EN1. The degradation judgment circuit 122 includes a comparator 126. The degradation judgment circuit 122 can be configured to determine whether the target memory block 114 meets the degradation condition when the target memory block 114 fails the erase verification. In some embodiments, the degradation judgment circuit 122 also includes a counter 127 coupled to the comparator 126. The counter 127 can be configured to receive an erase pulse during an erase operation and count the cumulative number of erase pulses according to the erase pulses. The comparator 126 can be configured to receive the cumulative number of erase pulses and compare it with a predetermined threshold value. When the cumulative number of erase pulses is greater than the predetermined threshold value, the degradation judgment circuit 122 determines that the target memory block 114 meets the degradation condition.

[0018] In another embodiment, the counter 127 may also be configured to receive a cycle operation signal during the erase operation, and count the number of executions of the cycle operation according to the cycle operation signal. The comparator 126 may be configured to receive the number of executions of the cycle operation and compare it with a predetermined threshold value. When the number of executions of the cycle operation is greater than the predetermined threshold value, the degradation determination circuit 122 determines that the target memory block 114 meets the degradation condition.

[0019] In other embodiments, the comparator 126 may also be configured to receive the erase voltage and compare it with a predetermined threshold value. When the erase voltage is greater than the predetermined threshold value, the degradation determination circuit 122 determines that the target memory block 114 meets the degradation condition.

[0020] The comparator 126 of the degradation determination circuit 122 can provide a second signal EN2. When the second signal EN2 is at a first logic level, it indicates that the target memory block 114 is degraded (meets the degradation condition). When the second signal EN2 is at a second logic level, it indicates that the target memory block 114 is not degraded (does not meet the degradation condition).

[0021] In addition, the memory array 110 may further include a count value storage unit 116. The count value storage unit 116 is coupled to the counter 127 of the degradation determination circuit 122 and may be used to store the accumulated number of erase pulses or the number of execution times of the cycle operation.

[0022] The soft programming verification circuit 123 is coupled to the erasure verification circuit 121 and the degradation judgment circuit 122 to receive the first signal EN1 and the second signal EN2 respectively from the erasure verification circuit 121 and the degradation judgment circuit 122. The soft programming verification circuit 123 can be configured to determine whether the target memory block 114 passes the soft programming verification when the target memory block 114 meets the degradation condition and to determine whether the target memory block 114 passes the soft programming verification when the target memory block 114 passes the erasure verification.

[0023] The soft programming verification circuit 123 may be further configured to determine again whether the target memory block 114 passes the soft programming verification after applying the soft programming voltage to the target memory block 114 .

[0024] The soft programming verification circuit 123 may provide a third signal EN3. When the third signal EN3 is at a first logic level, it indicates that the soft programming verification has passed. When the third signal EN3 is at a second logic level, it indicates that the soft programming verification has failed.

[0025] The voltage generation circuit 124 may be configured to generate a soft programming voltage or an erase voltage.

[0026] The control signal generating circuit 125 is coupled to the soft programming verification circuit 123 and the degradation judgment circuit 122, and receives the third signal EN3 and the second signal EN2 from the soft programming verification circuit 123 and the degradation judgment circuit 122, respectively. The control signal generating circuit 125 can be configured to provide a fourth signal EN4 to the voltage generating circuit 124 according to the output results of the soft programming verification circuit 123 and the degradation judgment circuit 122 (i.e., the third signal EN3 and the second signal EN2), so as to control the voltage generating circuit 124 to generate a soft programming voltage or an erase voltage. For example, when the fourth signal EN4 is at the second logic level, the voltage generating circuit 124 is disabled. When the fourth signal EN4 is at the third logic level, the voltage generating circuit 124 is generated to generate a soft programming voltage. When the fourth signal EN4 is at the fourth logic level, the voltage generating circuit 124 is generated to generate an increased erase voltage. In one embodiment, when the number of times the erase voltage is applied is greater than a predetermined threshold value, the voltage generating circuit 124 can increase the voltage value of the erase voltage.

[0027] In addition, the control signal generating circuit 125 may also provide an end signal END. When the end signal END is at a first logic level, it indicates that the erasing operation is ended. When the end signal END is at a second logic level, it indicates that the erasing operation is not ended.

[0028] Table 1 below illustrates the logic levels of the first signal EN1 to the fourth signal EN4 and the end signal END corresponding to the three results of ending the erase operation, applying the soft programming voltage, and applying the increased erase voltage. Among them, Y is the first logic level, N is the second logic level, SPV is the third logic level, and EV is the fourth logic level.

[0029]

[0030] Table 1

[0031] Please also refer to Figure 1 and Figure 2 The flash memory device erasing method of this embodiment is applicable to Figure 1The flash memory device 100 is shown in FIG. 1 . The following describes various steps of the erasing method according to the embodiment of the present invention in conjunction with various components in the flash memory device 100.

[0032] First, in step S202, during the erase operation, the memory control circuit 120 applies an erase voltage to the target memory block 114. Specifically, when the memory control circuit 120 receives an erase command, it applies an erase voltage to the memory cells in the target memory block 114 to reduce the threshold voltage Vt of the memory cells.

[0033] Next, in step S204, the memory control circuit 120 determines whether the target memory block 114 has passed the erasure verification. Specifically, the memory control circuit 120 may determine whether the threshold voltage Vt of all memory cells in the target memory block 114 is less than the erasure verification voltage EV. If so, the memory control circuit 120 determines that the target memory block 114 has passed the erasure verification. If not, the memory control circuit 120 determines that the target memory block 114 has not passed the erasure verification.

[0034] When the target memory block 114 passes the erase verification, in step S206, the memory control circuit 120 performs a soft programming procedure on the target memory block 114. The soft programming procedure may include performing a soft programming verification on the target memory block 114, and ending the erase operation when it is determined that the target memory block 114 passes the soft programming verification; and applying a soft programming voltage to the target memory block 114 and performing the soft programming verification again when it is determined that the target memory block 114 fails the soft programming verification.

[0035] When the target memory block 114 fails to pass the erase verification, in step S208, the memory control circuit 120 determines whether the target memory block 114 meets the degradation condition. When the target memory block 114 does not meet the degradation condition, the memory control circuit 120 increases the erase voltage and returns to step 202. By increasing the erase voltage after determining that the target memory block 114 does not meet the degradation condition, the erase efficiency can be improved. In other words, when it is determined that the target memory block 114 fails to pass the erase verification and does not meet the degradation condition, the memory control circuit 120 does not perform the soft programming procedure on the target memory block 114, but increases the erase voltage and returns to step 202.

[0036] In the present embodiment, the so-called degradation condition is a condition that can determine whether the target memory block 114 is degraded, such as degradation caused by the increase in the time required for the erase operation due to multiple cycle operations. The cycle operation is, for example, a combination of a programming operation and an erase operation. In one embodiment, the degradation condition can be selected from at least one of the following: the cumulative number of erase pulses during the erase operation is greater than a predetermined threshold value (for example, 20 times), the erase voltage is greater than a predetermined threshold value, and the number of executions of the cycle operation is greater than a predetermined threshold value (for example, 20 times), but the present invention is not limited thereto. In one embodiment, a counter for calculating the cumulative number of times the erase voltage is applied and / or a counter for calculating the number of executions of the cycle operation can be configured in the flash memory device 100, and the cumulative number of times the erase voltage is applied or the number of executions of the cycle operation can be stored in a non-volatile storage unit, for example, the cumulative number of times the erase voltage is applied or the number of executions of the cycle operation is stored in a portion of the storage units of the memory array 110.

[0037] In addition, when the target memory block 114 fails to pass the erase verification and meets the degradation condition, in step S210, the memory control circuit 120 alternately performs a soft programming procedure and applies an erase voltage to the target memory block 114. Specifically, in the soft programming procedure, the memory control circuit 120 may first determine whether the threshold voltage Vt of all memory cells in the target memory block 114 is greater than the soft programming verification voltage SPV. If so, the memory control circuit 120 determines that the target memory block 114 passes the soft programming verification. Then, the memory control circuit 120 applies the erase voltage to the target memory block 114 again. In one embodiment, after the erase voltage is applied to the target memory block 114 again, the process may return to step S204 to determine whether the target memory block 114 passes the erase verification.

[0038] In step S210, if the threshold voltages Vt of all memory cells in the target memory block 114 are not all greater than the soft programming verification voltage SPV, the memory control circuit 120 determines that the target memory block 114 has not passed the soft programming verification. At this time, in the soft programming procedure, the memory control circuit 120 may apply the soft programming voltage to the memory cells in the target memory block 114 to increase the threshold voltages Vt of the memory cells (especially the memory cells with lower threshold voltages Vt), and again determine whether the target memory block 114 has passed the soft programming verification. In addition, the memory control circuit 120 may repeatedly perform the steps of determining whether the target memory block 114 has passed the soft programming verification and applying the soft programming voltage if the target memory block 114 has not passed the soft programming verification (hereinafter also referred to as the soft programming procedure) on the target memory block 114 until the target memory block 114 passes the soft programming verification.

[0039] Through the above method, the present invention can dynamically adjust the process of the erase operation according to whether the target memory block 114 meets the degradation condition. That is, compared with the prior art that the soft programming procedure can be performed only when the erase verification is passed, in this embodiment, when the target memory block 114 meets the degradation condition, even if the erase verification is not passed, the memory control circuit 120 can still perform the soft programming procedure on the target memory block 114 to increase the threshold voltage Vt of the memory cell. In this way, the present embodiment can avoid the situation where the threshold voltage Vt of the memory cell in the target memory block 114 is reduced too low and over-erasure occurs, and can effectively reduce the time spent on the soft programming procedure, thereby reducing the time required for the erase operation.

[0040] The following is as follows Figure 3 and Figure 4 The embodiment shown in FIG. 1 further illustrates the erasing method disclosed herein. Figure 4 In FIG. 1 , (a) to (j) respectively represent the distribution range of the threshold voltage Vt of the memory cells in the target memory block 114 at each stage during the erase operation, the horizontal axis is the threshold voltage Vt, and the vertical axis is the number N of memory cells. Please also refer to Figure 1 , Figure 3 and Figure 4 Another embodiment of the flash memory device erasing method of the present invention is applicable to Figure 1 The flash memory device 100 of the present invention is used as an example. The following describes the steps of the erasing method according to the present invention in combination with the various components in the flash memory device 100. Figure 2 The same or similar parts will not be described again.

[0041] First, in step S302, in response to the erase command, the memory control circuit 120 may apply a pre-programming voltage to the target memory block 114. Specifically, Figure 4 As shown in (a), it illustrates the initial distribution range R1 of the threshold voltage Vt of the memory cell before the erase operation is started. In this embodiment, the initial distribution range R1 is less than the erase verification voltage EV, but the present invention is not limited to this. The memory control circuit 120 can apply a pre-programming voltage to all memory cells in the target memory block 114 according to the erase command, so that the threshold voltage Vt of the memory cell is increased to a voltage higher than the voltage corresponding to the logic "1" or equal to the voltage corresponding to the logic "0", thereby avoiding over-erasure after the subsequent application of the erase voltage. Figure 4 As shown in (b), it illustrates that after the pre-programming voltage is applied, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R1 to the distribution range R2.

[0042] Next, in step S304, during the erase operation, the memory control circuit 120 applies an erase voltage to the target memory block 114. The specific details are as described above for step S202 and will not be repeated here.

[0043] Next, in step S306, the memory control circuit 120 determines whether the target memory block 114 passes the erasure verification. The specific details are as described above for step S204 and will not be repeated here. Figure 4 As shown in (c), it illustrates that after the erase voltage is applied, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R2 to the distribution range R3. At this time, since the distribution range R3 is not less than the erase verification voltage EV, the memory control circuit 120 determines that the target memory block 114 has not passed the erase verification.

[0044] When the memory control circuit 120 determines that the target memory block 114 has not passed the erasure verification in step S306, in step S312, Figure 1 As shown, the memory control circuit 120 determines whether the target memory block 114 meets the degradation condition. The degradation condition and the determination method are as described in the previous step S208, and will not be repeated here.

[0045] In step S312, when the target memory block 114 does not meet the degradation condition, the memory control circuit 120 returns to step S304. In other words, when the target memory block 114 does not pass the erase verification and does not meet the degradation condition, the memory control circuit 120 does not perform the soft programming procedure on the target memory block 114, but returns to step S304 to apply the erase voltage to the target memory block 114 again to improve the erase efficiency. Figure 4 As shown in (d), it illustrates that after the memory control circuit 120 applies the erase voltage to the target memory block 114 again, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R3 to the distribution range R4. Since the distribution range R4 is not less than the erase verification voltage EV, the current target memory block 114 still cannot pass the erase verification, so step S312 is executed. When the target memory block 114 does not meet the degradation condition, the memory control circuit 120 returns to step S304. Figure 4 As shown in (e), it illustrates that after the memory control circuit 120 applies the erase voltage to the target memory block 114 again, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R4 to the distribution range R5. Since the distribution range R5 does not fall below the erase verification voltage EV, the current target memory block 114 still cannot pass the erase verification, so step S312 is executed.

[0046] In step S312, when the target memory block 114 meets the degradation condition, step S313 is executed. In the present embodiment, step S313 includes soft programming verification (i.e., step S314) and applying a soft programming voltage when the soft programming verification fails (i.e., step S316). In step S314, the memory control circuit 120 determines whether the target memory block 114 passes the soft programming verification. Specifically, the memory control circuit 120 can determine whether the threshold voltage Vt of all memory cells in the target memory block 114 is greater than the soft programming verification voltage SPV. If so, the memory control circuit 120 determines that the target memory block 114 passes the soft programming verification. If not (e.g., Figure 4 As shown in (e), a portion of the distribution range R5 is less than the soft programming verification voltage SPV), the memory control circuit 120 determines that the target memory block 114 fails the soft programming verification.

[0047] When the target memory block 114 meets the degradation condition and fails the soft programming verification, in step S316, the memory control circuit 120 applies a soft programming voltage to the target memory block 114. Specifically, the memory control circuit 120 may apply a soft programming voltage to the memory cells in the target memory block 114 to increase the threshold voltage Vt of the memory cells (especially the memory cells with a lower threshold voltage Vt) (e.g., Figure 4 Afterwards, the memory control circuit 120 returns to step S314 until the target memory block 114 passes the soft programming verification, thereby avoiding the situation of causing leakage current and affecting the subsequent reading operation. Figure 4 As shown in (f), it illustrates that after the soft programming voltage is applied to the target memory block 114, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R5 to the distribution range R6 (wherein the highest value of the distribution range remains unchanged, and only the lowest value is changed). At this time, since the distribution range R6 is completely located on the right side of the soft programming verification voltage SPV, the memory control circuit 120 can determine that the target memory block 114 passes the soft programming verification when returning to step S314.

[0048] In step S314 , when the memory control circuit 120 determines that the target memory block 114 passes the soft programming verification, the memory control circuit 120 returns to step 304 .

[0049] In one embodiment, before returning to step 304, the memory control circuit 120 may first increase the intensity of the erase voltage, for example, increase the pulse amplitude or pulse width of the erase voltage, so as to apply the erase voltage with increased intensity in the subsequent step 304. In one embodiment, before increasing the intensity of the erase voltage, the memory control circuit 120 may first determine whether the number of times the erase voltage is applied is greater than a predetermined threshold value. When the number of times the erase voltage is applied is greater than the predetermined threshold value, the memory control circuit 120 increases the intensity of the erase voltage, thereby improving the efficiency of the erase operation and avoiding over-erasure.

[0050] like Figure 4 As shown in (g), it illustrates the case where the distribution range of the threshold voltage Vt of the memory cell changes from distribution range R6 to distribution range R7 after returning to step 304. At this time, since the distribution range R7 is not less than the erase verification voltage EV, the current target memory block 114 still cannot pass the erase verification, so step S312 is executed. In this example, as previously described, since the result of step S312 is yes, step S314 is then executed. In step S314, since a portion of the distribution range R7 is less than the soft programming verification voltage SPV (i.e., it fails the soft programming verification), step S316 is then executed. Figure 4 As shown in (h), it illustrates that after the soft programming voltage is applied to the target memory block 114, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R7 to the distribution range R8 (wherein the highest value of the distribution range remains unchanged, and only the lowest value is changed). At this time, since the distribution range R8 is completely located to the right of the soft programming verification voltage SPV, the memory control circuit 120 can determine that the target memory block 114 passes the soft programming verification when returning to step S314. Then, in this example, return to step 304. Figure 4 As shown in (i), it illustrates the case where the distribution range of the threshold voltage Vt of the memory cell changes from distribution range R8 to distribution range R9 after returning to step 304. At this time, since distribution range R9 is smaller than the erase verification voltage EV (i.e., completely falls on the left side of the erase verification voltage EV), in step S306, the memory control circuit 120 can determine that the current target memory block 114 passes the erase verification, and thus executes step S307.

[0051] After the target memory block 114 passes the erase verification, in step S307, the memory control circuit 120 performs a soft programming procedure on the target memory block 114. In the present embodiment, step S307 includes soft programming verification (i.e., step S308) and applying a soft programming voltage when the soft programming verification fails (i.e., step S310). For details of the soft programming verification and the application of the soft programming voltage when the soft programming verification fails, reference may be made to the details previously described, and thus will not be repeated here. However, the difference is that in step S308, when the target memory block 114 passes the soft programming verification, the memory control circuit 120 ends the entire erase operation. That is, when the target memory block 114 passes the erase verification and the soft programming verification, the erase operation ends.

[0052] In this example, since the distribution range R9 is smaller than the erase verification voltage EV and a portion thereof is smaller than the soft program verification voltage SPV, the result of step S308 is no, and step S310 is then executed. Figure 4 As shown in (j), it illustrates that after the soft programming voltage is applied to the target memory block 114, the distribution range of the threshold voltage Vt of the memory cell changes from the distribution range R9 to the distribution range R10 (wherein the highest value of the distribution range remains unchanged, and only the lowest value is changed). At this time, since the distribution range R10 is completely located on the right side of the soft programming verification voltage SPV, the memory control circuit 120 can determine that the target memory block 114 passes the soft programming verification when returning to step S314, and then terminate the entire erase operation.

[0053] It should be noted that Figure 4 The change of the distribution range during the erasing operation is only an example of the present invention, and the present invention is not limited thereto. For example, according to the flash memory device and the erasing method thereof of the present invention, in another embodiment not explicitly shown, after the erasing voltage is applied to the target memory block for the Nth time, the distribution range of the threshold voltage Vt of the memory cell may be as shown in the distribution range R5, and then in step S312, the memory control circuit 120 determines that the target memory block 114 does not meet the degradation condition, and returns to step S304 to apply the erasing voltage to the target memory block for the N+1th time, so that the distribution range of the threshold voltage Vt of the memory cell is as shown in the distribution range R9. Then, step S307 is executed, so that the distribution range of the threshold voltage Vt of the memory cell is between the erase verification voltage EV and the soft programming verification voltage SPV as shown in the distribution range R10, and the erasing operation is terminated. Those skilled in the art can obtain relevant variant embodiments from the spirit of the present invention and the prior art, so all the embodiments are not described one by one in this article.

[0054] The following examples illustrate the technical effect of reducing the erasure time of the present invention. Figure 5 , Figure 5 The horizontal axis is the number of executions of the cycle operation CT, and the vertical axis is the erase time tERS required for the erase operation. Curve T1 shows the relationship between the erase time of the conventional flash memory device and the number of executions of the cycle operation, and curve T2 shows the relationship between the erase time of the flash memory device of the present invention and the number of executions of the cycle operation. Conventional flash memory devices do not dynamically adjust the process of the erase operation, and will not perform the soft programming procedure on the target memory block before passing the erase verification, regardless of whether the degradation condition is met. Therefore, Figure 5 It can be clearly seen that the curve T1 will continue to rise as the number of executions of the cycle operation increases, and the rising trend will not slow down even when the number of executions of the cycle operation is greater than the threshold value th (for example, indicating that the target memory block has met the degradation condition). In other words, the erasing time tERS spent by the traditional flash memory device after executing multiple cycle operations will become longer and longer, becoming a bottleneck that is difficult to break through.

[0055] On the other hand, when the number of executions of the loop operation is below the threshold value th, the curve T2 almost overlaps with the curve T1. However, when the number of executions of the loop operation is greater than the threshold value th (indicating that the target memory block has met the degradation condition), the flash memory device of the present invention can dynamically adjust the process of the erase operation to be as follows: Figure 4 As shown in the example of FIG, even if the erase verification fails, the soft programming process is performed on the target memory block in real time. Figure 5 As shown, when the number of executions of the cycle operation is greater than the threshold value th, the rising trend will gradually slow down. In other words, even after executing multiple cycle operations, the erasing time of the flash memory device of the present invention will not increase indefinitely, and a faster erasing time can be obtained.

[0056] In summary, the flash memory device and the erasing method of the present invention can dynamically adjust the process of the erasing operation according to whether the target memory block meets the degradation condition, so as to appropriately alternately execute the soft programming procedure and apply the erasing voltage. In this way, even after performing multiple cycles, it can be ensured that the erasing time does not increase rapidly to obtain a faster erasing time. In addition, since the erasing time is shortened, the present invention can reduce the energy consumption required for the erasing operation, and the reliability and durability of the flash memory device and the erasing method of the present invention are improved, so the present invention provides a green semiconductor technology.

[0057] Although some embodiments of the present invention and their advantages have been described in detail above, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the invention as defined by the claims of the present invention. For example, those skilled in the art to which the present invention belongs should readily understand that many of the circuits, components and functions described may be changed without departing from the scope of the present invention.

Claims

1. A method for erasing a flash memory device, characterized in that: The following steps are involved: During an erase operation, applying an erase voltage to a target memory block, and determining whether the target memory block passes erase verification; When the target memory block fails the erasure verification, determining whether the target memory block meets a degradation condition; When the target memory block meets the degradation condition, determining whether the target memory block passes the soft programming verification, and returning to the step of applying the erase voltage to the target memory block after the target memory block passes the soft programming verification; When the target memory block does not meet the degradation condition, returning to the step of applying the erase voltage to the target memory block; When the target memory block passes the erasure verification, determining whether the target memory block passes the soft programming verification, and applying a soft programming voltage to the target memory block after the target memory block fails the soft programming verification; as well as When the target memory block passes the erasure verification and the soft programming verification, the erasure operation is ended.

2. The method for erasing a flash memory device according to claim 1, wherein: After applying the soft programming voltage to the target memory block, the method returns to the step of determining whether the target memory block passes the soft programming verification.

3. The method for erasing a flash memory device according to claim 1, wherein: Also includes: When the target memory block meets the degradation condition and after the target memory block fails soft programming verification, the soft programming voltage is applied to the target memory block.

4. The method for erasing a flash memory device according to claim 1, wherein: The degradation condition includes at least one of a cumulative number of erase pulses during the erase operation being greater than a first threshold value, the erase voltage being greater than a preset voltage, and a number of executions of the cycle operation being greater than a second threshold value.

5. The method for erasing a flash memory device according to claim 1, wherein: Also includes: During the erase operation, a pre-programming voltage is applied to the target memory block, The step of determining whether the target memory block passes the erasure verification comprises: Determining whether the threshold voltages of all memory cells in the target memory block are less than an erase verification voltage; as well as If so, it is determined that the target memory block passes the erase verification.

6. The method for erasing a flash memory device according to claim 1, wherein: Also includes: Before returning to the step of applying the erase voltage to the target memory block, determining whether the number of times the erase voltage is applied is greater than a third threshold value; as well as When the number of times the erase voltage is applied is greater than the third threshold value, the erase voltage is increased, and the increased erase voltage is used when returning to the step of applying the erase voltage to the target memory block.

7. A flash memory device, characterized in that: include: a memory array comprising a plurality of memory blocks; as well as A memory control circuit, coupled to the memory array, comprises: an erase verification circuit configured to determine whether the target memory block passes the erase verification after applying an erase voltage to the target memory block during an erase operation; a degradation judgment circuit coupled to the erasure verification circuit, the degradation judgment circuit comprising a comparator configured to judge whether the target memory block meets a degradation condition when the target memory block fails the erasure verification; and A soft programming verification circuit is coupled to the erasure verification circuit and the degradation judgment circuit, and the soft programming verification circuit is configured as follows: When the target memory block meets the degradation condition, determining whether the target memory block passes soft programming verification; and When the target memory block passes the erasure verification, determining whether the target memory block passes the soft programming verification; The memory control circuit is further configured to: After the target memory block meets the degradation condition and passes the soft programming verification, applying the erase voltage to the target memory block again; When the target memory block does not meet the degradation condition, applying the erase voltage to the target memory block again; When the target memory block passes the erase verification but fails the soft programming verification, applying a soft programming voltage to the target memory block; and When the target memory block passes the erasure verification and the soft programming verification, the erasure operation is ended.

8. The flash memory device according to claim 7, wherein: The degradation judgment circuit further includes a counter coupled to the comparator, wherein the counter is configured to receive an erase pulse during the erase operation and count the cumulative number of erase pulses according to the erase pulse. The comparator is configured to receive the accumulated number of the erase pulses and compare it with a predetermined threshold value. When the accumulated number of the erase pulses is greater than the predetermined threshold value, the degradation judgment circuit determines that the target memory block meets the degradation condition.

9. The flash memory device according to claim 7, wherein: The degradation judgment circuit further includes a counter coupled to the comparator, wherein the counter is configured to receive a cycle operation signal during the erase operation and count the number of executions of the cycle operation according to the cycle operation signal. The comparator is configured to receive the execution times of the loop operation and compare it with a predetermined threshold value. When the execution times of the loop operation is greater than the predetermined threshold value, the degradation judgment circuit judges that the target memory block meets the degradation condition.

10. The flash memory device according to claim 8 or 9, characterized in that: The memory array further includes a count value storage unit for storing the accumulated number of the erase pulses or the number of execution times of the cycle operation.

11. The flash memory device according to claim 7, wherein: The soft programming verification circuit is further configured to: After applying the soft programming voltage to the target memory block, it is determined again whether the target memory block passes the soft programming verification.

12. The flash memory device according to claim 7, wherein: The memory control circuit is further configured to apply the soft programming voltage to the target memory block when the target memory block meets the degradation condition and after the target memory block fails soft programming verification.

13. The flash memory device according to claim 7, wherein: The comparator is configured to receive the erase voltage and compare it with a predetermined threshold value. When the erase voltage is greater than the predetermined threshold value, the degradation judgment circuit determines that the target memory block meets the degradation condition.

14. The flash memory device according to claim 7, wherein: The memory control circuit is further configured to: During the erase operation, applying a pre-programming voltage to the target memory block; The erasure verification circuit is configured to determine whether the threshold voltages of all memory cells in the target memory block are less than the erasure verification voltage. If so, it is determined that the target memory block passes the erasure verification.

15. The flash memory device according to claim 11, wherein: Also includes: A voltage generating circuit configured to generate the soft programming voltage or the erase voltage; as well as The control signal generating circuit is coupled to the soft programming verification circuit and the degradation judgment circuit, and controls the voltage generating circuit to generate the soft programming voltage or the erasing voltage according to the output results of the soft programming verification circuit and the degradation judgment circuit.

16. The flash memory device according to claim 15, wherein: The memory control circuit is further configured to determine whether the number of times the erase voltage is applied is greater than a predetermined threshold value before applying the erase voltage to the target memory block again. When the number of times the erase voltage is applied is greater than the predetermined threshold value, the voltage generating circuit increases the voltage value of the erase voltage.

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