Flash memory test method

Abstract

The application discloses a flash memory testing method, which comprises the following steps: providing a flash memory, performing enhanced erasing on the memory cells of the flash memory, wherein the enhanced erasing refers to erasing the memory cells by applying an enhanced erasing voltage VEE' greater than a normal erasing voltage VEE on the word line of the memory cells; after the erasing is completed, performing a write "1" operation test on each memory cell of the flash memory; and if there is a memory cell with failed write "1" operation, the flash memory is rejected. According to the application, the defective flash memory can be fully screened out in the yield testing stage, so that the defective flash memory is prevented from flowing to the end user and the reliability risk of causing end failure is reduced. Moreover, the reliability of the flash memory can be further improved through the test, and the end user mode use failure of the flash memory is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit manufacturing, in particular to a flash memory testing method. BACKGROUND

[0002] As a kind of non-volatile memory, flash memory device has the characteristics of convenience, high storage density and strong reliability, and is widely used. Existing flash memory devices are divided into split gate structure, stacked gate structure or their combination according to different cell structures. Among them, the split gate flash memory device has the characteristics of high programming efficiency and does not have the over-erase effect, so it has been widely used.

[0003] In the process of split gate flash memory, due to process environment defects, some storage units may have abnormal morphology. For example Figure 1 As shown in the figure, in the process of split gate flash memory, due to process environment defects, some storage units have abnormal morphology. The storage structure on the left side of the trench 10 includes a first floating gate 11 and a first word line 21, and the storage structure on the right side of the trench 10 includes a second floating gate 12 and a second word line 22. The first floating gate 11 is normal morphology, and the position of the first floating gate 11 towards the first word line 21 has a sharp corner, and a longitudinal gap is formed between the first floating gate 11 and the first word line 21 downward from the sharp corner. The bit line is formed in the trench 10. The second floating gate 12 (in the red ellipse) is abnormal morphology, and the position of the second floating gate 12 towards the second word line 22 has a sharp corner shape, but extends from the sharp corner to the inside of the second word line 22, and no longitudinal interval is formed between the second floating gate 12 and the second word line 22, but a horizontal interval is formed.

[0004] In general, such defective storage units will be screened out and repaired by the chip erase / read function detection process in the yield test process, and can be normally shipped and used. Although the defective storage unit is repaired in the yield test, other rows in the storage array still share the bit line with the defective storage unit and are not completely independent. Although it is shipped as a normal sample and put into the terminal market, due to the different sizes of the defect morphology, in the continuous use of the terminal user, the bit line of the defective storage unit leaks due to the existence of the defect, which causes the whole column of storage units to fail when writing "1", and further becomes a terminal failure event. SUMMARY

[0005] The embodiment of the present application provides a flash memory testing method to screen out the flash memory with bit line and suspended gate channel leakage defects in the yield test stage, so as to avoid its flow to the terminal user.

[0006] The embodiment of the present application provides a flash memory testing method, which comprises:

[0007] The flash memory includes a memory cell array including a plurality of memory cells arranged in a matrix, the memory cells being split-gate flash memory cells; each of the memory cells includes a floating gate and a bit line; the memory cells in each column share the bit line;

[0008] The memory cells of the flash memory are subjected to enhanced erase, which refers to erasing the memory cells by applying an enhanced erase voltage VEE' greater than a normal erase voltage VEE to the word lines of the memory cells;

[0009] After the erasing is completed, the memory cells of the flash memory are subjected to a write-1 operation test;

[0010] If there is a memory cell whose write-1 operation is failed, the flash memory is rejected.

[0011] Optionally, 1.01VEE≤VEE′≤1.08VEE.

[0012] Optionally, the write-1 operation test is performed multiple times.

[0013] Optionally, the write-1 operation test includes:

[0014] Respective write-1 operation corresponding voltages are applied to the source region, the bit line and the word line of the memory cell;

[0015] Then, a read operation is performed on the memory cell to determine whether the storage bit state is maintained as "1";

[0016] If there is a memory cell whose storage bit state is "0", it is determined that the write-1 operation of the memory cell is failed.

[0017] Optionally, the write-1 operation corresponding voltages include: a source region voltage V S of 8.2V, a bit line voltage V B of 2.5V, and a word line voltage V W of 1.6V.

[0018] Optionally, the method further includes:

[0019] Before the memory cells of the flash memory are subjected to the enhanced erase, the flash memory is subjected to a first test; the first test refers to a pre-baking test

[0020] If the first test is passed, a second test is performed, the second test refers to a post-baking test, and the second test at least includes a data retention capability test;

[0021] After the data retention capability test is passed, the step of subjecting the memory cells of the flash memory to the enhanced erase is performed.

[0022] Optionally, the gate-type flash memory cell includes two memory structures that share a source region and are symmetrically distributed; the memory structure includes a drain region and the source region located in the substrate, the drain region is connected to the bit line, the floating gate and word line are formed on the substrate between the source region and the drain region, a floating gate tip is formed on the side of the floating gate near the word line, and a tunneling oxide layer is formed between the floating gate and the word line.

[0023] Optionally, the method further includes: if multiple memory cells in the same column fail to write "1", then it is determined that the memory cell has a problem with bit line and floating gate channel leakage.

[0024] Alternatively, the leakage problem in the bit lines and floating gate channels may be caused by an abnormal floating gate.

[0025] Optionally, the abnormal floating grid includes a situation where the floating grid tip is not formed on the side of the floating grid near the word line.

[0026] The flash memory testing method provided in this application embodiment performs enhanced erasure on the flash memory during the CP testing stage. This increases the word line channel leakage of memory cells with bit line and floating gate channel leakage problems. Then, a write "1" operation test is performed on the erased memory cells. If any memory cell fails to perform a write "1" operation, it indicates that the flash memory has a potential defect and is thus discarded. Using this solution, defective flash memory can be fully screened out during the yield testing stage, preventing it from reaching end users and reducing the reliability risk of causing end-user failure. Moreover, this test can further improve the reliability of flash memory and prevent flash memory from failing in end-user mode.

[0027] Furthermore, when performing write "1" operation tests, the distribution of write "1" operation failures can be used to roughly determine the location of the problem and the corresponding flash memory defect. For example, if multiple memory cells in the same column fail to perform write "1" operations, it can be determined that there is a problem with the bit line and floating gate channel leakage in that column of memory cells, and this problem is usually caused by abnormal floating gates. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a gate-division flash memory with an unusual morphology;

[0029] Figure 2 This is a diagram illustrating situations where a chip's erased sector would be deemed a failure during a chip erasure test.

[0030] Figure 3 This is a schematic diagram showing the gradual and complete erasure of failed cells when all sectors are erased.

[0031] Figure 4is a flow chart of a flash memory test method provided by an embodiment of the present application;

[0032] Figure 5 is a schematic diagram of a flash memory of an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of a principle of a flash memory of an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0035] It should be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0036] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0037] The terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0038] CP (Chip Pobing, chip probe test) is aimed at an uncut wafer, which needs to be contacted with a test pad on the wafer by a probe, and a single or multiple Die (die) on the wafer can be tested at a time. CP test generally includes three stages of test, i.e. CP1 test basic storage read-write function, and write certain content in the storage chip; then the wafer is baked at high temperature, and CP2 test is performed to detect whether the data written before can be maintained; finally, CPE test is performed on the logic function of the MCU (main control unit) part.

[0039] The test flow of CP1 mainly includes the following steps:

[0040] (1) Open / short test and leakage test

[0041] The open / short test is mainly used to find out whether there is a short circuit between the pins of the chip and whether a bonding wire is missing during the packaging of the chip. The leakage test is used to detect the leakage current of the input pin of the chip when a voltage is applied.

[0042] (2) Chip erase / read function detection

[0043] The detection is mainly used to screen out chips that cannot complete basic erase, program and read / write operations. During the test, the chip is subjected to erase and program operations on a single sector or the entire flash memory array under different operating voltages, and then the chip is read to determine whether it can pass the test.

[0044] In this process, the sector in which the failed unit with an abnormal floating gate morphology is located will be determined as a failed sector during the chip erase test, and will be counted as a sector to be repaired, as shown in FIG. 2. Figure 2

[0045] (3) Program crosstalk test

[0046] The crosstalk test detects whether the erase state of the unselected unit during programming is changed due to accidental programming by simulating the pressure condition of the unselected unit during programming.

[0047] (4) Writing a flag into the NVR1 and erasing the chip

[0048] In this process, all sectors are erased, that is, the sectors counted as sectors to be repaired in the detection process in step (2) above are also subjected to erase operations. During the erase, the F-N electron tunneling effect caused by the high electric field between the word line and the floating gate causes the electrons to be pulled out of the floating gate, as shown in FIG. 3. This means that the above-mentioned failed units will be gradually erased sufficiently, and the threshold voltage of the word line channel will be lowered. Figure 3

[0049] Through the above erase operation, the above-mentioned sectors to be repaired may be repaired and shipped as normal samples. However, due to the different sizes of defect morphology, the bit line of the defective storage unit may have a leakage during the continuous use of the end user, resulting in failure of the entire column of storage units during the write "1" operation. This problem poses a great potential risk for terminal applications with high reliability requirements such as vehicles.

[0050] The CP2 test is mainly a function test on the baked chip to detect its data retention capability. Generally, the CP2 test process mainly includes the following steps:

[0051] ​​(1) Open / short test and leakage test

[0052] Similar to the corresponding step in CP1 test, the open / short test is mainly used to find out whether there is a short circuit between pins of the chip and whether a bonding wire is missing during packaging of the chip; and the leakage test is used to detect the leakage current of the input pin of the chip when a voltage is applied.

[0053] (2) NVR1 verification

[0054] The NVR1 verification is used to verify whether the flag written in the NVR1 in the CP1 test is correct.

[0055] (3) Data retention capability and endurance test

[0056] The data retention capability refers to the capability of a storage unit to maintain a programmed state within an acceptable time period.

[0057] The endurance test is used to represent the maximum number of program / erase (P / E) times of a storage unit without failure after multiple P / E times.

[0058] It should be noted that the test items and processes of CP1 and CP2 described above are only some conventional test items and processes, and other test items and different test processes can be used in the CP test stage according to different manufacturers and products, and the embodiments of the present application do not limit this.

[0059] In view of the problem that the bit line of the storage unit of the sector repaired in the CP1 test stage may have a leakage, which may cause failure of the entire column of storage units during the write "1" operation, the embodiments of the present application provide a flash memory test method, which performs enhanced erasing on the flash memory before the flash memory flows into the end user, and performs a write "1" operation test on all storage units after the enhanced erasing, so as to further screen out the flash memory with certain defects and avoid the flash memory from flowing into the end user.

[0060] The flash memory test method provided by the embodiments of the present application can be performed in the CP test stage, and can be performed at any stage after the data retention capability test of CP2 described above.

[0061] It should be noted that the specific test items and processes of the first test (i.e., the CP1 test before baking) and the second test (i.e., the CP2 test after baking) can be different for different manufacturers and different types of flash memories produced by the same manufacturer, and the embodiments of the present application do not limit this.

[0062] For example, in one non-limiting embodiment, after the flash memory is provided, a first test is performed, the first test at least including a chip erase / read function detection, after the test is completed, a flag is written into the NVR1, and the chip is erased; after the first test is passed, the wafer is sent into an oven for high-temperature baking, and then a second test is performed, the second test at least including an open-short test, a data retention capability test, and a data durability test, after the test is passed, the enhanced erase operation in the embodiment of the present application is performed.

[0063] For example, in another non-limiting embodiment, after the flash memory is provided, a first test is performed, after the first test is passed, the wafer is sent into an oven for high-temperature baking, and then a second test is performed, during the second test, an open-short test, NVR1 verification, and a data retention capability test are performed in sequence, after the test is passed, the enhanced erase operation and the write "1" operation test in the embodiment of the present application are performed, after the test is passed, a data durability test is performed.

[0064] As shown in Figure 4 , it is a flow chart of the flash memory test method provided by the embodiment of the present application.

[0065] The execution process and principle of the flash memory test method of the embodiment of the present application will be described in detail below in combination with Figure 5 and Figure 6 , wherein, Figure 5 is a schematic diagram of the flash memory of the embodiment of the present application, Figure 6 is a principle schematic diagram of the flash memory of the embodiment of the present application.

[0066] In step 401, a flash memory is provided, the flash memory including a storage cell array, the storage cell array including a plurality of storage cells arranged in a matrix, the storage cells being split-gate flash memory cells; each of the storage cells including a floating gate and a bit line; the storage cells in each column sharing the bit line.

[0067] As shown in Figure 5 and Figure 6 , the flash memory includes a storage cell array, the storage cell array including a plurality of storage cells A arranged in a matrix, the storage cells being split-gate flash memory cells; each of the storage cells including a floating gate 11 and a bit line 13; the storage cells in each column sharing one bit line 13. A plurality of split-gate flash memory cells are formed in parallel on a semiconductor substrate. The material of the semiconductor substrate can be silicon, germanium, silicon germanium, or silicon carbide, etc., can also be Silicon-On-Insulator (SOI) or Germanium-on-Insulator (GOI), or can also be other materials, such as gallium arsenide, etc. Group III, Group V compound.

[0068] In this embodiment, one split-gate flash memory cell includes two memory structures which are symmetrically distributed and share the same source region 14. Each split-gate flash memory cell includes a drain region 15, a source region 14 formed in a semiconductor substrate, and a source line (not shown) connecting the source region 14 formed on the semiconductor substrate above the source region 14. The drain region 15 is connected to a bit line 13, and a word line 21 is formed between the source region 14 and the drain region 15. The two word lines 21 of the same split-gate flash memory cell are formed on the two sides of the source line. A floating gate oxide layer, a floating gate 11, and a side wall are formed on the semiconductor substrate between the source line and the word line 21. A tunneling oxide layer is formed between the floating gate 11 and the word line 21. The floating gate 11, the word line 21, and the source line can all be made of polysilicon. A floating gate tip is formed on one side of the floating gate 11 close to the word line 21. The left memory structure and the right memory structure are symmetrically distributed and share the same source line. In this embodiment, the source region 14 and the drain region 15 are both N-type doped, for example.

[0069] When the split-gate flash memory cell is programmed, the word line 21 acts as a control gate. A high voltage is applied to the source region 14, a voltage which can open the channel is applied to the word line 21, and a constant current is applied through the drain region 15. The source region 14 is at a high potential. Under the action of the high potential, on one hand, hot electrons are generated in the channel, and on the other hand, the high potential is coupled to the floating gate 11, and the floating gate 11 generates a coupling voltage. Under the action of the coupling voltage, electrons are injected from the channel to the floating gate 11, thereby realizing programming. Programming is also referred to as a write "0" operation.

[0070] In step 402, the memory cell of the flash memory is subjected to enhanced erasing, which refers to erasing the memory cell by applying an enhanced erasing voltage VEE' greater than a normal erasing voltage VEE to the word line of the memory cell.

[0071] The enhanced erasing voltage VEE' is greater than the normal erasing voltage VEE. In some embodiments, for example, the enhanced erasing voltage VEE' can satisfy the following condition: 1.01VEE≤VEE'≤1.08VEE.

[0072] For example, in a conventional CP test, the normal erasing voltage VEE applied to the word line is 12V. In the enhanced erasing test described above, a high voltage of 12.5V is applied to the word line.

[0073] Referring to Figure 5 and Figure 6 When the split-gate flash memory cell is subjected to enhanced erasing, the enhanced erasing voltage VEE' is applied to all the word lines. The floating gate tip lowers the channel voltage of the tunneling effect by the tip discharge principle, and can make electrons pass through the tunneling oxide layer from the tip of the floating gate 11 to the word line 21. After the memory cell is erased, the storage bit of the memory cell is in a "1" state; that is, all the memory cells of the flash memory are erased to "1".

[0074] Step 403, after erasing, write "1" operation test is performed on each memory cell of the flash memory.

[0075] If there is a memory cell whose write "1" operation is invalid, step 404 is performed to eliminate the flash memory; otherwise, the test is passed and the test is ended.

[0076] For the flash memory, programming is also called write "0" operation, through which the state of the memory cell can be changed from "1" to "0". Specifically, by applying a programming voltage on several memory cells that need to be programmed, the electrons of the corresponding memory cell are made to enter the floating gate from the substrate channel to complete the programming, and the state of the memory cell after programming is "0".

[0077] In the embodiment of the present application, the write "1" operation refers to maintaining the storage bit of the memory cell after erasing as "1" state, and the principle is to apply a voltage on the memory cell that does not need to be programmed, so that the memory cell does not meet the programming condition, the voltage of the channel is not opened, and the electrons of the corresponding memory cell will not enter the floating gate 11 from the substrate, so the state of the memory cell is "1".

[0078] In the embodiment of the present application, the source region, bit line and word line of the memory cell are respectively applied with write "1" operation corresponding voltage. For example, the write "1" operation voltage conditions can include: the source region voltage V S is 8.2V, the bit line voltage V B is 2.5V, and the word line voltage V W is 1.6V. Then, a read operation is performed on the memory cell to determine whether the storage bit state is maintained as "1"; if there is a memory cell whose storage bit state is "0", it is determined that the write "1" operation of the memory cell is invalid.

[0079] Step 404, eliminating the flash memory.

[0080] The principle of screening the memory cell with a floating gate and a floating gate channel leakage using the method of the present application will be further explained below. Figure 5 and Figure 6

[0081] Referring to Figure 5 and Figure 6 , the memory cell array includes a plurality of memory cells A arranged in a matrix, and it is assumed that the floating gate of a memory cell B is abnormal, for example, there is an abnormal condition as shown in the figure. Figure 1

[0082] When the memory cell B is first used, the source region voltage V S is applied with the bit line voltage V B ​​The differential pressure between the source voltage V

[0083] In continuous use, the bit line 13 of the storage unit B leaks, causing the suppression voltage, i.e. the bit line voltage V B to be pulled down, and accordingly, the source voltage V S becomes larger than the bit line voltage V B . When the differential pressure between the source voltage V S and the bit line voltage V B is greater than the channel opening voltage, the corresponding storage units on the entire column of the bit line 13 will have electrons from the substrate into the floating gate 11, and the entire column of storage units will be programmed to "0", i.e. the storage bit state of the entire column of storage units will change from "1" to "0".

[0084] Therefore, the storage unit B with a floating gate defect will cause the write "1" operation to fail in subsequent use due to the leakage between the bit line 13 and the floating gate in use.

[0085] According to the scheme, the enhanced erase voltage VEE' is applied to all word lines, and since the enhanced erase voltage VEE' is greater than the applied voltage VEE on the word line during the conventional erase test, the electrons in the floating gate 11 can pass through the tunneling oxide layer into the word line 21 as much as possible, so that the word line channel leakage of the storage unit with the leakage problem between the bit line and the floating gate channel is increased.

[0086] For the flash memory that passes the above test, the write "1" operation test is continued, and if the storage unit B has a leakage defect between the bit line and the floating gate channel, the storage bits of the entire column of storage units in which the storage unit B is located cannot be maintained as "1", i.e. the corresponding entire column or most of the storage units in the column fail to write "1", and thus the storage units in the entire column in which the storage unit B is located can be screened out to avoid flowing into the end user, thereby bringing potential risks to the application of the end user.

[0087] It should be noted that when the write "1" operation test is performed, if one or a few storage units fail to write "1", it may be caused by other reasons. For such flash memories, the scheme can also be used to eliminate them in the yield test stage, thereby fully guaranteeing the quality of the flash memories flowing to the end user.

[0088] It should be understood that the term "and / or" herein merely describes the association relationship of the associated objects, and can represent three relationships, for example, A and / or B, which can represent three cases of A alone, A and B together, and B alone. In addition, the character " / " herein represents an "or" relationship between the associated objects before and after it.

[0089] The "multiple" appearing in the embodiments of the present application refers to two or more than two.

[0090] The first, second and the like appearing in the embodiments of the present application are only for the purpose of description and distinguishing the description objects, and do not have the order, nor represent the special limitation of the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0091] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the device disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0092] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A flash memory testing method, characterized in that, The method includes: A flash memory is provided, the flash memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells arranged in a matrix, the memory cells being grid-type flash memory cells; each memory cell comprising a floating gate and a bit line; the memory cells in each column sharing the bit line; Enhanced erasure is performed on the memory cell of the flash memory. Enhanced erasure refers to applying an enhanced erasure voltage VEE′ greater than the normal erasure voltage VEE to the word line of the memory cell to erase the memory cell. After erasure, a write "1" operation test is performed on each memory cell of the flash memory. The write "1" operation means applying voltage to the memory cell so that the memory cell does not meet the programming conditions, the voltage of the channel is not turned on, and the memory bit of the memory cell is kept in the "1" state after erasure. If a write "1" operation fails in a storage cell, the flash memory is discarded.

2. The flash memory testing method according to claim 1, characterized in that, 1.01VEE≤VEE′≤1.08VEE.

3. The flash memory testing method according to claim 1, characterized in that, Perform multiple write "1" operations on the flash memory to test.

4. The flash memory testing method according to claim 1, characterized in that, The test of writing "1" to the flash memory includes: Apply the voltage corresponding to the write "1" operation to the source region, bit line, and word line of the memory cell respectively; Then, a read operation is performed on the storage unit to determine whether the storage bit state remains "1"; If the storage bit state of a storage cell is "0", then the write "1" operation of that storage cell is determined to be invalid.

5. The flash memory testing method according to claim 4, characterized in that, The voltages corresponding to the write "1" operation include: source voltage V S It is 8.2V, bit line voltage V B It is 2.5V, word line voltage V W It is 1.6V.

6. The flash memory testing method according to claim 1, characterized in that, The method further includes: Before performing enhanced erasure on the storage cells of the flash memory, a first test is performed on the flash memory; the first test refers to the pre-baking test; If the first test passes, the second test is performed. The second test refers to the test after baking, and the second test includes at least a data retention test. After the data retention capability test is passed, the step of enhancing the erasure of the storage cell of the flash memory is performed.

7. The flash memory testing method according to any one of claims 1 to 6, characterized in that, The gate-type flash memory cell includes two memory structures that share a source region and are symmetrically distributed. The memory structure includes a drain region and a source region located in the substrate. The drain region is connected to the bit line. The floating gate and word line are formed on the substrate between the source region and the drain region. A floating gate tip is formed on the side of the floating gate near the word line. A tunneling oxide layer is formed between the floating gate and the word line.

8. The flash memory testing method according to claim 7, characterized in that, The method further includes: If multiple memory cells in the same column fail to write "1", it is determined that the memory cell has a problem with leakage in the bit line and floating gate channel.

9. The flash memory testing method according to claim 8, characterized in that, The leakage issues in the bit lines and floating gate channels are caused by abnormal floating gates.

10. The flash memory testing method according to claim 9, characterized in that, The abnormal floating grid includes a situation where the floating grid tip is not formed on the side of the floating grid near the word line.

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