A plasma processing apparatus and a method of processing a wafer thereof

Abstract

The embodiments of the present disclosure disclose a plasma processing device and a method for processing a wafer by the plasma processing device. The plasma processing device comprises a reaction chamber, a carrier located at the bottom of the reaction chamber and used for carrying the wafer, a focusing ring located in the reaction chamber and arranged around the carrier, and a variable resistance layer covering the lower surface of the focusing ring, wherein the resistance of the variable resistance layer is adjustable.

Description

Technical Field

[0001] This disclosure relates to the field of plasma processing apparatus, and more particularly to a plasma processing apparatus and a method for processing wafers therein. Background Technology

[0002] Plasma processing equipment, such as plasma etching equipment, uses radio frequency coupled discharge to generate plasma, which is then used to process the wafer. The plasma typically includes a stage for supporting the wafer, and a focusing ring surrounding the wafer. The focusing ring is used to adjust the electric field distribution around the wafer, ensuring uniform etching.

[0003] However, the upper surface of the focusing ring is exposed to the plasma environment and will be consumed as the etching process proceeds. This will cause changes in the electric field around the wafer, resulting in changes in the etching direction and rate at the wafer edge, and affecting the uniformity of wafer processing. Summary of the Invention

[0004] This disclosure provides a plasma processing apparatus, including:

[0005] reaction chamber;

[0006] A stage, located at the bottom of the reaction chamber, is used to support the wafer;

[0007] A focusing ring is located within the reaction chamber and surrounds the stage;

[0008] A variable resistance layer covers the lower surface of the focusing ring, and the resistance of the variable resistance layer is adjustable.

[0009] In some embodiments, the variable resistance layer includes a photoresistor layer.

[0010] In some embodiments, the photoresistor layer includes a doped semiconductor layer.

[0011] In some embodiments, the material of the photoresistor layer includes one or a combination of metal sulfides, selenides, and tellurides.

[0012] In some embodiments, the plasma processing apparatus further includes at least one light source disposed below the photoresistor layer, the light source being used to provide illumination to the photoresistor layer, and the illumination intensity of the light source being adjustable.

[0013] In some embodiments, the light source includes an LED cold light source.

[0014] In some embodiments, the plasma processing apparatus further includes: a protective cover located below the photoresistor layer, the protective cover including a first sub-part and a second sub-part extending vertically below the first sub-part and connected to the first sub-part, the second sub-part being disposed around the light source, the light source being located within the space formed by the protective cover.

[0015] This disclosure also provides a method for processing a wafer using a plasma processing apparatus, employing the plasma processing apparatus as described in any of the preceding embodiments, the method comprising:

[0016] The wafer is placed on the stage;

[0017] The wafer is subjected to a processing procedure.

[0018] In some embodiments, during the processing of the wafer, the method further includes:

[0019] Adjust the resistance of the variable resistance layer.

[0020] In some embodiments, the variable resistance layer includes a photoresistor layer; the plasma processing apparatus further includes: at least one light source disposed below the variable resistance layer, the light source being used to provide illumination to the photoresistor layer, the illumination intensity of the light source being adjustable;

[0021] Adjusting the resistance of the variable resistance layer includes:

[0022] Adjust the light intensity of at least one of the light sources.

[0023] This disclosure provides a plasma processing apparatus and a method for processing a wafer, wherein the plasma processing apparatus includes: a reaction chamber; a stage located at the bottom of the reaction chamber for supporting the wafer; a focusing ring located within the reaction chamber and surrounding the stage; and a variable resistance layer covering the lower surface of the focusing ring, the resistance of which is adjustable. The lower surface of the focusing ring provided in this disclosure is provided with a variable resistance layer, the resistance of which is adjustable. Thus, by adjusting the resistance of the variable resistance layer, the overall impedance of the focusing ring and the variable resistance layer can be adjusted, thereby adjusting the thickness of the sheath layer above the focusing ring. This makes the wafer edge region and the upper surface of the sheath layer above the focusing ring flush or substantially flush, thereby adjusting the incident direction and incident rate of the plasma in the wafer edge region, improving the processing uniformity, such as etching uniformity, between the wafer edge region and the center region.

[0024] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of a plasma processing apparatus provided in an embodiment of this disclosure;

[0027] Figure 2 for Figure 1 The diagram shows a bottom view of the protective cover and light source.

[0028] Figures 3a to 3c Different examples of schematic diagrams of the sheath layer structure during wafer processing;

[0029] Figure 4 A top view schematic diagram of a chip provided in an embodiment of this disclosure;

[0030] Figure 5 This is a flowchart of a method for processing a wafer provided in an embodiment of the present disclosure;

[0031] Figure 6 A process flow diagram of a wafer processing method provided in an embodiment of this disclosure. Detailed Implementation

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Plasma processing equipment, such as plasma etching equipment, typically includes a reaction chamber and a stage located within the reaction chamber to hold the wafer to be processed. The stage also serves as the lower electrode of the reaction chamber. Reactive gas is introduced into the reaction chamber, and one or more radio frequency (RF) power supplies can be individually applied to the lower electrode to deliver RF power, thereby generating an RF electric field inside the reaction chamber. The reactive gas introduced into the reaction chamber is excited by the RF electric field to generate plasma (including active particles such as electrons, cations, and electrically neutral free radicals). Chemical reactions and / or physical interactions (such as etching) occur between the plasma and the wafer to form various feature structures.

[0039] In the manufacturing process, electrons, being smaller in mass than cations, are more easily accelerated by radio frequency electric fields, resulting in a higher velocity. Electrons gradually accumulate on the surfaces of the wafer and focusing ring, forming a negative electric field (i.e., a sheath). The wafer and focusing ring are gradually biased to a negative voltage. Under the pull of this negative electric field, cations are incident on the surface of the wafer to be processed, thus performing the processing. The thickness of the sheath determines the energy and direction of the cations incident on the wafer. The focusing ring controls the sheath thickness at the wafer's edge, ensuring uniform etching. However, the upper surface of the focusing ring is exposed to the plasma environment and is consumed during the etching process. This leads to changes in the electric field around the wafer, causing variations in the etching direction and rate at the wafer edges, thus affecting the uniformity of wafer processing.

[0040] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0041] This disclosure provides a plasma processing apparatus, including: a reaction chamber; a stage located at the bottom of the reaction chamber for supporting a wafer; a focusing ring located within the reaction chamber and disposed around the stage; and a variable resistance layer covering the lower surface of the focusing ring, wherein the resistance of the variable resistance layer is adjustable.

[0042] The lower surface of the focusing ring provided in this embodiment is provided with a variable resistance layer. The resistance of the variable resistance layer is adjustable. Thus, by adjusting the resistance of the variable resistance layer, the overall impedance of the focusing ring and the variable resistance layer can be adjusted, thereby adjusting the thickness of the sheath layer above the focusing ring. This makes the wafer edge region and the upper surface of the sheath layer above the focusing ring flush or substantially flush, thereby adjusting the incident direction and incident rate of plasma in the wafer edge region and improving the processing uniformity, such as etching uniformity, in the wafer edge region and the center region.

[0043] It should be noted that the plasma processing apparatus provided in this disclosure can be applied to plasma etching processes, such as ion beam etching (IBE) and reactive ion etching (RIE). However, it is not limited to these applications; the plasma processing apparatus can also be applied to other plasma processes.

[0044] The specific embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, the schematic diagrams may be partially enlarged without adhering to the usual proportions for ease of explanation, and the schematic diagrams are merely examples and should not be construed as limiting the scope of protection of this disclosure.

[0045] like Figure 1 As shown, the plasma processing apparatus includes: a reaction chamber 10; a stage 12 located at the bottom of the reaction chamber 10 for supporting a wafer; a focusing ring 16 located inside the reaction chamber 10 and surrounding the stage 12; and a variable resistance layer 17 covering the lower surface of the focusing ring 16, the resistance of which is adjustable.

[0046] like Figure 1 As shown, the plasma processing apparatus also includes a reaction chamber wall 101, which surrounds the reaction chamber 10, and a wafer inlet 102 is provided on the side of the reaction chamber wall 101. In actual processes, the wafer to be processed can be placed on the stage 12 through the wafer inlet 102.

[0047] In some embodiments, the plasma processing apparatus further includes a vacuum pump 11 in communication with the reaction chamber 10. In actual operation, the vacuum pump 11 can be used to discharge the processing gas in the reaction chamber 10 to regulate the pressure inside the reaction chamber 10.

[0048] In some embodiments, the stage 12 may be an electrostatic chuck. The electrostatic chuck may include a dielectric layer 121 and a base 122 located below the dielectric layer. Electrostatic electrodes may be disposed in the dielectric layer 121. When processing the wafer, a voltage may be applied to the electrostatic electrodes in the electrostatic chuck by a DC power supply, so that the surface of the electrostatic chuck and the back of the wafer generate polarized charges of opposite polarity, thereby generating electrostatic attraction between the electrostatic chuck and the wafer, and thus fixing the wafer on the electrostatic chuck.

[0049] In some embodiments, the plasma processing apparatus further includes: a gas spray head 14 disposed opposite to the stage 12, and a gas supply device 15 connected to the gas spray head 14. The gas spray head 14 serves as the upper electrode of the plasma processing apparatus and is also used to introduce the gas required for processing the wafer from the gas supply device 15 into the reaction chamber 10.

[0050] In some embodiments, the base 122 in the stage 12 can be made of metal or metal alloy, and the base 122 in the stage 12 can serve as the lower electrode of the plasma processing device; the plasma processing device also includes an RF power supply 13 connected to the base 122. The RF power supply 13 is used to generate an RF electric field between the upper and lower electrodes. Most of the RF electric field is contained in the processing region above the stage 12. This RF electric field accelerates a small number of electrons present inside the reaction chamber, causing them to collide with gas molecules of the reactive gas input into the reaction chamber 10. These collisions lead to ionization of the reactive gas and excitation of the plasma, thereby generating plasma (including active particles such as electrons, cations, and electrically neutral free radicals) within the reaction chamber 10. The plasma can be used to perform processes such as plasma etching on the wafer.

[0051] During the wafer processing, electrons, being less massive than cations, are more easily accelerated by the radio frequency electric field, resulting in a higher velocity. Electrons gradually accumulate on the surfaces of the wafer and focusing ring 16, forming a negative electric field, or sheath, on their surfaces. The wafer and focusing ring 16 are gradually biased to a negative voltage. Under the pull of this negative electric field, cations are incident on the surface of the wafer to be processed, thus performing the processing. The thickness of the sheath 21 determines the energy and direction of the cations incident on the wafer. The focusing ring 16 controls the sheath thickness at the edge of the wafer, ensuring uniform wafer etching.

[0052] Figures 3a to 3c Different examples of schematic diagrams of the sheath 21 during the processing of wafer 20 are shown, where arrow A indicates the incident direction of cations. Figure 4 This is a top view of the chip 20, which includes a central region 201 and an edge region 202 surrounding the central region 201.

[0053] like Figures 3a to 3c As shown, in some embodiments, the upper surface of the focusing ring 16 is higher than the upper surface of the stage 12, so that after the wafer 20 is placed on the stage 12, the focusing ring 16 can surround the wafer 20, thereby enabling the sheath thickness of the edge region 202 of the wafer 20 to be controlled by the focusing ring 16.

[0054] like Figure 3aAs shown, the applicant discovered that during the processing of wafer 20, the focusing ring 16 is also exposed to plasma. As the processing progresses, its material is lost, which leads to a decrease in the height of the upper surface of the focusing ring 16. Consequently, the height of the sheath 21 on the surface of the focusing ring 16 decreases. The upper surface of the sheath 21 above the wafer 20 is higher than the upper surface of the sheath 21 above the focusing ring 16. The sheath 21 at the junction of the wafer 20 and the focusing ring 16 tilts. During the processing of wafer 20, the incident direction of cations in the central region 201 of wafer 20 is perpendicular to the plane of wafer 20, while the incident direction of cations in the edge region 202 of wafer 20 tilts inward toward the wafer 20. This causes a difference in parameters such as the processing rate of the edge region 202 of wafer 20 compared to the central region 201 of wafer 20. For example, when performing an etching process on wafer 20, the etching direction of the edge region 202 of wafer 20 is tilted towards the inside of wafer 20, and the etching rate of the edge region 202 of wafer 20 is greater than the etching rate of the center region 201 of wafer 20, thus reducing the uniformity of wafer 20 processing.

[0055] Furthermore, the applicant also discovered that during the processing of wafer 20, there may be situations that cause an increase in the impedance of the focusing ring 16, resulting in the thickness of the sheath 21 above wafer 20 being greater than the thickness of the sheath 21 above the focusing ring 16. The upper surface of the sheath 21 above wafer 20 is higher than the upper surface of the sheath 21 above the focusing ring 16, causing the sheath 21 at the junction of wafer 20 and focusing ring 16 to tilt. This causes the incident direction of cations in the edge region 202 of wafer 20 to tilt inward toward wafer 20, resulting in a difference in parameters such as the processing rate of the edge region 202 of wafer 20 compared with the central region 201 of wafer 20.

[0056] like Figure 3bAs shown, the applicant also discovered that during the etching process of wafer 20, certain situations may occur that cause a decrease in the impedance of the focusing ring 16, resulting in a thinner sheath 21 above wafer 20 than the sheath 21 above the focusing ring 16. The upper surface of the sheath 21 above wafer 20 is lower than the upper surface of the sheath 21 above the focusing ring 16, causing the sheath 21 at the interface between wafer 20 and the focusing ring 16 to tilt. During the processing of wafer 20, the sheath 21's pull on the cations in the edge region 202 of wafer 20 tilts outwards, causing a difference in processing rate between the edge region 202 and the central region 201 of wafer 20. For example, during the etching process of wafer 20, the etching direction of the edge region 202 tilts outwards, and the etching rate of the edge region 202 is lower than the etching rate of the central region 201, reducing the uniformity of wafer 20 processing.

[0057] Specifically, in actual operation, a variety of situations may cause changes in the impedance of the focusing ring, such as: (1) the aging of the focusing ring material after long-term use may cause an increase in the impedance of the focusing ring; (2) mechanical damage such as scratches or wear on the surface of the focusing ring may cause an increase in the local resistance of the focusing ring, resulting in an increase in the overall impedance of the focusing ring; (3) when there are pollutants such as reaction byproducts, dust, and ions on the surface of the focusing ring, the pollutants may form additional conductive paths, resulting in a decrease in the impedance of the focusing ring; (4) water can act as an electrolyte, and an increase in ambient humidity may cause a decrease in the impedance of the focusing ring; (5) poor contact between the focusing ring and other components or oxidation at the connection points between the focusing ring and other components will increase the contact resistance, resulting in an increase in the impedance of the focusing ring; (6) the material of the focusing ring may react with chemicals in the environment, resulting in an increase or decrease in the impedance of the focusing ring; in addition, electrostatic effects may cause charge to accumulate on the surface of the focusing ring, which usually does not cause a change in the impedance of the focusing ring, but may affect the potential distribution on the surface of the focusing ring, indirectly affecting the overall electrical performance.

[0058] It should be noted that the impedance changes of the focusing ring under the above conditions are not absolute; they depend on the specific materials and conditions. In practical applications, it may be necessary to determine the specific changes in the focusing ring impedance through experiments or detailed analysis.

[0059] like Figure 3cAs shown, in this embodiment, a variable resistance layer 17 is provided on the lower surface of the focusing ring 16. The resistance of the variable resistance layer 17 is adjustable. Thus, by adjusting the resistance of the variable resistance layer 17, the overall impedance of the focusing ring 16 and the variable resistance layer 17 can be adjusted, thereby adjusting the thickness of the sheath layer 21 located above the focusing ring 16. This makes the sheath layer 21 on the surface of the wafer 20 and the upper surface of the sheath layer 21 on the surface of the focusing ring 16 flush or substantially flush, thereby adjusting the incident direction and incident rate of cations in the edge region 202 of the wafer 20 and improving the processing uniformity of the edge region 202 and the central region 201 of the wafer 20. For example, when the upper surface of the sheath 21 above the focusing ring 16 is lower than the upper surface of the sheath 21 above the wafer 20, the resistance of the variable resistor layer 17 can be decreased, thereby increasing the thickness of the sheath 21 above the focusing ring 16; when the upper surface of the sheath 21 above the focusing ring 16 is higher than the upper surface of the sheath 21 above the wafer 20, the resistance of the variable resistor layer 17 can be increased, thereby decreasing the thickness of the sheath 21 above the focusing ring 16. Thus, by adjusting the impedance of the focusing ring 16 and the variable resistor layer 17, the upper surfaces of the sheath 21 above the wafer 20 and the sheath 21 above the focusing ring 16 are made flush or substantially flush.

[0060] In actual operation, by monitoring parameters such as etching rate and etching direction of the central region 201 and edge region 202 of the wafer 20, the thickness of the sheath layer 21 above the focusing ring 16 and the sheath layer 21 above the wafer 20 can be determined, and the resistance value of the variable resistor layer 17 can be adjusted based on the determination result.

[0061] In some embodiments, the material of the focusing ring 16 is at least one of the following: quartz, alumina, aluminum nitride, monocrystalline silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxide, for example, silicon.

[0062] In practice, a variable resistance layer 17 can be formed on the lower surface of the focusing ring 16 using one or more thin film processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0063] In some embodiments, the variable resistive layer 17 includes a photoresistive layer 171. In actual operation, under dark conditions, most of the electrons inside the photoresistive layer 171 are valence band electrons that cannot move freely, and the resistance of the photoresistive layer 171 is very high. When there is light of a suitable wavelength, the valence band electrons in the photoresistive layer 171 absorb photon energy and jump to the conduction band, becoming free electrons that can conduct electricity, leaving a hole in the valence band. The resistance of the photoresistive layer 171 decreases, and the greater the light intensity, the more electron-hole pairs are excited in the photoresistive layer 171, and the lower the resistance of the photoresistive layer 171 becomes. Thus, the resistance of the photoresistive layer 171 can be adjusted by adjusting the light intensity applied to it, thereby adjusting the thickness of the sheath layer 21 located above the focusing ring 16.

[0064] In some embodiments, the photoresistor layer 171 includes a doped semiconductor layer, and by doping the semiconductor layer, the adjustable resistance range of the photoresistor layer 171 can be increased.

[0065] In some embodiments, the material of the photoresistor layer 171 includes one or a combination of metal sulfides, selenides, and tellurides, such as cadmium sulfide, cadmium telluride, and gallium arsenide. However, it is not limited to these; the material of the photoresistor layer 171 can also be other materials whose resistance changes with light intensity, such as organic dye light-absorbing materials, etc., and this disclosure does not impose specific limitations on this. In some embodiments, the thickness of the photoresistor layer 171 can be flexibly adjusted according to the actual process.

[0066] In some embodiments, the plasma processing apparatus further includes at least one light source 18 disposed below the photoresistive layer 171, the light source 18 being used to provide illumination to the photoresistive layer 171, and the illumination intensity of the light source 18 being adjustable. Thus, in practical operation, the resistance of the photoresistive layer 171 can be adjusted by regulating the illumination intensity of the light source 18, thereby adjusting the thickness of the sheath layer 21 located above the focusing ring 16. Here, the wavelength of the light emitted by the light source 18 is related to the material of the photoresistive layer 171, and it should be ensured that the light emitted by the light source 18 is sufficient to excite electron-hole pairs within the photoresistive layer 171.

[0067] In some embodiments, the light source 18 includes an LED cold light source. Using an LED cold light source to adjust the resistance of the photoresistor layer 171 can avoid introducing additional heat sources into the reaction chamber 10 that could affect the wafer processing.

[0068] like Figure 2As shown, in some embodiments, there can be multiple light sources 18, which can be evenly distributed below the focusing ring 16. Thus, when it is necessary to adjust the overall thickness of the sheath layer 21 above the focusing ring 16, the illumination intensity of multiple light sources 18 can be adjusted simultaneously, improving the uniformity of illumination in different areas, and consequently improving the uniformity of the thickness of the sheath layer 21 above the focusing ring 16. Furthermore, due to process differences or other reasons, such as different consumption patterns in different areas of the focusing ring 16, or different aggregation patterns of etching byproducts in different areas of the focusing ring 16, the thickness of the sheath layer 21 above these different areas may vary. Therefore, the illumination intensity of the light sources 18 below different areas of the focusing ring 16 can be flexibly adjusted to address the thickness differences of the sheath layer 21 above different areas of the focusing ring 16. This allows for flexible adjustment of the resistance of the photoresistor layer 171 below different areas of the focusing ring 16, enabling precise adjustment of the sheath layer 21 thickness above the focusing ring 16 for different areas, thereby improving the uniformity of wafer processing.

[0069] It should be noted that, Figure 2 The number and arrangement of the light sources 18 are just one possible example. In fact, the number of light sources 18 can be more or less, and the multiple light sources 18 can also have other uniform or non-uniform arrangements. The specific arrangements can be flexibly set according to actual needs.

[0070] In some embodiments, the plasma processing apparatus further includes a protective cover 19 located below the photoresistor layer 171. The protective cover 19 includes a first sub-part 191 and a second sub-part 192 extending vertically below the first sub-part 191 and connected to the first sub-part 191. The second sub-part 192 surrounds a light source 18, which is located within the space formed by the protective cover 19. In actual operation, when performing processing on a wafer, the protective cover 19 protects the light source 18 from plasma damage. The material of the protective cover 19 includes a transparent material, such as quartz.

[0071] like Figure 2 As shown, in some embodiments, the second sub-part 192 of the protective cover 19 includes a first annular sidewall 1921 and a second annular sidewall 1922 that are disposed opposite to each other and surround the stage 12. A plurality of light sources 18 are located in the space between the first annular sidewall 1921 and the second annular sidewall 1922. The arrangement of the first annular sidewall 1921 and the second annular sidewall 1922 can provide better protection for the light sources 18.

[0072] This disclosure also provides a method for processing a wafer using a plasma processing apparatus, the plasma processing apparatus comprising: a reaction chamber; a stage located at the bottom of the reaction chamber for supporting the wafer; a focusing ring located within the reaction chamber and surrounding the stage; and a variable resistance layer covering the lower surface of the focusing ring, the resistance of which is adjustable; as shown below. Figure 5 As shown, the method for processing a wafer includes the following steps:

[0073] Step S101: Place the wafer on the stage;

[0074] Step S102: Perform processing on the wafer.

[0075] The method for processing wafers using a plasma processing apparatus, as provided in the embodiments of this disclosure, will now be described in further detail with reference to the accompanying drawings.

[0076] like Figure 6 As shown, the plasma processing apparatus includes: a reaction chamber 10; a stage 12 located at the bottom of the reaction chamber 10 for supporting a wafer; a focusing ring 16 located inside the reaction chamber 10 and surrounding the stage 12; a variable resistance layer 17 covering the lower surface of the focusing ring 16, the resistance of the variable resistance layer 17 being adjustable; and performing step S101, placing the wafer 20 on the stage 12.

[0077] like Figure 6 As shown, the plasma processing apparatus also includes a reaction chamber wall 101, which surrounds the reaction chamber 10, and a wafer inlet 102 is provided on the side of the reaction chamber wall 101. In actual processes, the wafer 20 to be processed can be placed on the stage 12 through the wafer inlet 102.

[0078] In some embodiments, the plasma processing apparatus further includes a vacuum pump 11 in communication with the reaction chamber 10. In actual operation, the vacuum pump 11 can be used to discharge the processing gas in the reaction chamber 10 to regulate the pressure inside the reaction chamber 10.

[0079] In some embodiments, the stage 12 may be an electrostatic chuck, which may include a dielectric layer 121 and a base 122 located below the dielectric layer. Electrostatic electrodes may be disposed within the dielectric layer 121. In some embodiments, after placing the wafer 20 on the stage 12, the method further includes: applying a voltage to the electrostatic electrodes in the electrostatic chuck using a DC power supply, thereby generating polarized charges of opposite polarity on the surface of the electrostatic chuck and the back surface of the wafer 20, and generating an electrostatic attraction between the electrostatic chuck and the wafer 20, thereby fixing the wafer 20 on the electrostatic chuck.

[0080] In some embodiments, the plasma processing apparatus further includes: a gas spray head 14 disposed opposite to the stage 12, and a gas supply device 15 connected to the gas spray head 14. The gas spray head 14 serves as the upper electrode of the plasma processing apparatus and is also used to introduce the gas required for processing the wafer 20 from the gas supply device 15 into the reaction chamber 10.

[0081] In some embodiments, the base 122 in the stage 12 may be made of metal or metal alloy, and the base 122 may serve as the lower electrode of the plasma processing device; the plasma processing device further includes a radio frequency power supply 13 connected to the base 122.

[0082] In some embodiments, the material of the focusing ring 16 is at least one of the following: quartz, alumina, aluminum nitride, monocrystalline silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxide, for example, silicon.

[0083] In practice, a variable resistance layer 17 can be formed on the lower surface of the focusing ring 16 using one or more thin film processes, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0084] In some embodiments, the variable resistance layer 17 includes a photoresistor layer 171, the resistance of which can change with the light intensity; the plasma processing apparatus further includes at least one light source 18 disposed below the photoresistor layer 171, the light source 18 being used to provide illumination to the photoresistor layer 171, and the light intensity of the light source 18 being adjustable.

[0085] In some embodiments, the photoresistor layer 171 includes a doped semiconductor layer, and by doping the semiconductor layer, the adjustable resistance range of the variable resistor layer 17 can be increased.

[0086] In some embodiments, the material of the photoresistor layer 171 includes one or a combination of metal sulfides, selenides, and tellurides, such as cadmium sulfide, cadmium telluride, and gallium arsenide. However, it is not limited to these; the material of the photoresistor layer 171 can also be other materials whose resistance changes with light intensity, such as organic dye light-absorbing materials, etc., and this disclosure does not impose specific limitations on this. In some embodiments, the thickness of the photoresistor layer 171 can be flexibly adjusted according to the actual process.

[0087] In some embodiments, the light source 18 includes an LED (Light Emitting Diode) cold light source, thereby avoiding the introduction of additional heat sources into the reaction chamber 10 that could affect the processing of the wafer 20.

[0088] like Figure 2As shown, in some embodiments, there can be multiple light sources 18, and these multiple light sources 18 can be evenly distributed below the focusing ring 16. It should be noted that... Figure 2 The number and arrangement of the light sources 18 are just one possible example. In fact, the number of light sources 18 can be more or less, and the multiple light sources 18 can also have other uniform or non-uniform arrangements. The specific arrangements can be flexibly set according to actual needs.

[0089] In some embodiments, the plasma processing apparatus further includes a protective cover 19 located below the photoresistor layer 171. The protective cover 19 includes a first sub-part 191 and a second sub-part 192 extending vertically below the first sub-part 191 and connected to the first sub-part 191. The second sub-part 192 surrounds the light source 18, which is located within the space formed by the protective cover 19. During subsequent processing of the wafer 20, the protective cover 19 protects the light source 18 from plasma damage. The material of the protective cover 19 includes a transparent material, such as quartz.

[0090] like Figure 2 As shown, in some embodiments, the second sub-part 192 of the protective cover 19 includes a first annular sidewall 1921 and a second annular sidewall 1922 that are disposed opposite to each other and surround the stage 12. A plurality of light sources 18 are located in the space between the first annular sidewall 1921 and the second annular sidewall 1922. The arrangement of the first annular sidewall 1921 and the second annular sidewall 1922 can provide better protection for the light sources 18.

[0091] Next, step S102 is executed to perform a processing procedure on the wafer 20.

[0092] The processing of wafer 20 may include performing plasma etching processes on wafer 20, such as ion beam etching (IBE) process, reactive ion etching (RIE) process, etc.

[0093] In some embodiments, performing a processing process on the wafer 20 further includes: introducing reactive gas from a gas supply device 15 into the reaction chamber 10 through a gas spray head 14; generating a radio frequency electric field between the upper and lower electrodes through a radio frequency power supply 13, with most of the radio frequency electric field contained in the processing area above the stage 12; accelerating a small number of electrons present inside the reaction chamber, causing them to collide with gas molecules of the reactive gas input into the reaction chamber 10; these collisions lead to ionization of the reactive gas and excitation of plasma, thereby generating plasma (including active particles such as electrons, cations, and electrically neutral free radicals) within the reaction chamber 10; and using the plasma to perform processes such as plasma etching on the wafer 20.

[0094] During the processing of wafer 20, electrons, being smaller in mass than cations, are more easily accelerated by the radio frequency electric field, resulting in a higher velocity. Electrons gradually accumulate on the surfaces of wafer 20 and focusing ring 16, forming a negative electric field, or sheath, on their surfaces. Wafer 20 and focusing ring 16 are gradually biased to a negative voltage. Under the pull of this negative electric field, cations are incident on the surface of wafer 20, thus performing the processing. The thickness of the sheath 21 determines the energy and direction of cations incident on wafer 20 from the plasma. The focusing ring 16 controls the sheath thickness at the edge of wafer 20, ensuring uniform etching of wafer 20.

[0095] like Figure 6 As shown, in some embodiments, the upper surface of the focusing ring 16 is higher than the upper surface of the stage 12, so that after the wafer 20 is placed on the stage 12, the focusing ring 16 can surround the wafer 20, thereby enabling control of the sheath thickness of the edge region 202 of the wafer 20 through the focusing ring 16. Figure 4 As shown, in some embodiments, the wafer 20 includes a central region 201 and an edge region 202 surrounding the central region 201.

[0096] like Figure 3a As shown, the applicant discovered that during the processing of wafer 20, the focusing ring 16 is also exposed to plasma. As the processing progresses, its material is lost, which leads to a decrease in the height of the upper surface of the focusing ring 16. Consequently, the height of the sheath 21 on the surface of the focusing ring 16 decreases. The upper surface of the sheath 21 above the wafer 20 is higher than the upper surface of the sheath 21 above the focusing ring 16. The sheath 21 at the junction of the wafer 20 and the focusing ring 16 tilts. During the processing of wafer 20, the incident direction of cations in the central region 201 of wafer 20 is perpendicular to the plane of wafer 20, while the incident direction of cations in the edge region 202 of wafer 20 tilts inward toward the wafer 20. This causes a difference in parameters such as the processing rate of the edge region 202 of wafer 20 compared to the central region 201 of wafer 20. For example, when performing an etching process on wafer 20, the etching direction of the edge region 202 of wafer 20 is tilted towards the inside of wafer 20, and the etching rate of the edge region 202 of wafer 20 is greater than the etching rate of the center region 201 of wafer 20, thus reducing the uniformity of wafer 20 processing.

[0097] Furthermore, the applicant also discovered that during the processing of wafer 20, there may be situations that cause an increase in the impedance of the focusing ring 16, resulting in the thickness of the sheath 21 above wafer 20 being greater than the thickness of the sheath 21 above the focusing ring 16. The upper surface of the sheath 21 above wafer 20 is higher than the upper surface of the sheath 21 above the focusing ring 16, causing the sheath 21 at the junction of wafer 20 and focusing ring 16 to tilt. This causes the incident direction of cations in the edge region 202 of wafer 20 to tilt inward toward wafer 20, resulting in a difference in parameters such as the processing rate of the edge region 202 of wafer 20 compared with the central region 201 of wafer 20.

[0098] like Figure 3b As shown, the applicant also discovered that during the etching process of wafer 20, there may be situations that cause a decrease in the impedance of the focusing ring 16, resulting in the thickness of the sheath 21 above wafer 20 being less than that above the focusing ring 16. The upper surface of the sheath 21 above wafer 20 is lower than the upper surface of the sheath 21 above the focusing ring 16, causing the sheath 21 at the interface between wafer 20 and the focusing ring 16 to tilt. During the processing of wafer 20, the sheath 21's pull on the cations in the edge region 202 of wafer 20 tilts outwards, causing a difference in processing rate between the edge region 202 and the central region 201 of wafer 20. For example, during the etching process of wafer 20, the etching direction of the edge region 202 tilts outwards, and the etching rate of the edge region 202 is less than that of the central region 201, reducing the uniformity of wafer 20 processing.

[0099] In some embodiments, during the processing of wafer 20, the method further includes: adjusting the resistance of the variable resistance layer 17, such that, as Figure 3cAs shown, this embodiment adjusts the resistance of the variable resistor layer 17 to adjust the overall impedance of the focusing ring 16 and the variable resistor layer 17, thereby adjusting the thickness of the sheath layer 21 above the focusing ring 16. This makes the upper surfaces of the sheath layer 21 on the wafer 20 surface and the sheath layer 21 on the focusing ring 16 surface flush or substantially flush, thereby adjusting the incident direction and incident rate of cations in the edge region 202 of the wafer 20, and improving the processing uniformity of the edge region 202 and the center region 201 of the wafer 20. For example, when the upper surface of the sheath layer 21 above the focusing ring 16 is lower than the upper surface of the sheath layer 21 above the wafer 20, the resistance of the variable resistor layer 17 can be decreased, thereby increasing the thickness of the sheath layer 21 above the focusing ring 16; when the upper surface of the sheath layer 21 above the focusing ring 16 is higher than the upper surface of the sheath layer 21 above the wafer 20, the resistance of the variable resistor layer 17 can be increased, thereby decreasing the thickness of the sheath layer 21 above the focusing ring 16. Thus, by adjusting the impedance of the focusing ring 16 and the variable resistor layer 17, the sheath layer 21 above the wafer 20 and the upper surface of the sheath layer 21 above the focusing ring 16 are made flush or substantially flush.

[0100] In actual operation, by monitoring parameters such as etching rate and etching direction of the central region 201 and edge region 202 of the wafer 20, the thickness of the sheath layer 21 above the focusing ring 16 and the sheath layer 21 above the wafer 20 can be determined, and the resistance value of the variable resistor layer 17 can be adjusted based on the determination result.

[0101] In some embodiments, the variable resistance layer 17 includes a photoresistor layer 171; adjusting the resistance of the variable resistance layer 17 includes adjusting the light intensity of at least one light source 18.

[0102] In practical operation, under dark conditions, most of the electrons inside the photoresistor layer 171 are valence band electrons that cannot move freely, resulting in a high resistance of the photoresistor layer 171. When there is light of a suitable wavelength, the valence band electrons in the photoresistor layer 171 absorb photon energy and jump to the conduction band, becoming free electrons that can conduct electricity, leaving a hole in the valence band. This reduces the resistance of the photoresistor layer 171. Furthermore, the greater the light intensity, the more electron-hole pairs are excited in the photoresistor layer 171, and the lower the resistance of the photoresistor layer 171 becomes. Thus, the resistance of the photoresistor layer 171 can be adjusted by adjusting the light intensity of the light source 18, thereby adjusting the thickness of the sheath layer 21 located above the focusing ring 16.

[0103] Here, the wavelength of the light emitted by the light source 18 is related to the material of the photoresistor layer 171, and it should be ensured that the light emitted by the light source 18 is sufficient to excite electron-hole pairs in the photoresistor layer 171.

[0104] In some embodiments of this disclosure, the number of light sources 18 can be multiple. When it is necessary to adjust the overall thickness of the sheath layer 21 above the focusing ring 16, the illumination intensity of multiple light sources 18 can be adjusted simultaneously to improve the uniformity of illumination in different areas, thereby improving the uniformity of the thickness of the sheath layer 21 above the focusing ring 16. Furthermore, due to process differences or other reasons, such as different consumption patterns in different areas of the focusing ring 16, or different aggregation patterns of etching byproducts in different areas of the focusing ring 16, the thickness of the sheath layer 21 above these different areas may vary. Therefore, the illumination intensity of the light sources 18 below different areas of the focusing ring 16 can be flexibly adjusted to address the thickness differences of the sheath layer 21 above different areas of the focusing ring 16. This allows for flexible adjustment of the resistance of the photoresistor layer 171 below different areas of the focusing ring 16, enabling precise adjustment of the thickness of the sheath layer 21 above the focusing ring 16 for different areas of the focusing ring 16, thereby improving the uniformity of wafer 20 processing.

[0105] It should be noted that those skilled in the art can change the order of the above steps without departing from the scope of protection of this disclosure. The above description is only an optional embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A plasma processing device, characterized in that, include: reaction chamber; A stage, located at the bottom of the reaction chamber, is used to support the wafer; A focusing ring is located within the reaction chamber and surrounds the stage; A variable resistance layer covers the lower surface of the focusing ring, the resistance of the variable resistance layer is adjustable, and the variable resistance layer includes a photoresistor layer; At least one light source is disposed below the photoresistor layer, the light source being used to provide illumination to the photoresistor layer, and the illumination intensity of the light source is adjustable.

2. The plasma processing apparatus according to claim 1, characterized in that, The photoresistor layer includes a doped semiconductor layer.

3. The plasma processing apparatus according to claim 1, characterized in that, The material of the photoresistor layer includes one or a combination of metal sulfides, selenides, and tellurides.

4. The plasma processing apparatus according to claim 1, characterized in that, The light source includes LED cold light sources.

5. The plasma processing apparatus according to claim 1, characterized in that, The plasma processing apparatus further includes a protective cover located below the photoresistor layer, the protective cover including a first sub-part and a second sub-part extending vertically below the first sub-part and connected to the first sub-part, the second sub-part being arranged around the light source, the light source being located within the space formed by the protective cover.

6. A method for processing a wafer, employing a plasma processing apparatus as described in any one of claims 1-5, characterized in that, The method includes: The wafer is placed on the stage; The wafer is subjected to a processing procedure.

7. The method according to claim 6, characterized in that, During the processing of the wafer, the method further includes: Adjust the resistance of the variable resistance layer.

8. The method according to claim 7, characterized in that, Adjusting the resistance of the variable resistance layer includes: Adjust the light intensity of at least one of the light sources.

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