Metal interconnection structure and forming method thereof
By forming a buffer layer at the bottom of the metal grooves and through holes and forming a metal barrier layer on its surface, the damage problem of the metal barrier layer formation process to IMD is solved, and the TDDB life of IMD is improved and the device performance is improved.
Patent Information
- Application Number
- CN202510098761.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-04-18
AI Technical Summary
In the existing metal interconnect structure formation process, the metal barrier layer formation process causes IMD damage to the bottom of the metal trench, affecting the TDDB life of the IMD.
A buffer layer is formed at the bottom of the metal trench and through holes, and a metal barrier material layer is formed on the surface of the buffer layer. A metal barrier layer is formed by bombardment to protect the IMD at the bottom of the trench.
It effectively avoids damage to IMD by the metal barrier layer formation process, improves the TDDB life of IMD, and reduces the resistivity between the upper and lower metal interconnects, improving device performance.
Smart Images
Figure CN119852243A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a metal interconnection structure and a forming method thereof. Background Art
[0002] In the existing metal interconnect structure formation process, the process of forming a metal barrier layer on the sidewall of a metal trench usually causes damage to the metal interconnect dielectric layer (IMD) at the bottom of the metal trench (or between the upper and lower metal lines).
[0003] Specifically, in the existing metal barrier layer formation scheme, a metal barrier material layer is usually first deposited at the bottom of the metal trench; then the metal barrier material at the bottom of the metal trench is bombarded (for example, using a reverse sputtering process (Re-sputter) bombardment) so that the metal barrier material at the bottom of the metal trench is bombarded to the sidewall of the metal trench, forming a metal barrier layer on the sidewall, thereby effectively preventing the metal material in the metal trench from diffusing to the IMD outside the sidewall of the metal trench.
[0004] However, in a metal interconnect structure, in addition to IMD between the upper and lower metal wires (i.e., the two metal wires are insulated from each other by IMD), there is often a metal interconnection relationship between the current metal wire and other metal wires in the previous layer (i.e., electrical connection is achieved through metal through-holes). Therefore, in order to increase the coverage of the metal barrier material on the sidewalls of the metal trenches and through-holes (the higher the coverage of the metal barrier material on the sidewalls, the stronger the anti-metal diffusion effect is generally), and to reduce the resistivity between the upper and lower metal wires, during the bombardment of the metal barrier material layer at the bottom of the metal trenches and through-holes, the content of the metal barrier material remaining at the bottom of the metal trenches and through-holes after the bombardment will be minimized to reduce the resistivity. This inevitably causes the bombardment process to damage the IMD between the upper and lower metal wires (for example, irregular needle tips are formed at the bottom of the metal trenches), and the electric field enhancement effect of the needle tips will greatly reduce the breakdown voltage between the upper and lower metal wires, seriously affecting the time-dependent breakdown (TDDB) life of the IMD.
[0005] Therefore, there is an urgent need to provide an improved method for forming a metal interconnect structure, which can effectively avoid the IMD damage problem at the bottom of the metal trench caused by the metal barrier layer formation process. Summary of the invention
[0006] The technical problem solved by the embodiment of the present invention is how to avoid the IMD damage problem at the bottom of the metal trench caused by the formation process of the metal barrier layer and improve the TDDB life of the IMD.
[0007] To solve the above technical problems, an embodiment of the present invention provides a method for forming a metal interconnect structure, which specifically includes: providing a semiconductor substrate, wherein the surface of the semiconductor substrate has a metal interconnect dielectric layer; etching the metal interconnect dielectric layer to form grooves and through holes; forming a buffer layer at the bottom of the grooves and through holes; forming a metal barrier material layer on the surface of the buffer layer, and bombarding the metal barrier material layer to form a metal barrier layer on the side walls of the grooves and through holes; filling the grooves and through holes with metal material to form metal interconnect lines.
[0008] Optionally, the diffusion coefficient of the buffer layer is smaller than the diffusion coefficient of the metal material.
[0009] Optionally, the material of the metal barrier layer includes TaN, and the resistivity of the buffer layer material is smaller than the resistivity of TaN.
[0010] Optionally, one or more of the following is satisfied: the material of the metal barrier layer includes TaN and / or Ta; the material of the buffer layer is Ta and / or Co.
[0011] Optionally, before filling the grooves and through holes with metal material to form metal interconnects, the method further includes: depositing a copper seed crystal adhesion layer at the bottom of the grooves and through holes, wherein the copper seed crystal adhesion layer covers the bottom of the grooves and through holes.
[0012] Optionally, the material of the copper seed crystal adhesion layer is Ta and / or Co.
[0013] Optionally, the metal barrier material layer is a stacked structure of a Ta deposition layer and a TaN deposition layer.
[0014] Optionally, a metal barrier material layer is formed on the surface of the buffer layer, and the step of bombarding the metal barrier material layer is performed once or cyclically multiple times.
[0015] Optionally, the power used to bombard the metal barrier material layer each time during the multiple executions of the loop is less than the power used to bombard the metal barrier material layer during one execution.
[0016] An embodiment of the present invention also provides a metal interconnection structure, comprising: a semiconductor substrate; a metal interconnection dielectric layer, located on the surface of the semiconductor substrate; grooves and through holes, located in the metal interconnection dielectric layer; a buffer layer, located at the bottom of the grooves and through holes; a metal barrier layer, located in the grooves and through holes and covering the side walls of the grooves and through holes; and a metal interconnection line, covering the metal barrier layer.
[0017] Optionally, the diffusion coefficient of the buffer layer is smaller than the diffusion coefficient of the metal material forming the metal interconnect line.
[0018] Optionally, the material of the metal barrier layer includes TaN, and the resistivity of the buffer layer material is smaller than the resistivity of TaN.
[0019] Optionally, one or more of the following is satisfied: the material of the metal barrier layer includes TaN and / or Ta; the material of the buffer layer is Ta and / or Co.
[0020] Optionally, the metal interconnect structure further includes a copper seed crystal adhesion layer, and the copper seed crystal adhesion layer is located between the buffer layer and the metal interconnect line.
[0021] Optionally, the material of the copper seed crystal adhesion layer is Ta and / or Co.
[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:
[0023] An embodiment of the present invention provides a method for forming a metal interconnect structure, which specifically includes: providing a semiconductor substrate, wherein the surface of the semiconductor substrate has a metal interconnect dielectric layer; etching the metal interconnect dielectric layer to form grooves and through holes; forming a buffer layer at the bottom of the grooves and through holes; forming a metal barrier material layer on the surface of the buffer layer, and bombarding the metal barrier material layer to form a metal barrier layer on the sidewalls of the grooves and through holes; filling the grooves and through holes with metal material to form metal interconnect lines.
[0024] As described above, before forming the metal barrier material layer, by first forming the buffer layer at the bottom of the groove, the buffer layer can protect the bottom of the groove during the subsequent bombardment of the metal barrier material layer, which helps to avoid the bombardment process causing damage to the IMD at the bottom of the groove (for example, forming irregular spikes), thereby improving the anti-puncture capability of the IMD between the current layer of metal interconnection lines and the previous layer of metal interconnection lines formed subsequently, and improving its TDDB life.
[0025] Furthermore, since the metal interconnection lines formed in the current layer often have a metal interconnection relationship with the metal interconnection lines in the previous layer, in an embodiment of the present invention, the buffer layer is formed by selecting a material with a smaller resistivity. Compared with the small amount of metal barrier material (with a higher resistivity than the buffer layer) remaining at the bottom of the through hole after bombarding the metal barrier material layer in the prior art, the buffer layer of this embodiment can not only protect the bottom of the groove, but also achieve a lower resistivity between the upper and lower layers of metal interconnection lines that form an interconnection relationship through the through hole (meaning better electrical connectivity), thereby improving device performance.
[0026] Furthermore, the diffusion coefficient of the buffer layer is smaller than that of the metal material, which can effectively reduce the IMD diffusion of the buffer layer material itself to the bottom of the trench and effectively block the IMD diffusion of the metal material filled in the trench to the bottom of the trench.
[0027] Furthermore, since Ta and / or Co have both the function of preventing metal material diffusion and lower resistivity or better conductivity than non-metallic materials (such as TaN) with diffusion prevention function, by selecting Ta and / or Co as the material of the buffer layer, it is possible to simultaneously achieve multiple functions such as preventing the metal material in the trench from diffusing to the IMD at the bottom of the trench, protecting the bottom of the trench during the bombardment of the metal barrier material layer, and ensuring better electrical connectivity between the upper and lower metal interconnects.
[0028] Furthermore, before the metal material is filled in the groove, the copper seed crystal adhesion layer is first deposited, which helps to strengthen the anti-diffusion effect of the metal material to the IMD at the bottom of the groove on the basis of the buffer layer remaining at the bottom of the groove after bombardment. Furthermore, by selecting Ta and / or Co as the material of the copper seed crystal adhesion layer, since Ta and / or Co have the anti-metal diffusion effect and relatively low resistivity, the electrical connectivity between the upper and lower metal interconnects can also be guaranteed.
[0029] Furthermore, by repeatedly performing the steps of forming a metal barrier material layer on the surface of the buffer layer and bombarding the metal barrier material layer, it is helpful to improve the uniformity of the metal barrier layer covering the sidewalls of the groove. Furthermore, since the thickness of the metal barrier material layer formed each time during the multiple cycles can be designed to be smaller than the thickness of the metal barrier material layer formed during the one-time execution, a relatively low power can be used for bombardment. Lower power means less bombardment force and greater controllability, thereby further reducing damage to the bottom of the groove. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 is a flow chart of a method for forming a metal interconnect structure in an embodiment of the present invention;
[0031] Figures 2 to 7 is a schematic cross-sectional view of a device corresponding to each step of a method for forming a metal interconnect structure in an embodiment of the present invention;
[0032] Figure 8 is a comparison diagram of metal interconnect structures formed by the metal interconnect structure forming method according to an embodiment of the present invention and the metal interconnect structure forming method according to an existing method;
[0033] Description of reference numerals:
[0034] 100-semiconductor substrate; 110-metal interconnect dielectric layer; 111-previous metal interconnect dielectric layer; 121-previous metal interconnect line; 1311-groove; 1312-through hole; 141-buffer layer; 151-metal barrier material layer; 161-metal barrier layer; 1511-TaN deposition layer; 1512-Ta deposition layer; 161-metal barrier layer; 171-copper seed crystal adhesion layer; 181-metal interconnect line. DETAILED DESCRIPTION
[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0036] Reference Figure 1 , Figure 1 1 is a flow chart of a method for forming a metal interconnect structure in an embodiment of the present invention. The forming method may include steps S11 to S15:
[0037] Step S11: providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a metal interconnect dielectric layer;
[0038] Step S12: etching the metal interconnect dielectric layer to form grooves and through holes;
[0039] Step S13: forming a buffer layer at the bottom of the groove and the through hole;
[0040] Step S14: forming a metal barrier material layer on the surface of the buffer layer, and bombarding the metal barrier material layer to form a metal barrier layer on the sidewalls of the trench and the through hole;
[0041] Step S15: filling the trenches and through holes with metal materials to form metal interconnects.
[0042] Combine the following Figures 2 to 7 The above steps are described in detail.
[0043] Figures 2 to 7 It is a schematic cross-sectional diagram of a device corresponding to each step of a method for forming a metal interconnect structure in an embodiment of the present invention.
[0044] Reference Figure 2 , a semiconductor substrate 100 is provided, wherein a surface of the semiconductor substrate 100 has an Inter-Metal Dielectric (IMD) layer 110 .
[0045] Among them, the metal interconnect dielectric layer 110 can be a bottom metal interconnect dielectric layer, or a middle metal interconnect dielectric layer or a top metal interconnect dielectric layer. When the metal interconnect dielectric layer 110 is a middle metal interconnect dielectric layer or a top metal interconnect dielectric layer, the surface of the semiconductor substrate 100 can also have a previous metal interconnect dielectric layer 111 and a previous metal interconnect line 121.
[0046] In a specific implementation, the semiconductor substrate 100 may be a silicon substrate, or the material of the semiconductor substrate 100 may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, etc. The semiconductor substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or a substrate with an epitaxy layer (Epi layer) grown thereon. Preferably, the semiconductor substrate 100 may be a lightly doped semiconductor substrate.
[0047] The metal interconnect dielectric layer 110 may be a silicon oxide layer (e.g. SiO2), fluorine-doped silicon oxide (F-SIO2), a low dielectric constant material (Low-K), an ultra-low dielectric constant material (Ultra Low-K, ULK), a silicon nitride layer (e.g. Si3N4), silicon carbide (SiC), nitrogen-doped silicon carbide (NDC), aluminum nitride (AlN) and combinations thereof.
[0048] Reference Figure 3 , the metal interconnect dielectric layer 110 is etched to form a groove 1311 and a through hole 1312.
[0049] In a specific implementation, a patterned mask layer may be formed on the surface of the metal interconnect dielectric layer 110 , and the metal interconnect dielectric layer 110 may be etched using the patterned mask layer as a mask to form the grooves 1311 and the through holes 1312 .
[0050] Among them, for the groove 1311, there is a metal interconnect dielectric layer between the bottom of the groove 1311 and the top surface of the previous metal interconnect line 121. After the current metal interconnect line is formed in the groove 1311, it is insulated from the previous metal interconnect line 121.
[0051] Among them, for the through hole 1312, the bottom of the through hole 1312 can expose the top surface of the previous layer of metal interconnection line 121, and after the current layer of metal interconnection line is formed in the through hole 1312, metal interconnection with the previous layer of metal interconnection line 121 can be achieved.
[0052] Reference Figure 4 A buffer layer 141 is formed at the bottom of the trench 1311 and the bottom of the through hole 1312 , and then a metal barrier material layer 151 is formed on the surface of the buffer layer 141 .
[0053] In a specific implementation, a deposition process may be used to form a buffer layer 141 at the bottom of the trench 1311 and the through hole 1312 .
[0054] Furthermore, the metal barrier material layer 151 is bombarded.
[0055] Reference Figure 5 , by bombarding the metal barrier material layer 151 (refer to Figure 4 ), so as to form a metal barrier layer 161 on the sidewalls of the trench 1311 and the sidewalls of the through hole 1312 respectively.
[0056] In a specific implementation, a reverse sputtering process or other existing appropriate processes can be used to bombard the metal barrier material layer 151 (for example, inert gas ions can be used for bombardment) so that the material of the metal barrier material layer 151 is sputtered to the side walls of the groove 1311 and the through hole 1312 to cover the metal barrier layer 161 on the side walls of the groove 1311 and the through hole 1312.
[0057] In the embodiment of the present invention, before forming the metal barrier material layer 151, the buffer layer 141 is first formed at the bottom of the groove 1311. The buffer layer 141 can protect the bottom of the groove 1311 during the subsequent bombardment of the metal barrier material layer 151, which helps to prevent the bombardment process from causing damage to the bottom IMD of the groove 1311 (for example, forming irregular spikes), thereby improving the subsequent formation of the current layer metal interconnection line 181 (refer to Figure 7 ) and the previous metal interconnection line 121 to improve the IMD breakdown resistance and increase its TDDB life.
[0058] Furthermore, the material of the metal barrier material layer 151 and the metal barrier layer 161 includes TaN, and the resistivity of the material of the buffer layer 141 is lower than the resistivity of TaN.
[0059] It should be noted that, as mentioned above, since the metal interconnection line 181 formed in the current layer and the metal interconnection line 121 in the previous layer often form a metal interconnection relationship (or electrical connection relationship) through the through hole 1312 (for details, please refer to Figure 7The current metal interconnection line 181 and the previous metal interconnection line 121 shown on the right side of the metal interconnection dielectric layer 110 are in a metal interconnection relationship). Therefore, in an embodiment of the present invention, the buffer layer 141 is formed by selecting a material with a smaller resistivity. Compared with the small amount of metal barrier material (with a resistivity higher than that of the buffer layer 141) remaining at the bottom of the through hole 1312 after bombarding the metal barrier material layer 151 in the prior art, the buffer layer 141 of this embodiment can not only protect the bottom of the groove 1311, but also ensure that the resistivity between the upper and lower metal interconnection lines that form an interconnection relationship through the through hole 1312 is low (meaning that it has better electrical connectivity), thereby improving device performance.
[0060] Without limitation, the material of the metal barrier layer 161 may include tantalum nitride (TaN) and / or tantalum (Ta); the material of the buffer layer 141 may include tantalum (Ta) and / or cobalt (Co).
[0061] In a specific implementation, a layer of Ta may be deposited at the bottom of the trench 1311 and the through hole 1312 to form a buffer layer 141 .
[0062] In another specific implementation, a layer of Co may be deposited at the bottom of the trench 1311 and the through hole 1312 to form a buffer layer 141 .
[0063] In another specific embodiment, the buffer layer 141 may be a stacked structure of a Ta deposition layer and a Co deposition layer (not shown). Preferably, a layer of Ta may be first deposited at the bottom of the groove 1311 and the through hole 1312 to form a Ta deposition layer; and then a layer of Co may be deposited on the surface of the Ta deposition layer to form a Co deposition layer.
[0064] In the embodiment of the present invention, since Ta and / or Co have both the function of preventing metal material diffusion and lower resistivity or better conductivity compared to non-metallic materials (such as TaN) with diffusion prevention function, Ta and / or Co are selected as the material of the buffer layer 141, it is possible to simultaneously prevent the metal material in the groove 1311 from diffusing to the IMD bottom of the groove 1311, protect the bottom of the groove 1311 during the bombardment of the metal barrier material layer 151, and ensure better electrical connectivity between the upper and lower metal interconnects.
[0065] In a specific embodiment, the metal barrier material layer 151 is a stacked structure of a TaN deposition layer 1511 and a Ta deposition layer 1512 (see Figure 4). Specifically, a layer of TaN may be first deposited on the surface of the buffer layer 141 to form a TaN deposition layer 1511; and then a layer of Ta may be deposited on the surface of the TaN deposition layer 1511 to form a Ta deposition layer 1512. Thus, a stacked structure of the TaN deposition layer 1511 and the Ta deposition layer 1512 is formed.
[0066] In an embodiment of the present invention, by adopting a stacked structure of a TaN deposition layer 1511 and a Ta deposition layer 1512, it is helpful to cover the side walls of the groove 1311 and the through hole 1312 with a metal barrier layer 161 comprising a Ta and TaN composite material under bombardment. Compared with a metal barrier layer comprising only a single material of Ta or TaN, the Ta and TaN composite material has a stronger anti-metal diffusion effect.
[0067] Reference Figure 6 A copper seed crystal adhesion layer 171 is deposited at the bottom of the groove 1311 and the bottom of the through hole 1312 , and the copper seed crystal adhesion layer 171 covers the bottom of the groove 1311 and the bottom of the through hole 1312 .
[0068] It is understandable that after bombarding the metal barrier material layer 151, the bottom of the groove 1311 and the through hole 1312 may only include a portion of the buffer layer 141, or may include a portion of the buffer layer 141 and a portion of the metal barrier material layer 151 remaining after the bombardment. Accordingly, the copper seed crystal adhesion layer 171 may cover a portion of the buffer layer 141, or may cover a portion of the buffer layer 141 and a portion of the metal barrier material layer 151 remaining after the bombardment.
[0069] Furthermore, the material of the copper seed crystal adhesion layer 171 is Ta and / or Co.
[0070] In a specific implementation, a layer of Ta may be deposited at the bottom of the trench 1311 and the through hole 1312 to form a copper seed crystal adhesion layer 171 .
[0071] In another specific implementation, a layer of Co may be deposited at the bottom of the trench 1311 and the through hole 1312 to form a copper seed crystal adhesion layer 171 .
[0072] In another specific embodiment, the copper seed crystal adhesion layer 171 may be a stacked structure of a Ta deposition layer and a Co deposition layer (not shown). Preferably, a layer of Ta may be first deposited at the bottom of the groove 1311 and the through hole 1312 to form a Ta deposition layer; and then a layer of Co may be deposited on the surface of the Ta deposition layer to form a Co deposition layer.
[0073] In the embodiment of the present invention, before the metal material is filled in the groove 1311, the copper seed crystal adhesion layer 171 is first deposited, which helps to strengthen the anti-diffusion effect of the metal material to the IMD of the groove bottom 131 on the basis of the buffer layer 141 remaining at the bottom of the groove 131 after bombardment. Further, by selecting Ta and / or Co as the material of the copper seed crystal adhesion layer 171, since Ta and / or Co have the anti-metal diffusion effect and relatively low resistivity, it can also ensure that the upper and lower metal interconnects (such as Figure 7 The electrical connectivity between the metal interconnect line 181 and the metal interconnect line 121 is shown.
[0074] Reference Figure 7 , metal material is filled in the trench 1311 and the through hole 1312 to form a metal interconnection line 181.
[0075] In a specific implementation, the metal material may be copper (Cu). Alternatively, other appropriate metal materials (such as cobalt) or metal alloy materials may also be selected.
[0076] It should be noted that when the metal material is Cu, a copper seed layer of a copper interconnection line can be first deposited in the groove 1311 and the through hole 1312, and then the copper material can be filled in the groove 1311 and the through hole 1312 by an electrochemical deposition process. After the metal material is filled, the metal material can be planarized to form a metal interconnection line 181. Through the planarization process, a metal interconnection line 181 can be formed inlaid in the metal interconnection dielectric layer 110, and a metal interconnection structure with a flat surface can be formed to prepare for subsequent processes.
[0077] Furthermore, the diffusion coefficient of the buffer layer 141 is smaller than the diffusion coefficient of the metal material filled in the trench 1311 and the through hole 1312. Therefore, the buffer layer 141 can effectively reduce the IMD diffusion of the buffer layer material itself to the bottom of the trench, and can also effectively block the IMD diffusion of the metal material filled in the trench to the bottom of the trench.
[0078] Furthermore, a metal barrier material layer 151 is formed on the surface of the buffer layer 141 , and the step of bombarding the metal barrier material layer 151 is performed once or cyclically performed multiple times.
[0079] Furthermore, the power of bombarding the metal barrier material layer 151 each time during the multiple executions of the cycle is less than the power of bombarding the metal barrier material layer 151 during the one execution.
[0080] In an embodiment of the present invention, by performing the steps of forming the metal barrier material layer 151 once and bombarding the metal barrier material layer 151, it is helpful to improve efficiency and reduce process costs. By performing the aforementioned steps multiple times, it is helpful to improve the uniformity of the metal barrier layer 161 covering the sidewalls of the groove 1311 and the through hole 1312. Furthermore, since the thickness of the metal barrier material 151 layer formed each time during the multiple executions of the cycle is smaller than that of the metal barrier material 151 layer formed in the process of only performing it once, a relatively low power can be used for bombardment. Lower power means less bombardment force and greater controllability, thereby further reducing damage to the bottom of the groove 1311.
[0081] The embodiment of the present invention also discloses a metal interconnect structure, such as Figure 7 As shown, the metal interconnect structure may include: a semiconductor substrate 100; a metal interconnect dielectric layer 110, located on the surface of the semiconductor substrate 100; a groove 1311 and a through hole 1312, located in the metal interconnect dielectric layer 110; a buffer layer 141, located at the bottom of the groove 1311 and the bottom of the through hole 1312; a metal barrier layer 161, located in the groove 1311 and the through hole 1312, and covering the sidewalls of the groove 1311 and the sidewalls of the through hole 1312; and a metal interconnect line 181, covering the metal barrier layer 161.
[0082] Furthermore, the diffusion coefficient of the buffer layer 141 is smaller than the diffusion coefficient of the metal material forming the metal interconnection line 181 .
[0083] Furthermore, the material of the metal barrier layer 161 includes TaN, and the resistivity of the material of the buffer layer 141 is lower than the resistivity of TaN.
[0084] In some non-limiting embodiments, the material of the metal barrier layer 161 includes TaN and / or Ta; the material of the buffer layer 141 is Ta and / or Co.
[0085] Furthermore, the metal interconnection structure further includes a copper seed crystal adhesion layer 171 , and the copper seed crystal adhesion layer 171 is located between the buffer layer 141 and the metal interconnection line 181 .
[0086] In a non-limiting embodiment, the copper seed adhesion layer 171 is made of Ta and / or Co.
[0087] Regarding the principle, specific implementation and beneficial effects of the metal interconnect structure, please refer to the relevant description of the method for forming the metal interconnect structure mentioned above, which will not be repeated here.
[0088] Reference Figure 8 , Figure 8It is a comparison diagram of metal interconnect structures formed by the metal interconnect structure forming method of the embodiment of the present invention and the existing metal interconnect structure forming method. Figure 8 The left and right pictures are both the effects presented under a transmission electron microscope (TEM). The left picture is a metal interconnect structure formed by using an existing metal interconnect structure forming method, and the right picture is a metal interconnect structure formed by using a metal interconnect structure forming method according to an embodiment of the present invention.
[0089] As can be seen from the figure, there are spikes at the bottom of the groove of the current layer in the left picture, while the bottom of the groove of the current layer in the right picture is smoother and flatter without spikes.
[0090] In addition, as shown in the IMD reliability test experimental results in Table 1 below, the results show that in the metal interconnect structure formed by the embodiment of the present invention, the IMD between the upper and lower metal interconnect lines has a longer TDDB life (see the life index in the third column of Table 1 below for details), and the TDDB life of the IMD at the bottom of the trench at different positions on the wafer shows better uniformity (see the Weibull slope in the second column of Table 1 below for details, the larger the value, the closer the TDDB life of the IMD at different positions on the wafer).
[0091] Table 1
[0092]
[0093] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.
[0094] The "plurality" appearing in the embodiments of the present application refers to two or more.
[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A method for forming a metal interconnect structure, characterized in that: include: Providing a semiconductor substrate, wherein a surface of the semiconductor substrate has a metal interconnect dielectric layer; Etching the metal interconnect dielectric layer to form grooves and through holes; forming a buffer layer at the bottom of the groove and the through hole; forming a metal barrier material layer on the surface of the buffer layer, and bombarding the metal barrier material layer to form a metal barrier layer on the sidewalls of the trench and the through hole; Metal materials are filled in the trenches and through holes to form metal interconnection lines.
2. The method according to claim 1, characterized in that The diffusion coefficient of the buffer layer is smaller than the diffusion coefficient of the metal material.
3. The method according to claim 1, characterized in that The material of the metal barrier layer includes TaN, The resistivity of the buffer layer material is lower than that of TaN.
4. The method according to claim 1, characterized in that Meet one or more of the following: The material of the metal barrier layer includes TaN and / or Ta; The material of the buffer layer is Ta and / or Co.
5. The method according to claim 1, characterized in that Before filling the grooves and through holes with metal materials to form metal interconnects, the method further includes: A copper seed crystal adhesion layer is deposited at the bottom of the groove and the through hole, and the copper seed crystal adhesion layer covers the bottom of the groove and the through hole.
6. The method according to claim 5, characterized in that The material of the copper seed crystal adhesion layer is Ta and / or Co.
7. The method according to claim 1, characterized in that The metal barrier material layer is a stacked structure of a Ta deposition layer and a TaN deposition layer.
8. The method according to any one of claims 1 to 7, characterized in that The steps of forming a metal barrier material layer on the surface of the buffer layer and bombarding the metal barrier material layer are performed once or cyclically for multiple times.
9. The method according to claim 8, characterized in that The power of bombarding the metal barrier material layer each time during the multiple executions of the cycle is less than the power of bombarding the metal barrier material layer during the one execution.
10. A metal interconnect structure, characterized in that: include: Semiconductor substrate; A metal interconnect dielectric layer, located on the surface of the semiconductor substrate; Grooves and vias are located in the metal interconnect dielectric layer; A buffer layer, located at the bottom of the groove and the through hole; A metal barrier layer, located in the trench and the through hole and covering the sidewalls of the trench and the through hole; A metal interconnection line covers the metal barrier layer.
11. The metal interconnect structure according to claim 10, wherein: The diffusion coefficient of the buffer layer is smaller than the diffusion coefficient of the metal material forming the metal interconnection line.
12. The metal interconnect structure according to claim 10, wherein: The material of the metal barrier layer includes TaN, and the resistivity of the buffer layer material is lower than that of TaN.
13. The metal interconnect structure according to claim 10, wherein: Meet one or more of the following: The material of the metal barrier layer includes TaN and / or Ta; The material of the buffer layer is Ta and / or Co.
14. The metal interconnect structure according to claim 10, wherein: The metal interconnection structure further includes a copper seed crystal adhesion layer, and the copper seed crystal adhesion layer is located between the buffer layer and the metal interconnection line.
15. The metal interconnect structure according to claim 14, wherein: The material of the copper seed crystal adhesion layer is Ta and / or Co.