Half-bridge power module and packaging method thereof

Abstract

The invention provides a half-bridge power module and a packaging method thereof.The half-bridge power module comprises a first substrate, a second substrate, a first chip, a second chip, a frame and a packaging layer, the first chip is welded to a first area of the first substrate, the first electrode, the second electrode and the third electrode are located on the upper surface and the lower surface of the first chip respectively, and the third electrode is electrically connected with the first area; the frame at least comprises first to fifth pins, the frame is welded above the first chip and the substrate, and the first to third pins are electrically connected with the first area, the first electrode and the second electrode respectively; the second chip and the substrate are welded above the frame, the fourth electrode, the fifth electrode and the sixth electrode are located on the upper surface and the lower surface of the second chip, and the sixth electrode is electrically connected with the second pin; the second substrate is welded with the second chip and the frame, the fourth electrode and the fifth electrode are electrically connected with the second area and the third area respectively, and the second area and the third area are electrically connected with the fourth pin and the fifth pin respectively; the packaging layer exposes the pins and the first and second substrates. The first chip, the frame and the second chip are stacked and packaged in sequence, the size of the module is reduced, and the performance of the module is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a half-bridge power module and a packaging method thereof. Background Art

[0002] Usually, two metal field effect transistors (MOSFET, MOS tube for short) are connected in series (drain and source are short-circuited) to build a half-bridge circuit as a motor drive circuit, such as Figure 1 Two MOS tubes can be connected to form a half bridge through a circuit, as shown in Figure 2 As shown, the half-bridge is used as one of the full-bridge circuits for driving the motor. However, the size of a typical MOS tube is 5mm×6mm. Two MOS tubes are laid flat on a printed circuit board (PCB), and the size of the connecting circuit between the two MOS tubes is about 15mm×8mm, which occupies a large amount of space on the PCB board. In addition, the two MOS tubes need to be interconnected through the exposed surface on the PCB board, which increases the circuit length between the two MOS tubes, and then increases the parasitic resistance and parasitic inductance of the entire half-bridge circuit structure. A single MOS tube has its drain electrode on the back mounted on the PCB board, and the large area of ​​metal layer on the back of the MOS tube is used as its heat dissipation layer, so that the heat of the MOS tube needs to be dissipated through the PCB, resulting in low heat dissipation efficiency.

[0003] Therefore, there is an urgent need to find a half-bridge power module that can improve the heat dissipation capability of the half-bridge circuit structure, reduce the parasitic inductance and resistance of the half-bridge circuit structure, and reduce the size of the half-bridge circuit structure. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a half-bridge power module and a packaging method thereof, so as to solve the problems of large size, poor heat dissipation capability, and large parasitic inductance and capacitance of the half-bridge circuit structure in the prior art.

[0005] To achieve the above objectives and other related objectives, the present invention provides a half-bridge power module, comprising:

[0006] a first substrate;

[0007] A first chip, the lower surface of which is welded to the upper surface of the first region of the first substrate, a first electrode and a second electrode are located on the upper surface of the first chip, a third electrode is located on the lower surface of the first chip, and the third electrode is electrically connected to the first region;

[0008] A frame, comprising at least a first pin, a second pin, a third pin, a fourth pin and a fifth pin, wherein the frame is welded directly above the first chip and the first substrate, wherein the first pin is electrically connected to the first region, the second pin is electrically connected to the first electrode, and the third pin is electrically connected to the second electrode;

[0009] A second chip, the lower surface of which is welded to the upper surface of the second pin, the fourth pole and the fifth pole are located on the upper surface of the second chip, the sixth pole is located on the lower surface of the second chip, and the sixth pole is electrically connected to the second pin;

[0010] A second substrate, the upper surface of which is welded to the upper surfaces of the second chip and the corresponding pins in the frame, the fourth electrode is electrically connected to the second area in the second substrate, the fifth electrode is electrically connected to the third area in the second substrate, the second area is electrically connected to the fourth pin, and the third area is electrically connected to the fifth pin;

[0011] The packaging layer covers the first chip, the second chip, the first substrate, the second substrate and the frame, and the packaging layer exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate and the second substrate.

[0012] Optionally, the first substrate includes a ceramic substrate; and the second substrate includes a ceramic substrate.

[0013] Optionally, the first chip includes a MOS chip, and the second chip includes a MOS chip.

[0014] Optionally, a lower diode chip is provided between the frame and the first substrate, and an anode and a cathode of the lower diode chip are electrically connected to the second pin and the first region respectively; an upper diode chip is provided between the frame and the second substrate, and an anode and a cathode of the upper diode are electrically connected to the second region and the second pin respectively.

[0015] Optionally, a plurality of fourth zones which are spaced apart and insulated from each other are provided in the edge area of ​​the upper surface of the first substrate, the fourth zones are spaced apart from the first zones and insulated from each other, and the portions of the pins in each frame located directly above the fourth zones are respectively welded to the upper surface of the fourth zones.

[0016] Optionally, a size of the first substrate is larger than a size of the second substrate.

[0017] The present invention also provides a packaging method for a half-bridge power module, comprising the following steps:

[0018] A first chip and a first substrate are provided, wherein a first electrode and a second electrode are located on the upper surface of the first chip, and a third electrode is located on the lower surface of the first chip, and the lower surface of the first chip is welded to the upper surface of the first region of the first substrate, and the third electrode is electrically connected to the first region;

[0019] A second chip and a second substrate are provided, the fourth electrode and the fifth electrode are located on the upper surface of the second chip, the sixth electrode is located on the lower surface of the second chip, the upper surface of the second chip is flip-chip soldered to the upper surface of the second substrate, the fourth electrode is electrically connected to the second area in the second substrate, and the fifth electrode is electrically connected to the third area in the second substrate;

[0020] A frame including at least a first pin, a second pin, a third pin, a fourth pin and a fifth pin is provided, and the first substrate with the first chip welded thereon, the frame and the second substrate with the second chip welded thereon are sequentially stacked and assembled and welded synchronously, the first pin is electrically connected to the first region, the second pin is electrically connected to the first pole, the third pin is electrically connected to the second pole, the sixth pole is electrically connected to the upper surface of the second pin, the second region is electrically connected to the fourth pin, and the third region is electrically connected to the fifth pin;

[0021] A packaging layer is formed to cover the first chip, the second chip, the first substrate, the second substrate and the frame, wherein the packaging layer exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate and the second substrate.

[0022] Optionally, before welding the lower surface of the first chip to the upper surface of the first substrate, the step of metallizing the lower surface of the first chip is also included; before welding the upper surface of the second chip to the upper surface of the second substrate, the step of metallizing the lower surface of the second chip is also included.

[0023] Optionally, a welding temperature for welding the first core to the first substrate and the second chip to the second substrate is higher than a welding temperature for simultaneously welding the first chip to the first substrate, the frame, the second chip and the second substrate.

[0024] Optionally, after forming the packaging layer, the method further includes trimming each pin exposed outside the packaging layer and folding each pin into a seagull foot shape.

[0025] As described above, the half-bridge power module and packaging method of the present invention form a half-bridge circuit by stacking and welding the first substrate with the first chip welded thereon, the frame, and the second substrate with the second chip welded thereon in sequence, thereby reducing the size of the module and improving the power density of the module. At the same time, the first chip and the second chip in the module are interconnected through the pins in the first substrate, the second substrate, and the frame, thereby avoiding the interconnection of the first chip and the second chip by external leads or the interconnection of the first chip and the second chip by internal leads of the module, thereby reducing the parasitic inductance and parasitic resistance of the half-bridge power module and improving the performance of the half-bridge power module. In addition, since the upper and lower surfaces of the packaging layer respectively expose the lower surfaces of the first substrate and the second substrate, the half-bridge power module can perform double-sided heat dissipation, thereby improving the heat dissipation performance and reliability of the half-bridge power module, and having a high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Shown is a structural diagram of a single MOS tube.

[0027] Figure 2 Displayed as two Figure 1 The half-bridge circuit structure is composed of the MOS tube.

[0028] Figure 3 It is a schematic cross-sectional structure diagram of a half-bridge power module of the present invention.

[0029] Figure 4 It is a process flow chart of the packaging method of the half-bridge power module of the present invention.

[0030] Figure 5 It is a schematic structural diagram showing the packaging method of the half-bridge power module of the present invention after the first chip is welded to the upper surface of the first substrate.

[0031] Figure 6 It is a schematic structural diagram showing the packaging method of the half-bridge power module of the present invention after the second chip is welded to the upper surface of the second substrate.

[0032] Figure 7 It is a schematic diagram showing an assembly frame, a first substrate and a second substrate of a packaging method for a half-bridge power module of the present invention.

[0033] Figure 8 It is a schematic structural diagram showing the packaging method of the half-bridge power module of the present invention after the packaging layer is formed.

[0034] Description of Figure Numbers

[0035] 1. First substrate

[0036] 11 First Chip

[0037] 2 Second substrate

[0038] 21 Second Chip

[0039] 3 Framework

[0040] 31 Second pin

[0041] 32 Third pin

[0042] 33 Fourth pin

[0043] 4 First welding layer

[0044] 41 Second welding layer

[0045] 41a Second solder layer

[0046] 42 Third welding layer

[0047] 42a Third solder layer

[0048] 43 Fourth welding layer

[0049] 44 Fifth welding layer

[0050] 44a Fifth solder layer

[0051] 5 Encapsulation layer DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] See also Figures 3 to 8 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] Embodiment 1

[0055] This embodiment also provides a half-bridge power module, such as Figure 3As shown, it is a schematic diagram of the cross-sectional structure of the half-bridge power module, including a first substrate 1, a first chip 11, a frame 3, a second chip 21, a second substrate 2 and a packaging layer 5, wherein the lower surface of the first chip 11 is welded to the upper surface of the first area of ​​the first substrate 1, the first pole and the second pole are located on the upper surface of the first chip 11, the third pole is located on the lower surface of the first chip 11, and the third pole is electrically connected to the first area; the frame 3 at least includes a first pin, a second pin 31, a third pin 32, a fourth pin 33 and a fifth pin, the frame 3 is welded directly above the first chip 11 and the first substrate 1, the first pin is electrically connected to the first area, the second pin 31 is electrically connected to the first pole, and the third pin 32 is electrically connected to the second pole; the The lower surface of the second chip 21 is welded to the upper surface of the second pin 31, the fourth pole and the fifth pole are located on the upper surface of the second chip 21, the sixth pole is located on the lower surface of the second chip 21, and the sixth pole is electrically connected to the second pin 31; the upper surface of the second substrate 2 is welded to the second chip 21 and the upper surface of the corresponding pins in the frame 3, the fourth pole is electrically connected to the second area in the second substrate 2, the fifth pole is electrically connected to the third area in the second substrate 2, the second area is electrically connected to the fourth pin 33, and the third area is electrically connected to the fifth pin; the packaging layer 5 covers the first chip 11, the second chip 21, the first substrate 1, the second substrate 2 and the frame 3, and the packaging layer 5 reveals one end of each pin away from the electrical connection and the lower surfaces of the first substrate 1 and the second substrate 2.

[0056] As an example, the first substrate 1 includes a ceramic substrate or other suitable substrates, for example, a direct bonded copper ceramic substrate (DBC), an active metal welded ceramic substrate (AMB), a direct electroplated copper ceramic substrate (DPC), a high temperature co-fired ceramic substrate (HTCC), etc.

[0057] Specifically, the first substrate 1 is usually composed of an insulating layer and a conductive metal layer covering the upper surface of the insulating layer. The conductive metal layer is etched into a plurality of corresponding conductive areas based on actual needs. While ensuring the performance of the power module, the thickness, size and shape of the first substrate 1 can be selected according to actual conditions; the size and shape of the first area on the upper surface of the first substrate 1 (the conductive area obtained by etching the conductive metal layer) can be selected according to actual conditions.

[0058] It should be noted that the back side of the insulating layer in the first substrate 1 can also be provided with a high thermal conductivity heat dissipation structure according to actual needs to improve the heat dissipation capacity of the substrate. Since flip-chip soldering and other processes for changing the structural position are used in the power module packaging process, the upper surface and the back side (lower surface) mentioned here and later are the initial defined positions, not the actual positions after the packaging is completed.

[0059] As an example, the first chip 11 includes a MOS chip or other suitable chips. Preferably, a MOS chip is used as the first chip 11, the first electrode is the source electrode of the MOS chip, the second electrode is the gate electrode of the MOS chip, and the third electrode is the drain electrode of the MOS chip.

[0060] It should be noted that, while ensuring the performance of the power module, the first chip 11 can also be an IGBT chip. The first pole is the emitter of the IGBT chip, and its specific size and shape can be selected according to actual conditions. The second pole is the gate of the IGBT chip, and its specific size and shape can be selected according to actual conditions. The third pole is the collector of the IGBT chip, and usually covers the lower surface of the first chip 11.

[0061] Specifically, while ensuring the performance of the half-bridge power module, the thickness, size and shape of the first chip 11 can be selected according to actual conditions.

[0062] Specifically, the lower surface of the first chip 11 is usually welded to the upper surface of the first substrate 1 through the first welding layer 4, so that the first chip 11 is fixed to the upper surface of the first substrate 1, and the third electrode is electrically connected to the first area through the first welding layer 4, that is, the first welding layer 4 is located between the third electrode and the first area, and the material of the first welding layer 4 includes at least one of gold, silver, tin, lead, and indium, and can also be other suitable welding materials. In this embodiment, the first welding layer 4 is formed by curing high-temperature solder paste after a reflow process.

[0063] Specifically, while ensuring the performance of the half-bridge power module, the size, shape and thickness of the first welding layer 4 can be selected according to actual conditions.

[0064] As an example, a lower diode chip is also provided between the frame 3 and the first substrate 1, and the anode and cathode of the lower diode chip are electrically connected to the second pin 31 and the first region respectively. That is, when the first chip 11 is a MOS chip, a lower diode chip can also be provided between the frame 3 and the first substrate 1. The lower diode chip is connected in parallel with the first chip 11 through the frame 3 and the first substrate 1, and the anode of the lower diode chip is electrically connected to the first pole of the first chip 11 through the second pin 31, and the cathode of the lower diode is electrically connected to the third pole through the first region.

[0065] Specifically, while ensuring the performance of the half-bridge power module, the size, thickness, shape and electrical performance parameters of the lower diode chip can be selected according to actual conditions.

[0066] It should be noted that the first chip 11 can also be a chip that is a combination of a MOS chip and a diode chip, and then there is no need to set a lower diode chip between the frame 3 and the first substrate 1. Alternatively, when the first chip 11 is a MOS chip, based on the packaging structure of the half-bridge power module, a diode chip connected in parallel with the first chip 11 is electrically connected outside the packaging structure.

[0067] Specifically, the frame 3 usually needs to be adapted to the various devices in the half-bridge power module, and its specific structure and size need to be designed according to the actual needs of the half-bridge power module. For example, when real-time feedback on the working status of the half-bridge power module is required, corresponding sensor pins need to be set, or when the thickness of the chip between the frame 3 and the first substrate 1 is inconsistent, the shape of the corresponding pins needs to be changed, etc.

[0068] Specifically, while ensuring the performance of the half-bridge power module, the size and shape of each pin (the first pin, the second pin 31 , the third pin 32 , the fourth pin 33 and the fifth pin) in the frame 3 can be selected according to actual conditions.

[0069] Specifically, the material of each pin includes copper, aluminum, silver, gold, titanium, platinum, nickel or other suitable conductive materials. Preferably, each pin is a copper pin.

[0070] As an example, a plurality of fourth zones which are spaced apart and insulated from each other are provided in the edge area of ​​the upper surface of the first substrate 1. The fourth zones are spaced apart from the first zones and insulated from each other. The portions of the pins in each frame 3 located directly above the fourth zones are respectively welded to the upper surface of the fourth zones.

[0071] Specifically, the portion of each pin located directly above the fourth area is bent toward the first substrate 1 and fits with the fourth area, so as to provide a support point for the frame 3 during the process of welding the frame 3 and the first chip 11, so that the frame 3 can be stably stacked on the top of the first chip 11, which is convenient for welding the first chip 11 and the frame 3. At the same time, the portion of each pin located directly above the edge area of ​​the first substrate 1 and fits with the fourth area is welded together, so that the frame 3 is firmly combined with the first substrate 1, thereby improving the reliability of the power module.

[0072] It should be noted that, usually, the fourth area is fixedly connected to each pin through the second welding layer 41, and the first pin is fixedly electrically connected to the first area through the second welding layer 41, and the second pin 31 and the first pole and the third pin 32 and the second pole are fixedly electrically connected through the third welding layer 42 arranged at intervals. At the same time, when a lower diode is provided in the module, the anode and cathode of the lower diode are electrically connected to the second pin 31 through the third welding layer 42 and to the first area through the first welding layer 4, respectively.

[0073] Specifically, the material of the second welding layer 41 includes gold, silver, tin, lead, indium or other suitable welding materials; the material of the third welding layer 42 includes gold, silver, tin, lead, indium or other suitable welding materials. Preferably, the second welding layer 41 and the third welding layer 42 are made of the same material.

[0074] Specifically, while ensuring the performance of the half-bridge power module, the thickness, size and shape of the second welding layer 41 can be selected according to actual conditions; the thickness, size and shape of the third welding layer 42 can be selected according to actual conditions.

[0075] As an example, the second substrate 2 includes a ceramic substrate or other suitable substrates, for example, a direct bonded copper ceramic substrate (DBC), an active metal soldered ceramic substrate (AMB), a direct electroplated copper ceramic substrate (DPC), a high temperature co-fired ceramic substrate (HTCC), etc. Preferably, the first substrate 1 and the second substrate 2 are of the same type.

[0076] Specifically, the second substrate 2 is usually composed of an insulating layer and a conductive metal layer covering the upper surface of the insulating layer. The conductive metal layer is etched into a plurality of corresponding conductive areas based on actual needs. While ensuring the performance of the half-bridge power module, the thickness and shape of the second substrate 2 can be selected according to actual conditions; the size and shape of the second area on the upper surface of the second substrate 2 (the conductive area obtained by etching the conductive metal layer) can be selected according to actual conditions; the size and shape of the third area on the upper surface of the second substrate 2 (the conductive area obtained by etching the conductive metal layer) can be selected according to actual conditions.

[0077] It should be noted that a high thermal conductivity heat dissipation structure may also be provided on the back side of the insulating layer in the second substrate 2 according to actual needs to enhance the heat dissipation capability of the substrate.

[0078] As an example, the size of the first substrate 1 is larger than that of the second substrate 2 , so as to facilitate flip-chip welding of the second substrate 2 welded with the second chip 21 onto the frame 3 .

[0079] Specifically, while ensuring the performance of the half-bridge power module, the size of the first substrate 1 may also be smaller than the size of the second substrate 2 , or the size of the first substrate 1 may be equal to the size of the second substrate 2 .

[0080] As an example, the second chip 21 includes a MOS chip or other suitable chips. Preferably, a MOS chip is used as the second chip 21, the fourth electrode is the source electrode of the MOS chip, the fifth electrode is the gate electrode of the MOS chip, and the sixth electrode is the drain electrode of the MOS chip.

[0081] It should be noted that, while ensuring the performance of the power module, the second chip 21 can also be an IGBT chip, in which case the fourth pole is the emitter of the IGBT chip, the fifth pole is the gate of the IGBT chip, and the sixth pole is the collector of the IGBT chip.

[0082] Specifically, while ensuring the performance of the power module, the thickness, size and shape of the second chip 21 can be selected according to actual conditions.

[0083] Specifically, the upper surface of the second chip 21 is usually welded to the upper surface of the second substrate 2 through the fourth welding layer 43 arranged at intervals, so that the second chip 21 is fixed to the upper surface of the second substrate 2. At the same time, the fourth pole is electrically connected to the second area through the fourth welding layer 43, and the fifth pole is electrically connected to the third area through the fourth welding layer 43, that is, the fourth welding layer 43 is respectively located between the fourth pole and the second area and between the fifth pole and the third area. The material of the fourth welding layer 43 includes gold, silver, tin, lead, indium or other suitable welding materials.

[0084] Specifically, the sixth electrode and the second pin 31, the fourth pin 33 and the second area, and the fifth pin and the third area are respectively electrically connected via a spaced fifth welding layer 44. The fifth welding layer 44 is made of gold, silver, tin, lead, indium or other suitable welding materials.

[0085] Specifically, while ensuring the performance of the half-bridge power module, the size, shape and thickness of each fourth welding layer 43 can be selected according to actual conditions; the size, shape and thickness of each fifth welding layer 44 can be selected according to actual conditions.

[0086] As an example, an upper diode chip is also provided between the frame 3 and the second substrate 2, and the anode and cathode of the upper diode chip are electrically connected to the second area and the second pin 31 respectively, that is, when the second chip 21 is a MOS chip, an upper diode chip can also be provided between the frame 3 and the second substrate 2, and the upper diode chip is connected in parallel with the second chip 21 through the frame 3 and the second substrate 2, and the anode of the upper diode chip is electrically connected to the second area through the fourth welding layer 43, and is electrically connected to the fourth pole of the second chip 21 at the same time, and the cathode of the upper diode is electrically connected to the second pin 31 through the fifth welding layer 44, and is electrically connected to the sixth pole of the second chip 21 at the same time, and the second chip 21 is electrically connected to the first pole of the first chip 11 through the second pin 31, thereby realizing the series connection of the parallel structure formed by the first chip 11 and the lower diode chip and the parallel structure formed by the second chip 21 and the upper diode chip, and forming a half-bridge circuit structure at the same time.

[0087] Specifically, while ensuring the performance of the half-bridge power module, the size, thickness, shape and electrical performance parameters of the upper diode chip can be selected according to actual conditions.

[0088] It should be noted that the second chip 21 can also be a chip that is sealed with a MOS chip and a diode chip, and then there is no need to set a diode chip between the frame 3 and the second substrate 2. Alternatively, when the second chip 21 is a MOS chip, based on the packaging structure of the half-bridge power module, a diode chip connected in parallel with the second chip 21 is electrically connected outside the packaging structure.

[0089] Specifically, the packaging layer 5 is used to protect various devices in the half-bridge power module to ensure the reliability of the module. The material of the packaging layer 5 includes epoxy resin, silicone, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB) or other suitable packaging materials.

[0090] It should be noted that since the upper and lower surfaces of the packaging layer 5 respectively expose the back side of the first substrate 1 and the back side of the second substrate 2, the thickness, size and shape of the packaging layer 5 are related to the structure of each device after welding in the corresponding half-bridge power module, and are no longer limited here.

[0091] Specifically, while ensuring the performance of the half-bridge power module, the size and shape of each pin exposed outside the packaging layer 5 can be selected according to actual conditions.

[0092] Specifically, by welding the first chip 11 and the second chip 21 to the upper and lower surfaces of the frame 3 that leads out the power module electrodes, the first substrate 1, the first chip 11, the frame 3, the second chip 21 and the second substrate 2 form a stacked structure in sequence, thereby reducing the overall size of the half-bridge power module and improving the power density of the module.

[0093] Specifically, a half-bridge circuit is formed by stacking and interconnecting the first substrate 1, the first chip 11, the frame 3, the second chip 21 and the second substrate 2, thereby avoiding external lead interconnection or internal lead interconnection of the module, reducing the parasitic inductance and parasitic resistance of the half-bridge power module, and improving the performance of the half-bridge power module.

[0094] Specifically, since the upper and lower surfaces of the packaging layer 5 respectively expose the lower surfaces of the first substrate 1 and the second substrate 2 , the half-bridge power module can perform double-sided heat dissipation, thereby improving the heat dissipation performance of the half-bridge power module.

[0095] The half-bridge power module of this embodiment improves the structure of the half-bridge power module, stacks and welds the first substrate 1, the first chip 11, the frame 3, the second chip 21 and the second substrate 2 in sequence to form a half-bridge circuit, reduces the overall size of the half-bridge power module, and improves the power density of the module. At the same time, since the interconnection of each device in the half-bridge circuit is achieved through the first substrate 1, the second substrate 2 and the pins in the frame 3, it avoids the interconnection of external leads or the interconnection of each device by the internal leads of the module, reduces the parasitic inductance and parasitic resistance of the half-bridge power module, and improves the performance of the half-bridge power module. In addition, since the upper and lower surfaces of the encapsulation layer 5 respectively expose the lower surfaces of the first substrate 1 and the second substrate 2, the half-bridge power module can perform double-sided heat dissipation, which improves the heat dissipation performance and reliability of the half-bridge power module.

[0096] Embodiment 2

[0097] This embodiment provides a packaging method for a half-bridge power module. Figure 4 FIG. 1 is a process flow chart of the packaging method of the half-bridge power module, comprising the following steps:

[0098] S1: providing a first chip and a first substrate, wherein a first electrode and a second electrode are located on the upper surface of the first chip, and a third electrode is located on the lower surface of the first chip, and the lower surface of the first chip is welded to the upper surface of the first region of the first substrate, and the third electrode is electrically connected to the first region;

[0099] S2: providing a second chip and a second substrate, wherein the fourth electrode and the fifth electrode are located on the upper surface of the second chip, and the sixth electrode is located on the lower surface of the second chip, and the upper surface of the second chip is flip-chip soldered to the upper surface of the second substrate, wherein the fourth electrode is electrically connected to the second region of the second substrate, and the fifth electrode is electrically connected to the third region of the second substrate;

[0100] S3: providing a frame including at least a first pin, a second pin, a third pin, a fourth pin and a fifth pin, stacking and assembling the first substrate welded with the first chip, the frame and the second substrate welded with the second chip in sequence and welding them synchronously, the first pin is electrically connected to the first area, the second pin is electrically connected to the first pole, the third pin is electrically connected to the second pole, the sixth pole is electrically connected to the upper surface of the second pin, the second area is electrically connected to the fourth pin, and the third area is electrically connected to the fifth pin;

[0101] S4: forming a packaging layer covering the first chip, the second chip, the first substrate, the second substrate and the frame, wherein the packaging layer exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate and the second substrate.

[0102] See also Figure 5 to Figure 6 , perform step S1 and step S2: provide a first chip 11 and a first substrate 1, the first pole and the second pole are located on the upper surface of the first chip 11, the third pole is located on the lower surface of the first chip 11, the lower surface of the first chip 11 is welded to the upper surface of the first area of ​​the first substrate 1, and the third pole is electrically connected to the first area; provide a second chip 21 and a second substrate 2, the fourth pole and the fifth pole are located on the upper surface of the second chip 21, the sixth pole is located on the lower surface of the second chip 21, the upper surface of the second chip 21 is flip-chip welded to the upper surface of the second substrate 2, the fourth pole is electrically connected to the second area in the second substrate 2, and the fifth pole is electrically connected to the third area in the second substrate 2.

[0103] Specifically, the first chip 11 includes a MOS chip or other suitable chips, and the first substrate 1 includes a ceramic substrate or other suitable substrates.

[0104] As an example, before welding the lower surface of the first chip 11 to the upper surface of the first substrate 1 , the process further includes metallizing the lower surface of the first chip 11 .

[0105] Specifically, by metallizing the lower surface of the first chip 11, that is, forming a first metal layer of a preset thickness on the lower surface of the first chip 11, the lower surface of the first chip 11 and the upper surface of the first substrate 1 after welding are more firmly bonded, and the electrical connection between the third electrode and the first area and the welding of the first chip 11 are facilitated.

[0106] Specifically, the method of metallizing the back side of the first chip 11 includes chemical vapor deposition, magnetron sputtering, evaporation, electroplating, atomic layer deposition, atomic vapor deposition or other suitable methods.

[0107] Specifically, the thickness and material of the first metal layer can be selected according to actual conditions while ensuring the reliability of the combination of the first chip 11 and the first substrate 1 after subsequent welding.

[0108] Specifically, the first substrate 1 is composed of stacked insulating layers and conductive metal layers. Before welding the lower surface of the first chip 11 to the upper surface of the first substrate 1, it is also necessary to etch the conductive metal layer into multiple corresponding conductive areas based on actual conditions to facilitate subsequent interconnection between devices and welding of pins.

[0109] Specifically, the method of etching the conductive metal layer in the first substrate 1 into a plurality of conductive regions includes dry etching, wet etching, laser etching or other suitable methods.

[0110] Specifically, Figure 5As shown, it is a schematic diagram of the structure after the first chip 11 is welded to the upper surface of the first substrate 1, and welding the lower surface of the first chip 11 to the upper surface of the first substrate 1 includes the following steps: printing a first solder layer of a preset thickness in the first area on the upper surface of the first substrate 1, and placing the first chip 11 on the upper surface of the first solder layer; welding through a reflow process to weld the first chip 11 to the upper surface of the first area of ​​the first substrate 1, and at the same time, the first solder layer forms a first welding layer 4 that fixes and electrically connects the first chip 11 and the first area after the welding process.

[0111] Specifically, when the first chip 11 is a MOS chip, a lower diode can be welded to the first region simultaneously with welding the first chip 11, and the cathode of the lower diode can be welded to the first region synchronously with the first chip 11 through the first solder layer.

[0112] As an example, before soldering the upper surface of the second chip 21 to the upper surface of the second substrate 2 , the process further includes metallizing the lower surface of the second chip 21 .

[0113] Specifically, by metallizing the lower surface of the second chip 21, that is, forming a second metal layer of a preset thickness on the lower surface of the second chip 21, the lower surface of the second chip 21 after welding and the upper surface of the subsequently welded frame can be more firmly bonded, and the electrical connection between the sixth pole and the second pin in the subsequent frame and the welding between the second chip 21 and the subsequent frame can be facilitated.

[0114] Specifically, the method of metallizing the back side of the second chip 21 includes chemical vapor deposition, magnetron sputtering, evaporation, electroplating, atomic layer deposition, atomic vapor deposition or other suitable methods.

[0115] Specifically, the thickness and material of the second metal layer can be selected according to actual conditions while ensuring the reliability of the subsequent bonding between the second chip 21 and the upper surface of the frame.

[0116] Specifically, the second substrate 2 is composed of stacked insulating layers and conductive metal layers. Before welding the upper surface of the second chip 21 to the upper surface of the second substrate 2, it is also necessary to etch the conductive metal layer into multiple corresponding conductive areas, namely the second area and the third area, based on actual conditions, to facilitate subsequent interconnection between devices and welding of pins.

[0117] Specifically, the method of etching the conductive metal layer in the second substrate 2 into a plurality of conductive regions includes dry etching, wet etching, laser etching or other suitable methods.

[0118] Specifically, Figure 6As shown, it is a schematic diagram of the structure after the second chip 21 is welded to the upper surface of the second substrate 2. Welding the upper surface of the second chip 21 to the upper surface of the second substrate 2 includes the following steps: printing a fourth solder layer of preset thickness in the second area and the third area on the upper surface of the second substrate 2, and placing the second chip 21 on the upper surface of the fourth solder layer; welding through a reflow soldering process to weld the second chip 21 to the upper surface of the second substrate 2, and at the same time, the fourth solder layer forms a fourth welding layer 43 after the welding process, wherein the fourth pole is located directly above the second area and is fixedly electrically connected through the fourth welding layer 43 between the fourth pole and the second area, and the fifth pole is located directly above the third area and is fixedly electrically connected through the fourth welding between the fifth pole and the third area.

[0119] Specifically, when the second chip 21 is a MOS chip, an upper diode can be welded to the second region simultaneously with welding the second chip 21, and the cathode of the upper diode can be welded to the second region synchronously with the second chip 21 through the fourth solder layer.

[0120] See also Figures 7 and 8 , perform step S3 and step S4: provide a frame 3 including at least a first pin, a second pin 31, a third pin 32, a fourth pin 33 and a fifth pin, stack and assemble the first substrate 1 welded with the first chip 11, the frame 3 and the second substrate 2 welded with the second chip 21 in sequence and perform synchronous welding, the first pin is electrically connected to the first area, the second pin 31 is electrically connected to the first pole, the third pin 32 is electrically connected to the second pole, the sixth pole is electrically connected to the upper surface of the second pin 31, the second area is electrically connected to the fourth pin 33, and the third area is electrically connected to the fifth pin; form a packaging layer 5 covering the first chip 11, the second chip 21, the first substrate 1, the second substrate 2 and the frame 3, the packaging layer 5 exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate 1 and the second substrate 2.

[0121] Specifically, a plurality of fourth zones which are spaced apart and insulated from each other are provided in the edge area of ​​the upper surface of the first substrate 1. The fourth zones are spaced apart from the first zones and insulated from each other. The fourth zones are support points for placing corresponding pins in the frame 3. The pins located directly above the fourth zones are bent toward the fourth zones and fit with the fourth zones. At the same time, the fourth zones are also used as welding zones for fixing and welding the frame 3 to the first substrate 1.

[0122] Specifically, while ensuring the performance of the subsequently packaged half-bridge power module, the size and shape of each fourth area can be selected according to actual conditions.

[0123] Specifically, Figure 7As shown, it is a schematic diagram of assembling the frame 3, the first substrate 1 and the second substrate 2. The synchronous welding of the frame 3 with the first chip 11, the second chip 21, the first substrate 1 and the second substrate 2 includes the following steps: the upper surface of the first substrate 1 after welding the first chip 11 is facing upward and placed on the process platform; a second solder layer 41a is formed on the upper surfaces of the fourth area and the first area respectively, and a third solder layer 42a is formed on the upper surfaces of the first pole and the second pole respectively; the frame 3 is assembled above the first substrate 1, and the portion of each pin located directly above the edge area of ​​the first substrate 1 is bonded to the second solder layer 41a on the upper surface of the corresponding fourth area, the welding area of ​​the first pin is bonded to the second solder layer 41a on the upper surface of the first area, the lower surface of the welding area of ​​the second pin 31 and the lower surface of the welding area of ​​the third pin 32 are bonded to the third solder layer 42a on the upper surfaces of the first pole and the second pole respectively, and the second pin 31, A fifth solder layer 44a is formed on the upper surfaces of the welding areas of the fourth pin 33 and the fifth pin; the second substrate 2 welded with the second chip 21 is assembled to the top of the frame 3, and the sixth pole is attached to the fifth solder layer 44a on the upper surface of the second pin 31, the second area is attached to the fifth solder layer 44a on the upper surface of the fourth pin 33, and the fifth solder layer 44a on the upper surface of the fifth pin in the third area is attached; the structure after assembling the second substrate 2 is welded to simultaneously form the second welding layer 41, the third welding layer 42 and the fifth welding layer 44, wherein the second welding layer 41 is fixedly connected to the fourth area and each pin and is fixedly electrically connected to the first pin and the first area, the third welding layer 42 is fixedly electrically connected to the welding area of ​​the second pin 31 and the first pole and the welding area of ​​the third pin 32 and the second pole, and the fifth welding layer 44 is fixedly electrically connected to the second pin 31 and the sixth pole, the second area and the fourth pin 33, and the third area and the fifth pin.

[0124] As an example, the welding temperature of welding the first core and the first substrate 1 and the second chip 21 and the second substrate 2 is higher than the welding temperature of synchronously welding the first chip 11 and the first substrate 1, the frame 3 and the second chip 21 and the second substrate 2. That is, the welding temperatures of the second solder layer 41a, the third solder layer 42a, and the fifth solder layer 44a are lower than the welding temperatures of the first solder layer and the fourth solder layer.

[0125] Specifically, since the frame 3 is welded only after the first chip 11 and the second chip 21 are respectively welded to the first substrate 1 and the second substrate 2, in order to avoid affecting the welding reliability between the first chip 11 and the first substrate 1 and the second chip 21 and the second substrate 2 during the welding process of the frame 3, it is necessary to make the welding temperatures of the second solder layer 41a, the third solder layer 42a, and the fifth solder layer 44a lower than the welding temperatures of the first solder layer and the fourth solder layer to ensure the reliability of the half-bridge power module.

[0126] It should be noted that, since the upper surfaces of the first area and the fourth area are flush, the edge area of ​​the first substrate 1 below the first pin may not need to be provided with a corresponding fourth area, or the fourth area may be connected to the first area.

[0127] Specifically, the method of synchronously soldering the components (the first substrate 1, the first chip 11, the frame 3, the second chip 21 and the second substrate 2) through the second solder layer 41a, the third solder layer 42a and the fifth solder layer 44a includes reflow soldering or other suitable methods.

[0128] Specifically, Figure 8 , which is a schematic diagram of the structure after the encapsulation layer 5 is formed. The method of forming the encapsulation layer 5 includes compression molding, transfer molding, liquid sealing molding, vacuum lamination or other suitable methods.

[0129] As an example, after forming the packaging layer 5, the steps of trimming each pin exposed outside the packaging layer 5 and folding each pin into a seagull foot shape are also included, such as Figure 3 shown.

[0130] Specifically, after the encapsulation layer 5 is formed, the pins exposed from the encapsulation layer 5 and outside the encapsulation layer 5 are trimmed to avoid affecting the use of the half-bridge power module due to excessively long pins or burrs on the edge of the encapsulation layer 5. At the same time, the pins exposed outside the encapsulation layer 5 are folded into a seagull foot shape to facilitate the subsequent installation of the half-bridge power module.

[0131] It should be noted that, in order to facilitate the subsequent installation of the half-bridge power module, each pin may also be bent into other suitable shapes based on actual conditions.

[0132] Specifically, after the first chip 11 and the second chip 21 are respectively welded to the first substrate 1 and the second substrate 2, the first substrate 1 welded with the first chip 11, the frame 3, and the second substrate 2 welded with the second chip 21 are stacked and welded in sequence, wherein the first pin in the frame 3 is electrically connected to the third pole through the second welding layer 41 and the first zone, the second pin 31 is electrically connected to the first pole and the sixth pole respectively through the third welding layer 42 and the fifth welding layer 44, the third pin 32 is electrically connected to the second pole through the third welding layer 42, the fourth pin 33 is electrically connected to the fourth pole through the fifth welding layer 44 and the second zone, and the fifth pin is electrically connected to the fifth pole through the fifth welding layer 44 and the third zone, thereby reducing the size of the half-bridge power module, improving the power density of the module, and reducing the parasitic inductance and parasitic resistance of the module.

[0133] Specifically, since the upper and lower surfaces of the packaging layer 5 respectively expose the lower surfaces of the first substrate 1 and the second substrate 2 , the heat dissipation performance of the module is improved, thereby improving the reliability of the module.

[0134] The packaging method of the half-bridge power module of the present embodiment reduces the size of the half-bridge power module, improves the power density of the module, and reduces the parasitic inductance and parasitic resistance of the module by stacking and welding the first substrate 1 welded with the first chip 11, the frame 3, and the second substrate 2 welded with the second chip 21 in sequence after welding the first chip 11 and the second chip 21 to the first substrate 1 and the second substrate 2 respectively.

[0135] In summary, the half-bridge power module and its packaging method of the present invention improve the structure of the half-bridge power module, stack and weld the first substrate with the first chip welded thereon, the frame and the second substrate with the second chip welded thereon in sequence to form a half-bridge circuit, reduce the overall size of the half-bridge power module, and improve the power density of the module. At the same time, the first chip and the second chip are interconnected through the pins in the first substrate, the second substrate and the frame, avoiding the interconnection of the first chip and the second chip by external leads or the interconnection of the first chip and the second chip by internal leads of the module, reducing the parasitic inductance and parasitic resistance of the half-bridge power module. At the same time, since the upper and lower surfaces of the packaging layer respectively expose the lower surfaces of the first substrate and the second substrate, the half-bridge power module can perform double-sided heat dissipation through the lower surfaces of the first substrate and the second substrate, thereby improving the heat dissipation performance and reliability of the half-bridge power module. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0136] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A half-bridge power module, characterized in that: include: a first substrate; A first chip, the lower surface of which is welded to the upper surface of the first region of the first substrate, a first electrode and a second electrode are located on the upper surface of the first chip, a third electrode is located on the lower surface of the first chip, and the third electrode is electrically connected to the first region; A frame, comprising at least a first pin, a second pin, a third pin, a fourth pin and a fifth pin, wherein the frame is welded directly above the first chip and the first substrate, wherein the first pin is electrically connected to the first region, the second pin is electrically connected to the first electrode, and the third pin is electrically connected to the second electrode; A second chip, the lower surface of which is welded to the upper surface of the second pin, the fourth pole and the fifth pole are located on the upper surface of the second chip, the sixth pole is located on the lower surface of the second chip, and the sixth pole is electrically connected to the second pin; A second substrate, the upper surface of which is welded to the upper surfaces of the second chip and the corresponding pins in the frame, the fourth electrode is electrically connected to the second area in the second substrate, the fifth electrode is electrically connected to the third area in the second substrate, the second area is electrically connected to the fourth pin, and the third area is electrically connected to the fifth pin; The packaging layer covers the first chip, the second chip, the first substrate, the second substrate and the frame, and the packaging layer exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate and the second substrate.

2. The half-bridge power module according to claim 1, characterized in that: The first substrate includes a ceramic substrate; the second substrate includes a ceramic substrate.

3. The half-bridge power module according to claim 1, characterized in that: The first chip includes a MOS chip, and the second chip includes a MOS chip.

4. The half-bridge power module according to claim 3, characterized in that: A lower diode chip is also provided between the frame and the first substrate, and an anode and a cathode of the lower diode chip are electrically connected to the second pin and the first area respectively; an upper diode chip is also provided between the frame and the second substrate, and an anode and a cathode of the upper diode are electrically connected to the second area and the second pin respectively.

5. The half-bridge power module according to claim 1, characterized in that: The edge area of ​​the upper surface of the first substrate is also provided with a plurality of fourth areas which are spaced apart and insulated from each other. The fourth areas are spaced apart from the first areas and insulated from each other. Parts of the pins in each frame located directly above the fourth areas are respectively welded to the upper surface of the fourth areas.

6. The packaging method of a half-bridge power module according to claim 1, characterized in that: The size of the first substrate is larger than that of the second substrate.

7. A packaging method for a half-bridge power module, characterized in that: The following steps are involved: A first chip and a first substrate are provided, wherein a first electrode and a second electrode are located on the upper surface of the first chip, and a third electrode is located on the lower surface of the first chip, and the lower surface of the first chip is welded to the upper surface of the first region of the first substrate, and the third electrode is electrically connected to the first region; A second chip and a second substrate are provided, the fourth electrode and the fifth electrode are located on the upper surface of the second chip, the sixth electrode is located on the lower surface of the second chip, the upper surface of the second chip is flip-chip soldered to the upper surface of the second substrate, the fourth electrode is electrically connected to the second area in the second substrate, and the fifth electrode is electrically connected to the third area in the second substrate; A frame including at least a first pin, a second pin, a third pin, a fourth pin and a fifth pin is provided, and the first substrate with the first chip welded thereon, the frame and the second substrate with the second chip welded thereon are sequentially stacked and assembled and welded synchronously, the first pin is electrically connected to the first region, the second pin is electrically connected to the first pole, the third pin is electrically connected to the second pole, the sixth pole is electrically connected to the upper surface of the second pin, the second region is electrically connected to the fourth pin, and the third region is electrically connected to the fifth pin; A packaging layer is formed to cover the first chip, the second chip, the first substrate, the second substrate and the frame, wherein the packaging layer exposes one end of each pin away from the electrical connection and the lower surfaces of the first substrate and the second substrate.

8. The packaging method of the half-bridge power module according to claim 7, characterized in that: Before welding the lower surface of the first chip to the upper surface of the first substrate, the step of metallizing the lower surface of the first chip is also included; before welding the upper surface of the second chip to the upper surface of the second substrate, the step of metallizing the lower surface of the second chip is also included.

9. The packaging method of a half-bridge power module according to claim 7, characterized in that: The welding temperature of welding the first core to the first substrate and the second chip to the second substrate is higher than the welding temperature of simultaneously welding the first chip to the first substrate, the frame, and the second chip to the second substrate.

10. The packaging method of a half-bridge power module according to claim 7, characterized in that: After the packaging layer is formed, the method further includes the steps of trimming each pin exposed outside the packaging layer and folding each pin into a seagull foot shape.

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