Hybrid power module, multiphase full-bridge hybrid module, power conversion device, and vehicle

Abstract

The application provides a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device and a vehicle, comprising: a substrate; a first DC connection layer, a second DC connection layer and an AC connection layer located on the substrate; an upper bridge chip set located on the first DC connection layer and a lower bridge chip set located on the AC connection layer, wherein the upper bridge chip set comprises a first wide bandgap chip set and the lower bridge chip set comprises a second wide bandgap chip set; the first wide bandgap chip set is connected with the AC connection layer and the second wide bandgap chip set is connected with the second DC connection layer, thereby forming a half-bridge hybrid power module on one substrate, reducing the manufacturing process and improving the space utilization. The first wide bandgap chip set and the second wide bandgap chip set are arranged along a second direction, and the first wide bandgap chip set and the second wide bandgap chip set each comprise a plurality of wide bandgap power chips arranged along the second direction, thereby forming a relatively regular arrangement mode and further improving the space utilization.

Description

Technical Field

[0001] This application relates to the field of power conversion technology, and in particular to a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device, and a vehicle. Background Technology

[0002] Hybrid power modules, composed of wide-bandgap semiconductor power devices (e.g., silicon carbide metal-oxide-semiconductor field-effect transistors, SiMOSFETs) and silicon-based fully controllable power semiconductor devices (e.g., silicon insulated-gate bipolar transistors, SiIGBTs), are increasingly widely used in power circuits. By controlling the switching of the power circuit with wide-bandgap semiconductor power devices and handling the main conduction current with silicon-based fully controllable power semiconductor devices, the advantages of the two types of devices are combined to reduce switching losses and costs.

[0003] Currently, a half-bridge hybrid power module is mainly composed of multiple different substrates. Different substrates are used to carry different devices, and different substrates need to be connected. This results in too many manufacturing processes and low space utilization. Summary of the Invention

[0004] This application provides a hybrid power module, a multiphase full-bridge hybrid module, a power conversion device, and a vehicle to reduce manufacturing processes and improve space utilization.

[0005] In a first aspect, this application provides a hybrid power module, comprising:

[0006] substrate;

[0007] A first DC connection layer, an AC connection layer, and a second DC connection layer are located on the substrate;

[0008] And an upper bridge chipset located on the first DC connection layer, and a lower bridge chipset located on the AC connection layer, wherein the upper bridge chipset includes a first wide bandgap chipset and the lower bridge chipset includes a second wide bandgap chipset;

[0009] The first wide bandgap chipset is connected to the AC connection layer, and the second wide bandgap chipset is connected to the second DC connection layer;

[0010] The first wide bandgap chipset and the second wide bandgap chipset are arranged along the second direction, and each of the first wide bandgap chipset and the second wide bandgap chipset includes a plurality of wide bandgap power chips arranged along the second direction.

[0011] In some embodiments, the upper bridge chipset further includes a first silicon-based chipset, and the lower bridge chipset further includes a second silicon-based chipset. The silicon-based power chip in each of the first silicon-based chipset is connected in series with the silicon-based power chip in the second silicon-based chipset to form a half-bridge structure.

[0012] In some embodiments, the second wide bandgap chipset is connected in series with the wide bandgap power chips in the first wide bandgap chipset to form a half-bridge circuit, and the multiple wide bandgap power chips in the wide bandgap chipset are connected in parallel with each other.

[0013] In some embodiments, the hybrid power module includes a second DC connection terminal located on the second DC connection layer, and the current path length between the wide bandgap power chip of each of the second wide bandgap chipsets and the second DC connection terminal is the same.

[0014] In some embodiments, at least a portion of the AC connection layer is structurally spaced within the first DC connection layer and is insulated from the first DC connection layer to connect to the wide bandgap power chip in the first wide bandgap chipset.

[0015] In some embodiments, on the second DC connection layer shown, the second DC connection terminal is disposed close to the second wide bandgap chipset.

[0016] In some embodiments, the hybrid power module further includes a first DC connection terminal located on the first DC connection layer, wherein the current path length between each wide bandgap power chip of the first wide bandgap chipset and the first DC connection terminal is the same.

[0017] In some embodiments, the first DC connection layer includes a first connection layer and a second connection layer that are interconnected.

[0018] The first wide bandgap chipset is located on the first interconnect layer, and the first silicon-based chipset is located on the second interconnect layer.

[0019] In some embodiments, a recess is formed between the first connection layer and the second connection layer to accommodate at least a portion of the protruding structure of the AC connection layer, the protruding at least a portion of the structure being spaced apart from the first DC connection layer for electrically connecting a plurality of wide bandgap power chips in the first wide bandgap chipset.

[0020] In some embodiments, the arrangement of the plurality of wide bandgap power chips includes at least one of the following:

[0021] Each of the wide bandgap power chips is flush-mounted in the second direction;

[0022] Two adjacent wide-bandgap power chips are staggered in the first direction;

[0023] Each of the wide bandgap power chips is staggered in the first direction;

[0024] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0025] In some embodiments, the first silicon-based chipset further includes a plurality of diode chips.

[0026] In some embodiments, the second silicon-based chipset further includes a plurality of diode chips.

[0027] In some embodiments, a plurality of diode chips in each of the first silicon-based chipsets are connected in series with a plurality of diode chips in the second silicon-based chipset.

[0028] In some embodiments, the arrangement of multiple silicon-based power chips and multiple diode chips within any silicon-based chipset includes at least one of the following:

[0029] The silicon-based power chip and the diode chip are arranged crosswise in a first direction;

[0030] A first chip assembly and a second chip assembly are arranged in the first direction, the first chip assembly including a plurality of silicon-based power chips arranged in the first direction, and the second chip assembly including a plurality of diode chips arranged in the first direction.

[0031] Multiple third chip assemblies are arranged in the first direction, and the third chip assemblies include the silicon-based power chip and the diode chip arranged in the second direction;

[0032] Multiple fourth chip assemblies and multiple fifth chip assemblies are arranged in a crisscrossing manner in the first direction. The fourth chip assemblies and the fifth chip assemblies include silicon-based power chips and diodes arranged in the second direction, and the silicon-based power chips and diodes in the fourth chip assemblies and the fifth chip assemblies are arranged in opposite directions.

[0033] Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

[0034] In some embodiments, the arrangement of multiple silicon-based power chips and multiple diodes within any silicon-based chipset includes at least one of the following:

[0035] The silicon-based power chip and the diode chip are arranged in a cross pattern in the second direction;

[0036] A first chip assembly and a second chip assembly are arranged in the second direction, the first chip assembly including a plurality of silicon-based power chips arranged in the second direction, and the second chip assembly including a plurality of diode chips arranged in the second direction;

[0037] Multiple third chip combinations are arranged in the second direction, the third chip combinations including the silicon-based power chip and the diode chip arranged in the first direction;

[0038] Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in the second direction. The fourth chip combinations and the fifth chip combinations include the silicon-based power chip and the diode arranged in the first direction, and the silicon-based power chip and the diode chip are arranged in opposite directions in the fourth chip combinations and the fifth chip combinations.

[0039] In some embodiments, the hybrid power module includes:

[0040] An upper bridge driving layer located on the substrate, the upper bridge driving layer including a first gate driving layer and a first emitter driving layer;

[0041] The gate of each wide bandgap power chip in the first wide bandgap chipset is connected to the first gate driving layer, and the source of each wide bandgap power chip in the first wide bandgap chipset is connected to the first source driving layer.

[0042] In some embodiments, the upper bridge chipset further includes a second gate driving layer and a first emitter driving layer, wherein the gate of each silicon-based power chip in the first silicon-based chipset is connected to the second gate driving layer, and the emitter of each silicon-based power chip in the first silicon-based chipset is connected to the first emitter driving layer.

[0043] In some embodiments, the hybrid power module includes:

[0044] A lower bridge driving layer located on the substrate, the lower bridge driving layer including a third gate driving layer and a second emitter driving layer;

[0045] The gate of each wide bandgap power chip in the second wide bandgap chipset is connected to the third gate driving layer, and the source of each wide bandgap power chip in the second wide bandgap chipset is connected to the second source driving layer.

[0046] In some embodiments, the downbridge chipset further includes a fourth gate driving layer and a second emitter driving layer, wherein the gate of each silicon-based power chip in the second silicon-based chipset is connected to the fourth gate driving layer, and the emitter of each silicon-based power chip in the second silicon-based chipset is connected to the second emitter driving layer.

[0047] In some embodiments, the first source driving layer and the first emitter driving layer are the same driving layer.

[0048] In some embodiments, the hybrid power module includes:

[0049] A first gate driving terminal is disposed in the first gate driving layer, a second gate driving terminal is disposed in the second gate driving layer, a first source driving terminal is disposed in the first source driving layer, and a first emitter driving terminal is disposed in the first emitter driving layer.

[0050] In some embodiments, the second source driving layer and the second emitter driving layer are the same driving layer.

[0051] In some embodiments, at least one of the first gate driving terminal, the second gate driving terminal, the first source driving terminal, and the first emitter driving terminal is led out perpendicularly to the substrate.

[0052] In some embodiments, the hybrid power module includes:

[0053] The third gate driving terminal is disposed in the third gate driving layer, the fourth gate driving terminal is disposed in the fourth gate driving layer, the second source driving terminal is disposed in the second source driving layer, and the second emitter driving terminal is disposed in the second emitter driving layer.

[0054] In some embodiments, at least one of the third gate driving terminal, the fourth gate driving terminal, the second source driving terminal, and the second emitter driving terminal is led out perpendicularly to the substrate.

[0055] In some embodiments, the hybrid power module includes:

[0056] Two interconnected first source driving layers, at least one of the source driving layers is provided with multiple driving resistors;

[0057] The first end of each of the driving resistors is interconnected and connected to the first gate driving layer, and the second end of each of the driving resistors is connected to the gate of one of the first wide bandgap power chips in the first wide bandgap chipset.

[0058] In some embodiments, the hybrid power module includes:

[0059] Two interconnected second source driving layers, at least one of which has multiple driving resistors; the first end of each driving resistor is interconnected and connected to the third gate driving layer, and the second end of each driving resistor is connected to the gate of one of the wide bandgap power chips in the second wide bandgap chipset.

[0060] In some embodiments, the first wide bandgap chipset includes a plurality of wide bandgap power chips;

[0061] The hybrid power module includes an AC connection terminal located on the AC connection layer, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the AC connection terminal is the same.

[0062] In some embodiments, at least a portion of the structure of the AC connection layer, which is spaced and embedded in the first DC connection layer, includes an AC connection terminal, and the current path length between each wide bandgap power chip in the first wide bandgap chipset and the AC connection terminal is the same.

[0063] In some embodiments, the second DC connection layer is further provided with a second DC connection terminal, which is led out along a first direction.

[0064] In some embodiments, the first DC connection layer is further provided with a first DC connection terminal, which is led out along a first direction.

[0065] In some embodiments, the AC connection layer is further provided with AC connection terminals, which are led out along a first direction.

[0066] In some embodiments, at least one of the first DC connection layer, the second DC connection layer, and the AC connection layer is a copper layer.

[0067] In some embodiments, the wide bandgap power chip includes a silicon carbide metal-oxide-semiconductor field-effect transistor or a gallium nitride high electron mobility transistor.

[0068] In some embodiments, the silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor;

[0069] The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

[0070] Secondly, this application provides a multiphase full-bridge hybrid module, including at least two of the above-mentioned hybrid power modules.

[0071] Thirdly, this application provides a power conversion device including at least one of the above-described hybrid power modules.

[0072] Fourthly, this application provides a vehicle including the aforementioned power conversion device.

[0073] The hybrid power module, multiphase full-bridge hybrid module, power conversion device, and vehicle provided in this application include: a substrate; a first DC connection layer, a second DC connection layer, and an AC connection layer located on the substrate; an upper bridge chipset located on the first DC connection layer, and a lower bridge chipset located on the AC connection layer. The upper bridge chipset includes a first wide bandgap chipset, and the lower bridge chipset includes a second wide bandgap chipset. The first wide bandgap chipset is connected to the AC connection layer, and the second wide bandgap chipset is connected to the second DC connection layer. This reduces manufacturing processes and improves space utilization by forming a half-bridge hybrid power module on a single substrate. Furthermore, the first and second wide bandgap chipsets are arranged along a second direction, and both include multiple wide bandgap power chips arranged along the second direction, forming a relatively regular arrangement and further improving space utilization. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 A schematic diagram of the layout of a hybrid power module provided in an embodiment of this application;

[0076] Figure 2 A schematic diagram of the layout of a hybrid power module provided in an embodiment of this application;

[0077] Figure 3 A schematic diagram of the layout and wiring of a hybrid power module provided in an embodiment of this application;

[0078] Figure 4 This is a schematic diagram of the structure of a wide bandgap power chip provided in an embodiment of this application;

[0079] Figure 5 This is a schematic diagram of the current path of a wide bandgap chipset provided in an embodiment of this application;

[0080] Figure 6 A schematic diagram of the equivalent circuit and switching waveforms of a hybrid power module provided in an embodiment of this application;

[0081] Figure 7 This is a schematic diagram of the layout of a wide bandgap chipset provided in an embodiment of this application;

[0082] Figure 8 A layout schematic diagram of a hybrid power module provided for another embodiment of this application;

[0083] Figure 9 This is a schematic diagram of the layout of a silicon-based chipset provided in an embodiment of this application;

[0084] Figure 10 A schematic diagram of the layout of another hybrid power module provided in an embodiment of this application;

[0085] Figure 11 This is a schematic diagram of the drive circuit and drive terminal connection provided in an embodiment of this application;

[0086] Figure 12 A layout schematic diagram of a hybrid power module provided in another embodiment of this application;

[0087] Figure 13 This is a schematic diagram of a multiphase hybrid power module provided in an embodiment of this application. Detailed Implementation

[0088] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0089] In various fields such as automobiles and power systems, reducing power losses in power conversion devices such as inverters and frequency converters is crucial, and power semiconductor devices in these devices play a vital role. However, the performance of traditional silicon-based power semiconductor devices is insufficient to meet current demands for power switching devices in terms of blocking voltage, on-state current, operating frequency, high temperature, and high efficiency.

[0090] Silicon-based fully controllable power semiconductor devices, represented by silicon-insulated-gate bipolar transistors (SiIGBTs), possess excellent performance characteristics such as simple control circuits, high voltage resistance, and high current handling capacity, and are widely used in power conversion devices such as inverters and frequency converters. However, when silicon-based fully controllable power semiconductor devices, represented by SiIGBTs, turn off, the collector current decays slowly, i.e., a significant tail current. This tail current is amplified by switching losses, especially when used as a high-frequency switch.

[0091] Wide bandgap semiconductor materials, such as silicon carbide, possess excellent physical properties including a large bandgap, high saturated electron drift rate, and high thermal conductivity. These properties can significantly reduce losses in power conversion devices such as inverters and frequency converters, thereby improving conversion efficiency. However, wide bandgap semiconductor power devices, represented by silicon carbide, are relatively expensive.

[0092] Therefore, wide-bandgap semiconductor power devices and silicon-based fully controllable power semiconductor devices can be connected in parallel to form a hybrid power module. The wide-bandgap semiconductor power devices control the switching of the hybrid power module, while the silicon-based fully controllable power semiconductor devices bear the main conduction current, thereby combining the advantages of the two types of devices to reduce switching losses and costs.

[0093] Currently, a half-bridge hybrid power module is mainly composed of multiple different substrates (e.g., ceramic substrates). Different substrates are used to carry different devices. For example, the first substrate carries a wide-bandgap semiconductor power device for the upper bridge, the second substrate carries a silicon-based fully controllable power semiconductor device for the upper bridge, the third substrate carries a wide-bandgap semiconductor power device for the lower bridge, and the fourth substrate carries a silicon-based fully controllable power semiconductor device for the lower bridge. These different substrates need to be interconnected to form the half-bridge hybrid power module, which results in numerous manufacturing steps and low space utilization.

[0094] To address this, this application proposes a hybrid power module. A first DC-DC interconnect layer, a second DC-DC interconnect layer, and an AC interconnect layer are formed on a substrate. An upper-bridge chipset is formed on the first DC-DC interconnect layer, and a lower-bridge chipset is formed on the AC interconnect layer, thereby reducing manufacturing processes and improving space utilization. Furthermore, the wide-bandgap chipsets in both the upper-bridge and lower-bridge chipsets are arranged along a second direction. Both the first and second wide-bandgap chipsets include multiple wide-bandgap power chips arranged along the second direction, forming a more regular arrangement and further improving space utilization.

[0095] The technical solutions of this application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0096] Figure 1 A schematic diagram of a hybrid power module according to an embodiment of this application is shown. Figure 1 As shown, the hybrid power module in this embodiment may include:

[0097] A substrate 20; a first DC-DC interconnect layer 21, a second DC-DC interconnect layer 23, and an AC-DC interconnect layer 22 located on the substrate 20; and an upper-bridge chip assembly 31 located on the first DC-DC interconnect layer 21 and a lower-bridge chip assembly 32 located on the AC-DC interconnect layer 22. The upper-bridge chip assembly 31 includes a first wide-bandgap chip assembly 301, and the lower-bridge chip assembly 32 includes a second wide-bandgap chip assembly 303. The first wide-bandgap chip assembly 301 is connected to the AC-DC interconnect layer 22, and the second wide-bandgap chip assembly 303 is connected to the second DC-DC interconnect layer 23. The first wide-bandgap chip assembly 301 and the second wide-bandgap chip assembly 303 are arranged along a second direction, and both the first wide-bandgap chip assembly 301 and the second wide-bandgap chip assembly 303 include a plurality of wide-bandgap power chips 11 arranged along the second direction.

[0098] In this embodiment, substrate 20 is used to support the interconnect layer and the chipset. By forming the interconnect layer and the chipset on a single substrate, the problem of excessive manufacturing processes caused by the need for interconnection between multiple substrates is solved, reducing the number of manufacturing processes. Furthermore, forming the chipset and the interconnect layer on a single substrate allows for improved space utilization by rationally positioning the chipset and the interconnect layer on the substrate. In addition, in this embodiment, the wide bandgap chipset in the upper bridge chipset 31 and the wide bandgap chipset in the lower bridge chipset 32 ​​are arranged along a second direction. Both the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include multiple wide bandgap power chips 11 arranged in the second direction, forming a relatively regular arrangement, further improving space utilization.

[0099] For example, substrate 20 may include a ceramic substrate, such as an alumina substrate, a silicon nitride substrate, a zirconia substrate, etc.

[0100] In some embodiments, combined with Figure 2 and Figure 3 As shown, the upper bridge chipset 31 also includes a first silicon-based chipset 302, which controls the upper bridge chipset 31 to be turned on or off via the first wide bandgap chipset 301 and the first silicon-based chipset 302. The lower bridge chipset 32 ​​also includes a second silicon-based chipset 304, which controls the lower bridge chipset 32 ​​to be turned on or off via the second wide bandgap chipset 303 and the second silicon-based chipset 304.

[0101] Power device losses are categorized into switching losses and conduction losses. Switching losses are the losses incurred during the instant the power device switches on, while conduction losses are the losses that occur over a prolonged period after the device completes the switching process. Switching losses further include turn-on losses and turn-off losses. Turn-on losses are the losses incurred during the instant the power device turns on, and turn-off losses are the losses incurred during the instant the power device turns off. Wide-bandgap chipsets handle the switching action and bear the switching losses, while silicon-based chipsets handle the conduction current. Because wide-bandgap power chips have lower switching losses and silicon-based power chips have lower costs, the goal of reducing switching losses and costs can be achieved.

[0102] For example, a first wide bandgap chipset 301 and a first silicon-based chipset 302 are located on a first DC connection layer 21, and the first DC connection layer 21 can be used to connect to the positive terminal of a power supply, thereby allowing the first wide bandgap chipset 301 and the first silicon-based chipset 302 to be connected to the positive terminal of the power supply. A second wide bandgap chipset 303 and a second silicon-based chipset 304 are connected to a second DC connection layer 23, and the second DC connection layer 23 can be used to connect to the negative terminal of the power supply, thereby allowing the lower bridge chipset 32 ​​to be connected to the negative terminal of the power supply. The first wide bandgap chipset 301 and the first silicon-based chipset 302 are connected to an AC connection layer 22, and the second wide bandgap chipset 303 and the second silicon-based chipset 304 are located on the AC connection layer 22, and the AC connection layer 22 is used to connect to a load, thereby allowing the upper bridge chipset 31 and the lower bridge chipset 32 ​​to be connected to the load.

[0103] For example, the second wide bandgap chipset 303 and the second silicon-based chipset 304 can be connected to the second DC connection layer 23 by bonding wires, and the first wide bandgap chipset 301 and the first silicon-based chipset 302 can be connected to the AC connection layer 22 by bonding wires, or other connection wires.

[0104] In practical applications, at least one of the first DC connection layer 21, the second DC connection layer 23, and the AC connection layer 22 is a copper layer. For example, the first DC connection layer 21 can be a positive DC copper layer, the second DC connection layer 23 can be a negative DC copper layer, and the AC connection layer 22 can be an AC copper layer.

[0105] Considering that the parallel connection of power devices can share the power, enabling the device to withstand greater power and output greater current, the first wide bandgap chipset 301 and the second wide bandgap chipset 303 include a plurality of wide bandgap power chips 11 arranged in the second direction.

[0106] In some embodiments, the plurality of wide bandgap power chips 11 in the first wide bandgap chipset 301 are connected in parallel. Specifically, the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 are all located on the AC connection layer 23 and connected to the second DC connection layer 23, thereby realizing the parallel connection of the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303. For example, each wide bandgap power chip 11 in the second wide bandgap chipset 303 can be connected to the second DC connection layer 23 via bonding wires.

[0107] Multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are connected in parallel. Specifically, the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 303 are located on the first DC connection layer 21 and connected to the AC connection layer 22, thereby realizing the parallel connection of the multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301. For example, each wide-bandgap power chip 11 in the first wide-bandgap chipset 303 can be connected to the AC connection layer 22 via bonding wires.

[0108] Furthermore, the second wide bandgap chipset 303 is connected in series with the wide bandgap power chips 11 in the first wide bandgap chipset 301. The corresponding two wide bandgap power chips 11 can form a half-bridge circuit. Moreover, since multiple half-bridge circuits are connected in parallel, a half-bridge circuit with a current specification amplification of N times (the number of half-bridge circuits is N) can be formed, which is beneficial to improving the power level of the half-bridge power module.

[0109] In practical applications, wide bandgap power chips can include silicon carbide metal oxide semiconductor field effect transistors (SiCMOSFETs) or gallium nitride high electron mobility transistors (GaN HEMTs).

[0110] Figure 4 Figure (A) shows a schematic diagram of the structure of a wide bandgap power chip 11. The surface electrodes of the wide bandgap power chip 11 include a source 111, a gate 112, and a drain 113 located at the bottom. Correspondingly, the drain 113 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 is attached to the AC connection layer 22, and the source 111 of the wide bandgap power chip 11 in the second wide bandgap chip group 303 is connected to the second DC connection layer 23. The drain of the wide bandgap power chip 11 in the first wide bandgap chip group 301 is attached to the first DC connection layer 21, and the source of the wide bandgap power chip 11 in the first wide bandgap chip group 301 is connected to the AC connection layer 22.

[0111] In some embodiments, the first silicon-based chipset 302 includes a plurality of silicon-based power chips 12, thereby enabling the upper bridge chipset 31 to output a larger current. Specifically, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are connected in parallel. All of the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 are located on the first DC connection layer 21, and are connected to the AC connection layer 22, thus realizing the parallel connection of the plurality of silicon-based power chips 12 in the first silicon-based chipset 302. For example, the plurality of silicon-based power chips 12 in the first silicon-based chipset 302 can be connected to the AC connection layer 22 via bonding wires.

[0112] The second silicon-based chipset 304 includes multiple silicon-based power chips 12, enabling the lower-bridge chipset 32 ​​to output a larger current. Specifically, the multiple silicon-based power chips 12 in the second silicon-based chipset 304 are connected in parallel. All of the multiple silicon-based power chips 12 in the second silicon-based chipset 304 are located on the AC connection layer 22, and are connected to the second DC connection layer 23, thus achieving parallel connection of the multiple silicon-based power chips 12 in the second silicon-based chipset 304. For example, the multiple silicon-based power chips 12 in the second silicon-based chipset 304 can be connected to the second DC connection layer 23 via bonding wires.

[0113] Furthermore, the silicon-based power chip 12 in each of the first silicon-based chipsets 302 is connected in series with the silicon-based power chip 12 in the second silicon-based chipset 304 to form a half-bridge structure.

[0114] In some embodiments, considering that the dynamic current sharing of the wide-bandgap power chips 11 in the second wide-bandgap chipset 303 is mainly affected by the current path, when the hybrid power module includes a second DC connection terminal 42 located on the second DC connection layer 23, the current path length between each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same, thereby enabling the multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 303 to achieve a current sharing effect. The second DC connection terminal 42 is used to connect to external circuits, such as connecting to the negative terminal of a power supply.

[0115] In other embodiments, the first wide bandgap chipset 301 includes a plurality of wide bandgap power chips 11, and the hybrid power module includes an AC connection terminal 43. The current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, so that the wide bandgap power chips 11 in the first wide bandgap chipset 301 achieve a current sharing effect.

[0116] In some other embodiments, the hybrid power module includes a first DC connection terminal 41 located on a first DC connection layer 21. The current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the first DC connection terminal 41 is the same, further improving the current sharing effect of the wide bandgap power chips 11 in the first wide bandgap chipset 301.

[0117] It should be noted that the second DC connection terminal 42 and the AC connection terminal 43 constitute a single area. The second DC connection terminal 42 is the connection area for each wide-bandgap power chip 11 in the second wide-bandgap chipset 301, and the AC connection terminal 43 is the connection area for each wide-bandgap power chip 11 in the first wide-bandgap chipset 301. The size and length of the second DC connection terminal 42 and the AC connection terminal 43 will affect the current path length. The current path length between each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same. This can mean that the shortest current path length between the source of each wide-bandgap power chip 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is the same. This "same" can be approximately the same; for example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the second wide-bandgap chipset 303 and the second DC connection terminal 42 is within a preset difference range. The current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the AC connection terminal 42 is the same. This can mean that the shortest current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the AC connection terminal 43 is the same. For example, the difference between the current path lengths between any two wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the AC connection terminal 43 is within a preset difference range. The preset difference range can be determined according to the actual situation and is not limited here.

[0118] Similarly, the first DC connection terminal 41 is a region that is the connection area for each wide-bandgap power chip 11 in the first wide-bandgap chipset 301. The current path length between each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is the same, which can mean that the shortest current path length between the drain of each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is the same. This "same" can be approximately the same; for example, the difference between the current path lengths of any two wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the first DC connection terminal 41 is within a preset difference range.

[0119] As one implementation, the second DC connection layer 23 is also provided with a second DC connection terminal, which is led out along the first direction to connect to an external load.

[0120] As one implementation, the first DC connection layer 21 is also provided with a first DC connection terminal, which is led out along a first direction to connect to an external power source.

[0121] As one implementation, the AC connection layer 22 is also provided with AC connection terminals, which are led out along a first direction to connect to an external power source.

[0122] It is understandable that when multiple wide-bandgap power chips 11 are arranged in one direction, and the direction of the current after the multiple wide-bandgap power chips 11 are combined is perpendicular or nearly perpendicular to the arrangement direction of the multiple wide-bandgap power chips 11, such as Figure 5 As shown in (A), each wide bandgap power chip 11 has a current path of approximately the same length, i.e., approximately the same current path length, thus achieving good dynamic current sharing performance. When multiple wide bandgap power chips 11 are arranged in one direction, and the current direction after the multiple wide bandgap power chips 11 converge is parallel to the arrangement direction of the multiple wide bandgap power chips 11, as shown in (A), each wide bandgap power chip 11 has a current path of approximately the same length, thus achieving good dynamic current sharing performance. Figure 5 As shown in (B), each wide bandgap power chip 11 has a current path of different lengths, which can cause dynamic uneven current.

[0123] Therefore, in some examples, the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged along the second direction so that the current path length between the plurality of wide bandgap power chips 11 in the second wide bandgap chipset 303 and the second DC connection terminal 42 is the same.

[0124] In other examples, multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are arranged along the second direction to make the current path of each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 as similar as possible, thereby improving the current sharing effect of the first wide-bandgap power chipset 301.

[0125] In some examples, the second silicon-based chipset 304 may also include multiple diode chips 13, with a one-to-one correspondence between the silicon-based power chip 12 and the diode chip 13. Specifically, each diode chip 13 is connected in parallel with one silicon-based power chip 12 in the second silicon-based chipset 304 to undertake reverse current freewheeling, thereby improving the overall reverse current freewheeling capability of the module.

[0126] In other examples, the first silicon-based chipset 302 may also include multiple diode chips 13, with a one-to-one correspondence between the silicon-based power chip 12 and the diode chip 13. Specifically, each diode chip 13 is connected in parallel with one silicon-based power chip 12 in the first silicon-based chipset 302 to undertake reverse current flow and improve the overall reverse current flow capability of the module.

[0127] Furthermore, the multiple diode chips 13 in the first silicon-based chipset 302 are connected in series with the multiple diode chips in the second silicon-based chipset 304, respectively, to undertake reverse freewheeling current in the upper bridge and the lower bridge.

[0128] In practical applications, the silicon-based power chip 12 may include a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field effect transistor (Si MOSFET).

[0129] The diode chip 13 can be a silicon fast recovery diode (SiRFD) or a silicon carbide Schottky barrier diode (SiCSBD).

[0130] Figure 4 Figure (B) shows a schematic diagram of a silicon-based power chip. The surface electrodes of the silicon-based power chip 12 include an emitter 121, a gate 122, and a collector 123 located at the bottom. Correspondingly, the collector of the silicon-based power chip 12 in the second silicon-based chip group 304 is bonded to the AC connection layer 22, and the emitter of the silicon-based power chip 12 in the second silicon-based chip group 304 is bonded to the second DC connection layer 23. The collector of the silicon-based power chip 12 in the first silicon-based chip group 302 is bonded to the first DC connection layer 21, and the emitter of the silicon-based power chip 12 in the first silicon-based chip group 302 is bonded to the AC connection layer 22.

[0131] Figure 4 Figure (C) shows a schematic diagram of a diode chip structure. The diode chip 13 includes an anode 131 at the top and a cathode 132 at the bottom. Accordingly, the cathode of the diode chip 13 in the second silicon-based chipset 304 is bonded to an AC connection layer 22, and the anode of the diode chip 13 in the second silicon-based chipset 304 is bonded to a second DC connection layer 23. The cathode of the diode chip 13 in the first silicon-based chipset 302 is bonded to a first DC connection layer 21, and the anode of the diode chip 13 in the first silicon-based chipset 302 is bonded to an AC connection layer 22.

[0132] To better understand the impact of DC connection location on the commutation circuit of wide-bandgap power chips, the following explanation uses the equivalent circuit of a hybrid power module considering parasitic inductance as an example. Figure 6As shown, the wide bandgap power chip 11 is turned on first, at which point the voltage drops and the wide bandgap power chip 11 carries the entire current. Then the silicon-based power chip 12 is turned on, and the wide bandgap power chip 11 and the silicon-based power chip 12 commutate. Finally, the wide bandgap power chip 11 and the silicon-based power chip 12 each carry a portion of the current. During the turn-off process, the wide bandgap power chip 11 is turned off first. At this time, the silicon-based power chip 12 and the wide bandgap power chip 11 commutate. After the wide bandgap power chip 11 carries the entire current, it turns off, at which point the voltage rises and a turn-off voltage spike appears.

[0133] Because the wide-bandgap power chip 11 has a faster switching speed than the silicon-based power chip 12, the voltage spike generated by the wide-bandgap power chip 11 under the same inductance is much higher than that generated by the silicon-based power chip 12. Therefore, the turn-off spike caused by parasitic inductance in the switching commutation circuit of the wide-bandgap power chip 11 is more severe. Reducing the commutation circuit length of the wide-bandgap power chip 11 is the main problem.

[0134] Therefore, in some examples, on the second DC connection layer 23, the second DC connection terminal 42 is located close to the second wide bandgap chipset 303, that is, on the side of the second wide bandgap chipset 303 away from the second silicon-based chipset 304, so that the second DC connection terminal 42 is close to the second wide bandgap chipset 303, reducing the commutation loop length of the second wide bandgap chipset 303, reducing the parasitic inductance in the commutation loop, and thus reducing the voltage turn-off spike generated by the wide bandgap power chip 11.

[0135] In other examples, the hybrid power module includes a first DC connection terminal 41 located on a first DC connection layer and on the side of the first wide bandgap chipset 301 away from the first silicon-based chipset 302, thereby reducing the commutation loop length of the first wide bandgap chipset 301, reducing the parasitic inductance in the commutation loop, and thus reducing the voltage turn-off spike generated by the wide bandgap power chip 11.

[0136] In the above examples, the arrangement of the plurality of wide-bandgap power chips 11 in the first wide-bandgap chipset 301 and the plurality of wide-bandgap power chips 11 in the second wide-bandgap chipset 303 includes at least one of the following:

[0137] Each wide bandgap power chip 11 is aligned in the second direction; adjacent wide bandgap power chips 11 are staggered in the first direction.

[0138] Each wide-bandgap power chip is staggered in the first direction;

[0139] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0140] like Figure 7 As shown in (A), each wide bandgap power chip 11 is arranged sequentially and neatly along the second direction, with bonding wires connected to the corresponding interconnect layer along the first direction. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chip group 301 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC interconnect layer 22 along the first direction; similarly, when multiple wide bandgap power chips 11 in the second wide bandgap chip group 303 are arranged sequentially and neatly along the second direction, the bonding wires of each wide bandgap power chip 11 are connected to the AC interconnect layer 22 along the first direction. This arrangement is more compact and helps to improve space utilization.

[0141] like Figure 7 As shown in (B), each wide bandgap power chip 11 is arranged sequentially in the second direction, and adjacent wide bandgap power chips 11 are staggered in the first direction, with bonding wires connected to the corresponding interconnect layers along the first direction. This arrangement is optimized for heat dissipation, which can further reduce thermal coupling and improve heat dissipation performance.

[0142] like Figure 7 In (C), each wide bandgap power chip 11 is arranged sequentially in the second direction, and each wide bandgap power chip 11 is staggered in the first direction, with bonding wires connected to the corresponding interconnect layer along the first direction. This arrangement is optimized for current sharing and heat dissipation. It can adjust the source current path of different wide bandgap power chips 11, improve current sharing performance, and at the same time reduce thermal coupling and improve heat dissipation performance.

[0143] In practical applications, different wide-bandgap power chip arrangement methods can be flexibly selected according to requirements to meet different performance needs.

[0144] For example, such as Figure 8 As shown, when multiple wide-bandgap power chips 11 in the first wide-bandgap chipset 301 are arranged in the second direction, each wide-bandgap power chip 11 in the first wide-bandgap chipset 301 can be staggered in the first direction to improve the current sharing performance of the first wide-bandgap chipset 301 and to have better heat dissipation performance. When multiple wide-bandgap power chips 11 in the second wide-bandgap chipset 303 are arranged in the second direction, adjacent wide-bandgap power chips 11 in the second wide-bandgap chipset 303 can be staggered in the first direction to give the second wide-bandgap chipset 303 better heat dissipation performance.

[0145] In some embodiments, combined with Figure 3 and Figure 9As shown, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset 302, and the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset 304, can each include at least one of the following:

[0146] Multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a cross pattern in the first direction;

[0147] The first chip assembly and the second chip assembly are arranged in a first direction. The first chip assembly includes a plurality of silicon-based power chips 12 arranged in the first direction, and the second chip assembly includes a plurality of diode chips arranged in the first direction.

[0148] Multiple third chip assemblies are arranged in the first direction, and the third chip assemblies include silicon-based power chips 12 and diode chips 13 arranged in the second direction;

[0149] Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in a first direction. The fourth chip combinations and fifth chip combinations include silicon-based power chips 12 and diode chips 13 arranged in a second direction. In the fourth chip combinations and fifth chip combinations, the silicon-based power chips 12 and diode chips 13 are arranged in opposite directions.

[0150] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0151] like Figure 9 In (A) of the second chip assembly, multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a crisscross pattern in a first direction, with bonding wires connected to corresponding interconnect layers along a second direction. For example, in the first silicon-based chip assembly 302, the bonding wires of the silicon-based power chips 12 and diode chips 13 are connected to the AC interconnect layer 22 along the second direction; similarly, in the second silicon-based chip assembly 304, the bonding wires of the silicon-based power chips 12 and diode chips 13 are connected to the second DC interconnect layer 23 along the second direction. This arrangement provides high heat dissipation performance and a smaller dimension along the second direction.

[0152] like Figure 9 As shown in (B), the first chip assembly and the second chip assembly are arranged sequentially in the first direction. The first chip assembly includes a plurality of silicon-based power chips 12 arranged sequentially in the first direction, and the second chip assembly includes a plurality of diode chips 13 arranged sequentially in the first direction. In this arrangement, chips of the same type are adjacent to each other, and the bonding wires are connected to the corresponding connection layers along the second direction, which facilitates the connection of the bonding wires and results in a smaller size along the second direction.

[0153] like Figure 9As shown in (C), multiple third chip assemblies are arranged sequentially in the first direction, and the second chip assembly includes silicon-based power chips 12 and diode chips 13 arranged sequentially in the second direction. In this arrangement, a silicon-based power chip 12 and a diode chip 13 form a pair, and multiple pairs of chips are arranged along the first direction, so that chips of the same type are adjacent along the first direction. The bonding wires are connected to the corresponding connection layers along the second direction. The size along the first direction is small, and it is convenient to drive the bonding wire connection.

[0154] like Figure 9 As shown in (D), multiple fourth chip assemblies and multiple fifth chip assemblies are arranged alternately in the first direction. The combination of silicon-based power chips 12 and diode chips 13 in the fourth chip assemblies differs from that in the fifth chip assemblies. Multiple pairs of chips are arranged along the wide-bandgap power chip 11, ensuring that chips of the same type are not adjacent to each other. Bonding lines are connected to the corresponding interconnect layers along the second direction. This arrangement results in a smaller dimension along the first direction and better heat dissipation.

[0155] In practical applications, different arrangements of silicon-based power chips 12 and diode chips 13 can be flexibly selected according to requirements. For example, due to the slower switching speed of silicon-based power chips 12, the impact of parasitic inductance is relatively small. However, due to the lower thermal conductivity and larger size of silicon-based power chips 12, the layout can be mainly considered from the perspectives of heat dissipation and size.

[0156] As an implementation method, combined Figure 2 and Figure 3 As shown, the AC connection layer 22 may include two parts, a first part and a second part connected to each other. The first part extends in a first direction and the second part extends in a second direction. At this time, the first wide bandgap chip group 301 and the first silicon-based chip group 302 are located on both sides of the second part, thereby reducing the length of the bonding line between the first wide bandgap chip group 301 and the AC connection layer 22.

[0157] In some embodiments, such as Figure 10 As shown, the first DC connection layer 21 includes a first connection layer 211 and a second connection layer 212 that are electrically connected to each other. The first wide bandgap chipset 301 is located on the first connection layer 211, and the first silicon-based chipset 302 is located on the second connection layer 312 to suit different scenario requirements.

[0158] In some examples, a first DC connection terminal 41 is formed on both the first connection layer 211 and the second connection layer 212, thereby enabling the first wide bandgap chipset 301 on the first connection layer 211 and the first silicon-based chipset 302 on the second connection layer 212 to receive external voltages, such as positive voltage. A second DC connection terminal 42 is formed on the second DC connection layer 23, thereby enabling the second wide bandgap chipset 303 and the second silicon-based chipset 304 on the AC connection layer 22 to receive external voltages, such as negative voltage.

[0159] As one implementation method, such as Figure 10 As shown, a recess is formed between the first connection layer 211 and the second connection layer 212 to accommodate a portion of the protruding structure of the AC connection layer 22. At least a portion of the protruding structure is spaced apart from the first DC connection layer 21 and is used to electrically connect multiple wide bandgap power chips 11 in the first wide bandgap chipset 301, thereby reducing the length of the bonding lines between the second wide bandgap chipset 303 and the second silicon-based chipset 304 and the second DC connection layer 23.

[0160] For example, the second DC interconnect layer 23 can be located between the first interconnect layer 211 and the second interconnect layer 212, that is, the first interconnect layer 211 and the second interconnect layer 212 are located on both sides of the second DC interconnect layer 23, and the second DC interconnect layer 23 extends in the second direction. At this time, the second wide bandgap chip group 303 and the second silicon-based chip group 304 are located on both sides of the second DC interconnect layer 23, thereby reducing the length of the bonding line between the second wide bandgap chip group 303 and the second silicon-based chip group 304 and the second DC interconnect layer 23.

[0161] like Figure 10 As shown, a first portion of the AC interconnect layer 22 extends between the first interconnect layer 211 and the second DC interconnect layer 23, thereby reducing the length of the bonding wire between the first wide bandgap chipset 301 and the AC interconnect layer 22. A second portion of the AC interconnect layer 22 extends between the second DC interconnect layer 23 and the second interconnect layer 212 to reduce the length of the bonding wire between the first silicon-based chipset 302 and the AC interconnect layer 22.

[0162] In some examples, such as Figure 10 As shown, the first wide bandgap power chip 301 and the second wide bandgap chip group 302 both include multiple wide bandgap power chips 11. Each wide bandgap power chip 11 is arranged along the second direction to form a more regular arrangement and improve space utilization.

[0163] As one implementation, the arrangement of the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the first silicon-based chipset 302, and the plurality of silicon-based power chips 12 and the plurality of diode chips 13 in the second silicon-based chipset 304, can each include at least one of the following:

[0164] Multiple silicon-based power chips 12 and multiple diode chips 13 are arranged in a cross pattern in the second direction;

[0165] The first chip assembly and the second chip assembly are arranged in a second direction. The first chip assembly includes a plurality of silicon-based power chips 12 arranged in the second direction, and the second chip assembly includes a plurality of diode chips 13 arranged in the second direction.

[0166] Multiple third chip assemblies are arranged in the second direction, and the third chip assemblies include silicon-based power chips 12 and diode chips 13 arranged in the first direction;

[0167] Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in the second direction. The fourth chip combinations and fifth chip combinations include silicon-based power chips 12 and diode chips 13 arranged in the first direction, and the silicon-based power chips 12 and diode chips 13 are arranged in opposite directions in the fourth chip combinations and fifth chip combinations.

[0168] The first direction and the second direction are two mutually perpendicular directions on a plane.

[0169] In some embodiments, combined with Figure 3 and Figure 11 As shown in (B), the hybrid power module includes an upper bridge driving layer 24 located on the substrate 20. The upper bridge driving layer 24 includes a first gate driving layer 241 and a first source driving layer 243. For example, the first gate driving layer 241 and the first source driving layer 243 may be copper layers.

[0170] The gate of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first gate driving layer 241, and the source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first source driving layer 243. This allows control of the voltage difference between the gate and source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301, thereby controlling whether the wide-bandgap power chip 11 is in an on or off state. For example, the gate of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first gate driving layer 241 via a bonding wire, and the source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 is connected to the first source driving layer 243 via a bonding wire.

[0171] In some embodiments, the upper bridge driving layer 24 further includes a second gate driving layer 242 and a first emitter driving layer 244. For example, the second gate driving layer 242 and the first emitter driving layer 244 may be copper layers.

[0172] The gate of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the second gate driving layer 242, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the first emitter driving layer 244. This allows control of the voltage difference between the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset 302, thereby controlling whether the silicon-based power chip 12 in the first silicon-based chipset 302 is in an on or off state. For example, the gate of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the second gate driving layer 242 via a bonding wire, and the emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 is connected to the first emitter driving layer 244 via a bonding wire. For example, when multiple wide bandgap power chips 11 in the first wide bandgap chipset 301 are arranged in the second direction, and each wide bandgap power chip 11 in the first wide bandgap chipset 301 is staggered in the first direction, the first gate driving layer 241 and the first source driving layer 243 can be disposed on the side of the first wide bandgap chipset 301 near the first DC connection terminal 41, thereby shortening the bonding line between the first wide bandgap chipset 301 and the driving layer, as well as shortening the bonding line between the first wide bandgap chipset 301 and the AC connection layer 22.

[0173] Combination Figure 3 and Figure 11 As shown in (A), the first source driving layer 243 and the first emitter driving layer 244 can be the same driving layer, which shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0174] In some examples, combined Figure 3 and Figure 11 As shown, a first gate driving terminal 441 is formed in the first gate driving layer 241, a second gate driving layer 242 terminal is formed in the second gate driving layer 242, a first source driving terminal 443 is formed in the first source driving layer 243, and a first emitter driving terminal 444 is formed in the first emitter driving layer 244. External circuitry is connected via the first gate driving terminal 441 and the first source driving terminal 443, enabling the gate and source of the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 to receive external voltage, thereby controlling the wide-bandgap power chip 11 in the first wide-bandgap chipset 301 to be in an on or off state. Similarly, external circuitry is connected via the second gate driving terminal 442 and the first emitter driving terminal 444, enabling the gate and emitter of the silicon-based power chip 12 in the first silicon-based chipset 302 to receive external voltage, thereby controlling the silicon-based power chip 12 in the first silicon-based chipset 302 to be in an on or off state.

[0175] For example, when the first source driving layer 243 and the first emitter driving layer 244 are the same driving layer, the first source driving terminal 443 and the first emitter driving terminal 444 are the same driving terminal.

[0176] In one implementation, at least one of the first gate driving terminal 441, the second gate driving terminal 442, the first source driving terminal 443, and the first emitter driving terminal 444 is led out perpendicular to the substrate 20.

[0177] In other embodiments, combined with Figure 3 and Figure 11 As shown, the hybrid power module includes a lower bridge driver layer 25, which includes a third gate driver layer 251 and a second source driver layer 253. For example, the third gate driver layer 251 and the second source driver layer 253 are copper layers.

[0178] The gate of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the third gate driving layer 251, and the source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the second source driving layer 253. This allows control of the voltage difference between the gate and source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303, thereby controlling whether the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is in an on or off state. For example, the gate of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the third gate driving layer 251 via a bonding wire, and the source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 is connected to the second source driving layer 253 via a bonding wire.

[0179] In other embodiments, the lower bridge driving layer 25 further includes a fourth gate driving layer 252 and a second emitter driving layer 254. For example, the fourth gate driving layer 252 and the second emitter driving layer 254 are copper layers. The gate of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the fourth gate driving layer 252, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the second emitter driving layer 254, so that the voltage difference between the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 can be controlled, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 304 to be in an on or off state. For example, the gate of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the fourth gate driving layer 252 via a bonding wire, and the emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 is connected to the second emitter driving layer 254 via a bonding wire.

[0180] For example, when multiple wide bandgap power chips 11 in the second wide bandgap chipset 303 are arranged in the second direction, and adjacent wide bandgap power chips 11 in the first wide bandgap chipset 301 are staggered in the first direction, the third gate driving layer 251 and the second source driving layer 253 can be disposed on one side of the second wide bandgap chipset 303 from the second DC connection terminal 42, thereby shortening the bonding line between the second wide bandgap chipset 303 and the driving layer, as well as shortening the bonding line between the second wide bandgap chipset 303 and the second DC connection layer 23.

[0181] Combining 3 and Figure 11 As shown in (A), the second source driving layer 253 and the second emitter driving layer 254 can be the same driving layer, which further shortens the commutation loop between the wide bandgap power chip 11 and the silicon-based power chip 12 in the hybrid module, reduces the parasitic inductance between the wide bandgap power chip 11 and the silicon-based power chip 12, and reduces the commutation time.

[0182] In some examples, a third gate driving terminal 451 is formed in the third gate driving layer 251, a fourth gate driving terminal 452 is formed in the fourth gate driving layer 252, a second source driving terminal 453 is formed in the second source driving layer 253, and a second emitter driving terminal 454 is formed in the second emitter driving layer 254. External circuitry is connected via the third gate driving terminal 451 and the second source driving terminal 453, enabling the gate and source of the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 to receive external voltage, thereby controlling the wide-bandgap power chip 11 in the second wide-bandgap chipset 303 to be in an on or off state. Similarly, external circuitry is connected via the fourth gate driving terminal 452 and the second emitter driving terminal 454, enabling the gate and emitter of the silicon-based power chip 12 in the second silicon-based chipset 304 to receive external voltage, thereby controlling the silicon-based power chip 12 in the second silicon-based chipset 304 to be in an on or off state.

[0183] For example, when the second source driving layer 253 and the second emitter driving layer 254 are the same driving layer, the second source driving terminal 453 and the second emitter driving terminal 454 are the same driving terminal.

[0184] In one implementation, at least one of the third gate driving terminal 451, the fourth gate driving terminal 452, the second source driving terminal 453, and the second emitter driving terminal 454 is led out perpendicular to the substrate 20.

[0185] In some embodiments, such as Figure 3As shown, at least a portion of the structure of the AC connection layer 22 is embedded in the first DC connection layer 21 at intervals, and is insulated from the first DC connection point 23 to connect the wide bandgap power chip 11 in the first wide bandgap chipset 301, shortening the connection line between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection layer 22. Here, "interval embedding" means that at least a portion of the structure of the AC connection layer 22 is embedded in the first DC connection layer 21, and the at least portion of the structure of the AC connection layer 22 embedded in the first DC connection layer 21 is non-contact and spaced from the first DC connection layer 21 to avoid short circuits. As one implementation method, such as... Figure 3 As shown, the upper bridge driving layer 24 is located on the substrate 20 and between at least a portion of the structure of the AC connection layer 22 embedded in the first DC connection layer 21 and a portion of the structure of the first DC connection layer 21, for example, between the first wide bandgap chipset 301 and the first silicon-based chipset 302, thereby reducing the length of the bonding lines between the first wide bandgap chipset 301 and the first silicon-based chipset 302 and the upper bridge driving layer 24.

[0186] The lower bridge driving layer 25 is located on the substrate 20, between the second wide bandgap chip group 303 and the second silicon-based chip group 304, thereby reducing the length of the bonding line between the second wide bandgap chip group 303, the second silicon-based chip group 304 and the lower bridge driving layer 25.

[0187] As one implementation, at least a portion of the AC connection layer 22 embedded in the first DC connection layer 21 includes an AC connection terminal 43, wherein the current path length between each wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43 is the same, so as to shorten the current path length between the wide bandgap power chip 11 in the first wide bandgap chipset 301 and the AC connection terminal 43, while improving the current sharing effect of the wide bandgap power chip 11 in the first wide bandgap chipset 301.

[0188] In some examples, such as Figure 12 As shown, the hybrid power module includes two interconnected first source drive layers 243, with a plurality of drive resistors 5 formed in at least one first source drive layer 243. The first end of each drive resistor 5 is interconnected and connected to a first gate drive layer 241, and the second end of each drive resistor 5 is connected to the gate of a first chip in a first chipset. The drive resistors 5 can control the switching speed of the first wide bandgap chipset 301, thereby improving the dynamic current sharing performance of the upper bridge. The number of drive resistors 5 can be the same as or different from the number of wide bandgap power chips 11 in the first wide bandgap chipset 301. For example, the two first source drive layers 243 can be connected by bonding wires.

[0189] In other examples, the hybrid power module includes two interconnected second source drive layers 253, with at least one second source drive layer 253 having a plurality of drive resistors formed thereon. The first end of each drive resistor is interconnected and connected to a third gate drive layer 251; the second end of each drive resistor is connected to the gate of a wide-bandgap power chip 11 in a second wide-bandgap chipset 301. The drive resistors can control the switching speed of the second wide-bandgap chipset 303, thereby improving the dynamic current sharing effect of the lower bridge. The number of drive resistors can be the same as or different from the number of wide-bandgap power chips 11 in the second wide-bandgap chipset 303. For example, the two second source drive layers 253 can be connected by bonding wires.

[0190] The above describes the hybrid power module provided in this application. This application also provides a multiphase full-bridge hybrid module, including at least two of the above-described hybrid power modules.

[0191] like Figure 13 As shown, three hybrid power modules are connected together to form a three-phase full-bridge hybrid module. For example, the three hybrid power modules can be connected on the same heat sink 6.

[0192] This application also provides a power conversion device, including at least one of the above-described hybrid power modules.

[0193] This application also provides a vehicle including the aforementioned power conversion device.

[0194] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A hybrid power module, characterized in that, The hybrid power module includes: substrate(20); A first DC connection layer (21), an AC connection layer (22), and a second DC connection layer (23) are located on the substrate (20). And an upper bridge chip group (31) located on the first DC connection layer (21), and a lower bridge chip group (32) on the AC connection layer (22). The upper bridge chip group (31) includes a first wide bandgap chip group (301), and the lower bridge chip group (32) includes a second wide bandgap chip group (303). The first wide bandgap chipset (301) is connected to the AC connection layer (22), and the second wide bandgap chipset (303) is connected to the second DC connection layer (23). The first wide bandgap chipset (301) and the second wide bandgap chipset (303) are arranged along the second direction, and both the first wide bandgap chipset (301) and the second wide bandgap chipset (303) include a plurality of wide bandgap power chips (11) arranged along the second direction. The upper bridge chipset (31) also includes a first silicon-based chipset (302), which includes a plurality of diode chips (13), each diode chip (13) being connected in parallel with a silicon-based power chip (12) in the first silicon-based chipset (302); The lower bridge chipset (32) also includes a second silicon-based chipset (304), which includes a plurality of diode chips (13), each diode chip (13) being connected in parallel with a silicon-based power chip (12) in the second silicon-based chipset (304); The plurality of diode chips (13) of each of the first silicon-based chipset (302) are connected in series with the plurality of diode chips (13) of the second silicon-based chipset (304).

2. The hybrid power module according to claim 1, characterized in that, The silicon-based power chip in each of the first silicon-based chipset (302) is connected in series with the silicon-based power chip in the second silicon-based chipset (304) to form a half-bridge structure.

3. The hybrid power module according to claim 1, characterized in that, The second wide bandgap chipset (303) is connected in series with the wide bandgap power chips (11) in the first wide bandgap chipset (301) to form a half-bridge circuit, and the multiple wide bandgap power chips (11) in the wide bandgap chipset are connected in parallel with each other.

4. The hybrid power module according to claim 1, characterized in that, The hybrid power module includes a second DC connection terminal (42) located on the second DC connection layer (23), and the current path length between the wide bandgap power chip (11) of each second wide bandgap chipset (303) and the second DC connection terminal (42) is the same.

5. The hybrid power module according to claim 1, characterized in that, At least a portion of the structure of the AC connection layer is embedded within the first DC connection layer (21) and is insulated from the first DC connection layer (21) to connect the wide bandgap power chip (11) in the first wide bandgap chipset (301).

6. The hybrid power module according to claim 4, characterized in that, On the second DC connection layer (23), the second DC connection terminal (42) is located close to the second wide bandgap chipset (303).

7. The hybrid power module according to claim 1, characterized in that, The hybrid power module also includes a first DC connection terminal (41), which is located on the first DC connection layer (21). The current path length between the wide bandgap power chip (11) of each of the first wide bandgap chipsets (301) and the first DC connection terminal (41) is the same.

8. The hybrid power module according to claim 2, characterized in that, The first DC connection layer (21) includes a first connection layer (211) and a second connection layer (212) that are electrically connected to each other. The first wide bandgap chipset (301) is located on the first interconnect layer (211), and the first silicon-based chipset (302) is located on the second interconnect layer (212).

9. The hybrid power module according to claim 8, characterized in that, The first connection layer (211) and the second connection layer (212) are located on both sides of the second DC connection layer (23).

10. The hybrid power module according to claim 8, characterized in that, A recess is formed between the first connection layer (211) and the second connection layer (212) to accommodate at least a portion of the protruding structure of the AC connection layer. The protruding at least a portion of the structure is spaced apart from the first DC connection layer and is used to electrically connect multiple wide bandgap power chips (11) in the first wide bandgap chipset (301).

11. The hybrid power module according to any one of claims 1-10, characterized in that, The arrangement of the plurality of wide bandgap power chips (11) includes at least one of the following: Each of the wide bandgap power chips (11) is flush with each other in the second direction; The two adjacent wide-bandgap power chips (11) are staggered in the first direction; Each of the wide bandgap power chips (11) is staggered in the first direction; The first direction and the second direction are two mutually perpendicular directions on a plane.

12. The hybrid power module according to claim 1, characterized in that, The arrangement of multiple silicon-based power chips (12) and multiple diode chips (13) within any silicon-based chipset includes at least one of the following: The silicon-based power chip (12) and the diode chip (13) are arranged crosswise in the first direction; A first chip assembly and a second chip assembly are arranged in the first direction. The first chip assembly includes a plurality of silicon-based power chips (12) arranged in the first direction, and the second chip assembly includes a plurality of diode chips (13) arranged in the first direction. Multiple third chip combinations are arranged in the first direction, the third chip combinations including the silicon-based power chip (12) and the diode chip (13) arranged in the second direction. Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in the first direction. The fourth chip combinations and the fifth chip combinations include the silicon-based power chip (12) and the diode chip (13) arranged in the second direction. In the fourth chip combinations and the fifth chip combinations, the silicon-based power chip (12) and the diode chip (13) are arranged in opposite directions. Wherein, the first direction and the second direction are two mutually perpendicular directions on a plane.

13. The hybrid power module according to claim 1, characterized in that, The arrangement of multiple silicon-based power chips (12) and multiple diode chips (13) within any silicon-based chipset includes at least one of the following: The silicon-based power chip (12) and the diode chip (13) are arranged in a cross pattern in the second direction; A first chip assembly and a second chip assembly are arranged in the second direction. The first chip assembly includes a plurality of silicon-based power chips (12) arranged in the second direction, and the second chip assembly includes a plurality of diode chips (13) arranged in the second direction. Multiple third chip combinations are arranged in the second direction, the third chip combinations including the silicon-based power chip (12) and the diode chip (13) arranged in the first direction. Multiple fourth chip combinations and multiple fifth chip combinations are arranged in a cross pattern in the second direction. The fourth chip combinations and the fifth chip combinations include the silicon-based power chip (12) and the diode chip (13) arranged in the first direction. In the fourth chip combinations and the fifth chip combinations, the silicon-based power chip (12) and the diode chip (13) are arranged in opposite directions.

14. The hybrid power module according to claim 1, characterized in that, The hybrid power module includes: An upper bridge driving layer (24) is located on the substrate, the upper bridge driving layer (24) includes a first gate driving layer (241) and a first source driving layer (243). The gate of each of the wide bandgap power chips (11) in the first wide bandgap chipset (301) is connected to the first gate driving layer (241), and the source of each of the wide bandgap power chips (11) in the first wide bandgap chipset (301) is connected to the first source driving layer (243).

15. The hybrid power module according to claim 14, characterized in that, The upper bridge driving layer (24) further includes a second gate driving layer (242) and a first emitter driving layer (244), wherein the gate of each of the silicon-based power chips (12) in the first silicon-based chip group (302) is connected to the second gate driving layer (242), and the emitter of each of the silicon-based power chips (12) in the first silicon-based chip group (302) is connected to the first emitter driving layer (244).

16. The hybrid power module according to claim 1, characterized in that, The hybrid power module includes: The lower bridge driving layer (25) located on the substrate includes a third gate driving layer (251) and a second source driving layer (253). The gate of each of the wide bandgap power chips (11) in the second wide bandgap chipset (303) is connected to the third gate driving layer (251), and the source of each of the wide bandgap power chips (11) in the second wide bandgap chipset (303) is connected to the second source driving layer (253).

17. The hybrid power module according to claim 16, characterized in that, The lower bridge driving layer (25) further includes a fourth gate driving layer (252) and a second emitter driving layer (254). The gate of each of the silicon-based power chips (12) in the second silicon-based chipset (304) is connected to the fourth gate driving layer (252), and the emitter of each of the silicon-based power chips (12) in the second silicon-based chipset (304) is connected to the second emitter driving layer (254).

18. The hybrid power module according to claim 15, characterized in that, The first source driving layer (243) and the first emitter driving layer (244) are the same driving layer.

19. The hybrid power module according to claim 15, characterized in that, The hybrid power module includes: The first gate driving terminal (441) is provided in the first gate driving layer (241), the second gate driving terminal (442) is provided in the second gate driving layer (242), the first source driving terminal (443) is provided in the first source driving layer (243), and the first emitter driving terminal (444) is provided in the first emitter driving layer (244).

20. The hybrid power module according to claim 19, characterized in that, At least one of the first gate driving terminal (441), the second gate driving terminal (442), the first source driving terminal (443), and the first emitter driving terminal (444) is led out perpendicularly to the substrate.

21. The hybrid power module according to claim 17, characterized in that, The second source driving layer (253) and the second emitter driving layer (254) are the same driving layer.

22. The hybrid power module according to claim 17, characterized in that, The hybrid power module includes: The third gate driving terminal (451) is provided in the third gate driving layer (251), the fourth gate driving terminal (452) is provided in the fourth gate driving layer (252), the second source driving terminal (453) is provided in the second source driving layer (253), and the second emitter driving terminal (454) is provided in the second emitter driving layer (254).

23. The hybrid power module according to claim 22, characterized in that, At least one of the third gate driving terminal (451), the fourth gate driving terminal (452), the second source driving terminal (453), and the second emitter driving terminal (454) is led out perpendicularly to the substrate.

24. The hybrid power module according to claim 14, characterized in that, The hybrid power module includes: Two interconnected first source driving layers (243), at least one of the first source driving layers (243) is provided with multiple driving resistors (5); The first end of each of the driving resistors (5) is connected to each other and to the first gate driving layer (241), and the second end of each of the driving resistors (5) is connected to the gate of one of the wide bandgap power chips (11) in the first wide bandgap chipset (301).

25. The hybrid power module according to claim 16, characterized in that, The hybrid power module includes: Two interconnected second source driving layers (253), at least one of the second source driving layers (253) is provided with a plurality of driving resistors (5); the first end of each driving resistor (5) is interconnected and connected to the third gate driving layer (251), and the second end of each driving resistor (5) is connected to the gate of one of the wide bandgap power chips (11) in the second wide bandgap chipset (303).

26. The hybrid power module according to claim 5, characterized in that, At least a portion of the structure of the AC connection layer, which is interspersed with the first DC connection layer, includes an AC connection terminal (43), and the current path length between each of the wide bandgap power chips (11) in the first wide bandgap chipset (301) and the AC connection terminal (43) is the same.

27. The hybrid power module according to claim 1, characterized in that, The second DC connection layer (23) is also provided with a second DC connection terminal, which is led out along the first direction.

28. The hybrid power module according to claim 1, characterized in that, The first DC connection layer (21) is also connected to a first DC connection terminal, which is led out along a first direction.

29. The hybrid power module according to claim 1, characterized in that, The AC connection layer (22) is also provided with an AC connection terminal, which is led out along a first direction.

30. The hybrid power module according to any one of claims 1-10, characterized in that, At least one of the first DC connection layer (21), the second DC connection layer (23), and the AC connection layer (22) is a copper layer.

31. The hybrid power module according to any one of claims 1-10, characterized in that, The wide bandgap power chip includes silicon carbide metal-oxide-semiconductor field-effect transistors or gallium nitride high electron mobility transistors.

32. The hybrid power module according to claim 1, characterized in that, The silicon-based power chip includes a silicon insulated gate bipolar transistor or a silicon metal oxide semiconductor field-effect transistor. The diode chip includes a silicon fast recovery diode chip or a silicon carbide Schottky diode chip.

33. A multiphase full-bridge hybrid module, characterized in that, It includes at least two hybrid power modules as described in any one of claims 1-32.

34. A power conversion device, characterized in that, It includes at least one hybrid power module as described in any one of claims 1-32.

35. A vehicle, characterized in that, Includes the power conversion device as described in claim 34.

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