Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof. In the packaging structure, a first semiconductor chip is inversely arranged on a part of the upper surface of a first substrate; the plurality of discrete inter-board connecting structures are positioned between the first substrate and the second substrate and are used for electrically connecting the first bonding pad on the upper surface of the first substrate with the corresponding fourth bonding pad on the lower surface of the second substrate; the inter-board connection structure comprises a metal column located on the surface of a first bonding pad on the upper surface of the first substrate or the surface of a fourth bonding pad on the lower surface of the second substrate, and a metal core ball located on the surface of the top or the bottom of the metal column. The metal core ball comprises a metal core located in the center and a wrapping solder layer wrapping the metal core, and the diameter of the metal core is smaller than or equal to 75% of the diameter of the metal core ball; the plastic package layer is filled between the first substrate and the second substrate and covers the first semiconductor chip and the inter-board connection structure. And crack defects and hole defects in the packaging structure are prevented.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a packaging structure and a method for forming the same. Background Art

[0002] With the growing demand for applications such as smart phones, smart wearables, smart manufacturing, assisted driving for automobiles and motor vehicles, and AIoT, terminal products need to have higher performance while maintaining small size and low power consumption. In addition to the system integration (SoC, System on Chip) focused on advanced silicon technology nodes on the chip manufacturing side, the system integration (SiP, System in Package) focused on advanced packaging technology on the packaging and testing manufacturing side also has comparable competitiveness with low cost, flexibility, and high yield. With the increase in integration density, SiP has also developed from the early 2D packaging form (such as MCM, Multi-Chip Module) to 2.5D and 3D.

[0003] As a packaging form in 2.5D and 3D packaging, PoP (Package on Package) stacked packaging usually has an upper substrate and a lower substrate stacked up and down, and corresponding semiconductor chips are mounted on the upper substrate and the lower substrate respectively. The common connection method for the electrical connection between the upper substrate and the lower substrate is through a copper core ball, which generally includes a copper core and a solder layer covering the copper core. However, when the copper core ball is used to electrically connect the upper substrate and the lower substrate, a crack defect will occur at the contact position between the copper core ball and the lower surface of the upper substrate, and a void defect is easily generated when the back side of the semiconductor chip mounted on the upper surface of the lower substrate and the lower surface of the upper substrate are filled with a plastic sealing layer. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a packaging structure and a method for forming the same, by improving the structure of the connection structure between the upper substrate and the lower substrate to prevent the generation of crack defects and void defects in the packaging structure.

[0005] In order to solve the above problems, an embodiment of the present application provides a packaging structure, including:

[0006] A first substrate, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads;

[0007] A first semiconductor chip is flip-mounted on a portion of the upper surface of the first substrate and is electrically connected to a portion of the first pads on the upper surface of the first substrate;

[0008] A second substrate, located above the first semiconductor chip and the first substrate, the upper surface of the second substrate having a plurality of discrete third pads, and the lower surface of the second substrate having a plurality of discrete fourth pads;

[0009] A plurality of discrete inter-board connection structures, located between the first substrate and the second substrate, electrically connecting a first pad on the upper surface of the first substrate to a fourth pad corresponding to the lower surface of the second substrate, the inter-board connection structures comprising a metal column located on a surface of the first pad on the upper surface of the first substrate or a surface of the fourth pad on the lower surface of the second substrate and a metal core ball located on a top surface or a bottom surface of the metal column, the metal core ball comprising a metal core located at the center and a coating solder layer coating the metal core, and a diameter of the metal core is less than or equal to 75% of a diameter of the metal core ball;

[0010] The plastic packaging layer is filled between the first substrate and the second substrate and covers the first semiconductor chip and the inter-board connection structure.

[0011] In some embodiments, the diameter of the metal column is smaller than the diameter of the metal core ball, the height of the metal column is 20% to 40% of the distance between the upper surface of the first substrate and the lower surface of the second substrate, and the diameter of the metal core ball is 60% to 80% of the distance between the upper surface of the first substrate and the lower surface of the second substrate.

[0012] In some embodiments, the metal core ball further includes a metal bonding layer between the cladding solder layer and the metal core.

[0013] In some embodiments, the diameter of the metal core is 65%-75% of the diameter of the metal core ball, the thickness of the metal bonding layer on the surface of the metal core is 1%-5% of the diameter of the metal core ball, and the thickness of the coating solder layer on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball.

[0014] In some embodiments, the spacing between the upper surface of the first substrate and the lower surface of the second substrate ranges from 170 microns to 250 microns, the height of the metal column ranges from 45 microns to 70 microns, the diameter of the metal column ranges from 130 microns to 160 microns, the diameter of the metal core is 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core is 1 micron to 4 microns, and the thickness of the coated solder layer on the surface of the metal bonding layer is 20 microns to 40 microns.

[0015] In some embodiments, the metal pillar and the metal core are made of copper, tungsten or aluminum, the metal adhesion layer is made of nickel or titanium, and the cladding solder layer is made of tin or a tin alloy.

[0016] In some embodiments, among the several discrete inter-board connection structures, the metal column of each of the inter-board connection structures is located on the surface of the first pad on the upper surface of the first substrate, and the metal core ball is located on the top surface of the metal column that is not in contact with the first pad and is in contact with the fourth pad on the lower surface of the second substrate.

[0017] In some embodiments, among the several discrete inter-board connection structures, the metal column of each of the inter-board connection structures is located on the surface of the fourth pad on the lower surface of the second substrate, and the metal core ball is located on the top surface of the metal column that is not in contact with the fourth pad and is in contact with the first pad on the upper surface of the first substrate.

[0018] In some embodiments, among the several discrete inter-board connection structures, the metal column of each of the inter-board connection structures is located on the surface of the first pad on the upper surface of the first substrate, and the metal core ball is located on the top surface of the metal column that is not in contact with the first pad and is in contact with the fourth pad on the lower surface of the second substrate.

[0019] In some embodiments, the plurality of discrete inter-board connection structures include a plurality of first inter-board connection structures and a plurality of second inter-board connection structures, and the first inter-board connection structures and the second inter-board connection structures are spaced apart between the first substrate and the second substrate, and each of the first inter-board connection structures includes a first metal column on a first pad surface on the upper surface of the first substrate and a first metal core ball located on a top surface of the first metal column, the first metal core ball including a first metal core located in the center and a first coating solder layer covering the first metal core; each of the second inter-board connection structures includes a second metal column on a fourth pad surface on the lower surface of the second substrate and a second metal core ball located on a bottom surface of the second metal column, the second metal core ball including a second metal core and a second coating solder layer covering the second metal core.

[0020] In some embodiments, the packaging structure also includes: a second semiconductor chip mounted on the upper surface of the second substrate, the second semiconductor chip is electrically connected to the third pad on the upper surface of the second substrate; and an external solder bump located on the surface of the second pad on the lower surface of the first substrate.

[0021] The present application also provides a method for forming a packaging structure, including:

[0022] A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; and a metal column is formed on a surface of a portion of the second pads around the first semiconductor chip;

[0023] A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; a metal core ball is mounted on the surface of a portion of the fourth pads on the lower surface of the second substrate, wherein the metal core ball comprises a metal core located at the center and a coating solder layer coating the metal core, and the diameter of the metal core is less than or equal to 75% of the diameter of the metal core ball;

[0024] Mounting the second substrate on the upper surface of the first substrate, and welding the coating solder layer in the metal core ball on the lower surface of the second substrate and the top surface of the metal column on the upper surface of the first substrate together to form an inter-board connection structure;

[0025] A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

[0026] In some embodiments, the height of the metal pillar is 20% to 40% of the distance between the first substrate upper surface and the second substrate lower surface, and the diameter of the metal core ball is 60% to 80% of the distance between the first substrate upper surface and the second substrate lower surface.

[0027] In some embodiments, the metal core ball further includes a metal bonding layer between the cladding solder layer and the metal core.

[0028] In some embodiments, the diameter of the metal core is 65%-75% of the diameter of the metal core ball, the thickness of the metal bonding layer on the surface of the metal core is 1%-5% of the diameter of the metal core ball, and the thickness of the coating solder layer on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball.

[0029] In some embodiments, the spacing between the upper surface of the first substrate and the lower surface of the second substrate ranges from 170 microns to 250 microns, the height of the metal column ranges from 45 microns to 70 microns, the diameter of the metal core is 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core is 1 micron to 4 microns, and the thickness of the coating solder layer on the surface of the metal bonding layer is 20 microns to 40 microns.

[0030] In some embodiments, it also includes: mounting a second semiconductor chip on the upper surface of the second substrate, the second semiconductor chip being electrically connected to a third pad on the upper surface of the second substrate; and forming an external solder bump on the surface of the second pad on the lower surface of the first substrate.

[0031] The present application also provides a method for forming a packaging structure, including:

[0032] A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; a metal core ball is mounted on a portion of the first pads surrounding the first semiconductor chip, wherein the metal core ball comprises a metal core located at the center and a coating solder layer coating the metal core, and the diameter of the metal core is less than or equal to 75% of the diameter of the metal core ball;

[0033] A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; and metal pillars are formed on the surfaces of some of the fourth pads on the lower surface of the second substrate;

[0034] Mounting the second substrate on the upper surface of the first substrate, and welding the coating solder layer in the metal core ball on the upper surface of the first substrate and the bottom surface of the metal column on the lower surface of the second substrate together to form an inter-board connection structure;

[0035] A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

[0036] The present application also provides a method for forming a packaging structure, which includes:

[0037] A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; a second metal core ball is mounted on a portion of the first pad surface surrounding the first semiconductor chip, the second metal core ball includes a second metal core located at the center and a second coating solder layer coating the second metal core, and the diameter of the second metal core in the second metal core ball is less than or equal to 75% of the diameter of the second metal core ball; a first metal column is formed on the surface of the first pad between adjacent second metal core balls;

[0038] A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; second metal pillars are formed on the surfaces of some of the fourth pads; first metal core balls are mounted on the surfaces of the fourth pads between adjacent second metal pillars, wherein the first metal core balls include a first metal core located at the center and a first coating solder layer coating the first metal core, and the diameter of the first metal core in the first metal core ball is less than 75% of the diameter of the first metal core ball;

[0039] Mounting the second substrate on the upper surface of the first substrate, welding the second cladding solder layer in the second metal core ball on the upper surface of the first substrate and the bottom surface of the second metal column corresponding to the lower surface of the second substrate to form a second inter-board connection structure, welding the first cladding solder layer in the first metal core ball on the lower surface of the second substrate and the top surface of the first metal column corresponding to the upper surface of the first substrate to form a first inter-board connection structure;

[0040] A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

[0041] The technical solution of this application has the following advantages:

[0042] Some of the aforementioned embodiments of the present application provide packaging structures and methods for forming the same, wherein a first semiconductor chip is flipped on a portion of the upper surface of the first substrate; a plurality of discrete inter-board connection structures are located between the first substrate and the second substrate, electrically connecting a first pad on the upper surface of the first substrate to a fourth pad corresponding to the lower surface of the second substrate, the inter-board connection structure comprising a metal column located on the surface of the first pad on the upper surface of the first substrate or on the surface of the fourth pad on the lower surface of the second substrate, and a metal core ball located on the top or bottom surface of the metal column, the metal core ball comprising a metal core located in the center and a coating solder layer coating the metal core, and a diameter of the metal core is less than or equal to 75% of the diameter of the metal core ball; a plastic encapsulation layer is filled between the first substrate and the second substrate, and covers the first semiconductor chip and the inter-board connection structure. That is, in the present application, the first substrate and the second substrate are electrically connected by combining a metal core ball and a metal column as an inter-board connection structure. Compared with the existing method of electrically connecting the upper substrate and the lower substrate only by using a copper core ball of a customized size, the existence of the metal column is equivalent to raising the metal core ball, so that the distance between the first substrate and the second substrate will increase. Therefore, when a first semiconductor chip with the same thickness as or thicker than the existing thickness (the thickness increase value is less than the height of the metal column) is mounted on the upper surface of the first substrate, the distance between the back side of the first semiconductor chip and the lower surface of the second substrate will increase, so that the difficulty of filling the plastic sealing layer between the back side of the first semiconductor chip and the lower surface of the second substrate is reduced, thereby preventing the generation of void defects in the plastic sealing layer in this area; and, compared with the existing copper core ball of the same size, the metal core ball in the present application has a smaller diameter of the metal core in the metal core ball than the diameter of the copper core in the existing copper core ball (the diameter of the metal core in the metal core ball in the present application is smaller than that ... The diameter of the metal core in the metal core ball of the application is less than or equal to 75% of the diameter of the metal core ball, and the diameter of the copper core in the copper core ball is generally greater than 75% of the diameter of the copper core ball). Therefore, the amount of the solder layer coated on the surface of the metal core of the metal core ball in the present application will be greater than the amount of the solder layer on the surface of the copper core of the existing copper core ball of the same size. Further, when the metal core ball in the present application is welded to the fourth soldering pad on the lower surface of the second substrate (or the first soldering pad on the upper surface of the first substrate is connected to the metal core ball in other subsequent embodiments), the amount of solder between the metal core ball and the fourth soldering pad on the lower surface of the second substrate (or the first soldering pad on the upper surface of the first substrate) will increase. The increase in the amount of solder can overcome the larger stress caused by the mismatch of the thermal expansion coefficient, and avoid or prevent the solder between the metal core ball and the fourth soldering pad on the lower surface of the second substrate (or the first soldering pad on the upper surface of the first substrate) from detaching from the surface of the metal core to produce crack defects.Furthermore, the present application increases the spacing between the first substrate and the second substrate, prevents void defects from being generated in the plastic sealing layer between the back side of the first semiconductor chip and the lower surface of the second substrate, and prevents the solder between the metal core ball and the fourth solder pad on the lower surface of the second substrate (or the first solder pad on the upper surface of the first substrate) from being separated from the surface of the metal core and generating crack defects, while maintaining a relatively small spacing (e.g., less than or equal to 50 microns) between adjacent inter-board connection structures. The reason is that although the coating solder layer in the metal core ball is increased in the present application, due to the presence of the metal column, part of the solder will spread to the side wall of the metal column during welding, thereby preventing the coating solder layers in adjacent metal core balls from being connected together and causing a short circuit. However, when the existing copper core balls are directly connected to the upper substrate and the lower substrate, if the amount of the solder layer in the copper core balls is further increased when the spacing between adjacent copper core balls is small, it is very easy for adjacent copper core balls to be connected together and cause a short circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a schematic diagram of the packaging structure in some embodiments of the present application.

[0044] Figure 2 It is a schematic diagram of the structure of the packaging structure in some other embodiments of the present application;

[0045] Figure 3 It is a schematic diagram of the structure of the packaging structure in some other embodiments of the present application;

[0046] Figure 4 A schematic structural diagram of a process for forming a packaging structure in some embodiments of the present application;

[0047] Figure 5 It is a structural schematic diagram of the formation process of the packaging structure in other embodiments of the present application. DETAILED DESCRIPTION

[0048] As mentioned in the background technology, when copper core balls are used to electrically connect the upper substrate and the lower substrate, crack defects will occur at the contact position between the copper core balls and the lower surface of the upper substrate, and void defects will easily occur when the back side of the semiconductor chip mounted on the upper surface of the lower substrate and the plastic packaging layer are filled on the lower surface of the upper substrate.

[0049] The study found that during the welding process between the upper end of the copper core ball and the lower surface of the upper substrate, the solder layer will spread downward under the action of gravity and surface tension after melting, so that the amount of solder between the upper end of the copper core ball and the lower surface of the upper substrate will be reduced, and because the thermal expansion coefficient of the copper core and the thermal expansion coefficient of the solder layer are greatly different (mismatched), during the heat reflow process, the mismatch of thermal expansion coefficients will generate a large stress, so that the less solder between the copper core ball and the lower surface of the upper substrate will be separated from the upper surface of the copper core and produce crack defects. In addition, since the existing copper core balls are all customized, the diameter or size of the copper core balls is fixed, which limits the spacing between the upper substrate and the lower substrate. When the thickness of the semiconductor chip mounted on the upper surface of the upper substrate is too large, this will make the spacing between the back of the semiconductor chip and the lower surface of the upper substrate very small. When filling the plastic sealing layer material, it is very easy to produce a void defect in the plastic sealing layer filled between the back of the semiconductor chip and the lower surface of the upper substrate.

[0050] To this end, the embodiments of the present application improve the structure of the connection structure between the upper substrate and the lower substrate to prevent the generation of crack defects and void defects in the packaging structure.

[0051] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0052] The embodiment of the present application first provides a packaging structure.

[0053] Figure 1 This is a schematic diagram of the packaging structure in some embodiments of the present application.

[0054] refer to Figure 1 , the packaging structure comprises:

[0055] A first substrate 211, wherein the upper surface of the first substrate 211 has a plurality of discrete first pads 201, and the lower surface of the first substrate 211 has a plurality of discrete second pads 202;

[0056] A first semiconductor chip 111 is flip-mounted on a portion of the upper surface of the first substrate 211 and electrically connected to a portion of the first pads 201 on the upper surface of the first substrate 211;

[0057] A second substrate 212 is located above the first semiconductor chip 111 and the first substrate 211 , the upper surface of the second substrate 212 has a plurality of discrete third pads 203 , and the lower surface of the second substrate 212 has a plurality of discrete fourth pads 204 ;

[0058] A plurality of discrete inter-board connection structures, located between the first substrate 211 and the second substrate 212, electrically connecting the first pad 201 on the upper surface of the first substrate 211 with the fourth pad corresponding to the lower surface of the second substrate 212, the inter-board connection structures comprising a metal column 206 located on the surface of the first pad 201 on the upper surface of the first substrate 211 and a metal core ball located on the top surface of the metal column 206, the metal core ball comprising a metal core 208 located at the center and a coating solder layer 207 coating the metal core 208, and the diameter of the metal core 208 is less than or equal to 75% of the diameter of the metal core ball;

[0059] The plastic packaging layer 213 is filled between the first substrate 211 and the second substrate 212 and covers the first semiconductor chip 111 and the inter-board connection structure.

[0060] Specifically, the first substrate 211 serves as a support carrier and a connection carrier in the packaging process. In some embodiments, the first substrate 211 includes a relative upper surface and a lower surface, the upper surface of the first substrate 211 has a plurality of discrete first pads 201, the lower surface of the first substrate 211 has a plurality of discrete second pads 202, the first substrate 211 has a first connection line 205, the first connection line 205 may include one or more of a metal layer, a connection plug, a through-hole connection structure (TSV), and a via connection structure, the first connection line 205 may be used for electrical connection between the first pad 201 on the upper surface of the first substrate 211 and the corresponding second pad 202 on the lower surface of the first substrate 211, the first connection line 205 may also be used for electrical connection between some of the first pads 201 on the upper surface of the first substrate 211, and the first connection line 205 may also be used for electrical connection between some of the second pads 202 on the lower surface of the first substrate 211. Part of the first pad 201 on the upper surface of the first substrate 211 is electrically connected to the flip-chip first semiconductor chip 111, and part of the first pad 201 is electrically connected to one end (lower end, the board-to-board connection structure may include an upper end and a lower end relative to each other) of the corresponding board-to-board connection structure. The second pad 202 on the lower surface of the first substrate 211 has an external solder bump 209, and the external solder bump 209 is used to connect with other substrates, other devices or packaging structures. In some embodiments, the material of the first pad 201, the second pad 202 and the first connecting line 205 is metal, specifically, one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver. The material of the external solder bump 209 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony.

[0061] The first substrate 211 may be of different types. In some embodiments, the first substrate 211 may be a resin substrate, a silicon substrate, a printed circuit board (PCB), a re-distribution layer (RDL), a ceramic substrate, a glass substrate, or a flexible circuit board (FPC). The first substrate 211 may be a single-layer board or a multi-layer board. In a specific example, the first substrate 211 may be used as a packaging substrate.

[0062] Continue to refer Figure 1, the first semiconductor chip 111 in the package structure is flipped on the upper surface of the first substrate 211 and electrically connected to the first substrate 211. Specifically, the first semiconductor chip 111 includes a first functional surface and a first back surface relative to each other, an integrated circuit (not shown in the figure) (having a specific function) is formed in the first semiconductor chip 111, and the first functional surface of the first semiconductor chip 111 has a first welding protrusion 101, and the first welding protrusion 101 is electrically connected to the integrated circuit. When performing a specific flip-up, the first functional surface of the first semiconductor chip 111 faces the upper surface of the first substrate 211, and the first welding protrusion 101 on the first functional surface of the first semiconductor chip 111 is welded together with the corresponding first welding pad 201 on the upper surface of the first substrate 211. In some embodiments, the first welding protrusion 101 includes a solder ball protruding from the first functional surface of the first semiconductor chip 111. In other embodiments, the first welding bump 101 may include a metal bump protruding from the first functional surface of the first semiconductor chip 111 and a welding cap located on the top surface of the metal bump. The material of the metal bump is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver; the material of the solder ball and solder cap is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.

[0063] The number of the first semiconductor chip 111 flipped on the upper surface of the first substrate 211 is at least one, and an underfill layer (Underfill) is also provided between the first semiconductor chip 111 and the upper surface of the first substrate 211. The first semiconductor chip 111 may be a logic chip or a memory chip. In some embodiments, the logic chip may include but is not limited to a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a graphics processing unit (GPU), a central processing unit (CPU), a microprocessing unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power chip, or a complementary metal oxide semiconductor (CMOS) image sensor. In some embodiments, the memory chip may include but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase change memory (PRAM), resistive random access memory (RRAM) or non-volatile memory chip (such as flash memory).

[0064] Continue to refer Figure 1The second substrate 212 is located above the first substrate 211 and the first semiconductor chip 111, and the second substrate 212 plays a role in electrical connection and support in the packaging structure. The first substrate 211 serves as a support carrier and a connection carrier in the packaging process. In some embodiments, the second substrate 212 includes a relative upper surface and a lower surface, the upper surface of the second substrate 212 has a plurality of discrete third pads 203, the lower surface of the second substrate 212 has a plurality of discrete fourth pads 204, the second substrate 212 has a second connecting line 215, the second connecting line 215 may include one or more of a metal layer, a connecting plug, a through-hole connection structure (TSV), and a via connection structure, the second connecting line 215 can be used for the electrical connection between the third pads 203 on the upper surface of the second substrate 212 and the corresponding fourth pads 204 on the lower surface of the second substrate 212, the second connecting line 215 can also be used for the electrical connection between part of the third pads 203 on the upper surface of the second substrate 212, and the second connecting line 215 can also be used for the electrical connection between part of the fourth pads 204 on the lower surface of the second substrate 212. Part of the third pad 203 on the upper surface of the second substrate 212 is electrically connected to a second semiconductor chip (not shown in the figure) that can be mounted, and the fourth pad 204 on the lower surface of the second substrate 212 is electrically connected to the other end of the corresponding inter-board connection structure (the upper end of the inter-board connection structure). In some embodiments, the material of the third pad 203, the fourth pad 204 and the second connection line 215 is metal, specifically, one or more of aluminum, copper, nickel, tin, titanium, tungsten, platinum, chromium, tantalum, gold, and silver.

[0065] The second substrate 212 may be of the same type or a different type as the first substrate 211. In some embodiments, the second substrate 212 may be a resin substrate, a silicon substrate, a printed circuit board (PCB), a re-distribution layer (RDL), a ceramic substrate, a glass substrate, or a flexible printed circuit board (FPC). The second substrate 212 may be a single-layer board or a multi-layer board. In a specific example, the second substrate 212 may be used as an adapter board or an interposer.

[0066] Continue to refer Figure 1The inter-board connection structure is located between the first substrate 211 and the second substrate 212, and plays the role of supporting the second substrate 212 and electrically connecting the first pad 201 on the upper surface of the first substrate 211 with the fourth pad corresponding to the lower surface of the second substrate 212. The inter-board connection structure includes a metal column 206 located on the surface of the first pad 201 on the upper surface of the first substrate 211 and a metal core ball located on the top surface of the metal column 206. The metal core ball includes a metal core 208 located in the center and a coating solder layer 207 coating the metal core 208, and the diameter of the metal core 208 is less than or equal to 75% of the diameter of the metal core ball. That is, in the present application, the first substrate 211 and the second substrate 212 are electrically connected by combining the metal core ball and the metal column 206 as an inter-board connection structure. Compared with the existing method of electrically connecting the upper substrate and the lower substrate only by using a copper core ball of a customized size, the existence of the metal column 206 is equivalent to raising the metal core ball, so that the distance between the first substrate 211 and the second substrate 212 is increased. Therefore, when the first semiconductor chip 111 with the same thickness or thicker than the existing thickness (the thickness increase value is less than the height of the metal column 206) is mounted on the upper surface of the first substrate 211, the distance between the back side of the first semiconductor chip 111 and the lower surface of the second substrate 212 will be increased, so that the difficulty of filling the plastic sealing layer 213 between the back side of the first semiconductor chip 111 and the lower surface of the second substrate 212 is reduced, thereby preventing the generation of void defects in the plastic sealing layer in this area; and, compared with the existing copper core ball of the same size, the metal core ball in the present application has a smaller diameter of the metal core in the metal core ball than the diameter of the copper core in the existing copper core ball (the diameter of the metal core in the present application is smaller than that of the copper core in the existing copper core ball). The diameter of the metal core 208 in the metal core ball is less than or equal to 75% of the diameter of the metal core ball, and the diameter of the copper core in the copper core ball is generally greater than 75% of the diameter of the copper core ball). Therefore, the amount of the coating solder layer 207 on the surface of the metal core 208 of the metal core ball in the present application is greater than the amount of the solder layer on the surface of the copper core of the existing copper core ball of the same size, and then the metal core ball in the present application is welded to the fourth soldering pad 204 on the lower surface of the second substrate 212 (or the metal core ball is used in other subsequent embodiments to connect the first substrate 212 to the fourth soldering pad 204). When the first solder pad 201 on the upper surface of the board 211 is connected, the amount of solder between the metal core ball and the fourth solder pad 204 on the lower surface of the second substrate 212 (or the first solder pad 201 on the upper surface of the first substrate 211) will increase. The increase in the amount of solder can overcome the larger stress caused by the mismatch of thermal expansion coefficients, thereby avoiding or preventing the solder between the metal core ball and the fourth solder pad 204 on the lower surface of the second substrate 212 (or the first solder pad 201 on the upper surface of the first substrate 211) from detaching from the surface of the metal core and causing crack defects.Furthermore, the present invention increases the spacing between the first substrate 211 and the second substrate 212, prevents void defects from being generated in the plastic layer 213 between the back surface of the first semiconductor chip 111 and the lower surface of the second substrate 212, and prevents the solder between the metal core ball and the fourth solder pad 204 on the lower surface of the second substrate 212 (or the first solder pad 201 on the upper surface of the first substrate 211) from being separated from the surface of the metal core to generate crack defects, while the adjacent inter-board connection structures can also maintain a small spacing (for example, less than 1 / 4") between them. The reason is that although the coating solder layer 207 in the metal core ball will increase in the present application, due to the existence of the metal column 206, part of the solder will spread to the side wall of the metal column 206 during welding, thereby preventing the coating solder layer 207 in adjacent metal core balls from being connected together and causing a short circuit. When the existing copper core balls are directly connected to the upper substrate and the lower substrate, when the spacing between adjacent copper core balls is small, if the amount of the solder layer in the copper core balls is further increased, it is very easy for adjacent copper core balls to be connected together and cause a short circuit.

[0067] In one embodiment, the diameter of the metal column is smaller than the diameter of the metal core ball, the height of the metal column 206 is 20% to 40% of the distance between the upper surface of the first substrate 211 and the lower surface of the second substrate 212, and the diameter of the metal core ball is 60% to 80% of the distance between the upper surface of the first substrate 211 and the lower surface of the second substrate 212. The height of the metal column 206 cannot be too high. If it is too high, the coating solder layer 207 of the metal core ball will spread too much to the side of the metal column 206, so that the amount of solder between the metal core ball and the fourth pad 204 on the lower surface of the second substrate 212 (or the first pad 201 on the upper surface of the first substrate 211) will increase undesirably. The effect of avoiding or preventing the solder between the metal core ball and the fourth solder pad 204 on the lower surface of the second substrate 212 (or the first solder pad 201 on the upper surface of the first substrate 211) from detaching from the surface of the metal core and causing a crack defect will be deteriorated. The height of the metal column 206 cannot be too small. If it is too small, the increase in the distance between the first substrate 211 and the second substrate 212 will be small, which is not conducive to increasing the distance between the back side of the first semiconductor chip 111 and the lower surface of the second substrate 212, thereby preventing the generation of void defects in the plastic layer 213 between the back side of the first semiconductor chip 111 and the lower surface of the second substrate 212.

[0068] In one embodiment, the metal core ball further includes a metal bonding layer (not shown) located between the coating solder layer 207 and the metal core 208. The metal pillar 206 and the metal core 208 are made of copper, tungsten or aluminum, the metal bonding layer is made of nickel or titanium, and the coating solder layer 207 is made of tin or a tin alloy.

[0069] In some specific embodiments, the diameter of the metal core 208 is 65%-75% of the diameter of the metal core ball, which can be 65%, 66%, 67%, 68%, 69%, 70%. 、 71%, 72%, 73%, 74%, 75%, the thickness of the metal bonding layer on the surface of the metal core 208 is 1%-5% of the diameter of the metal core ball, which can be 1%, 2%, 3%, 4%, 5%, the thickness of the coating solder layer 207 on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball, which can be 7.5% 、 8% 、 8.5%, 9%, 9.5%, 10%, 10.5%, 11%, 11.5%, 12%, 12.5%, 13%, 13.5%, 14%, 14.5%, 15%, 15.5%, 16%, 16.5%. This particular structure can keep the spacing between adjacent board connection structures small, so as to better avoid or prevent the solder between the metal core ball and the fourth pad 204 on the lower surface of the second substrate 212 (or the first pad 201 on the upper surface of the first substrate 211) from separating from the surface of the metal core to produce crack defects.

[0070] In some embodiments, the metal column 206 is a cylinder with a circular cross-sectional shape, and the metal core 208 of the metal core ball is a sphere. In other embodiments, the metal column 206 and the metal core 208 of the metal core ball can be other shapes, for example, the metal column 206 can be a columnar structure with a rectangular, elliptical, or polygonal cross-sectional shape, and the metal core 208 of the metal core ball can be an elliptical sphere. It should be noted that, regardless of whether the metal column 206 and the metal core ball are regular shapes, the limitations on the various parameters of the metal column 206 and the metal core ball in this application are all limitations on the maximum size of the metal column 206 and the metal core ball.

[0071] In some specific embodiments, the distance between the upper surface of the first substrate 211 and the lower surface of the second substrate 212 ranges from 170 microns to 250 microns, the height of the metal column 206 ranges from 45 microns to 70 microns, the diameter of the metal column ranges from 130 microns to 160 microns, the diameter of the metal core 208 ranges from 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core 208 ranges from 1 micron to 4 microns, and the thickness of the coated solder layer 207 on the surface of the metal bonding layer ranges from 20 microns to 40 microns. It should be noted that: the diameter of the metal core ball = the diameter of the metal core 208 + 2 times the thickness of the metal bonding layer + 2 times the thickness of the coating solder layer 207. After actual welding, the coating solder layer 207 of the metal core ball will be deformed to a certain extent. Therefore, in this application, the diameter of the metal core ball, the diameter of the metal core 208, the thickness of the metal bonding layer and the thickness of the coating solder layer 207 all refer to the corresponding diameters or thicknesses before welding, that is, the relevant parameters of the metal core ball provided by the supplier.

[0072] Continue to refer Figure 1 The plastic encapsulation layer 213 is filled between the first substrate 211 and the second substrate 212, and covers the first semiconductor chip 111 and the inter-board connection structure. The plastic encapsulation layer 213 electrically isolates and protects the inter-board connection structure and the solder joints between the first substrate 211 and the second substrate 212. In some embodiments, the material of the plastic encapsulation layer 213 can be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin containing fillers; or can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol containing fillers. In some embodiments, the filler can be an inorganic filler or an organic filler.

[0073] Some other embodiments of the present application also provide a packaging structure, please refer to Figure 2The main difference between the packaging structure in this embodiment and the packaging structure in the aforementioned embodiment is that: in the plurality of separate inter-board connection structures, the metal pillar 206 of each of the inter-board connection structures is located on the surface of the fourth pad 204 on the lower surface of the second substrate 212, and the metal core ball (including the metal core 208 and the coating solder layer 207 coating the metal core 208) is located on the bottom surface of the metal pillar 206 that is not in contact with the fourth pad 204 and is in contact with the first pad 201 on the upper surface of the first substrate 211. In this embodiment, since the metal pillar 206 is located above the metal core ball, during welding, the amount of the coating solder layer 207 in the metal core ball that spreads toward the side wall of the metal pillar 206 will be smaller due to the effect of gravity, which is more conducive to preventing crack defects from occurring in the solder between the lower surface of the metal core 208 in the metal core ball and the first pad 201 on the upper surface of the first substrate 211.

[0074] Some other embodiments of the present application also provide a packaging structure, please refer to Figure 3The main difference between the packaging structure in this embodiment and the packaging structure in the aforementioned embodiment is that the several discrete inter-board connection structures include multiple first inter-board connection structures and multiple second inter-board connection structures, and the first inter-board connection structures and the second inter-board connection structures are spaced apart between the first substrate 211 and the second substrate 212, the first inter-board connection structure includes a first metal column 206a and a first metal core ball located on the top surface of the first metal column 206a, the first metal core ball includes a first metal core 208a and a first coating solder layer 207a covering the first metal core 208a, the second inter-board connection structure includes a second metal column 206b and a second metal core ball located on the bottom surface of the second metal column 206b, the second metal core ball includes a second metal core 208b and a second coating solder layer 207b covering the second metal core 208b. Specifically, each of the first metal pillars 206a of the first inter-board connection structure is located on the surface of the first solder pad 201 on the upper surface of the first substrate 211, and the first metal core ball of the first inter-board connection structure is located on the top surface of the first metal pillar 206a that is not in contact with the first solder pad 201 and is in contact with the fourth solder pad 204 on the lower surface of the second substrate 212; each of the second metal pillars 206b of the second inter-board connection structure is located on the surface of the fourth solder pad 204 on the lower surface of the second substrate 212, and the second metal core ball of the second inter-board connection structure is located on the bottom surface of the second metal pillar 206b that is not in contact with the fourth solder pad 204 and is in contact with the first solder pad 201 on the upper surface of the first substrate 211. When the first inter-board connection structure and the second inter-board connection structure are distributed between the first substrate 211 and the second substrate 212, since there will be no solder in the portion of the first metal column 206a in the first inter-board connection structure that contacts the first pad 201, the space occupied by the first metal column 206a will be reduced compared to the metal core ball. Therefore, the distance between the second metal core ball of the second inter-board connection structure on both sides of the first metal column 206a and the first metal column 206a can be smaller than the method in which both metal core balls are welded to the first pad 201. Similarly, the distance between the first metal core ball of the first inter-board connection structure on both sides of the second metal column 206b and the second metal column 206b can be smaller than the method in which both metal core balls are welded to the fourth pad 204. Therefore, in the embodiment, while avoiding or preventing the solder between the metal core ball and the fourth pad 204 on the lower surface of the second substrate 212 (or the first pad 201 on the upper surface of the first substrate 211) from detaching from the surface of the metal core to produce a crack defect, the spacing between the inter-board connection structures can be smaller.

[0075] The embodiment of the present application also provides a method for forming a packaging structure.

[0076] In some embodiments, reference Figure 4 , the method for forming the packaging structure comprises:

[0077] like Figure 4 As shown in the first figure, a first substrate 211 is provided, the upper surface of the first substrate 211 has a plurality of discrete first solder pads 201, and the lower surface of the first substrate 211 has a plurality of discrete second solder pads 202; a first semiconductor chip 111 is flipped on a portion of the upper surface of the first substrate 211, and the first semiconductor chip 111 is electrically connected to a portion of the first solder pads 201; a metal column 206 is formed on the surface of a portion of the first solder pads 201 around the first semiconductor chip 111.

[0078] In some embodiments, the first substrate 211 may include a plurality of discrete packaging regions and scribe line regions between the packaging regions, and the first semiconductor chip 111 is mounted on each packaging region of the first substrate 211 and the metal pillar 206 is formed. Figure 4 Only one packaging area is shown as an example, and the scribe line area and other packaging areas are not shown.

[0079] like Figure 4 As shown in the second figure, a second substrate 212 is provided, the upper surface of the second substrate 212 has a plurality of discrete third solder pads 203, and the lower surface of the second substrate 212 has a plurality of discrete fourth solder pads 204; a metal core ball is mounted on the surface of part of the fourth solder pads 204 on the lower surface of the second substrate 212, and the metal core ball includes a metal core 208 located in the center and a coating solder layer 207 coating the metal core 208, and the diameter of the metal core 208 is less than or equal to 75% of the diameter of the metal core ball.

[0080] In some embodiments, corresponding to the first substrate 211 , the second substrate 212 may also include a plurality of discrete packaging areas and cutting road areas between the packaging areas, and the metal core ball is mounted on each packaging area of ​​the second substrate 212 .

[0081] like Figure 4 As shown in the third figure, the second substrate 212 is mounted on the upper surface of the first substrate 211, and the coated solder layer 207 in the metal core ball on the lower surface of the second substrate 212 is welded to the top surface of the metal column 206 on the upper surface of the first substrate 211 to form an inter-board connection structure.

[0082] like Figure 4 As shown in the fourth figure, a plastic encapsulation layer 213 is filled between the first substrate 211 and the second substrate 212, and the plastic encapsulation layer 213 covers the first semiconductor chip 111 and the inter-board connection structure.

[0083] The forming method may further include: Figure 4 As shown in the fifth figure, the first substrate 212 and the second substrate 212 are cut along the cutting line area to form a plurality of discrete packaging structures; an external solder bump 209 is formed on the surface of the second pad 202 on the lower surface of the second substrate 212 of each discrete packaging structure.

[0084] In some embodiments, the height of the metal pillar 206 is 20% to 40% of the distance between the upper surface of the first substrate 211 and the lower surface of the second substrate 212 , and the diameter of the metal core ball is 60% to 80% of the distance between the upper surface of the first substrate 211 and the lower surface of the second substrate 212 .

[0085] In some embodiments, the metal core ball further includes a metal bonding layer between the cladding solder layer 207 and the metal core 208 .

[0086] In some embodiments, the diameter of the metal core 208 is 65%-75% of the diameter of the metal core ball, the thickness of the metal bonding layer on the surface of the metal core 208 is 1%-5% of the diameter of the metal core ball, and the thickness of the coating solder layer 207 on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball.

[0087] In some embodiments, the spacing between the upper surface of the first substrate 211 and the lower surface of the second substrate 212 ranges from 220 microns to 250 microns, the height of the metal column 206 ranges from 45 microns to 70 microns, the diameter of the metal core 208 ranges from 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core 208 ranges from 1 micron to 4 microns, and the thickness of the coated solder layer 207 on the surface of the metal bonding layer ranges from 20 microns to 40 microns.

[0088] In some embodiments, it also includes: mounting a second semiconductor chip on the upper surface of the second substrate 212, the second semiconductor chip is electrically connected to the third pad 203 on the upper surface of the second substrate 212; and forming an external solder bump on the surface of the second pad 202 on the lower surface of the first substrate 211.

[0089] In some other embodiments of the present application, a method for forming a packaging structure is also provided. Figure 5 , the forming method comprises:

[0090] like Figure 5As shown in the second figure, a first substrate 211 is provided, wherein the upper surface of the first substrate 211 has a plurality of discrete first pads 201, and the lower surface of the first substrate 211 has a plurality of discrete second pads 202; a first semiconductor chip 111 is flip-mounted on a portion of the upper surface of the first substrate 211, and the first semiconductor chip 111 is electrically connected to a portion of the first pads 201; a metal core ball is mounted on a portion of the surface of the first pads 201 surrounding the first semiconductor chip 111, and the metal core ball includes a metal core 208 located at the center and a coating solder layer 207 coating the metal core 208, and the diameter of the metal core 208 is less than or equal to 75% of the diameter of the metal core ball;

[0091] like Figure 5 As shown in the first figure, a second substrate 212 is provided, the upper surface of the second substrate 212 has a plurality of discrete third pads 203, and the lower surface of the second substrate 212 has a plurality of discrete fourth pads 204; a metal column 206 is formed on the surface of a portion of the third pads 203 on the lower surface of the second substrate 212;

[0092] like Figure 5 As shown in the third figure, the second substrate 212 is mounted on the upper surface of the first substrate 211, and the coated solder layer 207 in the metal core ball on the upper surface of the first substrate 211 is welded with the top surface of the metal column 206 on the lower surface of the second substrate 212 to form an inter-board connection structure;

[0093] like Figure 5 As shown in the fourth figure, a plastic encapsulation layer 213 is filled between the first substrate 211 and the second substrate 212, and the plastic encapsulation layer 213 covers the first semiconductor chip 111 and the inter-board connection structure.

[0094] The forming method may further include: Figure 5 As shown in the fifth figure, the first substrate 212 and the second substrate 212 are cut along the cutting line area to form a plurality of discrete packaging structures; an external solder bump 209 is formed on the surface of the second pad 202 on the lower surface of the second substrate 212 of each discrete packaging structure.

[0095] In some other embodiments of the present application, a method for forming a packaging structure is also provided. Figure 3 , the forming method comprises:

[0096] A first substrate 211 is provided, wherein the upper surface of the first substrate 211 has a plurality of discrete first pads 201, and the lower surface of the first substrate 211 has a plurality of discrete second pads 202; a first semiconductor chip 111 is flip-mounted on a portion of the upper surface of the first substrate 211, and the first semiconductor chip 111 is electrically connected to a portion of the first pads 201; a second metal core ball is mounted on a portion of the surface of the first pads 201 around the first semiconductor chip 111, wherein the second metal core ball includes a second metal core 208b located at the center and a second coating solder layer 207b coating the second metal core 208b, and the diameter of the second metal core 208b in the second metal core ball is less than or equal to 75% of the diameter of the second metal core ball; a first metal column 206a is formed on the surface of the first pads 201 between adjacent first metal core balls;

[0097] A second substrate 212 is provided, wherein the upper surface of the second substrate 212 has a plurality of discrete third pads 203, and the lower surface of the second substrate 212 has a plurality of discrete fourth pads 204; second metal pillars 206b are formed on the surfaces of some of the fourth pads 204; first metal core balls are mounted on the surfaces of the fourth pads 204 between adjacent second metal pillars 206b, wherein the first metal core balls include a first metal core 208a located at the center and a first coating solder layer 207a coating the first metal core 208a, and the diameter of the first metal core 208a in the first metal core ball is less than 75% of the diameter of the first metal core ball;

[0098] The second substrate 212 is mounted on the upper surface of the first substrate 211, and the second cladding solder layer 207b in the second metal core ball on the upper surface of the first substrate 211 is welded to the bottom surface of the second metal column 206b corresponding to the lower surface of the second substrate 212 to form a second inter-board connection structure, and the first cladding solder layer 207a in the first metal core ball on the lower surface of the second substrate 212 is welded to the top surface of the first metal column 206a corresponding to the upper surface of the first substrate 211 to form a first inter-board connection structure;

[0099] A plastic encapsulation layer 213 is filled between the first substrate 211 and the second substrate 212 , and the plastic encapsulation layer 213 covers the first semiconductor chip 111 and the inter-board connection structure.

[0100] It should be noted that the terms "including" and "having" and their variations involved in this application are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the embodiments in this application and the features in the embodiments can be combined with each other unless there is a conflict. In addition, in the above description, the description of well-known components and technologies has been omitted to avoid unnecessary confusion of the concepts of this application. In the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to (or referenced) with each other.

[0101] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A packaging structure, characterized in that: include: A first substrate, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; A first semiconductor chip is flip-mounted on a portion of the upper surface of the first substrate and is electrically connected to a portion of the first pads on the upper surface of the first substrate; A second substrate, located above the first semiconductor chip and the first substrate, the upper surface of the second substrate having a plurality of discrete third pads, and the lower surface of the second substrate having a plurality of discrete fourth pads; A plurality of discrete inter-board connection structures, located between the first substrate and the second substrate, electrically connecting a first pad on the upper surface of the first substrate to a fourth pad corresponding to the lower surface of the second substrate, the inter-board connection structures comprising a metal column located on a surface of the first pad on the upper surface of the first substrate or a surface of the fourth pad on the lower surface of the second substrate and a metal core ball located on a top surface or a bottom surface of the metal column, the metal core ball comprising a metal core located at the center and a coating solder layer coating the metal core, and a diameter of the metal core is less than or equal to 75% of a diameter of the metal core ball; The plastic packaging layer is filled between the first substrate and the second substrate and covers the first semiconductor chip and the inter-board connection structure.

2. The packaging structure according to claim 1, characterized in that: The diameter of the metal column is smaller than the diameter of the metal core ball, the height of the metal column is 20% to 40% of the distance between the upper surface of the first substrate and the lower surface of the second substrate, and the diameter of the metal core ball is 60% to 80% of the distance between the upper surface of the first substrate and the lower surface of the second substrate.

3. The packaging structure according to claim 1 or 2, characterized in that: The metal core ball further includes a metal bonding layer located between the cladding solder layer and the metal core.

4. The packaging structure according to claim 3, characterized in that: The diameter of the metal core is 65%-75% of the diameter of the metal core ball, the thickness of the metal bonding layer on the surface of the metal core is 1%-5% of the diameter of the metal core ball, and the thickness of the coating solder layer on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball.

5. The packaging structure according to claim 4, characterized in that: The spacing between the upper surface of the first substrate and the lower surface of the second substrate ranges from 170 microns to 250 microns, the height of the metal column ranges from 45 microns to 70 microns, the diameter of the metal column ranges from 130 microns to 160 microns, the diameter of the metal core is 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core is 1 micron to 4 microns, and the thickness of the coated solder layer on the surface of the metal bonding layer is 20 microns to 40 microns.

6. The packaging structure according to claim 3, characterized in that: The metal pillar and the metal core are made of copper, tungsten or aluminum, the metal bonding layer is made of nickel or titanium, and the coating solder layer is made of tin or tin alloy.

7. The packaging structure according to claim 1, characterized in that: Among the several discrete inter-board connection structures, the metal column of each of the inter-board connection structures is located on the surface of the first pad on the upper surface of the first substrate, and the metal core ball is located on the top surface of the metal column that is not in contact with the first pad and is in contact with the fourth pad on the lower surface of the second substrate.

8. The packaging structure according to claim 1, characterized in that: Among the several discrete inter-board connection structures, the metal column of each of the inter-board connection structures is located on the surface of the fourth pad on the lower surface of the second substrate, and the metal core ball is located on the bottom surface of the metal column that is not in contact with the fourth pad and is in contact with the first pad on the upper surface of the first substrate.

9. The packaging structure according to claim 1, characterized in that: The several discrete inter-board connection structures include a plurality of first inter-board connection structures and a plurality of second inter-board connection structures, and the first inter-board connection structures and the second inter-board connection structures are spaced apart between the first substrate and the second substrate, and each of the first inter-board connection structures includes a first metal column on the surface of the first pad on the upper surface of the first substrate and a first metal core ball located on the top surface of the first metal column, the first metal core ball including a first metal core located in the center and a first coating solder layer covering the first metal core; each of the second inter-board connection structures includes a second metal column on the surface of the fourth pad on the lower surface of the second substrate and a second metal core ball located on the bottom surface of the second metal column, the second metal core ball including a second metal core and a second coating solder layer covering the second metal core.

10. The packaging structure according to claim 1, wherein: The packaging structure also includes: a second semiconductor chip mounted on the upper surface of the second substrate, the second semiconductor chip is electrically connected to the third pad on the upper surface of the second substrate; and an external solder bump located on the surface of the second pad on the lower surface of the first substrate.

11. A method for forming a packaging structure, characterized in that: include: A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; and a metal column is formed on a surface of a portion of the first pads around the first semiconductor chip; A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; a metal core ball is mounted on the surface of a portion of the fourth pads on the lower surface of the second substrate, wherein the metal core ball comprises a metal core located at the center and a coating solder layer coating the metal core, and the diameter of the metal core is less than or equal to 75% of the diameter of the metal core ball; Mounting the second substrate on the upper surface of the first substrate, and welding the coating solder layer in the metal core ball on the lower surface of the second substrate and the top surface of the metal column on the upper surface of the first substrate together to form an inter-board connection structure; A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

12. The method for forming a package structure according to claim 11, wherein: The height of the metal column is 20% to 40% of the distance between the upper surface of the first substrate and the lower surface of the second substrate, and the diameter of the metal core ball is 60% to 80% of the distance between the upper surface of the first substrate and the lower surface of the second substrate.

13. The method for forming a package structure according to claim 12, wherein: The metal core ball further includes a metal bonding layer located between the cladding solder layer and the metal core.

14. The method for forming a package structure according to claim 13, wherein: The diameter of the metal core is 65%-75% of the diameter of the metal core ball, the thickness of the metal bonding layer on the surface of the metal core is 1%-5% of the diameter of the metal core ball, and the thickness of the coating solder layer on the surface of the metal bonding layer is 7.5%-16.5% of the diameter of the metal core ball.

15. The method for forming a package structure according to claim 14, wherein: The spacing between the upper surface of the first substrate and the lower surface of the second substrate ranges from 170 microns to 250 microns, the height of the metal column ranges from 45 microns to 70 microns, the diameter of the metal core is 120 microns to 160 microns, the thickness of the metal bonding layer on the surface of the metal core is 1 micron to 4 microns, and the thickness of the coated solder layer on the surface of the metal bonding layer is 20 microns to 40 microns.

16. The method for forming a package structure according to claim 11, wherein: Also includes: A second semiconductor chip is mounted on the upper surface of the second substrate, and the second semiconductor chip is electrically connected to a third pad on the upper surface of the second substrate; and an external solder bump is formed on the surface of the second pad on the lower surface of the first substrate.

17. A method for forming a packaging structure, characterized in that: include: A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; a metal core ball is mounted on a portion of the first pads surrounding the first semiconductor chip, wherein the metal core ball comprises a metal core located at the center and a coating solder layer coating the metal core, and the diameter of the metal core is less than or equal to 75% of the diameter of the metal core ball; A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; and metal pillars are formed on the surfaces of some of the fourth pads on the lower surface of the second substrate; Mounting the second substrate on the upper surface of the first substrate, and welding the coating solder layer in the metal core ball on the upper surface of the first substrate and the bottom surface of the metal column on the lower surface of the second substrate together to form an inter-board connection structure; A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

18. A method for forming a packaging structure, characterized in that: include: A first substrate is provided, wherein the upper surface of the first substrate has a plurality of discrete first pads, and the lower surface of the first substrate has a plurality of discrete second pads; a first semiconductor chip is flipped on a portion of the upper surface of the first substrate, and the first semiconductor chip is electrically connected to a portion of the first pads; a second metal core ball is mounted on a portion of the first pad surface surrounding the first semiconductor chip, the second metal core ball includes a second metal core located at the center and a second coating solder layer coating the second metal core, and the diameter of the second metal core in the second metal core ball is less than or equal to 75% of the diameter of the second metal core ball; a first metal column is formed on the surface of the first pad between adjacent second metal core balls; A second substrate is provided, wherein the upper surface of the second substrate has a plurality of discrete third pads, and the lower surface of the second substrate has a plurality of discrete fourth pads; second metal pillars are formed on the surfaces of some of the fourth pads; first metal core balls are mounted on the surfaces of the fourth pads between adjacent second metal pillars, wherein the first metal core balls include a first metal core located at the center and a first coating solder layer coating the first metal core, and the diameter of the first metal core in the first metal core ball is less than 75% of the diameter of the first metal core ball; Mounting the second substrate on the upper surface of the first substrate, welding the second cladding solder layer in the second metal core ball on the upper surface of the first substrate and the bottom surface of the second metal column corresponding to the lower surface of the second substrate to form a second inter-board connection structure, welding the first cladding solder layer in the first metal core ball on the lower surface of the second substrate and the top surface of the first metal column corresponding to the upper surface of the first substrate to form a first inter-board connection structure; A plastic encapsulation layer is filled between the first substrate and the second substrate, and the plastic encapsulation layer covers the first semiconductor chip and the inter-board connection structure.

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