Package substrate, package device and design method of package substrate

Abstract

The invention relates to the technical field of packaging, and discloses a packaging substrate, a packaging device and a design method of the packaging substrate, the packaging substrate comprises a plurality of conductive layers stacked in the thickness direction of the packaging substrate and insulating layers formed between every two adjacent conductive layers, and the insulating layers comprise a first insulating layer with a target hole structure and a second insulating layer with a target hole structure; the second insulating layer is provided with a porous structure, and the porous structure comprises at least two via hole structures; wherein in the two conducting layers adjacent to the second insulating layer, the conducting layer away from the first insulating layer is provided with a target bonding pad, the at least two via hole structures are electrically connected with the target bonding pad, and the target bonding pad is electrically connected with the target hole structure through the at least two via hole structures, so that a signal link in the packaging substrate is formed. The technical effect of improving the signal transmission quality is achieved through a single-layer porous impedance optimization mode.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a packaging substrate, a packaging device, and a design method for a packaging substrate. Background Art

[0002] Since impedance discontinuity (such as impedance mismatch, excessive insertion loss, etc.) can cause signal reflection, distortion and attenuation, the impedance of the signal link needs to be controlled within a certain range when designing the packaging substrate to ensure signal quality, especially for high-speed signal links.

[0003] In the related art, impedance optimization is usually performed on signal routing, such as changing line width and line spacing, materials, stacking thickness, via size, etc. Although impedance optimization can be performed using related technologies, the signal transmission quality in the package substrate still needs to be further improved. Summary of the invention

[0004] The present application provides a packaging substrate, a packaging device and a packaging substrate design method, which improve the impedance discontinuity problem of a signal link in the packaging substrate and achieve the technical effect of effectively improving the signal transmission quality.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides a packaging substrate, the packaging substrate comprising a plurality of conductive layers stacked in a thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers, the insulating layer comprising:

[0007] A first insulating layer having a target hole structure, wherein the target hole structure electrically connects two conductive layers adjacent to the first insulating layer;

[0008] A second insulating layer has a porous structure, wherein the porous structure includes at least two via structures, and the at least two via structures are electrically connected to two conductive layers adjacent to the second insulating layer;

[0009] Among them, among the two conductive layers adjacent to the second insulating layer, the conductive layer away from the first insulating layer has a target pad, and the at least two via structures are electrically connected to the target pad. The electrical connection between the target pad and the target hole structure is achieved through the at least two via structures to form a signal link in the packaging substrate.

[0010] In the above embodiment, the package substrate includes a first insulating layer having a target hole structure and a second insulating layer having a porous structure. The porous structure includes at least two via structures. In the two conductive layers adjacent to the second insulating layer, a target pad is provided on the conductive layer away from the first insulating layer, and the at least two via structures are electrically connected to the target pad. The electrical connection between the target pad and the target hole structure is achieved through the at least two via structures to form a signal link in the package substrate. By adopting a single-layer porous impedance optimization method in the second insulating layer, the discontinuity of the signal link impedance in the package substrate is improved, thereby improving the signal transmission quality.

[0011] Optionally, a third insulating layer is provided between the first insulating layer and the second insulating layer; the second insulating layer has a first porous structure; the third insulating layer has a second porous structure; wherein the electrical connection between the target pad and the target hole structure is achieved through the first porous structure and the second porous structure, and the number of via structures in the second porous structure is less than the number of via structures in the first porous structure.

[0012] In the above embodiment, porous structures are arranged in the second insulating layer and the third insulating layer, and the number of via structures in the second porous structure is less than the number of via structures in the first porous structure. The impedance mutation is further mitigated by gradually reducing the number of via structures in some insulating layers.

[0013] Optionally, the packaging substrate also includes a conductive pad; the conductive pad is located in two conductive layers adjacent to the second insulating layer, on a conductive layer close to the first insulating layer; the second insulating layer has a first porous structure, and the first ends of at least two via structures of the first porous structure pass through the conductive pad; wherein, the electrical connection between the target pad and the target hole structure is achieved through the first porous structure and the conductive pad, and the first end is an end of the via structure away from the target pad.

[0014] In the above embodiment, the first ends of at least two via structures of the first porous structure penetrate the conductive pad, and the conductive pad is connected to the at least two via structures of the first porous structure, which is conducive to realizing the signal link after the impedance is optimized in the packaging substrate.

[0015] Optionally, a third insulating layer is provided between the first insulating layer and the second insulating layer, and the third insulating layer has a second porous structure; the second ends of at least two via structures of the second porous structure and the first ends of at least two via structures of the first porous structure pass through the same conductive pad; wherein, the electrical connection between the target pad and the target hole structure is achieved through the first porous structure, the conductive pad and the second porous structure, and the second end is an end of the via structure close to the target pad.

[0016] In the above embodiment, the second ends of at least two via structures of the second porous structure and the first ends of at least two via structures of the first porous structure pass through the same conductive pad, which is beneficial to realize the signal link with optimized impedance in the packaging substrate.

[0017] Optionally, the conductive pad includes a plurality of first via pads, and adjacent first via pads are tangent to each other; the via structures correspond to the first via pads one by one, and the via structures penetrate the corresponding first via pads.

[0018] Optionally, the target pad includes a package pad, and the package pad is used to connect to a circuit board; at least two via structures in the porous structure of the second insulating layer are arranged on a surface of the package pad away from the circuit board. The impedance discontinuity at the package pad is improved by arranging at least two via structures in the second insulating layer on the package pad.

[0019] Optionally, the insulating layer further includes a core layer; the first insulating layer includes a first build-up layer, the target hole structure is a buried hole penetrating the first build-up layer and electrically connecting two conductive layers adjacent to the first build-up layer; the second insulating layer includes a second build-up layer, and the first build-up layer and the second build-up layer are both located between the core layer and the package pad. The impedance discontinuity between the package pad and the single buried hole in the corresponding build-up layer is improved by at least two via structures in the second build-up layer.

[0020] Optionally, the insulating layer further comprises a core layer, a third build-up layer and a fourth build-up layer which are stacked; the third build-up layer is located between the core layer and the fourth build-up layer; the third build-up layer has the porous structure, and the fourth build-up layer has the target hole structure; wherein the fourth build-up layer, the third build-up layer and the core layer are stacked in sequence along a preset direction, or the core layer, the third build-up layer and the fourth build-up layer are stacked in sequence along the preset direction; the preset direction is the direction from the circuit board to the package substrate. The impedance discontinuity between the via pad of the core hole structure and the single buried hole in the corresponding build-up layer is improved by the porous structure in the third build-up layer.

[0021] Optionally, the insulating layer also includes a core layer, a fifth buildup layer, and a sixth buildup layer, the fifth buildup layer is adjacent to the core layer and is located between the core layer and the sixth buildup layer; the core layer has a core hole structure, and the core hole structure electrically connects two conductive layers adjacent to the core layer; any conductive layer adjacent to the core layer has a second via pad with the core hole structure, and the target pad includes the second via pad with the core hole structure; the first insulating layer includes the sixth buildup layer; and the second insulating layer includes the fifth buildup layer.

[0022] Optionally, the packaging substrate is provided with at least one layer of anti-pad arranged opposite to the packaging pad; the hollowing size and / or the number of hollowing layers of the anti-pad are adjusted according to the target impedance value, and the target impedance value is determined based on the signal target resistance value and the impedance at the socket, and the socket is used to connect the packaging substrate and the circuit board.

[0023] Optionally, the target impedance value is determined based on an intermediate value of the signal target resistance value and the impedance at the socket.

[0024] In the above embodiment, compared with the related art in which the impedance at the package pad is raised to the signal target resistance value by adjusting the anti-pad hollowing size and / or the number of anti-pad hollowing layers, the present application uses the intermediate value between the signal target resistance value and the impedance at the socket as the target impedance value for optimization processing, thereby slowing down the impedance mutation and making its impedance curve smoother, so as to reduce the impact of the impedance discontinuity at this location.

[0025] In a second aspect, an embodiment of the present application provides a packaging device, comprising a packaging substrate as described in any one of the above-mentioned first aspects.

[0026] In a third aspect, an embodiment of the present application provides a design method for a packaging substrate, wherein the packaging substrate includes a plurality of conductive layers stacked in a thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers; the method includes: determining a first insulating layer and a second insulating layer; setting a target hole structure in the first insulating layer; wherein the target hole structure electrically connects two conductive layers adjacent to the first insulating layer; setting a porous structure in the second insulating layer, and determining the number of via structures in the porous structure; wherein the porous structure includes at least two via structures, wherein the at least two via structures electrically connect two conductive layers adjacent to the second insulating layer, and among the two conductive layers adjacent to the second insulating layer, a conductive layer away from the first insulating layer has a target pad; the at least two via structures are electrically connected to the target pad, and the electrical connection between the target pad and the target hole structure is achieved through the at least two via structures to form a signal link in the packaging substrate.

[0027] In the above embodiment, first, the first insulating layer and the second insulating layer are determined, and then, a target hole structure is set in the first insulating layer; and a porous structure is set in the second insulating layer, and the number of via structures in the porous structure is determined. By adopting a single-layer porous impedance optimization method in the second insulating layer, the problem of impedance discontinuity of the signal link in the packaging substrate is optimized, thereby improving the signal quality.

[0028] Optionally, the first insulating layer and the second insulating layer are determined in the following manner, including:

[0029] If the target pad is a package pad, determine the core layer, determine the insulating layer closest to the package pad as the second insulating layer; determine the first insulating layer in the insulating layer between the second insulating layer and the core layer; or

[0030] A core layer is determined, a buildup layer adjacent to the core layer is determined as the second insulating layer, and a buildup layer adjacent to the second insulating layer is determined as the first insulating layer.

[0031] Optionally, the packaging substrate is provided with at least one layer of anti-pad arranged opposite to the packaging pad; the method further includes: determining a target impedance value based on a signal target resistance value and an impedance at a socket; wherein the socket is used to connect the packaging substrate and a circuit board; and adjusting a hollow size and / or a number of hollow layers of the anti-pad according to the target impedance value.

[0032] Optionally, the target impedance value is determined based on an intermediate value of the signal target resistance value and the impedance at the socket. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1a A schematic diagram of a packaging structure provided in an embodiment of the present application;

[0035] Figure 1b A schematic diagram of a laminated structure inside a packaging substrate provided in an embodiment of the present application;

[0036] Figure 1c A schematic cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0037] Figure 1d A schematic diagram of a signal link in a packaging substrate provided in an embodiment of the present application;

[0038] Figure 1e A schematic diagram of a hole in a packaging substrate provided in an embodiment of the present application;

[0039] Figure 1f A schematic diagram of a 10-layer LGA package substrate provided in an embodiment of the present application;

[0040] Figure 2a A schematic cross-sectional view of a first insulating layer provided in an embodiment of the present application;

[0041] Figure 2b A schematic cross-sectional view of a second insulating layer provided in an embodiment of the present application;

[0042] Figure 2c A schematic diagram of a target pad provided by an embodiment of the present application;

[0043] Figure 2d A schematic diagram of a target pad provided in yet another embodiment of the present application;

[0044] Figure 3 A schematic diagram of a portion of a signal link within a packaging substrate provided in an embodiment of the present application;

[0045] Figure 4 A schematic cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0046] Figure 5a A schematic cross-sectional view of a packaging substrate provided in one embodiment of the present application;

[0047] Figure 5b A schematic cross-sectional view of a packaging substrate provided in yet another embodiment of the present application;

[0048] Figure 6a A schematic cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0049] Figure 6b A schematic diagram of a conductive layer in a packaging substrate provided in an embodiment of the present application;

[0050] Figure 7a A schematic cross-sectional view of a packaging substrate provided in an embodiment of the present application;

[0051] Figure 7b A schematic diagram of a package pad provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of a portion of a signal link within a 10-layer package substrate provided in an embodiment of the present application;

[0053] Fig. 9 A schematic diagram of a conductive pad provided in an embodiment of the present application;

[0054] Fig.10a A schematic diagram of a model including a packaging structure, an LGA Socket and a circuit board provided for an embodiment of the present application;

[0055] Fig.10b The impedance curve of the DDR signal provided in the embodiment of the present application;

[0056] Fig.11 A schematic flow chart of a method for designing a packaging substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0058] As mentioned in the background technology, when designing a package substrate, the impedance of the signal link needs to be controlled within a certain range to ensure signal quality, especially for high-speed signal links. If the high-speed signal link deviates from the target value within a certain range or the impedance changes suddenly, it is possible that the signal quality will not meet the standard. Therefore, the optimization effect of signal impedance continuity is particularly important for high-speed signals.

[0059] See also Figure 1a , an LGA (Land Grid Array) packaging structure is used as an example for exemplary description. The LGA substrate 110 is connected to the bare die 120 (DIE) and the circuit board 130 (PCB). Specifically, the LGA substrate involves a Bump Pad (or Bump Pin), an LGA Pad (or LGA Pin) and an LGA Socket. Among them, the LGA substrate 110 is connected to the bare die 120 through the Bump Pad. The LGA substrate 110 is connected to the circuit board 130 through the LGA Pad and the LGA Socket.

[0060] See also Figure 1b The laminated structure inside the package substrate includes a plurality of conductive layers stacked and an insulating layer formed between two adjacent conductive layers. The conductive layer may also be called a metal layer, and the insulating layer may also be called a dielectric layer. Figure 1bThe multiple straight lines in represent different conductive layers, which are used for wiring and laying power planes and ground planes. The materials of the conductive layers are all conductive metals. In the direction where the bare chip points to the circuit board PCB, the Bump Pad is located at the topmost conductive layer among the multiple conductive layers, and the LGA Pad is located at the bottommost conductive layer among the multiple conductive layers. The multiple insulating layers between the topmost conductive layer and the topmost conductive layer include a core layer (also called a CORE layer) and multiple buildup layers (also called non-CORE layers). The thickness of the core layer is different from the thickness of the buildup layer, and the material of the core layer is different from the material of the buildup layer. The function of the core layer is to maintain the strength of the substrate. Usually, the stacked buildup layers located on the upper and lower sides of the core layer are symmetrically distributed with the core layer as the symmetry line. A through hole (PTH) penetrating the core layer is provided in the core layer. If electrical connection is required between different conductive layers, a blind via (Bb Via, referred to as Via) is provided through the corresponding buildup layer. Among them, blind vias are collectively referred to as blind vias and buried vias. Blind vias can be understood as the type of vias that connect the inner wiring (or plane) of the substrate with the surface wiring (or plane or PIN) of the substrate. Blind vias do not penetrate the entire substrate. Buried vias can be understood as the type of vias that only connect the wiring (or plane) between the inner layers of the substrate, so they cannot be seen from the surface of the substrate.

[0061] See also Figure 1c , Figure 1c A schematic cross-sectional view of a package substrate is shown. Figure 1c The top black layer represents the bare die 120 (DIE). Figure 1c The mesoporous structure 101, the pore structure 106, the pore structure 105, and the pore structure 109 are blind holes. Figure 1c The middle hole structure 102, hole structure 103, hole structure 104, hole structure 107, and hole structure 108 are buried holes, and hole structure 103 is a via hole of the core layer, which penetrates the core layer and connects the signal lines in the upper and lower conductive layers of the core layer. It should be noted that the hole structure 103 can be distributed in two conductive layers and one insulating layer. The hollowing of the core layer via is carried out in other metal layers.

[0062] Anti-pad is introduced as an example. For elements such as holes, wires, PADs, etc. in a certain plane, if their net is different from the plane, it is necessary to leave a certain distance of conductor-free area around these elements, which is called anti-pad. In other words, anti-pad refers to the conductor-free area left in wiring design to prevent short circuit between conductor and metal layer.

[0063] Hollowing is introduced as an example. In the package substrate, except for elements such as pads, signal lines, blind and buried vias and their surrounding areas, other areas in the metal layer are generally covered with ground planes or power planes (conductive metal planes) for signal reference and power supply. Due to the requirements of signal design, the reference plane of high-speed signals (that is, the metal planes of the upper and lower layers of the signal line) is generally a ground plane. In order to meet some special design requirements, some small pieces of the planes will be intentionally dug out in certain areas of these planes to make them metal-free areas, which is called hollowing.

[0064] This is an example of a signal chain in a package substrate. Figure 1d , Figure 1d The figure shows the signal link between BUMPPAD and LGA PAD in the package substrate: BUMPPAD→via→line→via→line→Core via→line→via→line→via→LGA PAD. Usually, BUMPPAD and LGA PAD have a one-to-one connection relationship. They are connected by metal lines in the XY plane and by blind buried vias in the Z direction. It should be noted that the Z direction is parallel to the direction of the die pointing to the circuit board PCB, and the XY plane is a plane perpendicular to the Z direction.

[0065] Furthermore, due to the structure of the substrate and the number of blind and buried vias, it is necessary to connect the BUMP PAD and LGAPAD through a transfer via. Figure 1e After drilling a via from metal layer Layer_A to metal layer Layer_B, use a conductive wire or a conductive plane to connect to other positions of metal layer Layer_B, and then drill a via at this position to metal layer Layer_C.

[0066] The internal signal chain of the package substrate is composed of several elements, including Bump Pad, metal routing line, built-up layer blind buried vias, core layer PTH holes, and LGA Pad. In the related art, built-up layer blind buried vias are set on the Bump Pad, connected to the routing layer, and then connected to the top of the LGA Pad with a microstrip line. Among them, the Bump Pad is connected to the LGA Pad through the core layer PTH hole and the blind buried via in the built-up layer. In any built-up layer, the metal layers on the upper and lower sides of the built-up layer are recorded as adjacent metal layers of the built-up layer. A single via structure is set on any built-up layer, and the two ends of the via structure have via pads. The microstrip line on the adjacent metal layer of any built-up layer is connected to the via pad of the via structure, thereby achieving connectivity. It can be seen that a single via structure is set on any built-up layer in the related art, that is, the microstrip lines in the metal layers on the upper and lower sides of the built-up layer are connected in a single-layer single-hole manner.

[0067] See also Figure 1f, exemplarily described with a 10-layer LGA package substrate. Due to the process restrictions on the number of stacking of blind buried vias on the package, such as a maximum of 3 stacking of blind buried vias, the 10-layer LGA package substrate includes metal layers L1, L2, L3, L4, L5, L6, L7, L8, L9, and L10. There are insulating layers between adjacent metal layers, such as the insulating layer L1-2 between L1 and L2, the insulating layer L2-3 between L2 and L3, the insulating layer L3-4 between L3 and L4, the insulating layer L4-5 between L4 and L5, the insulating layer L5-6 between L5 and L6, the insulating layer L6-7 between L6 and L7, the insulating layer L7-8 between L7 and L8, the insulating layer L8-9 between L8 and L9, and the insulating layer L9-10 between L9 and L10. In the 10-layer LGA package substrate, the LGA Pad is set on the metal layer L10, the Bump Pad is set on the metal layer L1, the insulating layer L5-6 between L5 and L6 is the core layer, and the other insulating layers are build-up layers. There is a blind hole in the insulating layer L1-2 and the insulating layer L9-10, and there is a buried hole in the insulating layer L2-3, the insulating layer L3-4, the insulating layer L4-5, the insulating layer L6-7, the insulating layer L7-8 and the insulating layer L8-9. The signal connection method in the packaging substrate is as follows: a blind hole in the insulating layer L1-2 is set on the Bump Pad, and after the metal layer L2 is pulled to the corresponding position of the metal layer L2 directly above the corresponding signal LGAPad through a stripline; a buried hole in each of the insulating layers L2-3, L3-4 and L4-5 is stacked as three holes, and the center positions of the three buried holes coincide; connected to the via pad of the PTH hole of the core layer through a microstrip line; connected to the buried holes in the insulating layers L6-7, L7-8 and L8-9 through the microstrip line (that is, a buried hole in each of the insulating layers L6-7, L7-8 and L8-9 is stacked as three holes, and the center positions of the three buried holes coincide); connected to a blind hole in the insulating layer L9-10 through a microstrip line, and finally connected to the LGA Pad.

[0068] It should be noted that the PTH holes in the core layer are not stacked without special processes. Both the core holes in the core layer and the blind buried holes in the build-up layers are single-layer single-hole. That is, the vias in the insulating layer L1-2, insulating layer L2-3, insulating layer L3-4, insulating layer L4-5, insulating layer L5-6, insulating layer L6-7, insulating layer L7-8, insulating layer L8-9, and insulating layer L9-10 are all one.

[0069] Please continue reading Figure 1c , Figure 1d and 1fSince the related technology adopts a single-layer single-hole approach, and the size of the core layer PTH hole is larger than the size of the build-up layer blind buried hole, the impedance discontinuity points in the package substrate include: build-up layer blind buried hole to core layer PTH hole, core layer PTH hole to build-up layer blind buried hole, build-up layer blind buried hole to LGA Pad, and LGA Pad to LGA Socket.

[0070] In view of the above-mentioned impedance discontinuity points, a single-layer porous method is proposed in the embodiment of the present application, that is, at the position of the impedance discontinuity, the impedance discontinuity in the package substrate is improved by changing the number of vias. For example, the upper layer located above the core layer and adjacent to the core layer has a porous structure, and the via structure includes at least two buried holes. Alternatively, the lower layer located below the core layer and adjacent to the core layer has the same porous structure. Alternatively, any layer with a buried hole can be selected between the lower layer and the core layer, and in the multiple layers between the LGA PAD and the layer with a buried hole, the number of via structures in each layer may be different. For example, along the direction from the LGA PAD to the core layer, the number of via structures in each layer gradually decreases. In the embodiment of the present application, the problem of impedance discontinuity of the signal link in the LGA package substrate is solved by adopting a single-layer porous method in part of the insulating layer, thereby improving the signal quality.

[0071] Taking a 10-layer LGA package substrate as an example scenario, the impedance optimization method of a single-layer porous structure proposed in the embodiment of the present application is exemplarily introduced. In several insulating layers (such as insulating layers L9-10, insulating layers L8-9, and insulating layers L7-8) located above the LGA PAD, the number of via structures in the porous structure can be gradually reduced for the impedance discontinuity point at the LGA PAD. For example, in the insulating layer L9-10 adjacent to the LGA Pad, the porous structure of the insulating layer L9-10 is provided with 4 blind holes, which are turned upward, and the porous structure of the insulating layer L8-9 is provided with 2 buried holes, which are continued to be turned upward. The insulating layer L7-8 adopts a single-layer single-hole method, that is, a buried hole is set in the insulating layer L7-8. It can be seen that by changing the number of via structures of 4-2-1, a gradually increasing buffering effect is played at the position where the impedance fluctuation of the high-speed signal is large, so as to optimize the impedance.

[0072] For example, the metal layer L10 has an LGA pad. Since the impedance of the pad decreases as the pad diameter increases, if a blind hole with an aperture of 90 microns is set in the insulating layer L9-10, there will be an impedance mutation. Therefore, four blind holes with an aperture of 90 microns are set in the insulating layer L9-10 on the LGA pad. Then, it is connected to two buried holes with an aperture of 90 microns in the insulating layer L8-9 on the side through a stripline. Then, it is connected to a buried hole with an aperture of 90 microns in the insulating layer L7-8 on the side through a stripline.

[0073] Furthermore, since the impedance of the pad decreases as the pad diameter increases, it is necessary to consider the impedance mutation between the 90-micron buried via in the insulating layer L7-8 and the PTH hole in the core layer, a porous structure is set in the insulating layer L6-7, including two buried vias with an aperture of 90 microns, and the buried vias in the insulating layer L7-8 are connected to the two buried vias with an aperture of 90 microns in the insulating layer L6-7 next to it through a stripline. Then, the two buried vias in the insulating layer L6-7 are connected to the PTH hole with an aperture of 300 microns in the core layer L5-6 next to it through a stripline.

[0074] Furthermore, since the impedance of the pad decreases as the pad diameter increases, it is necessary to consider the impedance mutation between the 90-micron buried via in the insulating layer and the core layer PTH hole. Therefore, two buried vias with an aperture of 90 microns are set in the insulating layer L4-5 layer, and the core layer PTH hole is connected to two buried vias with an aperture of 90 microns in the insulating layer L4-5 layer next to it through a stripline. Then, it is connected to a buried via with an aperture of 90 microns in the insulating layer L3-4 layer next to it through a stripline. Then, it is connected to a buried via with an aperture of 90 microns in the insulating layer L2-3 layer next to it through a stripline. After the L2 layer is extended to the position directly below the corresponding signal BUMP Pad through the stripline, it is connected to a blind via with an aperture of 90 microns in the insulating layer L1-2, overlapping with the center of the BUMP Pad, to form the entire signal link structure in the package substrate.

[0075] In this scenario example, the via design method of the insulating layer in the package substrate is not limited to a single-layer single-hole via design. Some insulating layers have a single-layer multi-hole impedance optimization method, such as 4 blind holes in the insulating layer L9-10, and 2 buried holes in the insulating layer L8-9, the insulating layer L6-7, and the insulating layer L4-5. It should be noted that the via pads of the 4 blind holes in the insulating layer L9-10 can be arranged in 2 rows and 2 columns, and the two adjacent blind holes have a tangent relationship. The via pads of the 2 buried holes in the insulating layer L8-9 have a tangent relationship at the same end. The via pads of the 2 buried holes in the insulating layer L6-7 have a tangent relationship at the same end. The via pads of the 2 buried holes in the insulating layer L4-5 have a tangent relationship at the same end.

[0076] Furthermore, the reference layer anti-pad hollowing out for BGA Pad is introduced as an example. Since the larger the diameter of the pad, the stronger the fringe field coupling between the pad and the surrounding conductor will be, which is equivalent to increasing the capacitive load, the impedance of the pad decreases as the pad diameter increases. And the larger the anti-pad diameter, the more hollowing layers there are, and the higher the corresponding impedance, so the hollowing size is usually the BGA Pad size or larger. The impedance of the BGA PAD is increased to the target impedance by increasing the distance between the BGA PAD and the reference layer.

[0077] However, when facing LGA high-speed signals, the above-mentioned anti-pad hollowing method is no longer applicable due to the large size of LGA PAD. For example, the BGA Pad size is a 500 micron (um) disc, while the LGA Pad size is a 780um*620um square disc. The impedance at the LGAPad position is lower than that at the BGA Pad position. For the punching method, the impedance at the LGA pad is lower, and the impedance difference from the LGAPad to the via is larger than that of the BGA package, which has a greater impact on the signal quality. And for BGA, the impedance corresponding to the BGA Pad and the BGA solder ball position is relatively low, so raising the impedance at the corresponding position of the pad is a positive treatment, while the impedance at the LGA Pad is low, and the impedance at the LGA Socket position connected to it is relatively high. If the impedance at the Pad position is raised to the signal target resistance value and connected to the LGA Socket with relatively high impedance, there is still a difference between the two, resulting in impedance discontinuity (i.e., the impedance discontinuity point from the LGA Pad to the LGA Socket), which will also affect the signal quality.

[0078] After analysis, it is found that the method of hollowing out the anti-pad according to the signal target resistance value cannot solve the impedance discontinuity problem. Therefore, it is necessary to improve the method of hollowing out the anti-pad in the related art. In the embodiment of the present application, the target impedance value is reset, and the anti-pad hollowing size and the number of anti-pad hollowing layers are adjusted according to the new target impedance value. Considering that the high impedance of the LGA Socket is the cause of the impedance discontinuity point from LGA Pad to LGA Socket, the high impedance of the LGASocket is taken into consideration when resetting the target impedance value. Specifically, the new target impedance value is determined according to the signal target resistance value and the impedance value of the LGASocket. For example, the new target impedance value is equal to half of the sum of the signal target resistance value and the impedance value of the LGA Socket.

[0079] In the embodiment of the present application, by adjusting the hollowing size and / or the number of hollowing layers of the anti-pad according to the new target impedance value to perform impedance optimization processing, the impedance mutation from LGA Pad to LGA Socket can be slowed down, making its impedance curve smoother, thereby reducing the impact of the impedance discontinuity at this location.

[0080] In an embodiment of the present application, a packaging substrate is provided, which includes a plurality of conductive layers stacked in the thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers, and the number of the insulating layers is multiple. Figure 2a , Figure 2b , Figure 2c and Figure 2d , multiple insulation layers include:

[0081] The first insulating layer 210 has a target hole structure 212 , and the target hole structure 212 electrically connects two conductive layers adjacent to the first insulating layer 210 .

[0082] The second insulating layer 220 has a porous structure 222 , wherein the porous structure 222 includes at least two via structures 228 , and the at least two via structures 228 electrically connect two conductive layers adjacent to the second insulating layer.

[0083] Among them, among the two conductive layers adjacent to the second insulating layer 220, a target pad 230 is provided on the conductive layer away from the first insulating layer, and at least two via structures 228 are electrically connected to the target pad 230. The electrical connection between the target pad 230 and the target hole structure 212 is realized through at least two via structures 228 to form a signal link in the packaging substrate.

[0084] In this embodiment, please refer to Figure 2a The first insulating layer 210 has a target hole structure 212, and two conductive layers adjacent to the first insulating layer 210 are a first conductive layer 214 and a second conductive layer 216. The first conductive layer 214 and the second conductive layer 216 are electrically connected through the target hole structure 212. The first conductive layer 214 is far away from the second insulating layer 220, and the second conductive layer 216 is close to the second insulating layer 220.

[0085] In this embodiment, please refer to Figure 2b , the second insulating layer 220 has a porous structure 222, and the two conductive layers adjacent to the second insulating layer 220 are the third conductive layer 224 and the fourth conductive layer 226. The porous structure 222 includes at least two via structures 228, and the at least two via structures 228 electrically connect the third conductive layer 224 and the fourth conductive layer 226. Among them, the third conductive layer 224 is close to the first insulating layer 210, and the fourth conductive layer 226 is far away from the first insulating layer 210. It should be noted that the second conductive layer 216 and the third conductive layer 224 can be located in the same conductive layer or in different conductive layers. Each via structure 228 has a corresponding first via pad, and the via structure 228 passes through the corresponding first via pad, and the first via pads of each via structure 228 at the same end of the porous structure 222 are in contact with each other.

[0086] In this embodiment, a target pad is provided on the fourth conductive layer 226. The target pad may be a package pad, a via pad of a core hole in a core layer, or a pad of a via hole with a larger size in other insulating layers.

[0087] It should be noted that the target hole structure 212 is a blind buried hole in the first insulating layer 210. There is a large size difference between the blind buried hole in the first insulating layer 210 and the target pad (such as the package pad or the via pad of the core hole in the core layer), and this size difference causes the impedance discontinuity problem in the package substrate. Therefore, it is necessary to use a single-layer multi-porous method in the insulating layer between the blind buried hole and the target pad in the first insulating layer 210 to reduce the impedance mutation and improve the impedance discontinuity problem in the package substrate.

[0088] See also Figure 2c , at least two via structures 228 can be set on the target pad 230 in the fourth conductive layer 226. Further, the target hole structure 212 can be electrically connected to the at least two via structures 228 through the microstrip line in the second conductive layer 216 and the microstrip line in the third conductive layer 224, and at least two via structures 228 are electrically connected to the target pad 230. At this point, the electrical connection between the target hole structure 212 and the target pad 230 is achieved through the porous structure 222. In addition, the impedance mutation between the target hole structure 212 and the target pad 230 is mitigated by the at least two via structures 228 in the porous structure 222, so that the impedance curve is smoother. It can be understood that Figure 2c The gap between adjacent via structures 228 may be understood as a margin left in the design.

[0089] See also Figure 2d , one end of at least two via structures 228 facing the fourth conductive layer 226 may be located at a suitable position in the fourth conductive layer 226 except for the target pad 230. Further, the target hole structure 212 may be electrically connected to the at least two via structures 228 through the microstrip line in the second conductive layer 216 and the microstrip line in the third conductive layer 224, and the at least two via structures 228 are electrically connected to the target pad 230 through the microstrip line in the fourth conductive layer 226. Thus, the electrical connection between the target hole structure 212 and the target pad 230 is achieved through the porous structure 222.

[0090] In some embodiments, see Figure 3 The target pad includes a package pad 310, and the package pad 310 is used to connect to the circuit board. The second insulating layer 220 ( Figure 3 At least two via structures 228 in the porous structure 222 (not shown) are provided on the surface 330 of the package pad 310 away from the circuit board. The impedance discontinuity at the package pad is improved by at least two via structures in the second insulating layer.

[0091] In some embodiments, see Figure 4, the insulating layer further includes a core layer 410. The first insulating layer includes a first build-up layer 420, and the second insulating layer includes a second build-up layer 430, and the first build-up layer 420 and the second build-up layer 430 are both located between the core layer 410 and the package pad 310. The target hole structure is a buried via 320 that penetrates the first build-up layer, and the buried via 320 electrically connects two conductive layers adjacent to the first build-up layer 420. The impedance discontinuity between the package pad and the single buried via in the corresponding build-up layer is improved by at least two via structures in the second build-up layer.

[0092] Furthermore, the second insulating layer is located between the first build-up layer 420 and the package pad 310, and the second insulating layer may include multiple layers of second build-up layers, and each layer of the second build-up layer may have a porous structure. Figure 3 , for the second build-up layer closest to the circuit board among the multiple second build-up layers ( Figure 3 (not shown), the porous structure 222 of the second build-up layer closest to the circuit board can be arranged on the surface 330 of the package pad 310 away from the circuit board.

[0093] In some embodiments, see Figure 5a and Figure 5b The insulating layer further includes a core layer 410, a third build-up layer 510 and a fourth build-up layer 520 which are stacked. The third build-up layer 510 is located between the core layer 410 and the fourth build-up layer 520. The third build-up layer 510 has a porous structure, and the fourth build-up layer has a target hole structure. The impedance discontinuity between the via pad of the core hole structure in the core layer and the single buried hole in the corresponding build-up layer is improved by the porous structure in the third build-up layer.

[0094] In one example, see Figure 5a , the direction of the circuit board pointing to the package substrate is set as the preset direction. The fourth buildup layer 520, the third buildup layer 510 and the core layer 410 are stacked in sequence along the preset direction. The third buildup layer 510 is arranged on the side of the core layer 410 away from the circuit board, and the fourth buildup layer 520 is arranged on the side of the third buildup layer 510 away from the core layer. For further information, please continue to refer to Figure 3 In the core layer, the core hole structure 340 is far away from the top of the circuit board, and the porous structure of the third build-up layer can be Figure 3 The target pore structure of the fourth layer can be Figure 3 FIG. 4 is a diagram showing a first buried via 370 in a third build-up layer located above the core layer.

[0095] In another example, the direction from the circuit board to the package substrate is set as a preset direction. The core layer 410, the third build-up layer 510 and the fourth build-up layer 520 are stacked in sequence along the preset direction. Figure 5bThe fourth buildup layer 520 is disposed on a side of the core layer close to the circuit board, and the third buildup layer 510 is disposed on a side of the fourth buildup layer 520 away from the core layer. Figure 3 In the core layer, the core hole structure 340 is close to the bottom of the circuit board, and the porous structure of the third build-up layer can be Figure 3 The bottom porous structure 360 ​​shown in FIG. The target pore structure of the fourth layer can be Figure 3 FIG. 4 is a diagram showing a second buried via 380 in a third build-up layer below the core layer.

[0096] In some embodiments, see Figure 6a and 6b The insulating layer further includes a core layer 410 , a fifth buildup layer 610 , and a sixth buildup layer 620 . The fifth buildup layer 610 is adjacent to the core layer 410 and is located between the core layer 410 and the sixth buildup layer 620 .

[0097] The core layer 410 has a core hole structure, and the core hole structure electrically connects two conductive layers adjacent to the core layer. A second via pad having a core hole structure is provided in any conductive layer adjacent to the core layer, and the target pad includes the second via pad having the core hole structure. The first insulating layer includes the sixth buildup layer 620; and the second insulating layer includes the fifth buildup layer 610. It should be noted that the sixth buildup layer 620 may be a buildup layer adjacent to the fifth buildup layer 610, or there may be at least one other buildup layer between the sixth buildup layer 620 and the fifth buildup layer 610.

[0098] In one example, the fifth stacking layer 610 and the sixth stacking layer 620 are adjacent to each other. Figure 6b , and the core layer 410( Figure 6b The two conductive layers adjacent to the fifth buildup layer 610 (not shown) include an Nth conductive layer 630 and an N+1th conductive layer 640. Figure 6b The two conductive layers adjacent to the sixth buildup layer 620 (not shown) include an Nth conductive layer 630 and an N-1th conductive layer 650. Figure 6b Two adjacent conductive layers (not shown) include an N-1th conductive layer 650 and an N-2th conductive layer 660.

[0099] The core layer 410 has a core hole structure 340. The core hole structure 340 has a second via pad in the Nth conductive layer 630, which is recorded as the top via pad 632, that is, the target pad includes the top via pad 632. The single buried via in the sixth buildup layer 620 can be regarded as an implementation of the target hole structure. There is a large size difference between the top via pad 632 and the single buried via in the sixth buildup layer 620. It can be seen that there is an impedance mutation between the top via pad 632 and the single buried via in the sixth buildup layer 620. Therefore, a buried via is set in the fifth buildup layer 610 in a single-layer porous manner. Specifically, a porous structure is set in the fifth buildup layer 610, and the porous structure includes at least two via structures, and the Nth conductive layer 630 and the N-1th conductive layer 650 are electrically connected through the at least two via structures.

[0100] In another example, the fifth stacking layer 610 and the sixth stacking layer 620 are adjacent to each other. Figure 6b , and the core layer 410( Figure 6b The two conductive layers adjacent to the fifth buildup layer 610 (not shown) include an Nth conductive layer 630 and an N+1th conductive layer 640. Figure 6b The two conductive layers adjacent to the sixth buildup layer 620 (not shown) include the N+1th conductive layer 640 and the N+2th conductive layer 670. Figure 6b Two adjacent conductive layers (not shown) include an N+2-th conductive layer 670 and an N+3-th conductive layer 680.

[0101] The core layer 410 has a core hole structure 340. The core hole structure 340 has a second via pad in the N+1 conductive layer 640, which is recorded as the bottom via pad 642, that is, the target pad includes the bottom via pad 642. The single buried via in the sixth buildup layer 620 can be regarded as an implementation of the target hole structure. There is a large size difference between the bottom via pad 642 and the single buried via in the sixth buildup layer 620. It can be seen that there is an impedance mutation between the bottom via pad 642 and the single buried via in the sixth buildup layer 620. Therefore, a buried via is set in the fifth buildup layer 610 in a single-layer porous manner. Specifically, a porous structure is set in the fifth buildup layer 610, and the porous structure includes at least two via structures, through which the N+1 conductive layer 640 and the N+2 conductive layer 670 are connected.

[0102] In the above embodiment, the package substrate includes a first insulating layer having a target hole structure and a second insulating layer having a porous structure. The porous structure includes at least two via structures. In the two conductive layers adjacent to the second insulating layer, the conductive layer away from the first insulating layer has a target pad, and at least two via structures are electrically connected to the target pad. The electrical connection between the target pad and the target hole structure is achieved through at least two via structures to form a signal link in the package substrate. By adopting a single-layer porous impedance optimization method in the second insulating layer, the discontinuity of the signal link impedance in the package substrate is improved, thereby improving the signal transmission quality.

[0103] In the present application, please refer to Figure 7a and 7b The package substrate further includes a third insulating layer 710 disposed between the first insulating layer 210 and the second insulating layer 220. The second insulating layer 220 has a first porous structure 720. The third insulating layer 710 has a second porous structure 730. The electrical connection between the target pad 230 and the target hole structure 212 is achieved through the first porous structure 720 and the second porous structure 730. The number of via structures in the second porous structure 730 is less than the number of via structures in the first porous structure 720.

[0104] In this embodiment, the package substrate includes a first insulating layer 210, a second insulating layer 220 and a third insulating layer 710 stacked in sequence. The first insulating layer 210 has a target hole structure 212, and the target hole structure 212 is a single blind hole or a buried hole. The second insulating layer 220 has a first porous structure 720, and the first porous structure 720 includes at least two via structures. In order to further alleviate the impedance mutation between the target hole structure 212 and the porous structure 222, a second porous structure 730 is set in the third insulating layer 710, and the second porous structure 730 includes at least two via structures, and the number of via structures in the second porous structure 730 is less than the number of via structures in the first porous structure 720. For example, if the number of via structures in the first porous structure 720 is 4, the number of via structures in the second porous structure 730 can be 2 or 3.

[0105] In this embodiment, multiple third insulating layers may be provided between the first insulating layer 210 and the second insulating layer 220, and the number of via structures of the second porous structure in each third insulating layer may be gradually reduced along the direction from the second insulating layer 220 to the first insulating layer 210. Figure 7b , the target pad 230 is the package pad 310, and the second insulating layer is a build-up layer adjacent to the package pad 310 ( Figure 7b The third insulating layer is a built-up layer located on the side of the second insulating layer away from the package pad ( Figure 7bThe first insulating layer is a built-up layer located on the side of the third insulating layer away from the package pad ( Figure 7b ), the target hole structure 212 is provided in the build-up layer. The size difference between the target hole structure 212 and the package pad 310 may cause impedance mutation, therefore, porous structures are provided in the second insulating layer and the third insulating layer, and in order to further mitigate impedance mutation, the number of via structures of the first porous structure 720 in the second insulating layer is greater than the number of via structures of the second porous structure 730 in the third insulating layer, for example, the number of via structures of the first porous structure 720 in the second insulating layer is 4, and the number of via structures of the second porous structure 720 in the third insulating layer is 2.

[0106] In the above embodiment, porous structures are provided in the second insulating layer and the third insulating layer, and the number of via structures in the second porous structure is less than the number of via structures in the first porous structure. The impedance mutation is further mitigated by gradually reducing the number of via structures in some insulating layers.

[0107] In an embodiment of the present application, the package substrate further includes a conductive pad. The conductive pad is located in two conductive layers adjacent to the second insulating layer and on a conductive layer close to the first insulating layer. The second insulating layer has a first porous structure, and the first ends of at least two via structures of the first porous structure penetrate the conductive pad to achieve electrical connection between the target pad and the target hole structure through the first porous structure and the conductive pad.

[0108] The first end is an end of the via structure away from the target pad. Specifically, the two conductive layers adjacent to the second insulating layer 220 are the third conductive layer 224 and the fourth conductive layer 226. The third conductive layer 224 is close to the first insulating layer 210, and the conductive pad is located on the third conductive layer 224. The first ends of at least two via structures of the first porous structure in the second insulating layer 220 pass through the conductive pad. The conductive pad realizes the electrical connection of each via structure in the first porous structure.

[0109] For example, see Figure 8 , Figure 8 The schematic diagram of a part of the signal chain in the 10-layer package substrate is shown. The 10-layer package substrate includes a conductive layer L10, a conductive layer L9, a conductive layer L8, a conductive layer L7, a conductive layer L6, a conductive layer L5, a conductive layer L4, a conductive layer L3, a conductive layer L2 and a conductive layer L1 in the direction from the circuit board to the bare chip. The package pad is arranged on the conductive layer L10.

[0110] In this example, the stacking layer L9-10 between the conductive layer L10 and the conductive layer L9 has a porous structure, and the porous structure includes four via structures. The first end of each of the four via structures penetrates the first conductive pad 810 in the conductive layer L9, and the signal link in the package substrate includes the first conductive pad 810, so as to realize that the four via structures of the porous structure in the stacking layer L9-10 are electrically connected to each other. Furthermore, the first conductive pad 810 can be connected to a microstrip line, which is electrically connected to the porous structure in the stacking layer L8-9. The stacking layer L8-9 is the stacking layer between the conductive layer L8 and the conductive layer L9. It should be noted that the porous structure in the stacking layer L8-9 corresponds to a conductive pad in the conductive layer L9, which can be regarded as a conductive pad different from the first conductive pad 810, and the two conductive pads are electrically connected by a microstrip line. In some cases, the conductive pad corresponding to the porous structure in the conductive layer L9 in the stack L8-9 can also be regarded as a part of the first conductive pad 810. In this case, the first conductive pad 810 includes a first conductive region corresponding to the porous structure in the stack L9-10 and a second conductive region corresponding to the porous structure in the stack L8-9.

[0111] In this example, the stacking layer L8-9 between the conductive layer L9 and the conductive layer L8 has a porous structure, and the porous structure includes two via structures. The first ends of the two via structures respectively penetrate the second conductive pad 820 in the conductive layer L8, and the signal link in the package substrate includes the second conductive pad 820, so as to realize that the two via structures of the porous structure in the stacking layer L8-9 are electrically connected to each other. Furthermore, the second conductive pad 820 can be connected to a microstrip line, which is electrically connected to the target hole structure in the stacking layer L7-8. The stacking layer L7-8 is the stacking layer between the conductive layer L7 and the conductive layer L8.

[0112] In this example, the stacking layer L6-7 between the conductive layer L7 and the conductive layer L6 has a porous structure, and the porous structure includes two via structures. The first ends of the two via structures respectively penetrate the third conductive pad 830 in the conductive layer L6, and the signal link in the package substrate includes the third conductive pad 830, so as to realize that the two via structures of the porous structure in the stacking layer L6-7 are electrically connected to each other. Furthermore, the third conductive pad 830 can be connected to a microstrip line, which is electrically connected to the core hole structure in the core layer L5-6. The stacking layer L5-6 is the stacking layer between the conductive layer L5 and the conductive layer L6.

[0113] In this example, the stacking layer L4-5 between the conductive layer L5 and the conductive layer L4 has a porous structure, and the porous structure includes two via structures. The first ends of the two via structures respectively penetrate the fourth conductive pad 840 in the conductive layer L6, and the signal link in the package substrate includes the fourth conductive pad 840, so as to realize that the two via structures of the porous structure in the stacking layer L4-5 are electrically connected to each other. Furthermore, the fourth conductive pad 840 can be connected to a microstrip line, which is electrically connected to the target hole structure in the stacking layer L3-4. The stacking layer L3-4 is the stacking layer between the conductive layer L3 and the conductive layer L4.

[0114] In the above embodiment, the first ends of at least two via structures of the first porous structure penetrate the conductive pad, and the conductive pad is connected to the at least two via structures of the first porous structure, which is conducive to realizing the signal link with optimized impedance in the packaging substrate.

[0115] In some embodiments, a third insulating layer is provided between the first insulating layer and the second insulating layer, and the third insulating layer has a second porous structure. The second ends of at least two via structures of the second porous structure and the first ends of at least two via structures of the first porous structure penetrate the same conductive pad. The electrical connection between the target pad and the target hole structure is achieved through the first porous structure, the conductive pad, and the second porous structure.

[0116] Among them, the second end is an end of the via structure close to the target pad. Specifically, as mentioned above, the third conductive layer 224 is close to the first insulating layer 210, and the third conductive layer 224 is a conductive layer close to the second insulating layer among the two conductive layers adjacent to the third insulating layer. The conductive pad is located on the third conductive layer 224. The second insulating layer 220 has a first porous structure 720, and the first porous structure 720 includes at least two via structures. The third insulating layer 710 is provided with a second porous structure 730, and the second porous structure 730 includes at least two via structures. The second ends of the at least two via structures of the second porous structure 730 and the first ends of the at least two via structures of the first porous structure 720 both penetrate the conductive pad.

[0117] For example, see Fig. 9 The first porous structure 720 has four via structures, namely the first via structure, the second via structure, the third via structure and the fourth via structure. The second porous structure 730 has two via structures, namely the fifth via structure and the sixth via structure. The first end 910 of the first via structure, the first end 920 of the second via structure, the first end of the third via structure 930, the first end 940 of the fourth via structure, the second end 950 of the fifth via structure and the second end 960 of the sixth via structure all pass through the conductive pad 970.

[0118] For further information, please refer to Figure 8, the second insulating layer may be the buildup layer L9-10, and the third insulating layer may be the buildup layer L8-9. The conductive pad 970 may be understood as the first conductive pad 810 located on the conductive layer L9. The first conductive pad 810 connects the four via structures in the buildup layer L9-10 and the two via structures in the buildup layer L8-9.

[0119] The conductive pad may include a plurality of first via pads, and adjacent first via pads are tangent to each other. The via structures correspond to the first via pads one by one, and the via structures penetrate the corresponding first via pads.

[0120] In the above embodiment, the second ends of at least two via structures of the second porous structure and the first ends of at least two via structures of the first porous structure penetrate the same conductive pad, which is beneficial to realize the signal link with optimized impedance in the packaging substrate.

[0121] In an embodiment of the present application, at least one anti-pad is disposed in the package substrate and is disposed opposite to the package pad. The hollowing size and / or the number of hollowing layers of the anti-pad are adjusted according to the target impedance value. The target impedance value is determined based on the signal target resistance value and the impedance at the socket, and the socket is used to connect the package substrate and the circuit board.

[0122] Usually, the package substrate is connected to the circuit board through a socket. In order to reduce the impact of impedance discontinuity, and the resistance of the socket cannot be adjusted, the impedance optimization is performed on the package pad. In addition, if the impedance optimization at the package pad is performed with the signal target resistance as the target impedance, the package pad is raised to the signal target resistance, but there is still an impedance jump between the signal target resistance and the socket resistance. Therefore, in this embodiment, the impedance optimization is performed by considering both the socket impedance and the signal target resistance at the same time.

[0123] Specifically, the target impedance value is determined based on the signal target resistance value and the impedance at the socket, and at least one of the hollowing size and the number of hollowing layers of the anti-pad arranged relative to the package pad is determined according to the target impedance value. In some embodiments, the target impedance value is determined based on the intermediate value of the signal target resistance value and the impedance at the socket. In some real-time methods, the intermediate value of the signal target resistance value and the impedance at the socket is used as the target impedance value, and the impedance at the package pad is optimized with the target impedance value.

[0124] Take the DQ signal in the DDR high-speed signal as an example for an exemplary description. The package substrate and the circuit board are connected using LGASocket. The impedance value at the package pad LGA Pad is 36Ω, and the impedance value at the LGA Socket is 52Ω. Please refer to Fig.10a , Fig.10aThe model of the package structure 110, LGA Socket 1010 and circuit board 130 is shown. The target impedance of the single-ended DQ signal is 45Ω. The target impedance value of 48.5Ω is obtained by averaging the signal target impedance and the impedance value at the LGA Socket. The impedance at this location is raised to 48.5Ω by adjusting the anti-pad hollowing size and / or the number of anti-pad hollowing layers, which reduces the impedance mutation from 36Ω to 52Ω. Please refer to Fig.10b , Fig.10b is the impedance curve of the DDR signal under the above model. It should be noted that the DDR high-speed signal generally refers to the high-speed signal in the double data rate (DDR) memory interface, which is mainly used for fast data transmission.

[0125] In the above embodiment, compared with the related art in which the impedance at the package pad is raised to the signal target resistance value by adjusting the anti-pad hollowing size and / or the number of anti-pad hollowing layers, the present application uses the intermediate value between the signal target resistance value and the impedance at the socket as the target impedance value for optimization processing, slowing down the impedance mutation and making its impedance curve smoother, so as to reduce the impact of the impedance discontinuity at this location.

[0126] A packaging device is provided in an embodiment of the present application, including the packaging substrate mentioned in any of the above embodiments.

[0127] In an embodiment of the present application, a design method for a package substrate is provided, wherein the package substrate includes a plurality of conductive layers stacked in a thickness direction of the package substrate and an insulating layer formed between two adjacent conductive layers. Fig.11 , the design method may include the following steps:

[0128] S1110. Determine a first insulating layer and a second insulating layer.

[0129] S1120, setting a target hole structure in the first insulating layer; wherein the target hole structure electrically connects two conductive layers adjacent to the first insulating layer.

[0130] S1130, setting a porous structure in the second insulating layer, and determining the number of via structures in the porous structure.

[0131] Among them, the porous structure includes at least two via structures, at least two via structures are electrically connected to two conductive layers adjacent to the second insulating layer, and among the two conductive layers adjacent to the second insulating layer, a conductive layer away from the first insulating layer has a target pad; at least two via structures are electrically connected to the target pad, and the electrical connection between the target pad and the target hole structure is achieved through at least two via structures to form a signal link in the packaging substrate.

[0132] In the present embodiment, the packaging substrate includes a plurality of conductive layers stacked in the thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers. The number of insulating layers is multiple. In combination with the actual situation of the impedance discontinuity point in the packaging substrate, a first insulating layer and a second insulating layer are selected from the multiple insulating layers. A target hole structure is set in the first insulating layer, and the target hole structure is a blind hole or a buried hole. The two conductive layers adjacent to the first insulating layer are electrically connected through the target hole structure. It can be understood that the first insulating layer is a dielectric layer in the form of a single layer and a single hole. In order to mitigate the impedance mutation, a single-layer porous method is adopted in the second insulating layer, a porous structure is set in the second insulating layer, and the number of via structures in the porous structure is determined according to the impedance difference between the target hole structure and the target pad. The porous structure includes at least two via structures, and the via structures are blind holes or buried holes.

[0133] In this embodiment, in the second insulating layer between the core layer and the first insulating layer, a porous structure including two via structures can be set, or a porous structure including three via structures can be set. The number of via structures in the porous structure depends on the impedance discontinuity between the second via pad and the target hole structure in the first insulating layer.

[0134] For example, in the case where the second via pad of the core hole structure in the core layer is used as the target pad, a porous structure including two via structures may be provided in the second insulating layer between the core layer and the first insulating layer, or a porous structure including three via structures may be provided, and the number of via structures in the porous structure depends on the impedance discontinuity between the second via pad and the target hole structure. The number of second insulating layers between the second via pad and the first insulating layer also depends on the impedance discontinuity between the second via pad and the target hole structure.

[0135] Exemplarily, for the case where the package pad is used as the target pad, the number of first insulation layers, second insulation layers between the package pad and the first sterilization layer, and the number of via structures of the porous structure in each second insulation layer can be determined in multiple insulation layers in combination with the impedance at the package pad.

[0136] It should be noted that the number of the second insulating layer is at least one layer. When the number of the second insulating layer is multiple layers, the number of via structures of the porous structure in each second insulating layer may be equal or unequal. For example, the number of via structures of the porous structure in the second insulating layer may also depend on the distance between the second insulating layer and the target pad. The closer the second insulating layer is to the target pad, the more via structures of the porous structure therein.

[0137] In the above embodiment, first, the first insulating layer and the second insulating layer are determined, and then a target hole structure is set in the first insulating layer; and a porous structure is set in the second insulating layer, and the number of via structures in the porous structure is determined. By adopting a single-layer porous impedance optimization method in the second insulating layer, the problem of impedance discontinuity of the signal link in the packaging substrate is optimized, thereby improving the signal quality.

[0138] In the embodiment of the present application, the first insulating layer and the second insulating layer are determined by the following method, including:

[0139] If the target pad is a package pad, determine the core layer, determine the insulation layer closest to the package pad as the second insulation layer; determine the first insulation layer in the insulation layer between the second insulation layer and the core layer; or

[0140] A core layer is determined, a buildup layer adjacent to the core layer is determined as a second insulating layer, and a buildup layer adjacent to the second insulating layer is determined as a first insulating layer.

[0141] In this embodiment, for the case where the target pad is a package pad, if the insulation layer closest to the package pad adopts a single-layer single-hole method, there is an impedance mutation between the corresponding blind hole and the package pad. At the same time, considering minimizing process changes, a suitable buildup layer is selected between the core layer and the package pad as the first insulation layer, and the first insulation layer adopts a single-layer single-hole method. If the impedance mutation between the single hole in the buildup layer and the package pad is alleviated, it is necessary to adopt a single-layer porous impedance optimization method for the insulation layer closest to the package pad. Specifically, the insulation layer closest to the package pad is determined as the second insulation layer, and a porous structure is set in the second insulation layer.

[0142] In this embodiment, for the case where the second via pad of the core hole structure in the core layer is used as the target pad, there is a size difference between the second via pad and the first via pad of the via structure in the build-up layer. Therefore, it is necessary to adopt a single-layer multi-porous impedance optimization method for the build-up layer adjacent to the core layer, and the build-up layer adjacent to the core layer is determined as the second insulating layer, and the build-up layer adjacent to the second insulating layer is determined as the first insulating layer. It can be understood that the first insulating layer, the second insulating layer and the core layer are stacked in sequence along a preset direction. Alternatively, the core layer, the second insulating layer and the first insulating layer are stacked in sequence along a preset direction. The preset direction is the direction from the circuit board to the package substrate.

[0143] In an embodiment of the present application, at least one layer of anti-pads arranged opposite to the package pads is provided in the package substrate; the design method may also include: determining the target impedance value based on the signal target resistance value and the impedance at the socket; adjusting the hollowing size and / or the number of hollowing layers of the anti-pads according to the target impedance value. The socket is used to connect the package substrate and the circuit board. In some embodiments, the target impedance value is determined based on the intermediate value of the signal target resistance value and the impedance at the socket.

[0144] In the above embodiment, compared with the related art in which the impedance at the package pad is raised to the signal target resistance value by adjusting the anti-pad hollowing size and / or the number of anti-pad hollowing layers, the present application uses the intermediate value between the signal target resistance value and the impedance at the socket as the target impedance value for optimization processing, slowing down the impedance mutation and making its impedance curve smoother, so as to reduce the impact of the impedance discontinuity at this location.

[0145] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or is implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the design method shown in the above embodiment is implemented.

[0146] The embodiment of the present application provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the design method of any embodiment of the present application.

[0147] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations all fall within the scope defined by the appended claims. The systems, devices or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0148] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0149] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0150] The present application is described with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, and the combination of the process and / or box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram.

[0151] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0152] These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0153] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0154] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0155] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0156] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A packaging substrate, characterized in that: The packaging substrate includes a plurality of conductive layers stacked in a thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers, wherein the insulating layer includes: A first insulating layer having a target hole structure, wherein the target hole structure electrically connects two conductive layers adjacent to the first insulating layer; A second insulating layer has a porous structure, wherein the porous structure includes at least two via structures, and the at least two via structures are electrically connected to two conductive layers adjacent to the second insulating layer; Among them, among the two conductive layers adjacent to the second insulating layer, the conductive layer away from the first insulating layer has a target pad, and the at least two via structures are electrically connected to the target pad. The electrical connection between the target pad and the target hole structure is achieved through the at least two via structures to form a signal link in the packaging substrate.

2. The packaging substrate according to claim 1, characterized in that: A third insulating layer is provided between the first insulating layer and the second insulating layer; The second insulating layer has a first porous structure; The third insulating layer has a second porous structure; The target pad is electrically connected to the target hole structure through the first porous structure and the second porous structure, and the number of via structures in the second porous structure is less than the number of via structures in the first porous structure.

3. The packaging substrate according to claim 1, characterized in that: The packaging substrate also includes a conductive pad; The conducting pad is located in two conducting layers adjacent to the second insulating layer and on a conducting layer close to the first insulating layer; The second insulating layer has a first porous structure, and first ends of at least two via structures of the first porous structure penetrate the conducting pad; The target pad is electrically connected to the target via structure through the first porous structure and the conductive pad, and the first end is an end of the via structure away from the target pad.

4. The packaging substrate according to claim 3, characterized in that: A third insulating layer is provided between the first insulating layer and the second insulating layer, and the third insulating layer has a second porous structure; The second ends of the at least two via structures of the second porous structure and the first ends of the at least two via structures of the first porous structure penetrate the same conducting pad; The electrical connection between the target pad and the target via structure is achieved through the first porous structure, the conductive pad, and the second porous structure, and the second end is an end of the via structure close to the target pad.

5. The packaging substrate according to claim 1, characterized in that: The target pad includes a package pad, and the package pad is used to connect to a circuit board; At least two via structures in the porous structure of the second insulating layer are arranged on a surface of the package pad away from the circuit board.

6. The packaging substrate according to claim 5, characterized in that: The insulating layer also includes a core layer; The first insulating layer includes a first build-up layer, and the target hole structure is a buried hole penetrating the first build-up layer and electrically connecting two conductive layers adjacent to the first build-up layer; The second insulating layer includes a second build-up layer, and the first build-up layer and the second build-up layer are both located between the core layer and the package pad.

7. The packaging substrate according to claim 5, characterized in that: The insulating layer further comprises a core layer, a third buildup layer and a fourth buildup layer which are stacked; the third buildup layer is located between the core layer and the fourth buildup layer; The third layer has the porous structure, and the fourth layer has the target pore structure; The fourth buildup layer, the third buildup layer and the core layer are stacked in sequence along a preset direction, or the core layer, the third buildup layer and the fourth buildup layer are stacked in sequence along the preset direction; the preset direction is the direction from the circuit board to the packaging substrate.

8. The packaging substrate according to any one of claims 1 to 7, characterized in that: The packaging substrate is provided with at least one layer of anti-pad arranged opposite to the packaging pad; The hollowing size and / or the number of hollowing layers of the anti-pad are adjusted according to a target impedance value, which is determined based on a signal target resistance value and an impedance at a socket, and the socket is used to connect the package substrate and a circuit board.

9. A packaged device, characterized in that: A packaging substrate comprising any one of claims 1 to 8.

10. A method for designing a packaging substrate, characterized in that: The packaging substrate comprises a plurality of conductive layers stacked in a thickness direction of the packaging substrate and an insulating layer formed between two adjacent conductive layers; the method comprises: determining a first insulating layer and a second insulating layer; A target hole structure is provided in the first insulating layer; wherein the target hole structure electrically connects two conductive layers adjacent to the first insulating layer; A porous structure is set in the second insulating layer, and the number of via structures in the porous structure is determined; wherein the porous structure includes at least two via structures, and the at least two via structures are electrically connected to two conductive layers adjacent to the second insulating layer, and among the two conductive layers adjacent to the second insulating layer, a conductive layer away from the first insulating layer has a target pad; the at least two via structures are electrically connected to the target pad, and the electrical connection between the target pad and the target hole structure is achieved through the at least two via structures to form a signal link in the packaging substrate.

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