Power switching circuit and chip test system thereof
By designing a power switching circuit, the gate capacitance of the relay and high-voltage NMOS tubes control the power switching rate, the high cost and complex power switching problems in the wafer test stage are solved, low-cost and efficient power switching are achieved, chip yield is improved and voltage spike damage is avoided.
Patent Information
- Application Number
- CN202411980757.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-18
AI Technical Summary
The prior art has high costs in the chip wafer testing stage and cannot achieve parallel testing of multiple machines, and the power switching design is complex, resulting in serious yield loss in the chip production process.
A power switching circuit is designed, and a relay is used to change the resistor series voltage division ratio and the gate-to-ground capacitance of the discrete high-voltage NMOS tube to control the power supply voltage switching rate, so as to achieve flexible power switching and avoid voltage spikes.
It realizes low-cost and efficient power switching during the wafer testing stage, reduces chip production costs and improves yield, and avoids chip damage caused by too fast power switching.
Smart Images
Figure CN119853432A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip testing, and in particular to a power switching circuit and a chip testing system thereof. Background Art
[0002] After wafer production and processing, chip manufacturing needs to go through a series of testing processes. After passing the test, it needs to be sent to the packaging factory for the packaging process. The fully packaged chip also needs to complete the final product test and then pass the original factory inspection before it can be shipped.
[0003] There are certain failures in the chip production process from wafer testing to final product testing, which will lead to a decrease in the yield rate during the chip production process. However, the impact of yield loss at different stages on chip cost is different. Specifically, the yield loss at the wafer testing stage is only the wafer cost, while the yield loss at the final product testing will not only increase the wafer cost but also the packaging cost.
[0004] Therefore, in order to control the production cost of chips, it is necessary to discover various failed products early in the wafer testing stage, so that the manufacturing defects and functional defects of the chips can be exposed in advance. This will reduce the yield loss of finished product testing after packaging, thereby greatly reducing the manufacturing cost of the chip.
[0005] In order to cover as many potential failed products as possible in the finished chip testing, we need to add more test vectors during the wafer testing stage, such as input line regulation rate, input line transient response, input maximum withstand voltage level, chip functional testing at different power-on rates, etc.
[0006] Although the above problems can be solved by using ATE testers during the wafer testing stage, the high cost of ATE testers makes it impossible to implement parallel testing of multiple machines in large-scale testing.
[0007] Furthermore, ATE testers are designed with various types of power supplies, from negative voltage to positive voltage, from low voltage to high voltage. Therefore, the power switching design within the test system is an important factor in the test system.
[0008] It can be seen that how to design the power switching circuit flexibly at a low cost during the wafer testing stage of the chip is crucial. Summary of the invention
[0009] In a first aspect of the present invention, in order to solve the above technical problem, the present invention provides a power switching circuit, which is applied to a chip under test, comprising: The power supply voltage switching module is used to change the current power supply output voltage by changing the resistor string voltage division ratio through the relay; The power supply voltage switching rate control module includes a discrete high-voltage NMOS tube Q0. The chip under test is connected to the source of the discrete high-voltage NMOS tube Q0. The power supply voltage switching rate control module controls the switching rate of the power supply voltage by changing the gate-to-ground capacitance of the discrete high-voltage NMOS tube Q0.
[0010] Furthermore, the power supply voltage switching module includes a resistor R11 and a resistor R21 connected in series, wherein: A reference voltage VREF is generated between the resistor R11 and the resistor R21; The resistor R21 is connected in parallel with the capacitor C1; A high-voltage operational amplifier LT1010 is provided between the reference voltage VREF and the gate of the discrete high-voltage NMOS transistor Q0 to form a closed-loop high-voltage voltage buffer; The source of the discrete high-voltage NMOS transistor Q0 generates a power output voltage, and the power output voltage is equal to the reference voltage VREF.
[0011] Furthermore, the non-inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the reference voltage VREF, the inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the source of the discrete high-voltage NMOS tube Q0; the output terminal of the high-voltage operational amplifier LT1010 is connected to the gate of the discrete high-voltage NMOS tube Q0.
[0012] Furthermore, the source of the discrete high-voltage NMOS transistor Q0 is connected to a pseudo load Rlight.
[0013] Furthermore, the power supply voltage switching module further includes a relay S1 and a resistor R22. The relay S1 is connected in series with the resistor R22 and then connected in parallel with the resistor R21. When the relay S1 is disconnected, the power supply output voltage is:
[0014] in, Input voltage for the power supply.
[0015] Furthermore, when the second power supply voltage needs to be set, the relay S1 is closed, so that the resistor R21 is connected in parallel with the resistor R22, and the second power supply output voltage is: .
[0016] Further, the power supply voltage switching rate control module includes a capacitor C2, a capacitor C3, a relay S2 and a relay S3, wherein: The upper ends of the capacitor C2 and the capacitor C3 are both connected to the in-phase input terminal of the high-voltage operational amplifier LT1010; The lower ends of the capacitor C2 and the capacitor C3 are grounded through the relay S2 and the relay S3 respectively; When the relay S2 is closed and the relay S3 is open, the capacitance between the gate of the discrete high-voltage NMOS transistor Q0 and the ground is the capacitor C2; When the relay S2 is disconnected and the relay S3 is closed, the capacitance between the gate of the discrete high-voltage NMOS transistor Q0 and the ground is the capacitor C3.
[0017] A second aspect of the present invention provides a chip testing system, comprising the power switching circuit.
[0018] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: The present invention utilizes the relay in the power supply voltage switching module to realize the switching of different power supply output voltages; at the same time, the influence of the gate capacitance on the switching speed of the NMOS tube is utilized, and the gate-to-ground capacitance of the discrete high-voltage NMOS tube Q0 is changed to control the switching rate of the power supply voltage, thereby avoiding the voltage spike caused by the too fast switching of the power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0020] Figure 1 The schematic diagram of the circuit disclosed in the embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0022] The present invention aims to provide a power switching circuit, which is applied to a chip under test, so as to realize designing the power switching circuit at a lower cost during the wafer testing stage, and at the same time, avoid voltage spikes caused by too fast power supply voltage switching.
[0023] The power switching circuit mainly includes a power voltage switching module and a power voltage switching rate control module.
[0024] The power supply voltage switching module is used to change the current power supply output voltage by changing the resistor string voltage division ratio through a relay.
[0025] The power supply voltage switching rate control module includes a discrete high-voltage NMOS tube Q0. The chip under test is connected to the source of the discrete high-voltage NMOS tube Q0. The switching rate of the power supply voltage is controlled by changing the gate-to-ground capacitance of the discrete high-voltage NMOS tube Q0.
[0026] See also Figure 1 The power switching circuit includes a resistor R11, a resistor R21, a resistor R22, a pseudo load Rlight, a capacitor C1, a capacitor C2, a capacitor C3, a relay S1, a relay S2, a relay S3, a high-voltage operational amplifier LT1010, a discrete high-voltage NMOS tube Q0, an input capacitor CIN and an output capacitor COUT; and also includes a power module for providing a power supply input voltage .
[0027] In a further embodiment of the present invention, the power supply voltage switching module includes a resistor R11, a resistor R21 and a high voltage operational amplifier LT1010, wherein the resistor R21 is connected in parallel with the capacitor C1. The resistor R11 and the resistor R21 are connected in series and then connected in parallel with the input capacitor CIN.
[0028] A voltage divider between the resistors R11 and R21 connected in series generates a reference voltage VREF.
[0029] A high-voltage operational amplifier LT1010 is provided between the reference voltage VREF and the gate of the discrete high-voltage NMOS tube Q0 to form a closed-loop high-voltage voltage buffer to achieve precise voltage output and drive the gate of the high-voltage NMOS tube.
[0030] The non-inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the reference voltage VREF, the inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the source of the discrete high-voltage NMOS tube Q0; the output terminal of the high-voltage operational amplifier LT1010 is connected to the gate of the discrete high-voltage NMOS tube Q0.
[0031] The source of the discrete high-voltage NMOS tube Q0 generates a power output voltage, which is equal to the reference voltage VREF and has sufficient current driving capability.
[0032] In order to make the high-voltage buffer respond faster to the load current, a pseudo load Rlight needs to be added at the output end of the power supply, that is, the source of the discrete high-voltage NMOS tube Q0 is connected to the pseudo load Rlight.
[0033] The current power supply output voltage can be changed by changing the voltage division ratio of the resistor string, thus realizing the switching of the power supply voltage.
[0034] The power supply voltage switching module further includes a relay S1 and a resistor R22, and the relay is used to control the change of the connection relationship.
[0035] Among them, the relay S1 is connected in series with the resistor R22 and then in parallel with the resistor R21, where: When relay S1 is disconnected, the power supply output voltage for:
[0036] in, Input voltage for the power supply.
[0037] When the second power supply voltage needs to be set, the relay S1 is closed, so that the resistor R21 is connected in parallel with the resistor R22, thereby changing the resistor string voltage division ratio, and the new power supply output voltage is adjusted to:
[0038] The switching process of two different voltages is realized by relay S1. If more voltages need to be switched, a similar method can be used to achieve it.
[0039] In actual testing, due to the existence of parasitic inductance effects, if the voltage is switched too quickly, the power supply output is prone to produce various unexpected voltage spikes, which may cause chip damage; in addition, sometimes it is necessary to measure the function of the chip under conditions of different power switching rates. Therefore, while being able to switch the power supply voltage, it is also necessary to control the switching rate of the power supply voltage.
[0040] The present invention adjusts the power switching rate by utilizing the influence of the gate capacitance on the switching speed of the NMOS tube, that is, by changing the gate-to-ground capacitance of the discrete high-voltage NMOS tube Q0.
[0041] Specifically, the power supply voltage switching rate control module includes a capacitor C2, a capacitor C3, a relay S2 and a relay S3. Among them: The upper ends of capacitors C2 and C3 are both connected to the non-inverting input terminal of the high-voltage operational amplifier LT1010; The lower ends of capacitors C2 and C3 are grounded through relays S2 and S3 respectively; When relay S2 is closed and relay S3 is open, the capacitance between the gate of discrete high-voltage NMOS transistor Q0 and ground is capacitor C2; When the relay S2 is disconnected and the relay S3 is closed, the capacitance between the gate of the discrete high-voltage NMOS tube Q0 and the ground is the capacitor C3, thereby achieving control of the power supply voltage switching rate.
[0042] The present invention also protects a chip testing system, which includes the power switching circuit mentioned above.
[0043] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.
Claims
1. A power switching circuit, applied to a chip under test, characterized in that: include: The power supply voltage switching module is used to change the current power supply output voltage by changing the resistor string voltage division ratio through the relay; The power supply voltage switching rate control module includes a discrete high-voltage NMOS tube Q0. The chip under test is connected to the source of the discrete high-voltage NMOS tube Q0. The power supply voltage switching rate control module controls the switching rate of the power supply voltage by changing the gate-to-ground capacitance of the discrete high-voltage NMOS tube Q0.
2. The power switching circuit according to claim 1, characterized in that: The power supply voltage switching module includes a resistor R11 and a resistor R21 connected in series, wherein: A reference voltage VREF is generated between the resistor R11 and the resistor R21; The resistor R21 is connected in parallel with the capacitor C1; A high-voltage operational amplifier LT1010 is provided between the reference voltage VREF and the gate of the discrete high-voltage NMOS transistor Q0 to form a closed-loop high-voltage voltage buffer; The source of the discrete high-voltage NMOS transistor Q0 generates a power output voltage, and the power output voltage is equal to the reference voltage VREF.
3. The power switching circuit according to claim 2, characterized in that: The non-inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the reference voltage VREF, the inverting input terminal of the high-voltage operational amplifier LT1010 is connected to the source of the discrete high-voltage NMOS transistor Q0; the output terminal of the high-voltage operational amplifier LT1010 is connected to the gate of the discrete high-voltage NMOS transistor Q0.
4. The power switching circuit according to claim 1, characterized in that: The source of the discrete high-voltage NMOS transistor Q0 is connected to a pseudo load Rlight.
5. The power switching circuit according to claim 2, characterized in that: The power supply voltage switching module further includes a relay S1 and a resistor R22. The relay S1 is connected in series with the resistor R22 and then connected in parallel with the resistor R21. When the relay S1 is disconnected, the power supply output voltage is: in, Input voltage for the power supply.
6. The power switching circuit according to claim 5, characterized in that: When the second power supply voltage needs to be set, the relay S1 is closed, so that the resistor R21 is connected in parallel with the resistor R22, and the second power supply output voltage is: 。 7. The power switching circuit according to claim 2, characterized in that: The power supply voltage switching rate control module includes a capacitor C2, a capacitor C3, a relay S2 and a relay S3, wherein: The upper ends of the capacitor C2 and the capacitor C3 are both connected to the in-phase input terminal of the high-voltage operational amplifier LT1010; The lower ends of the capacitor C2 and the capacitor C3 are grounded through the relay S2 and the relay S3 respectively; When the relay S2 is closed and the relay S3 is open, the capacitance between the gate of the discrete high-voltage NMOS transistor Q0 and the ground is the capacitor C2; When the relay S2 is disconnected and the relay S3 is closed, the capacitance between the gate of the discrete high-voltage NMOS transistor Q0 and the ground is the capacitor C3.
8. A chip testing system, characterized in that: A power switching circuit comprising the power switching circuit described in any one of claims 1 to 7.