Correction circuit and correction method applied to pulse frequency modulation converter

Abstract

The invention provides a correction circuit and a correction method applied to a pulse frequency modulation converter. The correction circuit comprises a signal generator circuit and a correction control circuit. The signal generator circuit is configured to generate and output an analog slope signal to a comparator circuit in a correction mode, where the analog slope signal has an analog slope after an initial voltage. And the analog slope signal corresponds to a slope of a sensing signal indicating an electrical characteristic of an inductor of the pulse frequency modulation converter. The correction control circuit is used for correcting at least one circuit in the pulse frequency modulation converter by referring to an output signal generated by a pulse frequency modulation control circuit in response to an output signal of the comparator circuit.

Description

Technical Field

[0001] The present invention relates to voltage converter design, and more particularly to a method and apparatus for calibrating a pulse-frequency modulation (PFM) converter by using an emulated slope signal. Background Art

[0002] A switching direct current-direct current (DC-DC) voltage converter (or voltage regulator) is usually used to provide a regulated voltage output from a power source such as a battery. A common type of switching voltage converter is a step-down regulator (or buck converter), which provides an output voltage lower than the input voltage. The PFM mode has a very simple structure in a DC-DC buck converter, which can save chip area. In addition, PFM control can achieve high efficiency under light load conditions. Generally speaking, PFM control uses a pulse train to adjust the output voltage of the DC-DC buck converter. For example, a typical PFM converter has multiple comparator circuits to control the inductor current pulse in each PFM cycle. One comparator circuit monitors the output voltage of the PFM converter to control the start time of the inductor charging state, another comparator circuit monitors the peak value of the inductor current of the PFM converter to control the end time of the inductor charging state and the start time of the inductor discharging state, and another comparator circuit monitors the zero crossing of the inductor current to control the end time of the inductor discharging state. However, due to certain factors (including process variations, comparator DC offset, comparator delay time, power switch (metal oxide semiconductor field effect transistor (MOSFET)) channel impedance, power supply, temperature, etc.), the actual timing of stopping the inductor charging state and / or the actual timing of stopping the inductor discharging state may deviate from the expected timing. Due to the non-ideal state switching, the power efficiency is reduced. Therefore, an innovative correction scheme is needed to significantly improve the power efficiency of the PFM converter. Summary of the invention

[0003] One of the objects of the present invention is to provide a method and an apparatus for calibrating a pulse frequency modulation converter by using an analog slope signal.

[0004] In one embodiment of the present invention, a correction circuit for a pulse frequency modulation converter is disclosed. The correction circuit includes a signal generator circuit and a correction control circuit. The signal generator circuit is used to generate and output an analog slope signal to a comparator circuit under a correction mode, wherein the analog slope signal has an analog slope after an initial voltage, and the analog slope signal corresponds to the slope of a sensing signal indicating an electrical characteristic of an inductor of the pulse frequency modulation converter. The correction control circuit is used to calibrate at least one circuit in the pulse frequency modulation converter with reference to an output signal generated by a pulse frequency modulation control circuit in response to an output signal of the comparator circuit.

[0005] In one embodiment of the present invention, a calibration method for a pulse frequency modulation converter is disclosed. The calibration method includes: generating and outputting an analog slope signal to a comparator circuit in a calibration mode, wherein the analog slope signal has an analog slope after an initial voltage, and the analog slope signal corresponds to the slope of a sensing signal indicating an electrical characteristic of an inductor of the pulse frequency modulation converter; and calibrating at least one circuit in the pulse frequency modulation converter according to an output signal generated by a pulse frequency modulation control circuit in response to an output signal of the comparator circuit.

[0006] Due to certain factors, the actual timing of stopping the inductor charging state and / or the actual timing of stopping the inductor discharging state may deviate from the expected timing, so the power efficiency may be reduced due to the non-ideal state switching. In order to solve the problem of reduced power efficiency, the present invention proposes to use a correction circuit to correct at least one circuit in the pulse frequency modulation converter in a correction mode. For example, the at least one circuit may include a comparator circuit, and the correction mode may be a power-on correction mode or a background correction mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a schematic diagram of a PFM converter according to an embodiment of the present invention.

[0008] Figure 2 for Figure 1 Schematic diagram of waveforms of different signals of the PFM converter shown.

[0009] Figure 3 FIG. 4 is a schematic diagram of a calibration circuit operating in a power-on calibration mode according to an embodiment of the present invention.

[0010] Figure 4 is a schematic diagram of the zero-crossing path in correction mode.

[0011] Figure 5 is a schematic diagram illustrating the concept of correcting the zero-crossing path by using the analog slope signal proposed in the present application.

[0012] Figure 6 The figure is a flow chart of a power-on calibration method according to an embodiment of the present invention.

[0013] Figure 7 yes Figure 3 Waveform diagrams of different signals of the correction circuit shown.

[0014] Figure 8 FIG. 4 is a schematic diagram of a current / capacitance slope generator circuit according to an embodiment of the present invention.

[0015] Fig. 9 is a schematic diagram of the different stages of the switched capacitor slope generator circuit.

[0016] Fig.10 yes Fig. 9 Waveform diagrams of different signals of the switched capacitor slope generator circuit shown.

[0017] Fig.11 FIG. 4 is a schematic diagram of a correction circuit operating in a background correction mode according to an embodiment of the present invention.

[0018] Fig.12 is a flow chart of a background correction method according to an embodiment of the present invention.

[0019] Fig.13 FIG. 4 is a schematic diagram of another calibration circuit operating in a power-on calibration mode according to an embodiment of the present invention.

[0020] Fig.14 FIG. 4 is a schematic diagram of another correction circuit operating in a background correction mode according to an embodiment of the present invention.

[0021]

Explanation of symbols

[0022] 100:PFM Converter

[0023] 102: Power stage circuit

[0024] 104, 1134: PFM control circuit

[0025] 106: Feedback control circuit

[0026] 112:SR latch circuit

[0027] 114: switch control circuit

[0028] 116, 120, 122, 1132, 1432: Comparator circuit

[0029] 118: Current-to-voltage converter circuit

[0030] 124, 300, 1100, 1300, 1400: Correction circuit

[0031] 302, 1102, 1302: signal generator circuit

[0032] 304, 1104, 1304, 1404: clock generator circuit

[0033] 306, 1306: Mode switching circuit

[0034] 308, 1106, 1308, 1406: Correction control circuit

[0035] 310, 1108, 1310, 1408: Reference voltage generator circuit

[0036] 312, 1110, 1312, 1410: Analog slope generator circuit

[0037] 800: Current / Capacitance Slope Generator Circuit

[0038] 802: Voltage to Current Converter

[0039] 804: Unity Gain Buffer

[0040] 900: Switched Capacitor Slope Generator Circuit

[0041] 1120, 1420: Actual circuit

[0042] 1130, 1430: Replication circuit

[0043] L: Inductance

[0044] IL: Inductor current

[0045] V SEN :Sense voltage signal

[0046] V IPEAK : Target peak current value

[0047] V REF :Reference voltage

[0048] Co: output capacitance

[0049] VIN: Input voltage

[0050] VOUT: output voltage

[0051] GND: Ground voltage

[0052] VLX: Voltage

[0053] MP:PMOS transistor

[0054] MN:NMOS transistor

[0055] LX:Endpoint

[0056] ZX, VD_RST, VD_SET: feedback control signal LGATE, ZX_K, OC_K: output signal OS_code: control setting

[0057] VSLP: Analog slope signal

[0058] VSLP(0): Initial voltage

[0059] I REF :Current Source

[0060] C CAL , C G_K :Capacitors 806, 808, SW1, SW2, SW3, SW4:Switch INP:Non-inverting input node

[0061] INN: Inverting input node

[0062] POK_Done, POK_EN: control signal CK_CTRL, CK_SC: control clock ZX_sample: ZX sampling clock

[0063] CK REF :Process-independent clock

[0064] MPWR: Power Transistor

[0065] S602~S622, S1202~S1218: Steps DETAILED DESCRIPTION

[0066] Certain words are used in the specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the criterion for distinction. The "include" and "comprising" mentioned throughout the specification and claims are open-ended terms and should be interpreted as "including but not limited to". In addition, the term "coupled" or "coupled" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0067] Figure 1Schematic diagram of a PFM converter according to an embodiment of the present invention. The PFM converter 100 can be used as a DC-DC buck converter to adjust the output voltage VOUT (VOUT < VIN) according to the input voltage VIN. For example, the input voltage VIN can be provided by a battery. The PFM converter 100 includes a power stage (PS) circuit 102, a PFM control circuit 104, a feedback control circuit 106, an inductor L, an output capacitor Co, and a correction circuit 124 with a slope prediction function. The power stage circuit 102 is coupled between the input voltage VIN and a reference voltage (e.g., ground voltage GND), and includes a high-side power switch circuit and a low-side power switch circuit. In this embodiment, the high-side power switch circuit is implemented by a P-channel metal-oxide-semiconductor (PMOS) transistor MP, and the low-side power switch circuit is implemented by an N-channel metal-oxide-semiconductor (NMOS) transistor MN. The PFM control circuit 104 can include a logic gate and a pre-driver, and is responsible for processing PFM control. For example (but not limited to this invention), the PFM control circuit 104 can include an SR (set-reset) latch circuit 112 and a switch control circuit 114. The SR latch circuit 112 has a set input node (labeled "S"), a reset input node (labeled "R"), and an output node (labeled "Q"). The operation of the SR latch circuit 112 can be represented by the following truth table, but this invention is not limited thereto.

[0068] S R Q 0 0 Q(Latch) 0 1 0 1 0 1 1 1 0

[0069] The switch control circuit 114 is used to set the output signal and LGATE in response to the output signal of the SR latch circuit 112 or the feedback control signal ZX obtained from zero-crossing detection. The output signal is coupled to the gate terminal of the PMOS transistor MP, and the output signal LGATE is coupled to the gate terminal of the NMOS transistor MN. When the output node of the SR latch circuit 112 is set to a high logic level (i.e., Q = 1), the switch control circuit 114 sets each of the output signal and LGATE to a low logic level (i.e., ), so that the high-side power switch circuit (PMOS transistor MP) is turned on, and the low-side power switch circuit (NMOS transistor MN) is turned off. When the output node of the SR latch circuit 112 is reset to a low logic level (i.e., Q = 0), the switch control circuit 114 sets the output signal and LGATE are each set to a high logic level (i.e., ), so that the high-side power switch circuit (PMOS transistor MP) is not turned on, and the low-side power switch circuit (NMOS transistor MN) is turned on. In addition, when the feedback control signal ZX has a level transition from a low logic level (i.e., ZX=0) to a high logic level (i.e., ZX=1), the output signal LGATE is reset to a low logic level (i.e., LGATE=0), so that both the high-side power switch circuit (PMOS transistor MP) and the low-side power switch circuit (NMOS transistor MN) are not turned on.

[0070] The feedback control circuit 106 is used to generate a plurality of feedback control signals required by the PFM control circuit 104. In this embodiment, the feedback control circuit 106 includes a plurality of comparator circuits 116, 120, 122 and a current-to-voltage converter circuit (labeled as "I / V") 118. It is used to provide an inductor current flowing through the inductor L. The sensing current signal of the information is converted into a sensing voltage signal V by the current-to-voltage converter circuit 118. SEN , that is, the sensing voltage signal V SEN It will indicate the current value of the inductor current IL.

[0071] The comparator circuit 120 is used to compare the sensing voltage signal V SEN and the target peak current value V IPEAK (which is a voltage level for indicating the peak limit of the inductor current IL), and generates and outputs a feedback control signal VD_RST to a reset input node (labeled as “R”) of the SR latch circuit 112 .

[0072] The comparator circuit 116 is used to compare the output voltage VOUT of the PFM converter 100 with the reference voltage V REF , and generates and outputs a feedback control signal VD_SET to a set input node (labeled as “S”) of the SR latch circuit 112 .

[0073] The comparator circuit 122 is used to compare the voltage VLX at one end LX of the inductor L (which is also the connection node between the high-side power switch circuit (PMOS transistor MP) and the low-side power switch circuit (NMOS transistor MN) of the power stage circuit 102) with a reference voltage (e.g., the ground voltage GND) to perform zero crossing detection, and generate and output a feedback control signal ZX to the switch control circuit 114.

[0074] Please also read Figure 2 and Figure 1 . Figure 2 for Figure 1 Schematic diagram of waveforms of different signals of the PFM converter 100 shown in FIG. 1 . In order to better understand the technical features of the present invention, the operating principle of the PFM control adopted by the PFM converter 100 is briefly described as follows. When the output voltage VOUT drops below the reference voltage V REF When the feedback control signal VD_SET is set to a high logic level (i.e., VD_SET=1), the output node of the SR latch circuit 112 is set to a high logic level (i.e., Q=1) in response to the setting input node of the SR latch circuit 112 being set to be valid (i.e., S=VD_SET=1). Since the output node of the SR latch circuit 112 is set to a high logic level (i.e., Q=1), the high-side power switch circuit (PMOS transistor MP) is turned on, while the low-side power switch circuit (NMOS transistor MN) is not turned on. The inductor current IL increases due to charging through the turned-on high-side power switch circuit (PMOS transistor MP).

[0075] When the inductor current IL reaches the peak current limit, the sensing voltage signal V SEN (which has a voltage value representing the magnitude of the inductor current IL) will reach the target peak current value V IPEAK (which is a voltage level indicating the peak limit of the inductor current), and the feedback control signal VD_RST is set to a high logic level (i.e., VD_RST=1), so the output node of the SR latch circuit 112 is reset to a low logic level (i.e., Q=0) in response to the reset input node of the SR latch circuit 112 being set to be valid (i.e., R=VD_RST=1). Since the output node of the SR latch circuit 112 is reset to a low logic level (i.e., Q=0), the high-side power switch circuit (PMOS transistor MP) is not turned on, and the low-side power switch circuit (NMOS transistor MN) is turned on. The inductor current IL decreases due to discharge through the turned-on low-side power switch circuit (NMOS transistor MN). At this time, since the inductor current IL should be continuous, the voltage VLX becomes negative. Next, during the period when the inductor current IL decreases, the voltage VLX increases.

[0076] When the voltage VLX crosses the ground voltage GND, the feedback control signal ZX has a level transition from a low logic level (i.e., ZX=0) to a high logic level (i.e., ZX=1), thereby causing the switch control circuit 114 to turn off the low-side power switch circuit (NMOS transistor MN). Therefore, both the high-side power switch circuit (PMOS transistor MP) and the low-side power switch circuit (NMOS transistor MN) are not turned on, thereby causing the PFM converter 100 to enter an idle state.

[0077] The comparator circuit 116 monitors the output voltage VOUT of the PFM converter 100 to control the start time of the inductor charging state (at Figure 2 The comparator circuit 120 monitors the peak value of the inductor current IL of the PFM converter 100 to control the end time of the inductor charging state and the start time of the inductor discharging state (in Figure 2 The comparator circuit 122 monitors the zero crossing of the voltage VLX (ie, the zero crossing of the inductor current IL) to control the end time of the inductor discharge state (at Figure 2 However, due to certain factors, the actual timing of stopping the inductor charging state and / or the actual timing of stopping the inductor discharging state may deviate from Figure 2 , therefore, the power efficiency will be reduced due to the non-ideal state switching. In order to solve the problem of reduced power efficiency, the present invention proposes to use a correction circuit 124 to calibrate at least one circuit in the PFM converter 100 in a calibration mode. For example, at least one circuit in the PFM converter 100 may include one or both of the comparator circuit 120 and the comparator circuit 122. For example, the calibration mode may be a power-on calibration (POK) mode or a background calibration (background calibration) mode. The following describes further details of the correction circuit 124 with reference to the accompanying drawings.

[0078] Figure 3 3 is a schematic diagram of a calibration circuit operating in a power-on calibration mode according to an embodiment of the present invention. The calibration circuit 300 includes a signal generator circuit 302, a clock generator circuit (labeled as “clock generator”) 304, a mode switch circuit (labeled as “mode switch”) 306, and a calibration control circuit (labeled as “scan & search controller”) 308, wherein the signal generator circuit 302 includes a reference voltage generator circuit (labeled as “reference voltage generator”) 310 and an analog slope generator circuit (labeled as “analog slope generator”) 312. Figure 1 The calibration circuit 124 shown can be implemented using the calibration circuit 300. In the present embodiment, the calibration circuit 300 is used to calibrate the comparator circuit (labeled as “ZX CMP”) 122 by searching for an appropriate input DC offset VOS, wherein the input DC offset VOS is calibrated to ensure that the level transition of the output signal LGATE of the PFM control circuit (labeled as “Logic & Pre-driver”) 104 occurs at the expected timing.

[0079] The signal generator circuit 302 is used to perform slope prediction to generate and output an analog slope signal VSLP in a calibration mode (eg, a power-on calibration mode), wherein the analog slope signal VSLP has an analog slope after an initial voltage VSLP(0). And the simulated slope corresponds to the slope of the sensed signal indicating the electrical characteristics of the inductor L of the PFM converter 100. In this embodiment, the simulated slope Corresponding to the slope of the voltage VLX sensed from one end LX of the inductor L Specifically, the comparator circuit 122 has a non-inverting input node INP and an inverting input node INN, and the mode switching switch circuit 306 has a plurality of switches SW1, SW2, SW3, and SW4. When the PFM converter 100 operates in a normal mode, the switches SW1 and SW4 are turned on, while the switches SW2 and SW3 are turned off, thereby transmitting the voltage VLX and the ground voltage (e.g., 0V) to the non-inverting input node INP and the inverting input node INN, respectively. When the PFM converter 100 operates in a calibration mode (e.g., a power-on calibration mode), the switches SW1 and SW4 are turned off, while the switches SW2 and SW3 are turned on, thereby transmitting the ground voltage (e.g., 0V) and the analog slope signal VSLP to the non-inverting input node INP and the inverting input node INN, respectively.

[0080] like Figure 2 As shown in FIG. 1 , during the period when the voltage VLX is a negative voltage and increases as the inductor current IL decreases, the comparator circuit 122 is used to detect the occurrence of the zero crossing of the voltage VLX in the normal mode. From the hardware point of view, it is easier to generate a positive voltage than a negative voltage. In this embodiment, the analog slope signal VSLP generated by the signal generator circuit 302 has an initial voltage VSLP(0) set to a positive voltage and an analog slope set to a negative slope. Figure 2 As shown, in the normal mode, when the voltage VLX crosses zero, the output signal LGATE of the PWM control circuit 104 has a level transition from a high logic level “1” to a low logic level “0”. In order to keep the output signal LGATE having the same output polarity in the calibration mode, the analog slope signal VSLP (having a positive initial voltage and a negative slope) is provided to the inverting input node INN of the comparator circuit 122.

[0081] The calibration control circuit 308 is used to refer to the output signal generated by the PFM control circuit 104 in response to the output signal of the comparator circuit 122, so as to calibrate at least one circuit of the PFM converter 100 in the calibration mode. In the present embodiment, the output signal LGATE is received by the calibration control circuit 308, and the comparator circuit 122 is calibrated by the target control setting OS_code found by the calibration control circuit 308 in the calibration mode, wherein when the comparator circuit 122 operates in the normal mode, the target control setting OS_code sets the input DC offset VOS of the comparator circuit 122 (i.e., the DC offset of the input differential pair of the comparator circuit 122).

[0082] Please refer to Figure 5 and Figure 4 . Figure 4 is a schematic diagram of the zero crossing (hereinafter referred to as "ZX") path in the calibration mode. Figure 5 is a schematic diagram illustrating the concept of correcting the ZX path by using the analog slope signal proposed in this application. Figure 4 As shown, the comparator circuit 122 has an input DC offset VOS and a comparator delay Δt1, and the PFM control circuit 104 has a propagation delay Δt2. Therefore, when the analog slope signal VSLP (connected to the inverting input node INN of the comparator circuit 122) is equal to -VOS, the comparator circuit 122 detects a ZX event; the comparator output of the comparator circuit 122 has a delayed level transition in response to the detection of the ZX event; and the output signal LGATE of the PFM control circuit 104 has a delayed level transition in response to the comparator output of the comparator circuit 122. The total delay T of the ZX path is DLY Equal to Δt1+Δt2. Figure 5 As shown, the voltage VLX starts to rise at time point T0 (ie, the time point when the inductor current IL reaches the peak current limit) and is expected to reach the peak value at time point T2 (T2=T0+T COM ) across the ground voltage. The input DC offset VOS of the comparator circuit 122 is adjusted by the control setting OS_code output by the calibration circuit 300. Under the appropriate setting of the input DC offset VOS (eg, VOS=V DLY @OS_code=n), the comparator circuit 122 detects the ZX event at time point T1, and the output signal LGATE has a level transition at time point T2 (T2=T1+Δt1+Δt2). The initial voltage VSLP(0) of the analog slope signal VSLP can be designed according to the following formula.

[0083]

[0084] The analog slope of the analog slope signal VSLP may be designed according to the following formula.

[0085]

[0086] The DC offset and delay variation are all corrected together so that the output signal LGATE has a level transition (1→0) at or near the time point T2 when the voltage VLX just crosses the ground voltage.

[0087] In order to find an appropriate setting of the input DC offset VOS (e.g., OS_code=n) that enables the output signal LGATE to have a level transition (1→0) at or near the time point T2, the present invention proposes a calibration process that scans a plurality of different candidate control settings OS_code of the input DC offset VOS according to a control clock CK_CTRL. Figure 3 As shown, the clock generator circuit 304 receives a process-independent clock CK REF As a reference clock, the clock CK is independent of the process. REF The control clock CK_CTRL is generated by the clock generator circuit 304, and when the power-on calibration mode is enabled by the control signal POK_EN=1, the control clock CK_CTRL is output to the signal generator circuit 302 and the calibration control circuit 308. In addition, the clock generator circuit 304 generates and outputs the sampling clock ZX_sample to the calibration control circuit 308. The signal generator circuit 302 periodically resets the analog slope signal VSLP to the initial voltage VSLP(0) according to the control clock CK_CTRL, and the calibration control circuit 308 scans different candidate control settings OS_code of the input DC offset VOS according to the control clock CK_CTRL to find a target control setting OS_code of the input DC offset VOS that can make the output signal LGATE have a level transition (1→0) at or near the expected timing.

[0088] For example, the half cycle of the control clock CK_CTRL is equal to T COM (T COM =T2-T0), if the output signal LGATE is within a T under the current control setting OS_code of the input DC offset VOS COM If no level transition (1→0) occurs during the period, the analog slope signal VSLP will be reset at the end of one cycle of the control clock CK_CTRL. If the output signal LGATE is TCOM If no level transition (1→0) occurs during the period, the calibration control circuit 308 will control the T COM period to select the next control setting OS_code.

[0089] Please also read Figure 7 and Figure 6 . Figure 6 The figure is a flow chart of a power-on calibration method according to an embodiment of the present invention. Figure 7 yes Figure 3 Waveform diagrams of different signals of the correction circuit 300 are shown. Figure 3 The calibration circuit 300 shown can be used with the calibration method of the present invention. If the results are roughly the same, the steps do not necessarily need to be completely followed. Figure 6 After the PFM converter 100 is powered on (BUCK_EN=1) and the power-on calibration is enabled (POK_EN=1), the calibration circuit 300 begins to calibrate the input DC offset VOS of the comparator circuit 122 (steps S602, S604 and S606). In step S606, the clock generator circuit 304 sets the control clock CK_CTRL to 0 (CK_CTRL=0) to reset the power-on calibration, the calibration control circuit 308 sets the control signal POK_Done to 0 (POK_Done=0) to instruct the mode switching circuit 306 to select the ground voltage (e.g., 0V) and the analog slope signal VSLP as the input of the comparator circuit 122 in the power-on calibration mode, the calibration control circuit 308 sets the control setting OS_code to 0 (OS_code=0) to select the initial value VOS_RG of the input DC offset VOS of the comparator circuit 122 (e.g., depending on actual design considerations, the initial value VOS_RG may be the maximum positive value (positive maximum) of the input DC offset VOS of the comparator circuit 122 or the maximum negative value (negative maximum) of the input DC offset VOS of the comparator circuit 122), and the signal generator circuit 302 sets the analog slope signal VSLP to the initial voltage VSLP(0).

[0090] When the control clock CK_CTRL generated by the clock generator circuit 304 switches from 0 to 1 (CK_CTRL=1), the analog slope signal VSLP generated by the signal generator circuit 302 starts to decrease (steps S608 and S610). COMAt the end of the period, the analog slope signal VSLP switches from 1 to 0 (CK_CTRL=0), and the signal generator circuit 302 resets the analog slope signal VSLP to the initial voltage VSLP(0). During the period when the control clock CK_CTRL is set to 0, the calibration control circuit 308 is triggered by the ZX sampling clock ZX_sample to sample the output signal LGATE to determine whether the output signal LGATE has a level transition (1→0) under the current control setting OS_code. If it is determined that the output signal LGATE has not yet undergone a level transition (1→0), the calibration control circuit 308 increases the control setting OS_code (for example, OS_code=OS_code+1) to select the next value VOS_RG of the input DC offset VOS of the comparator circuit 122. For example, when OS_code=0 is to select the maximum positive value of the input DC offset VOS of the comparator circuit 122, OS_code+1 is to reduce the input DC offset VOS of the comparator circuit 122. In another example, when OS_code=0 is to select the maximum negative value of the input DC offset VOS of the comparator circuit 122, OS_code+1 is to increase the input DC offset VOS of the comparator circuit 122. Steps S608, S610, S612, S614, and S616 are repeatedly executed until the calibration control circuit 308 determines that the output signal LGATE has a level transition (1→0) in step S614. In step S618, the calibration control circuit 308 writes the current control setting OS_code to a storage device (e.g., a register) as the target control setting RG_ZX of the input DC offset VOS of the comparator circuit 122, wherein the target control setting RG_ZX found by the power-on calibration will be applied to the comparator circuit 122 in the normal mode. In step S620, the calibration control circuit 308 sets the control signal POK_Done to 1 (POKDone=1) to instruct the mode switching circuit 306 to select the ground voltage and the voltage VLX as the input of the comparator circuit 122 in the normal mode, and the calibration circuit 300 is turned off to stop the power-on calibration. In step S622, the PFM converter 100 executes a start-up sequence to enter the normal mode.

[0091] As described above, the signal generator circuit 302 is used to generate the analog slope signal VSLP having a positive initial voltage VSLP(0) and a negative slope. In one embodiment of the present invention, the signal generator circuit 302 may be implemented using a current over capacitor (I / C) slope generator circuit. Figure 8 FIG. 1 is a schematic diagram of a current / capacitance slope generator circuit according to an embodiment of the present invention. Figure 8As shown in the sub-diagram (A) of FIG. 8 , the current / capacitance slope generator circuit 800 includes a power transistor (NMOS transistor) MPWR having a channel resistance rds, a current source I REF , capacitor C CAL , a voltage-to-current converter 802, a unity-gain buffer 804, and a plurality of switches 806, 808, wherein the switches 806, 808 are controlled by non-overlapping clocks. Figure 8 As shown in sub-figure (B) of , the initial voltage VSLP(0) of the analog slope signal VSLP can be designed according to the following formula.

[0092] VSLP(0)=VSLP×T COM =I REF ×rds (3)

[0093] The analog slope of the analog slope signal VSLP may be designed according to the following formula.

[0094] V REF =I REF ×rds (4)

[0095]

[0096] The change of rds will produce a gain error, which will cause the VLX slope to change with a positive correlation. The initial voltage VSLP(0) is designed to have an rds-positive-variation, which is the same as the variation of the slope of VLX, so that the gain error caused by rds is also corrected. Note that the total delay Nothing to do with rds.

[0097] Please note that the present invention has no particular limitation on the implementation of the signal generator circuit 302. In another embodiment of the present invention, the signal generator circuit 302 may be implemented using a switched-capacitor (SC) slope generator circuit. Fig. 9 is a schematic diagram of different phases of the switched capacitor slope generator circuit 900 . Fig.10 yes Fig. 9 The waveform diagrams of different signals of the switched capacitor slope generator circuit 900 are shown. The initial voltage VSLP(0) of the analog slope signal VSLP can be designed according to the following formula.

[0098] VSLP(0)=VSLP×TC OM =K×IREF ×rds (6)

[0099] The analog slope of the analog slope signal VSLP may be designed according to the following formula.

[0100] V REF =I REF ×rds (7)

[0101]

[0102] In the above embodiment, Figure 1 The correction circuit 124 shown may be used Figure 3 The calibration circuit 300 is implemented to perform power-on calibration, so that the calibration of the PFM converter 100 is performed once each time the PFM converter 100 is powered on. However, this is only for illustrative purposes and is not intended to be a limitation of the present invention. The same concept of using an analog slope signal to calibrate a PFM converter can also be applied to the design of background calibration.

[0103] Fig.11 1 is a schematic diagram of a correction circuit operating in a background correction mode according to an embodiment of the present invention. The PFM converter 100 may further include a replica circuit 1130, which is subject to the same power supply effect and temperature effect as the real circuit 1120, wherein the real circuit 1120 actually participates in regulating the output voltage VOUT supplied by the PFM converter 100 to the load device, while the replica circuit 1130 is only used for background correction and does not actually participate in regulating the output voltage VOUT supplied by the PFM converter 100 to the load device. Fig.11 As shown, the comparator circuit (labeled as "ZX CMP") 1132 is Figure 1 A replica of the comparator circuit 122 shown, the PFM control circuit (labeled "Logic & Pre-Driver") 1134 is Figure 1 The PFM control circuit 104 is shown as a replica, and the capacitor C G_K The design is to have an estimated capacitance of the low-side power switch circuit (NMOS transistor MN), and the output signal ZX_K has an estimated voltage of the output signal LGATE.

[0104] The correction circuit 1100 includes a signal generator circuit 1102, a clock generator circuit (labeled as “clock generator”) 1104 and a correction control circuit (labeled as “scan & search controller”) 1106, wherein the signal generator circuit 1102 includes a reference voltage generator circuit (labeled as “reference voltage generator”) 1108 and an analog slope generator circuit (labeled as “analog slope generator”) 1110. Figure 1 The calibration circuit 124 shown can be implemented using the calibration circuit 1100. In the present embodiment, the calibration circuit 1100 is used to search for an appropriate input DC offset VOS under background calibration through the replica circuit 1130 to calibrate the comparator circuit 122, wherein the input DC offset VOS of the comparator circuit 122 is calibrated to ensure that the level transition of the output signal LGATE of the PFM control circuit 104 occurs at or near the expected timing.

[0105] The signal generator circuit 1102 is used to generate and output an analog slope signal VSLP to the comparator circuit (replica circuit) 1132 in the background correction mode, wherein the analog slope signal VSLP has an analog slope after the initial voltage VSLP(0). And the simulated slope corresponds to the slope of the sensed signal indicating the electrical characteristics of the inductor L of the PFM converter 100. In this embodiment, the simulated slope Corresponding to the slope of the voltage VLX sensed from one end LX of the inductor L Specifically, the comparator circuit 1132 has a non-inverting input node INP and an inverting input node INN. From a hardware point of view, it is easier to generate a positive voltage than a negative voltage. In this embodiment, the initial voltage VSLP(0) of the analog slope signal VSLP generated by the signal generator circuit 1100 is set to a positive voltage, and the analog slope is set to a negative slope. The signal generator circuit 1102 can adopt a switched capacitor slope generating circuit (for example, the switched capacitor slope generating circuit 900), so the clock generator circuit 1104 can also generate and output the control clock CK_SC required by the switched capacitor slope generator circuit. However, this is only used as an example for illustration and is not intended to be a limitation of the present invention. In another embodiment, the signal generator circuit 1102 can adopt a current / capacitance slope generator circuit (for example, the current / capacitance slope generator circuit 800), and the clock generator circuit 1104 can omit the generation of the control clock CK_SC.

[0106] The calibration control circuit 1106 is used to calibrate at least one circuit (actual circuit) in the PFM converter 100 by referring to the output signal generated by the PFM control circuit (replica circuit) 1134 in response to the output signal of the comparator circuit (replica circuit) 1132. In this embodiment, the output signal ZX_K of the PFM control circuit (replica circuit) 1134 is received by the calibration control circuit 1106, and the comparator circuit 122 is calibrated by the final control setting OS_code recorded by the calibration control circuit 1106, wherein the final control setting OS_code is determined by scanning a plurality of different candidate control settings OS_codes of the input DC offset VOS of the comparator circuit 1132.

[0107] Fig.12 is a flow chart of a background correction method according to an embodiment of the present invention. Fig.11 The calibration circuit 1100 shown uses the same steps as above, provided that the same results are obtained. Fig.12 The calibration circuit 1100 is executed in the order shown. After receiving the trigger pulse Auto_k_trigger, the calibration circuit 1100 starts to perform background calibration of the comparator circuit 122 of the PFM converter 100 (steps S1202 and S1204). If necessary, the trigger pulse Auto_k_trigger can be sent from the system periodically or once. In step S1204, the clock generator circuit 1104 sets the control clock CK_CTRL to 0 (CK_CTRL=0) to reset the background calibration, the calibration control circuit 1106 sets the control setting OS_code to 0 (OS_code=0) to select the initial value of the input DC offset VOS of the comparator circuit 1132 (for example, depending on actual design considerations, the initial value can be the maximum positive value of the input DC offset VOS of the comparator circuit 1132 or the maximum negative value of the input DC offset VOS of the comparator circuit 1132), and the signal generating circuit 1102 sets the analog slope signal VSLP to the initial voltage VSLP(0).

[0108] When the control clock CK_CTRL generated by the clock generator circuit 1104 switches from 0 to 1 (CK_CTRL=1), the analog slope signal VSLP generated by the signal generator circuit 1102 starts to decrease (steps S1206 and S1208). When the control clock CK_CTRL generated by the clock generator circuit 1104 switches from 1 to 0 (CK_CTRL=0), the signal generator circuit 1102 resets the analog slope signal VSLP to the initial voltage VSLP(0). During the period when the control clock CK_CTRL is set to 0, the calibration control circuit 1106 samples the output signal ZX_K under the triggering of the ZX sampling clock ZX_sample to determine whether the output signal ZX_K has a level transition (1→0) under the current control setting OS_code. If it is determined that the output signal ZX_K has not undergone a level transition (1→0), the calibration control circuit 1106 increases the control setting OS_code (for example, OS_code=OS_code+1) to select the next value of the input DC bias voltage VOS of the comparator circuit 122. For example, when OS_code=0 is the maximum positive value of the input DC bias voltage VOS of the comparator circuit 122, OS_code+1 will reduce the input DC bias voltage VOS of the comparator circuit 122. In another example, when OS_code=0 is the maximum negative value of the input DC bias voltage VOS of the comparator circuit 122, OS_code+1 will increase the input DC bias voltage VOS of the comparator circuit 122. Steps S1206, S1208, S1210, S1212, and S1214 are repeatedly performed until the calibration control circuit 1106 determines that the output signal ZX_K has a level transition (1→0) in step S1212. In step S1216, the calibration control circuit 1106 writes the current control setting OS_code into a storage device (e.g., a register) as a target control setting of the input DC offset VOS of the comparator circuit 122, wherein the target control setting found by the background calibration of the replica circuit is used to calibrate the comparator circuit 122. In step S1218, the correction circuit 1100 stops the background correction.

[0109] In the above embodiment, the calibration circuit 300 / 1100 is used to calibrate the comparator circuit 122 by finding a suitable input DC offset VOS, wherein the input DC offset VOS is calibrated to ensure that the output signal LGATE of the PFM control circuit 104 undergoes a level transition (1→0) at or near the expected timing. The same calibration concept can be applied to the comparator circuit 120, that is, the comparator circuit 120 can be calibrated by finding a suitable input DC offset VOS, wherein the input DC offset VOS is calibrated to ensure that the output signal OC (OC=LGATE or )A level transition (0→1) occurs at or near the expected timing.

[0110] Fig.13 Schematic diagram of another calibration circuit operating in a power-on calibration mode according to an embodiment of the present invention. The calibration circuit 1300 includes a signal generator circuit 1302, a clock generator circuit (labeled as “clock generator”) 1304, a mode switching circuit (labeled as “mode switching circuit”) 1306, and a calibration control circuit (labeled as “scan & search controller”) 1308, wherein the signal generator circuit 1302 includes a reference voltage generator circuit (labeled as “reference voltage generator”) 1310 and an analog slope generator circuit (labeled as “analog slope generator”) 1312. Figure 1 The calibration circuit 124 shown can be implemented using the calibration circuit 1300. In this embodiment, the calibration circuit 1300 is used to calibrate the comparator circuit (labeled as "OC CMP") 120 by finding a suitable input DC bias voltage VOS, wherein the input DC bias voltage VOS is calibrated to ensure that the output signal OC (e.g., OC=LGATE or OC=LGATE) of the PFM control circuit (labeled as "Logic & Pre-driver") 104 is ) occurs at or near the expected timing.

[0111] The signal generator circuit 1302 is used to generate and output an analog slope signal VSLP to a comparator circuit (e.g., the comparator circuit 120) in a calibration mode (e.g., a power-on calibration mode), wherein the analog slope signal VSLP has an analog slope after an initial voltage VSLP(0). And the simulated slope The slope of the sensing signal corresponding to the electrical characteristic of the inductor L of the PFM converter 100 is, in this embodiment, the analog slope It will correspond to the voltage V sensed from the inductor current IL of the inductor L. SEN The slope

[0112] Specifically, the comparator circuit 120 has a non-inverting input node INP and an inverting input node INN, and the mode switching circuit 1306 has a plurality of switches SW1, SW2, SW3, and SW4. When the PFM converter 100 operates in the normal mode, the switches SW1 and SW4 are turned on, and the switches SW2 and SW3 are not turned on, thereby transmitting the voltage V SEN and the target peak current value V IPEAK(which is a voltage level indicating the peak limit of the inductor current IL) to the non-inverting input node INP and the inverting input node INN. When the PFM converter 100 operates in a calibration mode (e.g., a power-on calibration mode), the switches SW1 and SW4 are not turned on, and the switches SW2 and SW3 are turned on, thereby respectively passing the target peak current value V IPEAK (which is a voltage level indicating the peak limit of the inductor current IL) and the analog slope signal VSLP to the non-inverting input node INP and the inverting input node INN.

[0113] When the calibration mode (eg, power-on calibration mode) is enabled by POK_EN=1, the clock generator circuit 1304 receives a clock CK that is independent of the process. REF , based on the process-independent clock CK REF To generate the control clock CK_CTRL, and output the control clock CK_CTRL to the signal generator circuit 1302 and the calibration control circuit 1308. In addition, the clock generator circuit 1304 generates the sampling clock OC_sample to the calibration control circuit 1308.

[0114] In this embodiment, the signal generator circuit 1302 may be a switched capacitor slope generator circuit (e.g., the switched capacitor slope generator circuit 900). Therefore, the clock generating circuit 1304 may generate and output a control clock CK_SC required by the switched capacitor slope generator circuit. The initial voltage VSLP(0) of the analog slope signal VSLP may be designed based on the following formula.

[0115] VSLP(0)=VSLP×T COM =K×I RRG ×R HR , where R HR is the channel resistance of the high-side power switch circuit (PMOS transistor MP) (9)

[0116] The analog slope of the analog slope signal VSLP may be designed based on the following formula.

[0117] V REF =I REF ×R HR (10)

[0118]

[0119] However, this is only used as an example and is not intended to be limiting of the present invention. In another embodiment, the signal generator circuit 1302 may use a current / capacitance slope generator circuit (eg, current / capacitance slope generator circuit 800), and the clock generator circuit 1304 may omit the generation of the control clock CK_SC.

[0120] The calibration control circuit 1308 is used to refer to the output signal generated by the PFM control circuit 104 in response to the output signal of the comparator circuit 120 to calibrate at least one circuit of the PFM converter 100 in the calibration mode. In this embodiment, the calibration control circuit 1308 receives the output signal OC (e.g., OC=LGATE or ), and calibrates the comparator circuit 120 by the control setting OS_code generated by the correction control circuit 1308, wherein the control setting OS_code sets the input DC offset VOS of the comparator circuit 120 (specifically, the DC offset of the input differential pair of the comparator circuit 120).

[0121] The working principle of the correction circuit 1300 is similar to Figure 3 The correction circuit 300 shown is similar. Since a person skilled in the art can easily understand the details of the correction circuit 1300 after reading the above description paragraphs for the correction circuit 300, for the sake of brevity, the similar description of the correction circuit 1300 is omitted here and will not be repeated.

[0122] Fig.14 FIG. 1 is a schematic diagram of another correction circuit operating in a background correction mode according to an embodiment of the present invention. The PFM converter 100 may further include a replica circuit 1430, which is subject to the same power supply effect and temperature effect as the actual circuit 1420, wherein the actual circuit 1420 actually participates in regulating the output voltage VOUT supplied by the PFM converter 100 to the load device, while the replica circuit 1430 is only used for background correction and does not actually participate in regulating the output voltage VOUT supplied by the PFM converter 100 to the load device. Fig.14 As shown, the comparator circuit (labeled as “OC CMP”) 1432 is a copy of the comparator circuit 120, the PFM control circuit (labeled as “Logic & Pre-driver”) 1434 is a copy of the PFM control circuit 104, and the capacitor C G_K The design is to have an estimated capacitance value of the power switch circuit (NMOS transistor MN or PMOS transistor MP), and the output signal OC_K has an estimated voltage of the output signal OC.

[0123] The correction circuit 1400 includes a signal generator circuit 1402, a clock generator circuit (labeled as “clock generator”) 1404, and a correction control circuit (labeled as “scan & search controller”) 1406, wherein the signal generator circuit 1402 includes a reference voltage generator circuit (labeled as “reference voltage generator”) 1408 and an analog slope generator circuit (labeled as “analog slope generator”) 1410. Figure 1The correction circuit 124 shown can be implemented using the correction circuit 1400. In this embodiment, the correction circuit 1400 is used to search for an appropriate input DC offset VOS through the replica circuit 1430 to calibrate the comparator circuit 120, wherein the input DC offset VOS of the comparator circuit 120 is corrected to ensure that the level transition of the output signal OC of the PFM control circuit 104 occurs at or near the expected timing.

[0124] The signal generator circuit 1402 is used to generate and output an analog slope signal VSLP to the comparator circuit (replica circuit) 1432 in the background correction mode, wherein the analog slope signal VSLP has an analog slope after the initial voltage VSLP(0). And the simulated slope corresponds to the slope of the sensed signal indicating the electrical characteristics of the inductor L of the PFM converter 100. In this embodiment, the simulated slope Corresponding to the slope of the voltage VLX sensed from one end LX of the inductor L In this embodiment, the signal generator circuit 1402 may adopt a switched capacitance slope generator circuit (e.g., the switched capacitance slope generator circuit 900), and therefore, the clock generator circuit 1404 may also generate and output the control clock CK_SC required by the switched capacitance slope generator circuit. However, this is only for illustrative purposes and is not intended to be a limitation of the present invention. In another embodiment, the signal generator circuit 1402 may adopt a current / capacitance slope generator circuit (e.g., the current / capacitance slope generator circuit 800), and the clock generator circuit 1404 may omit the generation of the control clock CK_SC.

[0125] The calibration control circuit 1406 is used to calibrate at least one circuit (actual circuit) in the PFM converter 100 by referring to the output signal generated by the PFM control circuit (replica circuit) 1434 in response to the output signal of the comparator circuit (replica circuit) 1432. In this embodiment, the output signal OC_K of the PFM control circuit (replica circuit) 1434 is received by the calibration control circuit 1406, and the comparator circuit 120 is calibrated by the final control setting OS_code recorded by the calibration control circuit 1406, wherein the final control setting OS_code is determined by scanning a plurality of different candidate control settings OS_codes of the input DC offset VOS of the comparator circuit 1432.

[0126] The working principle of the correction circuit 1400 is similar to Fig.11The correction circuit 1100 shown is similar. Since a person skilled in the art can easily understand the details of the correction circuit 1400 after reading the above description paragraphs for the correction circuit 1100, for the sake of brevity, similar descriptions of the correction circuit 1400 are omitted here and will not be repeated.

[0127] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A correction circuit for a pulse frequency modulation converter, comprising: a signal generator circuit for generating and outputting an analog slope signal to a comparator circuit under a calibration mode, wherein the analog slope signal has an analog slope after an initial voltage, and the analog slope signal corresponds to a slope of a sense signal indicating an electrical characteristic of an inductor of the pulse frequency modulation converter; and The calibration control circuit is used to calibrate at least one circuit in the pulse frequency modulation converter by referring to the output signal generated by the pulse frequency modulation control circuit in response to the output signal of the comparator circuit.

2. The calibration circuit as claimed in claim 1, wherein the sensing signal is received by the comparator circuit under a normal mode, and the output signal of the comparator circuit is received by the pulse frequency modulation control circuit under the normal mode. 3 . The calibration circuit of claim 2 , wherein the at least one circuit comprises the comparator circuit.

4. The correction circuit as described in claim 1, wherein the comparator circuit is a copy of another comparator circuit, and the other comparator circuit is used to receive the sensing signal; and the pulse frequency modulation control circuit is a copy of another pulse frequency modulation control circuit, and the other pulse frequency modulation control circuit is used to receive the output signal of the other comparator circuit. 5 . The calibration circuit of claim 4 , wherein the at least one circuit comprises the other comparator circuit.

6. The correction circuit as claimed in claim 1, further comprising: A clock generator circuit, for generating and outputting a control clock to the signal generator circuit and the calibration control circuit in the calibration mode; The signal generator circuit periodically resets the analog slope signal to the initial voltage according to the control clock; and the correction control circuit scans a plurality of different candidate control settings according to the control clock, wherein the at least one circuit is corrected by a target control setting selected from the plurality of different candidate control settings.

7. The calibration circuit as claimed in claim 6, wherein when the output signal of the pulse frequency modulation control circuit has a level transition under the candidate control setting, the calibration control circuit is further configured to write the candidate control setting into a storage device as the target control setting and stop the calibration mode. 8 . The calibration circuit as claimed in claim 1 , wherein the sensing signal is indicative of a voltage at a terminal of the inductor. 9 . The calibration circuit as claimed in claim 8 , wherein the initial voltage of the analog slope signal is a positive voltage, and the analog slope is a negative slope. 10 . The calibration circuit as claimed in claim 1 , wherein the sensing signal is indicative of an inductor current of the inductor.

11. A calibration method for a pulse frequency modulation converter, comprising: generating and outputting an analog slope signal to a comparator circuit in a calibration mode, wherein the analog slope signal has an analog slope after an initial voltage, and the analog slope signal corresponds to a slope of a sense signal indicative of an electrical characteristic of an inductor of the pulse frequency modulation converter; and At least one circuit in the pulse frequency modulation converter is calibrated according to an output signal generated by the pulse frequency modulation control circuit in response to the output signal of the comparator circuit. 12 . The calibration method of claim 11 , wherein the sensing signal is received by the comparator circuit in a normal mode, and the output signal of the comparator circuit is received by the pulse frequency modulation control circuit in the normal mode.

13. The calibration method as claimed in claim 12, wherein the at least one circuit comprises the comparator circuit.

14. The calibration method as claimed in claim 11, wherein the comparator circuit is a copy of another comparator circuit, and the other comparator circuit is used to receive the sensing signal; and the pulse frequency modulation control circuit is a copy of another pulse frequency modulation control circuit, and the other pulse frequency modulation control circuit is used to receive the output signal of the other comparator circuit.

15. The calibration method as claimed in claim 14, wherein the at least one circuit comprises the other comparator circuit.

16. The calibration method according to claim 11, further comprising: Generate and output control clock; The step of generating and outputting the analog slope signal to the comparator circuit under the calibration mode comprises: Periodically resetting the analog slope signal to the initial voltage according to the control clock; The step of calibrating the at least one circuit in the pulse frequency modulation converter according to the output signal generated by the pulse frequency modulation control circuit in response to the output signal of the comparator circuit comprises: A plurality of different candidate control settings are scanned according to the control clock, wherein the at least one circuit is calibrated by a target control setting selected from the plurality of different candidate control settings.

17. The calibration method of claim 16, wherein the step of calibrating the at least one circuit in the PFM converter according to the output signal generated by the PFM control circuit in response to the output signal of the comparator circuit further comprises: In response to the output signal of the pulse frequency modulation control circuit having a level transition under a candidate control setting, the candidate control setting is written into a storage device as the target control setting, and the calibration mode is stopped. 18 . The calibration method as claimed in claim 11 , wherein the sensing signal indicates a voltage at a terminal of the inductor. 19 . The calibration method as claimed in claim 18 , wherein the initial voltage of the analog slope signal is a positive voltage, and the analog slope is a negative slope. 20 . The calibration method as claimed in claim 11 , wherein the sensing signal is indicative of an inductor current of the inductor.

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