Three-level SVPWM (Space Vector Pulse Width Modulation) algorithm based on redundant switch sequence

Abstract

The invention provides a three-level SVPWM (Space Vector Pulse Width Modulation) algorithm based on a redundant switch sequence, and belongs to the technical field of pulse width modulation of a three-level inverter. According to the technical scheme, the method comprises the following steps that S1, a new region division mode is provided, and each large sector is divided into four small regions; s2, proposing a concept of a redundant switch sequence, and constructing the redundant switch sequence in the small region; s3, the redundant switching sequence is adjusted, and the switching frequency of the inverter is reduced; s4, determining a target area where the reference voltage vector is located; s5, determining a related voltage vector required for synthesizing the reference voltage vector, and solving the duty ratio of the related voltage vector; and S6, determining a target switch sequence, and emitting a PWM wave. The method has the beneficial effects that the midpoint potential fluctuation of the NPC three-level inverter within the full power factor and full modulation degree range can be inhibited, and the switching loss of the NPC three-level inverter is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of pulse width modulation of a three-level inverter, and in particular to a three-level SVPWM modulation algorithm based on a redundant switching sequence. Background Art

[0002] Neutral point clamped (NPC) three-level inverter (TLI) is widely used in renewable energy power generation, motor drive and other occasions due to its advantages such as small voltage stress on switching devices, high output efficiency and low total harmonic distortion of output voltage. However, NPC_TLI has the technical problem of unbalanced midpoint potential.

[0003] To solve the technical problem of unbalanced midpoint potential of NPC three-level inverter, the traditional Nearest Three Vector (NTV) algorithm mostly uses redundant small vectors to adjust the midpoint potential. However, the algorithm is not capable of suppressing midpoint potential fluctuation under high regulation and low power factor. Therefore, some experts proposed the Nearest Three Virtual Vector (NTV) algorithm. 2 ) algorithm, which synthesizes the virtual voltage space vector by selecting the appropriate basic voltage vector, so that the average midpoint current is zero when the virtual vector acts, thereby achieving unconditional suppression of midpoint potential fluctuations. However, the switching frequency is increased by 1 / 3 compared with the NTV algorithm, and the switching loss is high. Therefore, some experts have proposed a method based on NTV and NTV. 2 However, the hybrid control algorithm is more complicated to implement and still has high switching losses under high modulation index and low power factor.

[0004] In order to reduce the switching loss of the inverter, some experts have proposed various improved DPWM algorithms, which control the midpoint potential by selecting different clamping modes. The switching loss of this algorithm is significantly lower than that of the traditional NTV algorithm, but under high modulation and low power factor, the pre-selected clamping mode may have an average midpoint current in the same direction, and it is impossible to select a clamping mode that is favorable to the midpoint potential. Therefore, the midpoint potential has low-frequency oscillations. Due to the large number of pre-selected clamping modes, this algorithm is more complicated to implement.

[0005] How to solve the above technical problems is the subject faced by the present invention. Summary of the invention

[0006] The traditional Nearest Three Vector (NTV) algorithm and various improved DPWM algorithms have low-frequency oscillation of midpoint potential under high modulation degree and low power factor, as well as the traditional Nearest Three Virtual Vector (NTV 2) algorithm has high switching loss and slow speed of adjusting the midpoint potential deviation. The purpose of the present invention is to provide a three-level SVPWM modulation algorithm based on redundant switching sequence. To address the shortcomings of the existing three-level modulation technology, the present invention can suppress the midpoint potential fluctuation of the NPC three-level inverter within the full power factor and full modulation range, and reduce the switching loss of the NPC three-level inverter.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is specifically: a three-level SVPWM modulation algorithm based on redundant switching sequence, comprising the following steps:

[0008] S1: A new area division method is proposed, which divides each large sector into four small areas.

[0009] S2: Propose the concept of redundant switch sequence and construct the redundant switch sequence in the small area.

[0010] S3: Adjust the redundant switching sequence to reduce the switching frequency of the inverter.

[0011] S4: Determine the target area where the reference voltage vector is located.

[0012] S5: Determine the related voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the related voltage vector.

[0013] S6: Determine the target switching sequence and send out a PWM wave.

[0014] Furthermore, in step S1, a new area division method is proposed to divide each large sector into four small areas.

[0015] like Figure 4 As shown, the connection line L1 of the basic voltage vector POO (or ONN) and PPO (or OON), the voltage vector U m The connection line L2 with the basic voltage vector PPN, the voltage vector U m The line L3 connecting the basic voltage vector PNN divides sector I into four small areas: A1, A2, A3, and A4. m The basic voltage vectors POO (or ONN) and PPO (or OON) are applied for the same time to obtain:

[0016]

[0017] The other five large sectors are divided in the same way, e.g. Figure 6 shown.

[0018] Furthermore, in step S2, the concept of a redundant switch sequence is proposed, and a redundant switch sequence in the small area is constructed.

[0019] The concept of redundant switching sequence is proposed: two switching sequences with the same voltage effect, equal average midpoint current and opposite directions are redundant switching sequences.

[0020] Construct the redundant switch sequence in the four areas of sector I, as shown in Table 1 below:

[0021] Table 1

[0022]

[0023] Redundant switching sequences in other large sectors are constructed in the same way.

[0024] Furthermore, in step S3, the redundant switching sequence in step S2 is adjusted to reduce the switching frequency of the inverter.

[0025] The rules for adjusting the redundant switch sequence are as follows: before and after the adjustment, the action time of the three switch states P, O, and N of the three phases A, B, and C remain unchanged; after the adjustment, the switch tube does not operate when switching between switch sequence 1 and switch sequence 2; after the adjustment, the number of switch operations in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to a minimum.

[0026] Take sector I as an example: Figure 7 is the redundant switch sequence before adjustment of area A1, Figure 8 This is the redundant switch sequence after adjustment in region A1. It can be seen that after the adjustment, the switch tube operates 4 times in each switching cycle, and the switch tube does not operate when switching between switch sequence 1 and switch sequence 2. Compared with before adjustment, the number of switches is significantly reduced. Fig. 9 , Fig.10 , Fig.11 These are the adjusted redundant switch sequences for areas A2, A3, and A4 respectively.

[0027] The redundant switching sequences of other large sectors are adjusted in the same way.

[0028] Further, in step S4, the target region where the reference voltage vector is located is determined.

[0029] The target area is one of the four small areas described in step S1.

[0030] Take sector I as an example to illustrate:

[0031] In order to simplify the algorithm, the reference voltage U ref The coordinate system can be transformed from the α-β (90 degrees) coordinate system to the gh (60 degrees) coordinate system by coordinate transformation, with the reference voltage U ref The component on the gh axis is:

[0032]

[0033] Where: u α 、u β Respectively represent the reference voltage U ref The horizontal and vertical components in the α-β (90 degrees) coordinate system.

[0034] To u g1 and u h1 After normalization, we can get u g and u h , the reference value is u dc / 3,u dc is the DC side voltage:

[0035]

[0036] The lines L1, L2, and L3 in step S1 can be expressed as:

[0037] L1:u g +u h -1=0

[0038] L2:

[0039] L3:3u g +u h -2=0

[0040] From this, we can derive the judgment conditions of the target area, as shown in Table 2:

[0041] Table 2

[0042]

[0043] According to Table 2 above, the target area where the reference voltage vector is located can be determined. When the reference voltage vector is located in other large sectors, it can be rotated to sector I to determine the target area.

[0044] Furthermore, in step S5, the related voltage vector required for synthesizing the reference voltage vector is determined, and the duty cycle of the related voltage vector is calculated.

[0045] Based on the region determination in step S4 , a related voltage vector of the synthetic reference voltage may be determined.

[0046] like Figure 5 As shown, when the target area where the reference voltage vector is located is area A1, the related voltage vector is U s1 , U s2 , U0, according to the volt-second balance principle, the equation can be established:

[0047]

[0048] Where: d1, d2, d3 represent the voltage vector U s1 , U s2 , the duty cycle of U0.

[0049] The above formula can be expressed in the gh coordinate system as:

[0050]

[0051] From the above formula, we can get:

[0052]

[0053] Similarly, the duty cycle of the relevant voltage vector required when the reference vector is located in other areas can be calculated.

[0054] Furthermore, in step S6, a target switching sequence is determined and a PWM wave is emitted.

[0055] The target switching sequence is a switching sequence in the redundant switching sequences described in step S2.

[0056] The expected midpoint current is defined as:

[0057]

[0058] Where: T s represents the switching period, u c1 、u c2 are the voltages across the DC side capacitors c1 and c2 respectively, and C is the capacitance value of c1 and c2.

[0059] Take area A1 of sector Ⅰ as an example:

[0060] When the target region where the reference voltage vector is located is region A1, it is necessary to select an average midpoint current and the expected midpoint current i from the redundant switching sequence of region A1. NP The switch sequence with the same direction is taken as the target switch sequence to realize the midpoint potential control. Switch sequence 1 (ONN-OON-OOO) and switch sequence 2 (POO-PPO-OOO) are redundant switch sequences in region A1. In switch sequence 1, the switch states that affect the midpoint current are ONN and OON. The midpoint currents when the switch states ONN and OON are in effect are i A 、-i C , the duty ratios are d1 and d2 respectively. d1 and d2 are obtained in step S5, so the average midpoint current when the switch sequence 1 is in effect is:

[0061] i1=i A ·d1-i C ·d2

[0062] If i1 and i NP The direction of i1 and i NP The direction is opposite to that of the switch sequence, and the target switch sequence is switch sequence 2.

[0063] After the target switching sequence is determined, the duty ratios of the three switching states P, O, and N of the three phases A, B, and C can be calculated respectively, and the switching sequence adjusted in step S3 using the target switching sequence is used as the final switching sequence to generate a modulation wave and emit a PWM wave.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] 1. The present invention proposes a three-level SVPWM modulation algorithm based on redundant switching sequence, which can achieve midpoint potential fluctuation suppression within the full power factor and full modulation range. Fig.14 It can be seen that the modulation algorithm proposed in the present invention can well solve the problem of low-frequency oscillation of midpoint potential existing in the traditional NTV algorithm under high modulation degree and low power factor. Fig.13 and Fig.15 It can be seen that the modulation algorithm proposed in this invention can well solve the traditional NTV 2 The algorithm is slow in adjusting the midpoint potential deviation.

[0066] 2. The modulation algorithm proposed in the present invention effectively reduces the switching loss of the NPC three-level inverter: the average switching times of the modulation algorithm proposed in the present invention when the modulation index is less than 0.5 is 4 times, and the average switching times when the modulation index is greater than 0.5 is 4-6 times, while the average switching times of the traditional NTV algorithm under any modulation index is 6 times. 2 The average number of switching times of the algorithm under any modulation degree is 8 times, and the switching frequency of the modulation algorithm proposed in the present invention is significantly reduced.

[0067] 3. The modulation algorithm proposed in this invention is compared with the traditional NTV and NTV 2 The algorithm has fewer partitions and does not require precise adjustment of the redundant small vectors or the duty cycle of the zero level when adjusting the midpoint potential. Therefore, the amount of calculation is reduced, which is more conducive to digital realization. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0069] Figure 1 The present invention is a flowchart of a three-level SVPWM modulation algorithm based on a redundant switching sequence.

[0070] Figure 2 It is a topological diagram of the NPC three-level inverter in the present invention.

[0071] Figure 3 It is the basic voltage space vector diagram of the three-level inverter in the present invention.

[0072] Figure 4 It is a schematic diagram of the area division of the modulation algorithm in sector I according to an embodiment of the present invention.

[0073] Figure 5 3 is a voltage space vector diagram of the modulation algorithm of the embodiment of the present invention in a 60° coordinate system (gh coordinate system).

[0074] Figure 6 4 is a voltage space vector diagram of the modulation algorithm of the embodiment of the present invention.

[0075] Figure 7 1 is a redundant switch sequence before adjustment of the modulation algorithm in the embodiment of the present invention in the area A1, wherein the left side is the switch sequence 1 and the right side is the switch sequence 2.

[0076] Figure 8 , Fig. 9 , Fig.10 , Fig.11 They are respectively the adjusted redundant switch sequences of the modulation algorithm in the embodiment of the present invention in areas A1, A2, A3, and A4, wherein the left side is the switch sequence 1 and the right side is the switch sequence 2.

[0077] Fig.12 From left to right are the modulation algorithm of the embodiment of the present invention, the traditional NTV algorithm and the NTV 2 The steady-state experimental waveform of the algorithm; among them, the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.3.

[0078] Fig.13 From left to right are the modulation algorithm of the embodiment of the present invention, the traditional NTV algorithm and the NTV 2 Experimental waveform diagram of the dynamic process of the algorithm eliminating the midpoint potential deviation; among them, the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.3.

[0079] Fig.14 From left to right are the modulation algorithm of the embodiment of the present invention, the traditional NTV algorithm and the NTV 2 The steady-state experimental waveform of the algorithm; among them, the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.95.

[0080] Fig.15 From left to right are the modulation algorithm of the embodiment of the present invention, the traditional NTV algorithm and the NTV2 Experimental waveform diagram of the dynamic process of the algorithm eliminating the midpoint potential deviation; among them, the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.95. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.

[0082] Example 1

[0083] The technical solution provided by this embodiment is: Figure 1 The present invention is a flowchart of a three-level SVPWM modulation algorithm based on a redundant switching sequence. Figure 4 Schematic diagram of the area division of the modulation algorithm of the embodiment of the present invention in sector I. The embodiment of the present invention proposes a three-level SVPWM modulation algorithm based on redundant switching sequence, including the following steps:

[0084] S1: A new area division method is proposed, which divides each large sector into four small areas.

[0085] S2: Propose the concept of redundant switch sequence and construct the redundant switch sequence in the small area.

[0086] S3: Adjust the redundant switching sequence to reduce the switching frequency of the inverter.

[0087] S4: Determine the target area where the reference voltage vector is located.

[0088] S5: Determine the related voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the related voltage vector.

[0089] S6: Determine the target switching sequence and send out a PWM wave.

[0090] Specifically, in step S1, a new area division method is proposed to divide each large sector into four small areas.

[0091] like Figure 4 As shown, the connection line L1 of the basic voltage vector POO (or ONN) and PPO (or OON), the voltage vector U m The connection line L2 with the basic voltage vector PPN, the voltage vector U m The line L3 connecting the basic voltage vector PNN divides sector I into four small areas: A1, A2, A3, and A4. m The basic voltage vectors POO (or ONN) and PPO (or OON) are applied for the same time to obtain:

[0092]

[0093] The other five large sectors are divided in the same way, e.g. Figure 6 shown.

[0094] Specifically, in step S2, the concept of a redundant switch sequence is proposed, and a redundant switch sequence in the small area is constructed.

[0095] The concept of redundant switching sequence is proposed: two switching sequences with the same voltage effect, equal average midpoint current and opposite directions are redundant switching sequences.

[0096] Construct the redundant switch sequence in the four areas of sector I, as shown in Table 3 below:

[0097] Table 3

[0098]

[0099] Redundant switching sequences in other large sectors are constructed in the same way.

[0100] Specifically, in step S3, the redundant switching sequence is adjusted to reduce the switching frequency of the inverter.

[0101] The rules for adjusting the redundant switch sequence are as follows: before and after the adjustment, the action time of the three switch states P, O, and N of the three phases A, B, and C remain unchanged; after the adjustment, the switch tube does not operate when switching between switch sequence 1 and switch sequence 2; after the adjustment, the number of switch operations in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to a minimum.

[0102] Take sector I as an example:

[0103] Figure 7 is the redundant switch sequence before adjustment of area A1, Figure 8 This is the redundant switch sequence after adjustment in region A1. It can be seen that after the adjustment, the switch tube operates 4 times in each switching cycle, and the switch tube does not operate when switching between switch sequence 1 and switch sequence 2. Compared with before adjustment, the number of switches is significantly reduced. Fig. 9 , Fig.10 , Fig.11 These are the adjusted redundant switch sequences for areas A2, A3, and A4 respectively.

[0104] The redundant switching sequences of other large sectors are adjusted in the same way.

[0105] Specifically, in step S4, the target region where the reference voltage vector is located is determined.

[0106] The target area is one of the four small areas described in step S1.

[0107] Take sector I as an example to illustrate:

[0108] In order to simplify the algorithm, the reference voltage U ref The coordinate system can be transformed from the α-β (90 degrees) coordinate system to the gh (60 degrees) coordinate system by coordinate transformation, with the reference voltage U ref The component on the gh axis is:

[0109]

[0110] Where: u α 、u β Respectively represent the reference voltage U ref The horizontal and vertical components in the α-β (90 degrees) coordinate system.

[0111] To u g1 and u h1 After normalization, we can get u g and u h , the reference value is u dc / 3,u dc is the DC side voltage:

[0112]

[0113] The lines L1, L2, and L3 in step S1 can be expressed as:

[0114] L1:u g +u h -1=0

[0115] L2:

[0116] L3:

[0117] From this, we can derive the judgment conditions of the target area, as shown in Table 4 below:

[0118] Table 4

[0119]

[0120] According to the above table, the target area where the reference voltage vector is located can be determined. When the reference voltage vector is located in other large sectors, it can be rotated to sector I to determine the target area.

[0121] Specifically, in step S5, the related voltage vector required for synthesizing the reference voltage vector is determined, and the duty cycle of the related voltage vector is calculated.

[0122] Based on the region determination in step S4 , a related voltage vector of the synthetic reference voltage may be determined.

[0123] like Figure 5 As shown, when the target area where the reference voltage vector is located is area A1, the related voltage vector is U s1 , U s2 , U0, according to the volt-second balance principle, the equation can be established:

[0124]

[0125] Where: d1, d2, d3 represent the voltage vector U s1 , U s2 , the duty cycle of U0.

[0126] The above formula is expressed in the gh coordinate system as:

[0127]

[0128] From the above formula, we can get:

[0129]

[0130] Similarly, the duty cycle of the relevant voltage vector required when the reference vector is located in other regions can be calculated. Specifically, in step S6, the target switching sequence is determined and a PWM wave is emitted.

[0131] The target switching sequence is a switching sequence in the redundant switching sequences described in step S2.

[0132] The expected midpoint current is defined as:

[0133]

[0134] Where: T s represents the switching period, u c1 、u c2 are the voltages across the DC side capacitors c1 and c2 respectively, and C is the capacitance value of c1 and c2.

[0135] Take area A1 of sector Ⅰ as an example:

[0136] When the target area where the reference voltage vector is located is area A1, it is necessary to select a switch sequence whose average midpoint current is consistent with the expected midpoint current direction from the redundant switch sequences in area A1 as the target switch sequence, so as to achieve midpoint potential control. Switch sequence 1 (ONN-OON-OOO) and switch sequence 2 (POO-PPO-OOO) are redundant switch sequences in area A1. The switch states that affect the midpoint current in switch sequence 1 are ONN and OON. The midpoint currents when the switch states ONN and OON are in effect are iA 、-i C , the duty ratios are d1 and d2 respectively. d1 and d2 are obtained in step S5, so the average midpoint current when the switch sequence 1 is in effect is:

[0137] i1=i A ·d1-i C ·d2

[0138] If i1 and i NP The direction of i1 and i NP The direction is opposite to that of the switch sequence, and the target switch sequence is switch sequence 2.

[0139] After the target switching sequence is determined, the duty ratios of the three switching states P, O, and N of the three phases A, B, and C can be calculated respectively, and the switching sequence adjusted in step S3 using the target switching sequence is used as the final switching sequence to generate a modulation wave and emit a PWM wave.

[0140] In Example 1, the power factor angle of the resistive-inductive load is 2π / 5, and the DC voltage u dc Set to 120V and the modulation index to 0.3.

[0141] In Example 1, a three-level SVPWM modulation algorithm based on a redundant switching sequence, a traditional NTV algorithm and an NTV algorithm are used in the embodiment of the present invention. 2 The switching frequencies of the algorithm are f1, f2, and f3, and the relationship between them is shown in Table 5 below:

[0142] Table 5

[0143]

[0144] It can be seen that compared with the traditional NTV algorithm and NTV 2 The modulation algorithm of the embodiment of the present invention significantly reduces the switching frequency of the NPC three-level inverter, thereby effectively reducing the switching loss of the inverter.

[0145] In Example 1, the experimental waveform is measured as follows Fig.12 , Fig.13 As shown:

[0146] Depend on Fig.12 It can be seen that there is almost no capacitor voltage fluctuation in the three-level SVPWM modulation algorithm based on redundant switching sequence in the embodiment of the present invention.

[0147] like Fig.13 As shown, the capacitor voltage is set to an initial deviation of 12V. It can be seen that the modulation algorithm of the embodiment of the present invention is better than the traditional NTV 2The algorithm has a faster midpoint potential deviation adjustment speed.

[0148] In Example 1, Fig.13 The phase current i A Harmonic analysis: A three-level SVPWM modulation algorithm based on redundant switching sequence according to an embodiment of the present invention, a traditional NTV algorithm and an NTV 2 The current THD of the algorithm are THD1, THD2, and THD3, and their sizes are shown in Table 6 below:

[0149] Table 6

[0150]

[0151] It can be seen that the modulation algorithm of the embodiment of the present invention has better output power quality.

[0152] Example 2

[0153] Example 2 is based on Example 1, and the modulation degree is adjusted from 0.3 to 0.95.

[0154] In Example 2, a three-level SVPWM modulation algorithm based on a redundant switching sequence, a traditional NTV algorithm and an NTV algorithm are used in the embodiment of the present invention. 2 The switching frequencies of the algorithm are f A 、f B 、f c , the size relationship between them is shown in Table 7 below:

[0155] Table 7

[0156]

[0157] It can be seen that the modulation algorithm of the embodiment of the present invention effectively reduces the switching frequency of the inverter, especially compared with the traditional NTV 2 Compared with the above algorithm, the switching frequency is significantly reduced, so the modulation algorithm of the embodiment of the present invention can effectively reduce the switching loss of the NPC three-level inverter.

[0158] In Example 2, the experimental waveform is measured as follows Fig.14 , Fig.15 As shown:

[0159] Depend on Fig.14 It can be seen that the capacitor voltage u of the traditional NTV algorithm c1 、u c2 There is obvious low-frequency oscillation, and the modulation algorithm of the embodiment of the present invention is different from the traditional NTV 2The capacitor voltage fluctuations of the algorithm are very small. The modulation algorithm of the embodiment of the present invention can well solve the problem of low-frequency oscillation of mid-point potential existing in the traditional NTV algorithm under high modulation degree and low power factor.

[0160] like Fig.15 As shown, the initial deviation of the capacitor voltage is set to 12V. It can be seen that the speed of eliminating the midpoint potential deviation by the modulation algorithm of the embodiment of the present invention is significantly faster than that of the traditional NTV 2 The algorithm can effectively solve the traditional NTV 2 The algorithm is slow in adjusting the midpoint potential deviation.

[0161] In Example 2, Fig.14 The phase current i A Harmonic analysis: A three-level SVPWM modulation algorithm based on redundant switching sequence according to an embodiment of the present invention, a traditional NTV algorithm and an NTV 2 The current THD of the algorithm is THD A 、THD B 、THD C , their sizes are shown in Table 8 below:

[0162] Table 8

[0163]

[0164] It can be seen that the modulation algorithm of the embodiment of the present invention has better output power quality.

[0165] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-level SVPWM modulation algorithm based on redundant switching sequence, characterized in that: The following steps are involved: S1: A new area division method is proposed, which divides each large sector into four small areas. S2: Propose the concept of redundant switch sequence and construct the redundant switch sequence in the small area. S3: Adjust the redundant switching sequence to reduce the switching frequency of the inverter. S4: Determine the target area where the reference voltage vector is located. S5: Determine the related voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the related voltage vector. S6: Determine the target switching sequence and send out a PWM wave.

2. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1 is characterized in that: The step S1 is specifically as follows: The connection line L1 of the basic voltage vectors POO and OON, the voltage vector U m The connection line L2 with the basic voltage vector PPN, the voltage vector U m The line L3 connecting the basic voltage vector PNN divides sector I into four small areas: A1, A2, A3, and A4. m The basic voltage vectors POO and PPO or OON and ONN act for the same time to obtain: or The other five large sectors are divided into regions in the same manner.

3. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1, characterized in that: The step S2 comprises the following steps: S21. The concept of redundant switching sequence is proposed: two switching sequences with the same voltage effect, equal average midpoint current and opposite directions are redundant switching sequences; S22, construct redundant switch sequences in the four areas of sector I, Construct the redundant switch sequence in the four areas of sector I, as shown in the following table: Redundant switching sequences in other large sectors are constructed in the same way.

4. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1, characterized in that: In the step S3, the redundant switching sequence in the step S2 is adjusted to reduce the switching frequency of the inverter, including the following steps: S31. The rule for adjusting the redundant switch sequence is: before and after the adjustment, the action time of the three switch states P, O, and N of the three phases A, B, and C remains unchanged; after the adjustment, the switch tube does not act when switching between switch sequence 1 and switch sequence 2; after the adjustment, the number of switch actions in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to the minimum; S32. Take sector I as an example for explanation: FIG8, FIG9, FIG10, and FIG11 are respectively redundant switch sequences after adjustment of regions A1, A2, A3, and A4. The redundant switch sequences of other large sectors are adjusted in the same manner.

5. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1, characterized in that: In step S4, determining the target area where the reference voltage vector is located includes the following steps: S41, the target area is one of the four small areas described in step S1, and sector I is used as an example for description: S42, reference voltage U ref By coordinate transformation from the α-β coordinate system to the gh coordinate system, the reference voltage U ref The component on the gh axis is: Where: u α 、u β Respectively represent the reference voltage U ref The abscissa and ordinate components in the α-β coordinate system; S43, for u g1 and u h1 After normalization, we can get u g and u h , the reference value is u dc / 3,u dc is the DC side voltage: The lines L1, L2, and L3 in step S1 are expressed as: L1: in g +in h -1=0 <h2 style=";text-align:left;direction:ltr">L3:3u<h2 style=";text-align:left;direction:ltr"> g <h2 style=";text-align:left;direction:ltr"> +u<h2 style=";text-align:left;direction:ltr"> h <h2 style=";text-align:left;direction:ltr"> -2=0 The judgment conditions of the target area are obtained as shown in the table below: According to the judgment conditions of the target area in the above table, the target area where the reference voltage vector is located is judged. When the reference voltage vector is located in other large sectors, it is rotated to sector I to judge the target area.

6. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1, characterized in that: In the step S5, determining the relevant voltage vector required for synthesizing the reference voltage vector and calculating the duty cycle of the relevant voltage vector comprises the following steps: S51, determining a voltage vector related to the synthesized reference voltage based on the region determination in step S4; S52, when the target area where the reference voltage vector is located is area A1, the relevant voltage vector is U s1 , U s2 , U0, according to the volt-second balance principle, establish the equation: Where: d1, d2, d3 represent the voltage vector U s1 , U s2 , the duty cycle of U0; The above formula is expressed in the gh coordinate system as: From the above formula, we can get: Similarly, the duty cycle of the relevant voltage vector required when the reference vector is located in other areas is calculated.

7. The three-level SVPWM modulation algorithm based on redundant switching sequence according to claim 1, characterized in that: In step S6, the target switching sequence is determined and a PWM wave is emitted, which specifically includes the following steps: S61, the target switch sequence is a switch sequence in the redundant switch sequence described in step S2; The expected midpoint current is defined as: Where: T s represents the switching period, u c1 、u c2 are the voltages across the DC side capacitors c1 and c2 respectively, and C is the capacitance value of c1 and c2; S62, taking region A1 of sector I as an example, when the target region where the reference voltage vector is located is region A1, an average midpoint current i is selected from the redundant switch sequence of region A1. NP The switch sequence with the same direction is used as the target switch sequence, so as to realize the midpoint potential control; S63, switch sequence 1ONN-OON-OOO, switch sequence 2POO-PPO-OOO are redundant switch sequences in region A1. The switch states that affect the midpoint current in switch sequence 1 are ONN and OON. The midpoint currents when the switch states ONN and OON are in effect are i respectively. A 、-i C , the duty ratios are d1 and d2 respectively, d1 and d2 are obtained in step S5, and the average midpoint current when the switching sequence 1 is in effect is: i1=i A ·d1-i C ·d2 If i1 and i NP The direction of i1 and i NP The direction is opposite to that of the switch sequence, and the target switch sequence is switch sequence 2; S64. After the target switching sequence is determined, the duty ratios of the three switching states of P, O, and N of the three phases A, B, and C are calculated respectively, and the switching sequence adjusted in step S3 is used as the final switching sequence to generate a modulation wave and emit a PWM wave.

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