A three-level SVPWM modulation algorithm based on redundant switch sequence

Abstract

This invention provides a three-level SVPWM modulation algorithm based on redundant switching sequences, belonging to the field of pulse width modulation technology for three-level inverters. The technical solution includes the following steps: S1: Proposing a new region division method, dividing each large sector into four smaller regions; S2: Proposing the concept of redundant switching sequences and constructing redundant switching sequences within the smaller regions; S3: Adjusting the redundant switching sequences to reduce the inverter's switching frequency; S4: Determining the target region where the reference voltage vector is located; S5: Determining the relevant voltage vectors required to synthesize the reference voltage vector and calculating the duty cycle of the relevant voltage vectors; S6: Determining the target switching sequence and emitting a PWM wave. The beneficial effects of this invention are: it can suppress the midpoint potential fluctuation of the NPC three-level inverter within the full power factor and full modulation range, and reduce the switching losses of the NPC three-level inverter.

Description

Technical Field

[0001] This invention relates to the field of pulse width modulation technology for three-level inverters, and particularly to a three-level SVPWM modulation algorithm based on redundant switch sequences. Background Technology

[0002] The neutral-point clamped (NPC) three-level inverter (TLI) is widely used in renewable energy power generation, motor drive and other applications due to its advantages such as low voltage stress on switching devices, high output efficiency and low total harmonic distortion of output voltage. However, NPC_TLI has the technical problem of neutral-point potential imbalance.

[0003] To address the technical problem of neutral point potential imbalance in NPC three-level inverters, traditional Nearest Three Vector (NTV) algorithms mostly utilize redundant small vectors to adjust the neutral point potential. However, this algorithm is insufficient in suppressing neutral point potential fluctuations under high modulation and low power factor conditions. Therefore, some experts have proposed the Nearest Three Virtual Vector (NTV) algorithm. 2 The algorithm synthesizes a virtual voltage space vector by selecting a suitable basic voltage vector, making the average midpoint current zero when the virtual vector is applied, thus achieving unconditional suppression of midpoint potential fluctuations. However, the switching frequency increases by 1 / 3 compared to the NTV algorithm, resulting in higher switching losses. Therefore, some experts have proposed algorithms based on NTV and NTV. 2 A hybrid modulation algorithm is proposed, but the hybrid control algorithm is relatively complex to implement and still has high switching losses under high modulation and low power factor conditions.

[0004] To reduce inverter switching losses, experts have proposed various improved DPWM algorithms. These algorithms control the neutral point potential by selecting different clamping modes. While the switching losses of these algorithms are significantly lower than those of the traditional NTV algorithm, under high modulation and low power factor conditions, the pre-selected clamping modes may have average neutral point currents in the same direction, making it impossible to select a clamping mode favorable to the neutral point potential. Therefore, low-frequency oscillations occur at the neutral point potential. Furthermore, due to the large number of pre-selected clamping modes, this algorithm is relatively complex to implement.

[0005] How to solve the above-mentioned technical problems is the challenge facing this invention. Summary of the Invention

[0006] This paper addresses the low-frequency oscillation of the midpoint potential in traditional Nearest Three Vector (NTV) algorithms and various improved DPWM algorithms under high modulation and low power factor conditions, as well as the traditional Nearest Three Virtual Vector (NTV) algorithm. 2The present invention addresses the technical problems of high switching losses and slow adjustment of midpoint potential deviation in existing three-level modulation techniques. The purpose of this invention is to provide a three-level SVPWM modulation algorithm based on redundant switching sequences. In order to overcome the shortcomings of existing three-level modulation techniques, this invention can suppress midpoint potential fluctuations in NPC three-level inverters across the full power factor and full modulation range, and reduce the switching losses of NPC three-level inverters.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution: a three-level SVPWM modulation algorithm based on redundant switch sequences, comprising the following steps:

[0008] S1: Propose a new method of region division, which divides each large sector into four smaller regions.

[0009] S2: Propose the concept of redundant switch sequences and construct redundant switch sequences in the small region.

[0010] S3: Adjust the redundant switch sequence to reduce the switching frequency of the inverter.

[0011] S4: Determine the target region where the reference voltage vector is located.

[0012] S5: Determine the relevant voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the relevant voltage vector.

[0013] S6: Determine the target switching sequence and emit a PWM wave.

[0014] Furthermore, in step S1, a new method of region division is proposed, which divides each large sector into four smaller regions.

[0015] like Figure 4 As shown, the connection L1 between the basic voltage vectors POO (or ONN) and PPO (or OON), and the voltage vector U m The connection L2 with the basic voltage vector PPN, and the voltage vector U m The line L3 connecting the fundamental voltage vector PNN divides sector I into four smaller regions: A1, A2, A3, and A4. The voltage vector U... m It is obtained by applying the basic voltage vectors POO (or ONN) and PPO (or OON) for the same amount of time:

[0016]

[0017] The other five major sectors are divided into regions in the same way, such as Figure 6 As shown.

[0018] Furthermore, in step S2, the concept of redundant switch sequences is proposed, and redundant switch sequences are constructed in the small region.

[0019] The concept of redundant switching sequences is proposed: two switching sequences with the same voltage effect, equal average midpoint current, and opposite directions are redundant switching sequences.

[0020] The redundant switch sequences in the four regions of sector I are constructed as shown in Table 1 below:

[0021] Table 1

[0022] area Switch sequence 1 Switch sequence 2 A1 ONN-OON-OOO POO-PPO-OOO A2 OON-ONN-PNN PPO-POO-PNN A3 ONN-OON-PPN POO-PPO-PPN A4 PNN-ONN-OON-PPN PNN-POO-PPO-PPN

[0023] The redundant switch sequences in other large sectors are constructed in the same way.

[0024] Furthermore, in step S3, the redundant switching sequence described in step S2 is adjusted to reduce the switching frequency of the inverter.

[0025] The rules for redundancy switch sequence adjustment are as follows: before and after adjustment, the duration of the P, O, and N switching states of phases A, B, and C remains unchanged; after adjustment, the switching transistors do not operate when switching between switch sequence 1 and switch sequence 2; after adjustment, the number of switching operations in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to the minimum.

[0026] Let's take sector I as an example: Figure 7 This is the redundant switch sequence before adjustment in region A1. Figure 8 This is the adjusted redundant switching sequence for region A1. It can be seen that the adjusted switching sequence operates 4 times per switching cycle, and the switching transistor does not operate when switching between switching sequence 1 and switching sequence 2. Compared to before the adjustment, the number of switching operations is significantly reduced. Figure 9 , Figure 10 , Figure 11 These are the adjusted redundant switch sequences for regions A2, A3, and A4, respectively.

[0027] The redundant switch sequences of other large sectors are adjusted in the same way.

[0028] Further, in step S4, the target region where the reference voltage vector is located is determined.

[0029] The target area is one of the four small areas described in step S1.

[0030] Let's take sector I as an example:

[0031] To simplify the algorithm, the reference voltage U ref The coordinate system can be transformed from the α-β (90 degrees) coordinate system to the gh (60 degrees) coordinate system, with reference voltage U. ref The components along the gh axis are:

[0032]

[0033] In the formula: u α u β These represent the reference voltage U. ref The horizontal and vertical components in the α-β (90 degrees) coordinate system.

[0034] For u g1 and u h1 Normalization is performed to obtain u g and u h The baseline value is u dc / 3,u dc DC side voltage:

[0035]

[0036] The connections L1, L2, and L3 mentioned in step S1 can be represented as:

[0037]

[0038]

[0039]

[0040] Therefore, the criteria for determining the target region can be derived, as shown in Table 2:

[0041] Table 2

[0042] area <![CDATA[u g +in h -1]]> <![CDATA[u g / 3+u h -2 / 3]]> <![CDATA[3u g +in h -2]]> A1 <0 - - A2 ≥0 <0 - A3 ≥0 - <0 A4 - ≥0 ≥0

[0043] Based on Table 2 above, the target area where the reference voltage vector is located can be determined. When the reference voltage vector is located in other large sectors, it can be rotated to sector I to determine the target area.

[0044] Further, in step S5, the relevant voltage vector required for synthesizing the reference voltage vector is determined, and the duty cycle of the relevant voltage vector is calculated.

[0045] Based on the region determination in step S4, the relevant voltage vector of the synthesized reference voltage can be determined.

[0046] like Figure 5 As shown, when the target region where the reference voltage vector is located is region A1, the relevant voltage vector is U. s1 U s2 Based on the volt-second balance principle, the equation for U0 can be established as follows:

[0047]

[0048] In the formula: d1, d2, and d3 represent the voltage vector U, respectively. s1 Us2 The duty cycle of U0.

[0049] The above equation can be expressed in the gh coordinate system as:

[0050]

[0051] From the above formula, we can obtain:

[0052]

[0053] Similarly, the duty cycle of the relevant voltage vector required when the reference vector is located in other regions can be calculated.

[0054] Further, in step S6, the target switching sequence is determined and a PWM wave is emitted.

[0055] The target switch sequence is one of the redundant switch sequences described in step S2.

[0056] Define the desired midpoint current as:

[0057]

[0058] In the formula: T s Indicates the switching period, u c1 u c2 These are the voltages across capacitors C1 and C2 on the DC side, respectively. The capacitance values ​​of C1 and C2 are equal, both being C.

[0059] Let's take region A1 of sector I as an example for explanation:

[0060] When the target region where the reference voltage vector is located is region A1, it is necessary to select an average midpoint current and a desired midpoint current i from the redundant switching sequence of region A1. NP A sequence of switches with the same direction is used as the target switch sequence to achieve midpoint potential control. Switch sequence 1 (ONN-OON-OOO) and switch sequence 2 (POO-PPO-OOO) are redundant switch sequences in region A1. In switch sequence 1, the switch states that affect the midpoint current are ONN and OON, and the midpoint currents when switch states ONN and OON are active are i... A -i C The duty cycles are d1 and d2, respectively. d1 and d2 are calculated in step S5, so the average midpoint current when switch sequence 1 is in operation is:

[0061]

[0062] If i1 and i NP If the directions are the same, the target switch sequence is switch sequence 1; if i1 and i... NPThe directions are opposite, and the target switch sequence is switch sequence 2.

[0063] Once the target switching sequence is determined, the duty cycles of the three phases A, B, and C, P, O, and N switching states can be calculated respectively. The target switching sequence, after being adjusted in step S3, is used as the final switching sequence to generate a modulation wave and emit a PWM wave.

[0064] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0065] 1. This invention proposes a three-level SVPWM modulation algorithm based on redundant switch sequences, which can suppress midpoint potential fluctuations across the entire power factor and modulation range. Figure 14 It can be seen that the modulation algorithm proposed in this invention can effectively solve the problem of low-frequency oscillation of the midpoint potential in the traditional NTV algorithm under high modulation density and low power factor conditions. Figure 13 and Figure 15 It can be seen that the modulation algorithm proposed in this invention can effectively solve the problems of traditional NTV. 2 The algorithm adjusts the midpoint potential deviation slowly.

[0066] 2. The modulation algorithm proposed in this invention effectively reduces the switching losses of NPC three-level inverters: the proposed modulation algorithm has an average of 4 switching operations when the modulation depth is less than 0.5, and an average of 4-6 switching operations when the modulation depth is greater than 0.5, while the traditional NTV algorithm has an average of 6 switching operations under any modulation depth. 2 The algorithm has an average of 8 switching times under any modulation degree, and the switching frequency of the modulation algorithm proposed in this invention has been significantly reduced.

[0067] 3. The modulation algorithm proposed in this invention is superior to traditional NTV and NTV. 2 The algorithm has fewer partitions, and when adjusting the midpoint potential, it does not require precise adjustment of the duty cycle of redundant small vectors or zero levels, thus reducing the computational load and making it more conducive to digital implementation. Attached Figure Description

[0068] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0069] Figure 1 This is a flowchart of a three-level SVPWM modulation algorithm based on a redundant switch sequence according to an embodiment of the present invention.

[0070] Figure 2 This is the topology diagram of the NPC three-level inverter in this invention.

[0071] Figure 3 This is the basic voltage space vector diagram of the three-level inverter in this invention.

[0072] Figure 4 This is a schematic diagram of the modulation algorithm in sector I according to an embodiment of the present invention.

[0073] Figure 5 This is a voltage space vector diagram of the modulation algorithm in the 60° coordinate system (gh coordinate system) of an embodiment of the present invention.

[0074] Figure 6 This is a voltage space vector diagram of the modulation algorithm in an embodiment of the present invention.

[0075] Figure 7 This is the redundant switch sequence in region A1 before adjustment of the modulation algorithm in this embodiment of the invention, where the left side is switch sequence 1 and the right side is switch sequence 2.

[0076] Figure 8 , Figure 9 , Figure 10 , Figure 11 These are the adjusted redundant switch sequences of the modulation algorithm in regions A1, A2, A3, and A4 according to the embodiments of the present invention, where the left side is switch sequence 1 and the right side is switch sequence 2.

[0077] Figure 12 From left to right: the modulation algorithm of this invention, the traditional NTV algorithm, and NTV. 2 Steady-state experimental waveforms of the algorithm; where the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.3.

[0078] Figure 13 From left to right: the modulation algorithm of this invention, the traditional NTV algorithm, and NTV. 2 The experimental waveform diagram shows the dynamic process of the algorithm eliminating the midpoint potential deviation; where the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation degree is 0.3.

[0079] Figure 14 From left to right: the modulation algorithm of this invention, the traditional NTV algorithm, and NTV. 2 Steady-state experimental waveforms of the algorithm; where the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation index is 0.95.

[0080] Figure 15 From left to right: the modulation algorithm of this invention, the traditional NTV algorithm, and NTV. 2The experimental waveform diagram shows the dynamic process of the algorithm eliminating the midpoint potential deviation; where the DC side voltage is 120V, the load power factor angle is 2π / 5, and the modulation degree is 0.95. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0082] Example 1

[0083] The technical solution provided in this embodiment is as follows: Figure 1 This is a flowchart of a three-level SVPWM modulation algorithm based on a redundant switch sequence according to an embodiment of the present invention. Figure 4 This is a schematic diagram of the region division in sector I of the modulation algorithm according to an embodiment of the present invention. This embodiment of the present invention proposes a three-level SVPWM modulation algorithm based on redundant switch sequences, including the following steps:

[0084] S1: Propose a new method of region division, which divides each large sector into four smaller regions.

[0085] S2: Propose the concept of redundant switch sequences and construct redundant switch sequences in the small region.

[0086] S3: Adjust the redundant switch sequence to reduce the switching frequency of the inverter.

[0087] S4: Determine the target region where the reference voltage vector is located.

[0088] S5: Determine the relevant voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the relevant voltage vector.

[0089] S6: Determine the target switching sequence and emit a PWM wave.

[0090] Specifically, in step S1, a new method of region division is proposed, which divides each large sector into four smaller regions.

[0091] like Figure 4 As shown, the connection L1 between the basic voltage vectors POO (or ONN) and PPO (or OON), and the voltage vector U m The connection L2 with the basic voltage vector PPN, and the voltage vector U m The line L3 connecting the fundamental voltage vector PNN divides sector I into four smaller regions: A1, A2, A3, and A4. The voltage vector U... m It is obtained by applying the basic voltage vectors POO (or ONN) and PPO (or OON) for the same amount of time:

[0092]

[0093] The other five major sectors are divided into regions in the same way, such as Figure 6 As shown.

[0094] Specifically, in step S2, the concept of redundant switch sequences is proposed, and redundant switch sequences are constructed in the small region.

[0095] The concept of redundant switching sequences is proposed: two switching sequences with the same voltage effect, equal average midpoint current, and opposite directions are redundant switching sequences.

[0096] The redundant switch sequences in the four regions of sector I are constructed as shown in Table 3 below:

[0097] Table 3

[0098] area Switch sequence 1 Switch sequence 2 A1 ONN-OON-OOO POO-PPO-OOO A2 OON-ONN-PNN PPO-POO-PNN A3 ONN-OON-PPN POO-PPO-PPN A4 PNN-ONN-OON-PPN PNN-POO-PPO-PPN

[0099] The redundant switch sequences in other large sectors are constructed in the same way.

[0100] Specifically, in step S3, the redundant switch sequence is adjusted to reduce the switching frequency of the inverter.

[0101] The rules for redundancy switch sequence adjustment are as follows: before and after adjustment, the duration of the P, O, and N switching states of phases A, B, and C remains unchanged; after adjustment, the switching transistors do not operate when switching between switch sequence 1 and switch sequence 2; after adjustment, the number of switching operations in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to the minimum.

[0102] Let's take sector I as an example:

[0103] Figure 7 This is the redundant switch sequence before adjustment in region A1. Figure 8 This is the adjusted redundant switching sequence for region A1. It can be seen that the adjusted switching sequence operates 4 times per switching cycle, and the switching transistor does not operate when switching between switching sequence 1 and switching sequence 2. Compared to before the adjustment, the number of switching operations is significantly reduced. Figure 9 , Figure 10 , Figure 11 These are the adjusted redundant switch sequences for regions A2, A3, and A4, respectively.

[0104] The redundant switch sequences of other large sectors are adjusted in the same way.

[0105] Specifically, in step S4, the target region where the reference voltage vector is located is determined.

[0106] The target area is one of the four small areas described in step S1.

[0107] Let's take sector I as an example:

[0108] To simplify the algorithm, the reference voltage U ref The coordinate system can be transformed from the α-β (90 degrees) coordinate system to the gh (60 degrees) coordinate system, with reference voltage U. ref The components along the gh axis are:

[0109]

[0110] In the formula: u α u β These represent the reference voltage U. ref The horizontal and vertical components in the α-β (90 degrees) coordinate system.

[0111] For u g1 and u h1 Normalization is performed to obtain u g and u h The baseline value is u dc / 3,u dc DC side voltage:

[0112]

[0113] The connections L1, L2, and L3 mentioned in step S1 can be represented as:

[0114]

[0115]

[0116]

[0117] The criteria for determining the target region can be derived from this, as shown in Table 4 below:

[0118] Table 4

[0119] area <![CDATA[u g +in h -1]]> <![CDATA[u g / 3+u h -2 / 3]]> <![CDATA[3u g +in h -2]]> A1 <0 - - A2 ≥0 <0 - A3 ≥0 - <0 A4 - ≥0 ≥0

[0120] Based on the table above, the target area where the reference voltage vector is located can be determined. When the reference voltage vector is located in other large sectors, the target area can be determined by rotating to sector I.

[0121] Specifically, in step S5, the relevant voltage vector required for synthesizing the reference voltage vector is determined, and the duty cycle of the relevant voltage vector is calculated.

[0122] Based on the region determination in step S4, the relevant voltage vector of the synthesized reference voltage can be determined.

[0123] like Figure 5As shown, when the target region where the reference voltage vector is located is region A1, the relevant voltage vector is U. s1 U s2 Based on the volt-second balance principle, the equation for U0 can be established as follows:

[0124]

[0125] In the formula: d1, d2, and d3 represent the voltage vector U, respectively. s1 U s2 The duty cycle of U0.

[0126] The above equation can be expressed in the gh coordinate system as follows:

[0127]

[0128] From the above formula, we can obtain:

[0129]

[0130] Similarly, the duty cycle of the relevant voltage vector required when the reference vector is located in other regions can be calculated.

[0131] Specifically, in step S6, the target switching sequence is determined and a PWM wave is emitted.

[0132] The target switch sequence is one of the redundant switch sequences described in step S2.

[0133] Define the desired midpoint current as:

[0134]

[0135] In the formula: T s Indicates the switching period, u c1 u c2 These are the voltages across capacitors C1 and C2 on the DC side, respectively. The capacitance values ​​of C1 and C2 are equal, both being C.

[0136] Let's take region A1 of sector I as an example for explanation:

[0137] When the target region where the reference voltage vector is located is region A1, a switch sequence whose average midpoint current is in the same direction as the desired midpoint current needs to be selected from the redundant switch sequences in region A1 as the target switch sequence to achieve midpoint potential control. Switch sequence 1 (ONN-OON-OOO) and switch sequence 2 (POO-PPO-OOO) are redundant switch sequences in region A1. In switch sequence 1, the switch states that affect the midpoint current are ONN and OON, and the midpoint currents when switch states ONN and OON are active are i A -i CThe duty cycles are d1 and d2, respectively. d1 and d2 are calculated in step S5, so the average midpoint current when switch sequence 1 is in operation is:

[0138]

[0139] If i1 and i NP If the directions are the same, the target switch sequence is switch sequence 1; if i1 and i... NP The directions are opposite, and the target switch sequence is switch sequence 2.

[0140] Once the target switching sequence is determined, the duty cycles of the three phases A, B, and C, P, O, and N switching states can be calculated respectively. The target switching sequence, after being adjusted in step S3, is used as the final switching sequence to generate a modulation wave and emit a PWM wave.

[0141] In Example 1, the power factor angle of the resistive-inductive load is 2π / 5, and the DC voltage u is measured. dc Set to 120V and modulation to 0.3.

[0142] In Example 1, an embodiment of the present invention presents a three-level SVPWM modulation algorithm based on redundant switch sequences, a traditional NTV algorithm, and NTV. 2 The switching frequencies of the algorithm are f1, f2, and f3, and their relationship is shown in Table 5 below:

[0143] Table 5

[0144] <![CDATA[f1 / f1]]> <![CDATA[f2 / f1]]> <![CDATA[f3 / f1]]> 1 1.5 2

[0145] It can be seen that, compared to the traditional NTV algorithm and NTV... 2 The modulation algorithm in this embodiment of the invention significantly reduces the switching frequency of the NPC three-level inverter, thereby effectively reducing the switching losses of the inverter.

[0146] In Example 1, the experimental waveform was measured as follows: Figure 12 , Figure 13 As shown:

[0147] Depend on Figure 12 As can be seen, the three-level SVPWM modulation algorithm based on redundant switch sequences in this embodiment of the invention has almost no capacitor voltage fluctuations.

[0148] like Figure 13 As shown, an initial deviation of 12V is set for the capacitor voltage. It can be seen that the modulation algorithm of this embodiment of the invention is superior to the traditional NTV. 2 The algorithm has a faster speed for adjusting midpoint potential deviation.

[0149] In Example 1, for Figure 13 Phase current i A Harmonic analysis: An embodiment of the present invention provides a three-level SVPWM modulation algorithm based on redundant switch sequences, a traditional NTV algorithm, and NTV. 2 The current THDs of the algorithm are THD1, THD2, and THD3, and their magnitudes are shown in Table 6 below:

[0150] Table 6

[0151] <![CDATA[THD1]]> <![CDATA[THD2]]> <![CDATA[THD3]]> 2.06% 2.39% 2.75%

[0152] It can be seen that the modulation algorithm of this invention has good output power quality.

[0153] Example 2

[0154] Example 2 is based on Example 1, but the modulation index is adjusted from 0.3 to 0.95.

[0155] In Example 2, an embodiment of the present invention presents a three-level SVPWM modulation algorithm based on a redundant switch sequence, a traditional NTV algorithm, and NTV. 2 The switching frequencies of the algorithm are f A f B f c The size relationships between them are shown in Table 7 below:

[0156] Table 7

[0157] <![CDATA[f A / f A ]]> <![CDATA[f B / f A ]]> <![CDATA[f C / f A ]]> 1 1.026 1.368

[0158] As can be seen, the modulation algorithm of this invention effectively reduces the switching frequency of the inverter, especially compared with the traditional NTV. 2 Compared to the previous algorithm, the switching frequency has been significantly reduced. Therefore, the modulation algorithm of this invention can effectively reduce the switching losses of the NPC three-level inverter.

[0159] In Example 2, the experimental waveform was measured as follows: Figure 14 , Figure 15 As shown:

[0160] Depend on Figure 14 It can be seen that the capacitor voltage u in the traditional NTV algorithm c1 u c2 There is obvious low-frequency oscillation, while the modulation algorithm of this embodiment of the invention is different from that of traditional NTV. 2 The capacitor voltage fluctuations in the algorithm are very small. The modulation algorithm of this invention can effectively solve the problem of low-frequency oscillation of the midpoint potential in the traditional NTV algorithm under high modulation and low power factor conditions.

[0161] like Figure 15As shown, with an initial deviation of 12V set for the capacitor voltage, it can be seen that the modulation algorithm of this embodiment eliminates the midpoint potential deviation significantly faster than the traditional NTV. 2 The algorithm can effectively solve the problems of traditional NTV. 2 The algorithm adjusts the midpoint potential deviation slowly.

[0162] In Example 2, for Figure 14 Phase current i A Harmonic analysis: An embodiment of the present invention provides a three-level SVPWM modulation algorithm based on redundant switch sequences, a traditional NTV algorithm, and NTV. 2 The algorithm's current THD are respectively THD A THD B THD C Their sizes are shown in Table 8 below:

[0163] Table 8

[0164] <![CDATA[THD A ]]> <![CDATA[THD B ]]> <![CDATA[THD C ]]> 1.23% 1.41% 1.17%

[0165] It can be seen that the modulation algorithm of this invention has good output power quality.

[0166] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-level SVPWM modulation algorithm based on redundant switch sequences, characterized in that, Includes the following steps: S1: A new region partitioning method is proposed, dividing each large sector into four smaller regions. Specifically, step S1 involves: the connection L1 between the basic voltage vectors POO and OON, and the voltage vector U... m The connection L2 with the basic voltage vector PPN, and the voltage vector U m The line L3 connecting the fundamental voltage vector PNN divides sector I into four smaller regions: A1, A2, A3, and A4. The voltage vector U... m It is obtained by the basic voltage vectors POO and PPO or OON and ONN acting for the same duration: ； The other five major sectors are divided into regions in the same way; S2: Propose the concept of redundant switch sequences and construct redundant switch sequences in the small region. Step S2 includes the following steps: S21. The concept of redundant switching sequences is proposed: Two switching sequences with the same voltage effect, equal average midpoint current, and opposite directions are redundant switching sequences. S22. Construct redundant switch sequences in the four regions of sector I. The redundant switch sequences in the four regions of sector I are constructed as shown in the table below: ； The redundant switch sequences in other large sectors are constructed in the same way; S3: Adjust the redundant switching sequence to reduce the inverter's switching frequency. Step S3, adjusting the redundant switching sequence in step S2 to reduce the inverter's switching frequency, includes the following steps: S31. The rules for adjusting redundant switch sequences are as follows: Before and after adjustment, the duration of the P, O, and N switching states of phases A, B, and C remains unchanged; after adjustment, the switching transistors do not operate when switching between switch sequence 1 and switch sequence 2; after adjustment, the number of switching operations in each switching cycle of switch sequence 1 and switch sequence 2 is reduced to the minimum. S4: Determine the target region where the reference voltage vector is located. S5: Determine the relevant voltage vector required to synthesize the reference voltage vector, and calculate the duty cycle of the relevant voltage vector. S6: Determine the target switching sequence and emit a PWM wave. Step S6, determining the target switching sequence and emitting a PWM wave, specifically includes the following steps: S61. The target switch sequence is one of the switch sequences in the redundant switch sequence described in step S2. Define the desired midpoint current as: ； In the formula: T s Indicates the switching period, u c1 u c2 These are the voltages across capacitors C1 and C2 on the DC side, respectively. The capacitance values ​​of C1 and C2 are equal, both being C. S62. Taking region A1 of sector I as an example, when the target region where the reference voltage vector is located is region A1, select an average midpoint current and a desired midpoint current i from the redundant switching sequence of region A1. NP A switch sequence with the same direction is used as the target switch sequence to achieve midpoint potential control; S63, switch sequence 1 ONN-OON-OOO, and switch sequence 2 POO-PPO-OOO are redundant switch sequences in region A1. In switch sequence 1, the switch states that affect the midpoint current are ONN and OON. The midpoint currents when switch states ONN and OON are active are i... A -i C The duty cycles are d1 and d2, which are obtained in step S5. The average midpoint current when switch sequence 1 is in operation is: ； If i1 and i NP If the directions are the same, the target switch sequence is switch sequence 1; if i1 and i... NP The directions are opposite, and the target switch sequence is switch sequence 2; S64. After the target switching sequence is determined, the duty cycles of the three phases A, B, and C P, O, and N switching states are calculated respectively. The target switching sequence is used as the final switching sequence after adjustment in step S3 to generate a modulation wave and emit a PWM wave.

2. The three-level SVPWM modulation algorithm based on redundant switch sequences according to claim 1, characterized in that, In step S4, determining the target region where the reference voltage vector is located includes the following steps: S41. The target area is one of the four small areas described in step S1. Taking sector I as an example: S42, Reference Voltage U ref The reference voltage U is transformed from the α-β coordinate system to the gh coordinate system via coordinate transformation. ref The components along the gh axis are: ; In the formula: u α u β These represent the reference voltage U. ref The horizontal and vertical components in the α-β coordinate system; S43, for u g1 and u h1 Normalization is performed to obtain u g and u h The baseline value is u dc / 3,u dc DC side voltage: ； The connections L1, L2, and L3 mentioned in step S1 are represented as follows: ； ； ； The criteria for determining the target region are derived from this, as shown in the table below: Based on the judgment conditions of the target area in the table above, determine the target area where the reference voltage vector is located. When the reference voltage vector is located in other large sectors, rotate to sector I to judge the target area.

3. The three-level SVPWM modulation algorithm based on redundant switch sequences according to claim 1, characterized in that, In step S5, determining the relevant voltage vector required for synthesizing the reference voltage vector and calculating the duty cycle of the relevant voltage vector includes the following steps: S51. Based on the region determination in step S4, determine the relevant voltage vector of the synthesized reference voltage; S52. When the target region where the reference voltage vector is located is region A1, the relevant voltage vector is U. s1 U s2 Based on the volt-second balance principle, the equation for U0 is established as follows: ； In the formula: d1, d2, and d3 represent the voltage vector U, respectively. s1 U s2 Duty cycle of U0; The above equation can be expressed in the gh coordinate system as follows: ； From the above formula, we get: ； Similarly, calculate the duty cycle of the relevant voltage vector required when the reference vector is located in other regions.

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