Neutral point voltage control and leakage current suppression method for three-level converter based on SVPWM

Abstract

The present invention provides a method for controlling the midpoint voltage and suppressing leakage current in a three-level converter based on SVPWM. The method comprises: first, defining the basic output voltage vector of the three-level converter and dividing the spatial voltage vector diagram into sectors. Next, combining small vectors with small vectors, and small vectors with medium vectors, ensures that the sum of the midpoint currents generated by the combined vectors is zero, forming a first constraint. With the zero vector and large vector as fixed outputs, the combined vector is introduced to ensure that the arm state action time before and after introduction remains unchanged, thus obtaining a second constraint. A third constraint is established based on the small vector, the degree of midpoint voltage imbalance, and the direction of active power flow. The three-phase bridge arm switching states are unbound and optimized to suppress leakage current. Combining the constraints with the optimization sequence, the vector action time is calculated and a drive signal is generated. This method can accurately control the midpoint voltage, effectively suppress leakage current, reduce the number of switching cycles, achieve smooth switching, and improve converter performance.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a method for controlling the midpoint voltage and suppressing leakage current of a three-level converter based on SVPWM. Background Art

[0002] As an important power electronic converter, the NPC (Neutral Point Clamped) three-level converter occupies an important position in the field of power electronic application technology, especially in the NPC three-level converter technology.

[0003] Midpoint voltage control and leakage current suppression are technical challenges in NPC three-level converters. In NPC three-level converters, midpoint voltage imbalance disrupts the symmetric structure of the voltage space vector in equilibrium, resulting in uneven voltage stress on busbar capacitors and power devices, which in turn affects the lifespan of the capacitors and power devices and, in turn, the safe, stable, and reliable operation of the converter. In motor control applications, midpoint voltage imbalance can particularly affect the motor's control characteristics. Therefore, to ensure the long-term and reliable operation of NPC three-level converters, effective midpoint voltage balance must be controlled. Furthermore, NPC three-level converters also face the issue of leakage current suppression. Non-isolated NPC three-level inverters are widely used in photovoltaic power generation due to their small size, low cost, and high efficiency. However, in the absence of a system transformer, the presence of PV array-to-ground capacitance causes high-frequency common-mode voltage to act on parasitic capacitance. This voltage then forms a loop through filters, parasitic capacitance, and grid impedance, generating high-frequency common-mode current, known as leakage current. This high-frequency leakage current not only increases the harmonic content of the grid-connected current, causing electromagnetic interference, but also poses a safety hazard.

[0004] Traditional NPC three-level converter control methods typically employ a strategy to balance the midpoint voltage by adjusting the redundant vector action time. While this method can balance the midpoint voltage to a certain extent, its regulation capability is limited, and it cannot precisely control the midpoint current. Furthermore, traditional SVPWM (Space Vector Pulse Width Modulation) methods often require detailed partitioning and complex calculations to achieve midpoint voltage balance and leakage current suppression, resulting in a cumbersome and computationally intensive implementation. While some existing approaches reduce low-order harmonics and leakage current by introducing a midpoint voltage balancing loop or optimizing modulation strategies, these methods often only partially address the problem, failing to effectively suppress leakage current while ensuring midpoint voltage balance. Furthermore, their high implementation complexity hinders widespread adoption in practical applications. Summary of the Invention

[0005] In view of this, it is necessary to provide a three-level converter neutral point voltage control and leakage current suppression method based on SVPWM to solve the technical difficulties of the NPC three-level converter.

[0006] To solve the above problems, an embodiment of the present invention provides a method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM, comprising:

[0007] Based on the NPC three-level converter topology, a basic output voltage vector of the NPC three-level converter is defined, a space voltage vector diagram of the NPC three-level converter is drawn, and the space voltage vector diagram of the NPC three-level converter is divided into a plurality of sectors; wherein the basic output voltage vector includes a large vector, a medium vector, a small vector, and a zero vector;

[0008] Analyze the impact of each sector's small vector on the midpoint voltage. Combine small vectors with small vectors, and small vectors with the midpoint vector, to form two types of combined vectors. Ensure that the sum of the midpoint currents generated by each combined vector within a cycle is zero, thus obtaining the first constraint.

[0009] With the zero vector and the large vector as fixed output vectors, the action time of the large vector and the zero vector in each sector is calculated based on the volt-second balance principle. When introducing the combined vector to synthesize the spatial voltage vector, the action time of each switch state in each phase arm is ensured to remain unchanged before and after the introduction of the combined vector, thus obtaining the second constraint condition.

[0010] Based on the relationship between the time variation of the small vector action and the degree of midpoint voltage imbalance and the direction of active power flow, a third constraint condition is established;

[0011] Unbind the switching states of the three-phase bridge arms, and sort and optimize the switching states of each phase bridge arm separately to suppress leakage current;

[0012] Combining the first constraint, the second constraint, the third constraint and the optimized switch state sequence, the action time of the basic output voltage vector in each sector is solved to generate the drive signal of the switch tube of each phase bridge arm.

[0013] Preferably, the defining of the basic output voltage vector of the NPC three-level converter based on the NPC three-level converter topology structure includes:

[0014] The NPC three-level converter includes phase a, phase b, and phase c bridge arms. Each phase bridge arm contains four switching transistors and a pair of clamping diodes. The four switching transistors and the pair of clamping diodes are connected to the midpoint between the DC side upper capacitor and the DC side lower capacitor. The voltage at the midpoint between the DC side upper capacitor and the DC side lower capacitor is the midpoint voltage.

[0015] Each phase bridge arm has three switching state outputs: P, O, and N. If the first and second switching tubes of the bridge arm are turned on at the same time, it is represented by P; if the second and third switching tubes of the bridge arm are turned on at the same time, it is represented by O; if the third and fourth switching tubes of the bridge arm are turned on at the same time, it is represented by N.

[0016] Based on the three switching states P, O, and N of each phase bridge arm of the NPC three-level converter, 27 different switching state combinations of the three-phase bridge arms are obtained;

[0017] Each switching state combination corresponds to a basic output voltage vector; where:

[0018] Zero vector: The voltage vector with zero amplitude in the NPC three-level converter, represented as OOO;

[0019] Small vector: voltage vector with small amplitude in NPC three-level converter, including but not limited to POO and ONN;

[0020] Medium vector: a voltage vector with an amplitude between the large vector and the small vector, including but not limited to PON and OPN;

[0021] Large vector: The voltage vector with the largest amplitude in the NPC three-level converter, including but not limited to PPN and PNN.

[0022] Preferably, the drawing of the spatial voltage vector diagram of the NPC three-level converter includes:

[0023] Considering the impact of midpoint voltage imbalance, the midpoint voltage imbalance degree λ is defined as:

[0024]

[0025] Where, V dc1 、 V dc2 and V dc Represent the DC side upper capacitor voltage, DC side lower capacitor voltage and total voltage respectively;

[0026] Plot the spatial voltage vector diagram for λ>0, λ=0, and λ<0.

[0027] Preferably, the calculation of the action time of the large vector and the zero vector in each sector according to the volt-second balance principle includes:

[0028] For sector I, according to the volt-second balance principle, we get:

[0029]

[0030] Where, V rrepresents the space voltage vector, T s is the switching period, V pnn represents the voltage corresponding to the large vector PNN, V ppn represents the voltage corresponding to the large vector PPN, V ooo Represents the voltage corresponding to the zero vector OOO, t I_1 is the action time of the large vector PNN in sector I, t I_2 is the action time of the large vector PPN in sector I, t I_0 is the action time of zero vector OOO in sector I; V α 、 V β They represent the voltages of the two phases in the stationary coordinate system, j is an imaginary unit;

[0031] For other sectors, the same method as sector 1 is used to calculate the action time of large vectors and zero vectors in the sector.

[0032] Preferably, the first constraint condition is obtained by ensuring that the sum of the midpoint currents generated by each combination vector in one cycle is zero, including:

[0033] In order to maintain the balance of the midpoint voltage and ensure that the sum of the midpoint currents generated by all combination vectors in one cycle is zero, the first constraint condition is obtained as follows: the action time of each combination vector is equal.

[0034] Preferably, when introducing the combined vector to synthesize the space voltage vector, it is ensured that the action time of each switch state of each phase bridge arm remains unchanged before and after the introduction of the combined vector, and the second constraint condition is obtained, including:

[0035] A combination vector is introduced into the fixed output voltage vector sequence to synthesize the space voltage vector;

[0036] To ensure the stability of the output voltage after the combination vector is introduced, it is necessary to ensure that the P, O, and N switching state action time of each phase bridge arm remains unchanged before and after the combination vector is introduced. Therefore, the second constraint condition is: the switching state action time of each phase bridge arm remains unchanged before and after the combination vector is introduced;

[0037] For sector 1, the expression of the second constraint is:

[0038]

[0039] Where, t 10、 t 11 、 t 12 、 t 13 、 t 14 and t 15 They respectively represent the corresponding action times of the basic output voltage vectors OOO, PNN, PPN, PPO, PON and OPN in sector 1; for other sectors, the action times of the basic output voltage vectors also have a constraint relationship as expressed in the second constraint condition.

[0040] Preferably, the third constraint condition is established based on the relationship between the variation of the small vector action time and the degree of midpoint voltage imbalance and the direction of active power flow, including:

[0041] The degree of imbalance of the midpoint voltage is expressed by λ. When λ>0, the voltage of the capacitor on the DC side is greater than the voltage of the capacitor on the DC side; when λ<0, the voltage of the capacitor on the DC side is less than the voltage of the capacitor on the DC side.

[0042] Kpower is used to represent the direction of active power flow. Kpower>0 means that the active power flows from the DC side of the converter to the AC side. Kpower<0 means that the active power flows from the AC side of the converter to the DC side. Kpower=0 means that there is no active power flow.

[0043] The small vector of the NPC three-level converter generates a midpoint current, which in turn affects the midpoint voltage. When the voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side are inconsistent, the midpoint voltage becomes unbalanced. By controlling the action time of the small vector, the voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side can be adjusted to bring the midpoint voltage into a balanced state.

[0044] The expression of the third constraint is:

[0045]

[0046] Where, t is the time variation of the small vector action, k dc_P and k dc_I are the proportional and integral adjustment coefficients of the PI controller respectively; Sign is the direction of active power flow; s is the complex frequency variable in the Laplace transform.

[0047] Preferably, the step of unbinding the switch states of the three-phase bridge arms and individually sorting and optimizing the switch states of each phase bridge arm to suppress leakage current includes:

[0048] Unbind the switch states of the three-phase bridge arms, and sort the switch states of each phase bridge arm independently;

[0049] According to the switching state action time of each phase bridge arm, the switching sequence of the switching state is optimized to reduce the number of switching times;

[0050] By optimizing the switching state sequence, the vectors that generate common-mode voltage amplitudes exceeding a preset threshold are avoided, thereby reducing the rate of change of the common-mode voltage and suppressing leakage current.

[0051] The SVPWM-based three-level converter midpoint voltage control and leakage current suppression method provided by the present invention has the following beneficial effects compared with the prior art:

[0052] 1) This invention introduces two types of vector combinations (small vectors combined with small vectors, and small vectors combined with medium vectors) and ensures that the action time of each combination is equal, thus ensuring that the sum of the midpoint currents generated by each combination within a cycle is zero. This design effectively maintains midpoint voltage balance and avoids uneven voltage stress on busbar capacitance and power devices caused by midpoint voltage imbalance.

[0053] 2) By unbundling the switching states of the three-phase bridge arms and individually sorting and optimizing the switching state of each phase, this invention reduces the number of switching cycles and achieves smooth switching. This optimization avoids the large common-mode voltage amplitude caused by switching state jumps in traditional SVPWM, effectively suppressing leakage current.

[0054] 3) By optimizing the output voltage vector sequence, the use of small vectors with large common-mode voltage (such as PPO, ONN, etc.) is avoided, further reducing the change rate of the common-mode voltage, thereby significantly reducing the generation of leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Flowchart of the method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM provided by the present invention;

[0056] Figure 2 This is a topological diagram of the main circuit of the NPC three-level converter provided by the present invention;

[0057] Figure 3 (a) shows the NPC three-level space vector diagram when the midpoint voltage imbalance degree λ is greater than zero;

[0058] Figure 3 (b) shows the NPC three-level space vector diagram when the midpoint voltage imbalance degree λ is equal to zero;

[0059] Figure 3 (c) shows the NPC three-level space vector diagram when the midpoint voltage imbalance degree λ is less than zero;

[0060] Figure 4 (a) is the equivalent circuit diagram of the small vector PPO in sector I;

[0061] Figure 4(b) is the equivalent circuit diagram of the small vector OON in sector I;

[0062] Figure 4(c) is the equivalent circuit diagram of the small vector POO in sector I;

[0063] Figure 4(d) shows the equivalent circuit diagram of the small vector ONN in sector I;

[0064] Figure 4(e) is the equivalent circuit diagram of the medium-vector PON in sector I;

[0065] Figure 5 The action sequence when the three-phase bridge arm switch states in sector I are bound;

[0066] Figure 6 The action sequence of the switch state of each phase bridge arm in sector I after unbinding;

[0067] Figure 7 To optimize the action sequence of the switching state of each phase bridge arm in sector I;

[0068] Figure 8 (a) shows the voltage waveforms of the upper and lower capacitors on the DC side when modulation strategy I is adopted;

[0069] Figure 8(b) shows the output current waveform of the NPC three-level converter when modulation strategy I is adopted;

[0070] Figure 9(a) shows the common-mode voltage waveform when modulation strategy I is adopted;

[0071] Figure 9(b) shows the waveform of the enlarged area in Figure 9(a);

[0072] Figure 10 is the converter leakage current waveform when modulation strategy I is adopted;

[0073] Figure 11 (a) shows the voltage waveforms of the upper and lower capacitors on the DC side when modulation strategy II is adopted;

[0074] Figure 11(b) shows the output current waveform of the NPC three-level converter when modulation strategy II is adopted;

[0075] Figure 12 (a) shows the common-mode voltage waveform when modulation strategy II is adopted;

[0076] Figure 12(b) shows the waveform of the enlarged area in Figure 12(a);

[0077] Figure 13 This is the converter leakage current waveform when modulation strategy II is adopted. DETAILED DESCRIPTION

[0078] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0079] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0080] Traditional SVPWM modulation strategies struggle to simultaneously balance midpoint voltage and suppress leakage current. Their implementation is cumbersome and computationally intensive. While some existing approaches reduce low-order harmonics and leakage current by introducing a midpoint voltage balancing loop or optimizing the modulation strategy, these methods often only partially address the problem, failing to effectively suppress leakage current while ensuring midpoint voltage balance. Furthermore, traditional methods suffer from jumps during switching, increasing switching losses, reducing system efficiency, and making smooth switching difficult.

[0081] In light of this, the present invention provides a method for controlling the midpoint voltage and suppressing leakage current in a three-level converter based on SVPWM. This method aims to achieve precise control of the midpoint voltage by introducing two types of combined vectors and rationally configuring their action times. Furthermore, by unbundling and optimizing the switching states of the three-phase bridge arms, the number of switching cycles is reduced, smooth switching is achieved, and leakage current is effectively suppressed. This method will be described and illustrated below through multiple embodiments.

[0082] Figure 1 The flow chart of the method for controlling the midpoint voltage and suppressing the leakage current of the three-level converter based on SVPWM provided by the present invention is as follows. Figure 1 As shown, the SVPWM-based three-level converter neutral point voltage control and leakage current suppression method includes the following steps.

[0083] Step S1, based on the NPC three-level converter topology, defining the basic output voltage vector of the NPC three-level converter, drawing the NPC three-level converter space voltage vector diagram, and dividing the NPC three-level converter space voltage vector diagram into multiple sectors; wherein the basic output voltage vector includes a large vector, a medium vector, a small vector and a zero vector.

[0084] Specifically, the method provided by the present invention is described by taking the application of a diode neutral point clamped (NPC) three-level converter in a photovoltaic storage microgrid as an example. Figure 2This is the main circuit topology diagram of the NPC three-level converter provided by the present invention. Figure 2 The NPC three-level converter includes phase a, phase b, and phase c bridge arms. Each phase bridge arm contains four switching tubes and a pair of clamping diodes. The four switching tubes and the pair of clamping diodes are all connected to the midpoint O1 of the upper and lower capacitors (C1 and C2) on the DC side. The voltage at the midpoint O1 of the upper and lower capacitors on the DC side is the midpoint voltage.

[0085] Each phase arm of the NPC three-level converter outputs three different voltage levels, including a positive level P, a zero level O, and a negative level N. Figure 2 In the diagram, each phase bridge arm has three state outputs: P, O, and N. If the first and second switches of the bridge arm are turned on at the same time, it is represented by P; if the second and third switches of the bridge arm are turned on at the same time, it is represented by O; if the third and fourth switches of the bridge arm are turned on at the same time, it is represented by N. PV1 is the parasitic capacitance of the photovoltaic panel positive electrode to the ground, C PV2 is the parasitic capacitance of the negative electrode of the photovoltaic panel to the ground, C PV2 ≈C PV1 =C PV .

[0086] The inconsistency of the parameters of the upper and lower capacitors C1 and C2 will affect the midpoint voltage of the NPC three-level converter. Considering the impact of the midpoint voltage imbalance, the midpoint voltage imbalance degree λ is defined as:

[0087]

[0088] Where, V dc1 、 V dc2 and V dc They represent the upper capacitor voltage on the DC side, the lower capacitor voltage on the DC side and the total voltage respectively.

[0089] In this embodiment, the space voltage vector diagrams are plotted for λ>0, λ=0, and λ<0. When the midpoint voltage imbalance λ is greater than zero, the NPC three-level space vector diagram is shown in Figure 3(a). When the midpoint voltage imbalance λ is zero, the NPC three-level space vector diagram is shown in Figure 3(b). When the midpoint voltage imbalance λ is less than zero, the NPC three-level space vector diagram is shown in Figure 3(c).

[0090] Referring to Figures 3(a) to 3(c), in this embodiment, each vector diagram is divided into six sectors, each of which is an equilateral triangle and labeled I, II, III, IV, V, and VI. Within each vector diagram, there are 19 basic vectors in the six sectors, corresponding to 27 switching states.

[0091] Based on the three possible switching states of each phase bridge arm, P, O, and N, 27 different switching state combinations of the three-phase bridge arm are obtained. Each switching state combination corresponds to a basic output voltage vector. According to the magnitude of the vector amplitude, the basic voltage vector can be divided into zero vector, small vector, medium vector, and large vector. Among them:

[0092] Zero vector: The voltage vector with zero amplitude in the NPC three-level converter, represented as OOO;

[0093] Small vector: voltage vector with small amplitude in NPC three-level converter, including but not limited to POO and ONN;

[0094] Medium vector: a voltage vector with an amplitude between the large vector and the small vector, including but not limited to PON and OPN;

[0095] Large vector: The voltage vector with the largest amplitude in the NPC three-level converter, including but not limited to PPN and PNN.

[0096] Step S2: Analyze the impact of the small vectors of each sector on the midpoint voltage, combine the small vectors with the small vectors, and combine the small vectors with the midpoint vector to form two types of combined vectors; ensure that the sum of the midpoint currents generated by each combined vector in one cycle is zero, and obtain the first constraint condition.

[0097] It should be noted that both the small vector and the medium vector of the NPC three-level converter will generate a midpoint current. i NP , thus affecting the balance of the midpoint voltage, as shown in Table 1. However, neither the zero vector nor the large vector will generate midpoint current and will not affect the balance of the midpoint voltage.

[0098] Table 1 Midpoint currents corresponding to the mid-point vectors and small vectors in the six sectors i NP

[0099]

[0100] According to the analysis of Figures 3(a) and 3(c), when the initial values of the upper and lower capacitor voltages are inconsistent (i.e., λ≠0), λ affects the small and middle vectors but has no effect on the zero and large vectors. When using an SVPWM strategy, the basic output voltage vector typically includes a middle or small vector. In this case, λ interacts with the small and middle vectors, potentially leading to a serious imbalance in the upper and lower capacitor voltages and consequently damaging the capacitors. Therefore, for situations where λ≠0, the midpoint voltage must first be adjusted using the middle or small vector to bring λ close to zero. Secondly, the small and middle vectors in the basic output voltage vector must be properly configured to ensure that the sum of the midpoint currents generated within a cycle is zero. This is the key to achieving active midpoint voltage control.

[0101] Within sector I, although OOO, PPN, and PNN can be used as output voltage vectors to synthesize Vr, these vectors cannot actively regulate the midpoint voltage. Therefore, a small vector is needed to balance the midpoint voltage while ensuring that the sum of the midpoint currents generated by all output voltage vectors within a cycle is zero. Furthermore, the number of switching cycles of the switching transistors in each phase arm must be considered. When the output voltage vector includes OOO, PNN, and PPN, the switching state of the phase a arm involves O and P, switching at least twice; the switching state of the phase b arm involves O, N, and P, switching at least four times; and the switching state of the phase c arm involves O and N, switching at least twice. To reduce switching losses, the number of switching cycles of the switching transistors in each phase arm should be minimized. Therefore, the additional small vector or midpoint vector should meet the following two conditions: 1) the switching state of the phase a arm only includes O and P; 2) the switching state of the phase c arm only includes O and N.

[0102] Based on the above embodiment and in conjunction with Table 1, it is possible to configure combinations of small or neutral vectors within sector 1, where all voltage vectors in each combination have the same action time, as shown in Table 2. Similarly, combinations of small or neutral vectors within other sectors can be configured with reference to Table 2. The combinations in Table 2 can be divided into two categories: the first category is a combination of small vectors and neutral vectors, and the second category is a combination of small vectors and small vectors. The first category can be further divided into five combinations, and the second category can be further divided into four combinations. Taking the first combination in the first category as an example, the small vector PPO can be used to actively adjust the balance of the midpoint voltage. In combination with the two neutral vectors PON and OPN, as long as their action times are the same, the sum of the midpoint currents generated within a cycle is guaranteed to be zero, thereby maintaining midpoint voltage balance.

[0103] Table 2 Two combinations of medium or small vectors in sector I

[0104]

[0105] By combining two small vectors, their effects on the midpoint current can be canceled out. For example, if one small vector causes the midpoint current to flow into the midpoint, and another small vector causes the midpoint current to flow out of the midpoint, their combination can make the sum of the midpoint currents zero within a cycle, thus maintaining the balance of the midpoint voltage.

[0106] The first type of combination vector is formed by combining a small vector with a neutral vector. For example, within a sector, a small vector and two neutral vectors can be combined. By properly configuring their action times, the sum of the midpoint currents generated within a cycle is zero.

[0107] The second type of combination vector is formed by combining two small vectors. By selecting two small vectors with opposite effects on the midpoint current, the sum of the midpoint currents generated by their combination within one cycle is zero. There are five possible combinations of the first type of combination vector, and four possible combinations of the second type of combination vector.

[0108] To maintain midpoint voltage balance and ensure that the sum of the midpoint currents generated by all combined vectors within a cycle is zero, the first constraint is that the action time of each combined vector is equal. For example, within sector I, a small vector PPO can be combined with medium vectors PON and OPN. By properly configuring their action time, the sum of the midpoint currents generated within a cycle is zero.

[0109] For sector I, when λ = 0, in order to ensure that the sum of the midpoint currents generated by vectors PPO, PON, and OPN is zero within one cycle, the first constraint condition is that the action time of each combination vector is equal. The expression of the first constraint condition is:

[0110] t 13 = t 14 = t 15 = t com

[0111] Where, t 13 、 t 14 and t 15 They represent the corresponding action times of the basic output voltage vectors PPO, PON and OPN in sector I respectively; t com is a variable, t com ≤min( t I_0 , 0.5 t I_2 ). For other sectors, under the premise that the first constraint condition remains unchanged, the expression can be adaptively adjusted according to demand.

[0112] For other sectors, the same first constraint condition is adopted to ensure that the action time of the combined vector is equal and the midpoint voltage balance is maintained.

[0113] By ensuring that the action time of the combined vector is equal, fluctuation of the mid-point voltage can be avoided and the mid-point voltage can be kept balanced.

[0114] In step S3, the zero vector and the large vector are used as fixed output vectors. Based on the volt-second balance principle, the action time of the large vector and the zero vector in each sector is calculated. When the combined vector is introduced to synthesize the spatial voltage vector, the action time of each switch state in each phase arm is ensured to remain unchanged before and after the introduction of the combined vector, thereby obtaining the second constraint condition.

[0115] According to the above embodiments, it is known that the midpoint voltage can be adjusted from an unbalanced state to a balanced state by adjusting the small vector. In order to maintain the balance of the midpoint voltage, it is also necessary to reasonably configure the small vector or the middle vector in the basic output voltage vector. First, the appropriate basic output voltage vector can be selected according to Figure 3 (b). V r Represents the spatial voltage vector of the three-phase NPC three-level converter. According to the principle of adjacent three vectors, it can be seen that in sector I, only the zero vector and two large vectors are used as the basic output voltage vectors to synthesize V r .when V r Located in sector I, according to the volt-second balance principle:

[0116]

[0117] Where, V r represents the space voltage vector, T s is the switching period, V pnn represents the voltage corresponding to the large vector PNN, V ppn represents the voltage corresponding to the large vector PPN, V ooo Represents the voltage corresponding to the zero vector OOO, t I_1 is the action time of the large vector PNN in sector I, t I_2 is the action time of the large vector PPN in sector I, t I_0 is the action time of zero vector OOO in sector I; V α 、 V β They represent the voltages of the two phases in the stationary coordinate system, j Is an imaginary unit.

[0118] According to the above equation, we can solve t I_0 、 t I_1 and t I_2The value of , thus obtaining the action time of the zero vector (OOO) and two large vectors (PPN, PNN) in sector I. V r When located in other sectors, the action time of the zero vector and the large vector in the corresponding sector can be derived by similar equations.

[0119] When λ=0, it can be seen from Figure 3(b) that V PPN =0.5(V PON +V OPN ), V PPN =2V PPO Therefore, the same space voltage vector can be synthesized using OOO, PNN, PPN, PPO, PON and OPN as new basic output voltage vectors V r , while the action time of the switching state of each phase bridge arm remains unchanged. The basic output voltage vectors in other sectors can also be configured according to the above method, as shown in Table 3.

[0120] Table 3 Basic output voltage vectors in six sectors

[0121]

[0122] In sector 1, when only OOO, PNN and PPN are used to synthesize V r From the above embodiment, it can be seen that the action time of the a-phase bridge arm in the O state is tI_0, and the action time of the P state is tI_1+tI_2; the action time of the b-phase N state is t I_1 , the time of O state is t I_0 , the time of P state is t I_2 ; The time of the c-phase N state is t I_1 + t I_2 , the time of O state is t I_0 When OOO, PNN, PPN, PPO, PON and OPN are used as new output voltage vectors to synthesize V r When the combined vector is introduced, the action time of the P, O, and N states of each phase bridge arm remains unchanged before and after the introduction. Based on this, the expression of the second constraint condition can be derived as follows:

[0123]

[0124] Where, t10 、 t 11 、 t 12 、 t 13 、 t 14 and t 15 They represent the corresponding action times of the basic output voltage vectors OOO, PNN, PPN, PPO, PON, and OPN in sector 1. For other sectors, the action times of the output voltage vectors also have the same constraint relationship as above, and the second constraint condition also applies. The expression can be adaptively adjusted according to needs.

[0125] The second constraint provided in this embodiment ensures the stability and consistency of the output voltage by keeping the action time of the P, O, and N states of each phase arm unchanged before and after the introduction.

[0126] Step S4: establishing a third constraint condition based on the relationship between the time variation of the small vector action and the degree of midpoint voltage imbalance and the direction of active power flow;

[0127] When the NPC three-level converter is connected to the load or grid in AC mode, the equivalent circuit diagram of the middle vector and small vector in sector I is shown in Figure 4. When the converter transmits active power from the DC side to the AC side, the small vectors PPO and POO will cause the upper capacitor to discharge, thereby reducing the voltage of the upper capacitor. On the contrary, when the AC side transmits active power to the DC side, the small vectors PPO and POO will charge the upper capacitor, causing the voltage of the upper capacitor to rise. Therefore, the voltage of the upper capacitor can be controlled by adjusting the action time of the small vector PPO or POO. Similarly, the voltage of the lower capacitor can be controlled by adjusting the action time of the small vector ONN or OON. In the middle vector PON state, the midpoint current i NP Equal to i b This also affects the balance of the midpoint voltage. However, the impact on the upper and lower capacitor voltages cannot be determined based on the direction of active power flow. Therefore, when the initial voltages of the upper and lower capacitors are inconsistent, the voltages of the upper and lower capacitors can be controlled by adjusting the application time of the small vectors (PPO, POO, ONN, and OON) within sector I, thereby achieving a balanced midpoint voltage. Similarly, the midpoint voltage can be balanced in other sectors by adjusting the application time of the small vectors.

[0128] In the embodiment of the present invention, λ is used to represent the degree of imbalance of the midpoint voltage. When λ>0, the voltage of the upper capacitor on the DC side is greater than the voltage of the lower capacitor on the DC side; when λ<0, the voltage of the upper capacitor on the DC side is less than the voltage of the lower capacitor on the DC side.

[0129] Kpower is used to represent the direction of active power flow. Kpower>0 means that the active power flows from the DC side of the converter to the AC side. Kpower<0 means that the active power flows from the AC side of the converter to the DC side. Kpower=0 means that there is no active power flow.

[0130] The small vector of the NPC three-level converter will generate a midpoint current, which in turn affects the midpoint voltage. When the voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side are inconsistent, the midpoint voltage becomes unbalanced. The voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side can be adjusted by controlling the action time of the small vector to bring the midpoint voltage into a balanced state.

[0131] When λ≠0, it is necessary to adjust the action time of the small vector according to the imbalance degree λ of the midpoint voltage and the direction of active power flow, so as to adjust the balance of the midpoint voltage.

[0132] Taking the small vector PPO in sector I as an example, when λ > 0 and Kpower > 0, the upper capacitor voltage is higher than the lower capacitor voltage, and active power flows from the DC side to the AC side. The action time of the small vector PPO needs to be increased to discharge the upper capacitor and reduce the upper capacitor voltage.

[0133] When λ>0 and Kpower<0, the upper capacitor voltage is higher than the lower capacitor voltage, and active power flows from the AC side to the DC side. It is necessary to reduce the action time of the small vector PPO to charge the upper capacitor and reduce the upper capacitor voltage.

[0134] When λ<0 and Kpower>0, the voltage of the lower capacitor is higher than that of the upper capacitor, and active power flows from the DC side to the AC side. It is necessary to reduce the action time of the small vector PPO to discharge the lower capacitor and increase the voltage of the upper capacitor.

[0135] When λ < 0 and Kpower < 0, the voltage on the lower capacitor is higher than the voltage on the upper capacitor, and active power flows from the AC side to the DC side. The action time of the small vector PPO needs to be increased to charge the lower capacitor and increase the voltage on the upper capacitor. Similarly, the relationship between the action time of the other small vectors in Table 2 and the voltages on the upper and lower capacitors and the direction of active power flow is similar. A sign function, Sign, is defined based on the direction of active power flow, as follows:

[0136]

[0137] According to the above analysis, the time variation of the small vector action △t has a certain correlation with λ and Kpower. The expression of the third constraint condition is:

[0138]

[0139] Where,t is the time variation of the small vector action, k dc_P and k dc_I are the proportional and integral adjustment coefficients of the PI controller respectively; Sign is the direction of active power flow; s is the complex frequency variable in the Laplace transform.

[0140] When λ≠0, combining the expressions of the first constraint and the third constraint, the expression of the small vector PPO action time can be obtained as:

[0141] t 13 = t com +△ t

[0142] The above formula can also be used to refer to the constraints of the action time, λ and Kpower of other small vectors in Table 2.

[0143] For the constraints on the action time of other small vectors and λ and Kpower in Table 2, the third constraint mentioned above can also be referred to. From the expression of the third constraint, it can be seen that, in theory, as long as Sign≠0, the action time of the small vector and the value of λ form a closed-loop regulation, and will eventually enter a steady state, when λ is equal to 0 and △t is also equal to 0, which means that the action time of the combined vectors PPO, PON and OPN will also be equal. Therefore, even if the initial voltages of the upper and lower capacitors are inconsistent (that is, λ≠0), by introducing small vectors for closed-loop regulation, the midpoint voltage can be restored to balance and the sum of the midpoint currents generated by all output voltage vectors within one cycle can be ensured to be zero. The third constraint provided in this embodiment uses closed-loop regulation to make the midpoint voltage imbalance λ approach zero, thereby achieving active control of the midpoint voltage.

[0144] Step S5: unbinding the switch states of the three-phase bridge arms, and sorting and optimizing the switch states of each phase bridge arm separately to suppress leakage current.

[0145] Specifically, in the traditional SVPWM implementation process, the switching states of the three-phase bridge arms are bound to each other. Therefore, the switching times of the three-phase bridge arm switches and the switching state jumps are closely related to the arrangement order of the basic output voltage vectors. In sector I, the arrangement order of the basic output voltage vectors is OOO, PNN, PPN, PPO, PON and OPN, and their corresponding action times are t 10 、 t 11 、 t 12 、 t13 、 t 14 and t 15 , the action sequence of the three-phase bridge arm switch state is as follows Figure 5 As shown. Figure 5 It can be seen that within a single sampling period, the switching state of the phase a bridge arm switched four times; the switching state of the phase b bridge arm switched eight times, sometimes jumping directly from the N state to the P state; and the switching state of the phase c bridge arm switched six times. In addition, the switching state of the phase b bridge arm jumped, causing its four switches to switch states simultaneously, increasing the risk of switch damage and preventing smooth switching.

[0146] To reduce switching frequency and achieve smoother switching, the switching states of the three-phase bridge legs can be unbundled. Unbundling separates the switching states of the three-phase bridge legs, allowing each phase's switching state to be independently sequenced and optimized, rather than switching synchronously. This approach effectively reduces unnecessary switching, lowers switching losses, and minimizes common-mode voltage variations.

[0147] like Figure 6 As shown, based on the principle of the phase duty cycle method, while maintaining the same operating time (or duty cycle) of the three switching states N, O, and P in each bridge arm, the sequence of these three switching states can be adjusted without changing the output voltage of each bridge arm. By unbundling the switching states of the three-phase bridge arm and sequencing the switching states of each phase arm independently, the output voltage of the three-phase bridge arm is also not affected.

[0148] By individually sequencing the switching states of each phase bridge arm, the switching order can be optimized, making switching smoother and reducing switching state jumps. This not only reduces switching losses but also reduces the amplitude of the common-mode voltage, thereby suppressing leakage current.

[0149] from Figure 6 It can be seen that within one sampling period, the switching state of the bridge arm of phase a switched twice, in the order of O→P→O; the switching state of the bridge arm of phase b switched four times, in the order of N→O→P→O→N, and no state jump occurred; the switching state of the bridge arm of phase c switched twice, in the order of N→O→N. Figure 5 In comparison, after the switch states of the three-phase bridge arms are untied, the number of switching times is significantly reduced, and smooth switching is achieved.

[0150] In step S5, the switching states of the three-phase bridge arms are first untied, and the switching states of each phase bridge arm are independently sorted. Next, the switching state switching sequence is optimized based on the switching state duration of each phase bridge arm to reduce the number of switching cycles. Finally, by optimizing the switching state sequence, vectors that generate common-mode voltage amplitudes exceeding a preset threshold are avoided, thereby reducing the rate of change of the common-mode voltage and suppressing leakage current.

[0151] For the active control of the midpoint voltage of the three-phase three-level converter, the suppression of leakage current must also be considered. Figure 2 It can be seen that the leakage current i of the positive and negative electrodes of the photovoltaic panel is PV1 、i PV2 They are:

[0152]

[0153] Where, C PV1 Indicates the parasitic capacitance of the positive electrode of the photovoltaic panel to the ground, C PV2 Indicates the parasitic capacitance between the negative electrode of the photovoltaic panel and the ground; V PV1 Indicates the voltage between the positive pole of the photovoltaic panel and the ground. V PV2 Indicates the voltage between the negative pole of the photovoltaic panel and the ground.

[0154] Since the parasitic capacitance is much smaller than the upper and lower bus capacitors, only high-frequency voltage signals can generate a large leakage current on them, and the high-frequency voltage signals on the upper and lower bus capacitors are very small, that is, V NO1 = V PV1 = V PV2 .use V CM Represents the common mode voltage, which can be derived from the bridge arm voltage of the three-phase NPC three-level converter V CM The expression is:

[0155]

[0156] Where, v ao 、 v bo and v co are the voltages of the three-phase bridge arms of the converter respectively.

[0157] Then, we can get the expression of the leakage current of the positive and negative electrodes of the photovoltaic panel:

[0158]

[0159] Where, C PV Represents the parasitic capacitance of the photovoltaic panel to the ground.

[0160] From the above formula, we can see that reducing the change rate of the common mode voltage d V CM / d t Can effectively suppress leakage current.

[0161] Table 4 Three-phase bridge arm switch status corresponding V CM

[0162]

[0163] According to the above analysis, the common-mode voltage is closely related to the bridge arm voltage, and the bridge arm voltage is mainly affected by the modulation strategy. The common-mode voltage corresponding to each voltage vector in Figure 3 V CM As shown in Table 4, the common-mode voltage amplitude of the zero vectors PPP and NNN is the largest, followed by the small vectors PPO, ONN, NON, OPP, NNO and POP. Due to the large number of partitions in traditional SVPWM, the switching process between zones is not smooth enough, resulting in a large common-mode voltage amplitude, which is prone to generate a large leakage current, thus affecting the safety and reliability of the photovoltaic microgrid. In order to suppress the leakage current, it is usually necessary to avoid using vectors that generate a common-mode voltage amplitude exceeding a preset threshold. In this embodiment, the preset threshold refers to a pre-set common-mode voltage amplitude threshold, which is set to V dc / 6. Taking the first combination of the first category in Table 2 as an example, combined with Figure 6 It can be seen that the basic output voltage vector in sector I contains small vectors ONN and PPO. Therefore, it is necessary to Figure 6 The output voltage vector sequence in is optimized, and the optimized sequence is as follows Figure 7 shown.

[0164] exist Figure 7 In the example, the sum of the P and O states in the b-phase bridge arm is greater than the O state in the a-phase bridge arm. Therefore, when the a-phase bridge arm is in the O state, the b-phase bridge arm will not be in the N state. This means that the small vector ONN does not appear in the basic output voltage vector. Furthermore, the P state in the b-phase bridge arm is less than the N state in the c-phase bridge arm. Therefore, when the b-phase bridge arm is in the P state, the c-phase bridge arm will definitely be in the N state. This means that the small vector PPO does not appear in the basic output voltage vector. Furthermore, the a-phase bridge arm will not be in the N state, and the c-phase bridge arm will not be in the P state. Therefore, the small vectors OPP, POP, NON, and NNO do not appear in the basic output voltage vector. Figure 7The switching state sequence for phase a is O→P→O; the switching state sequence for phase b is P→O→N→O→P; and the switching state sequence for phase c is N→O→N. The above analysis shows that after optimizing the three-phase switching state action sequence, although some small vectors still appear in the basic output voltage vector, these small vectors PPO, OPP, POP, NON, NNO, and ONN are not included. Similarly, the switching state action sequence for the three-phase arms in other sectors can be optimized using the above method to avoid the use of vectors that would generate large common-mode voltages. The switching state action sequences for the three-phase arms in the six sectors are shown in Table 5.

[0165] Table 5 Action sequence of three-phase bridge arm switch states in six sectors

[0166]

[0167] Combining the analysis of Table 4 and Table 5, we can see that Figure 7 The common mode voltage corresponding to all basic output voltage vectors in V CM The magnitude is less than or equal to V dc / 6, can further suppress the common mode voltage. V dc Represents the total voltage on the DC side of the NPC three-level converter. Similarly, for other combinations in the first category or all combinations in the second category introduced in Table 2, similar methods can also be used to suppress leakage current.

[0168] Step S6, combining the first constraint condition, the second constraint condition, the third constraint condition and the optimized switch state sequence, solves the action time of the basic output voltage vector in each sector, and generates a drive signal for the switch tube of each phase bridge arm.

[0169] In this embodiment, when the space voltage vector V r When it is within its sector, it can be Figure 7 The optimized switching state sequence for each phase bridge arm within sector I is calculated. Combining the first, second, and third constraints, the action time of the basic output voltage vector (see Table 3) can be calculated. For the remaining four combinations in the first approach and the four combinations in the second approach, the above method can be used to solve for the action time of the basic output voltage vector within each sector.

[0170] Based on the calculated action time of the basic output voltage vector, the action time of the P, O, and N states of each phase bridge arm is calculated. Based on the on / off action time of each phase bridge arm, the corresponding drive signal is generated to control the on / off of the switch. This optimized switching state sequence ensures smooth switching of the switch, reducing switching losses and electromagnetic interference.

[0171] To summarize, the zero vector (OOO) and two large vectors within each sector are first used as fixed output vectors, and their action times are calculated based on the volt-second balance principle. Next, any combination of vectors listed in Table 2 is introduced to achieve active midpoint voltage control. Next, the three-phase bridge arm switch states are unbundled, and the switch states of each phase arm are individually sorted. These sorted switch states are then optimized. Based on the optimized switch state sequence and combined with the three constraints, the action times of all output voltage vectors are solved, thereby obtaining the drive signals for the switches in each phase arm of the three-phase three-level converter.

[0172] The SVPWM-based three-level converter midpoint voltage control and leakage current suppression method provided by the present invention has the following beneficial effects compared with the prior art:

[0173] 1) This invention introduces two types of vector combinations (small vectors combined with small vectors, and small vectors combined with medium vectors) and ensures that the action time of each combination is equal, thus ensuring that the sum of the midpoint currents generated by each combination within a cycle is zero. This design effectively maintains midpoint voltage balance and avoids uneven voltage stress on busbar capacitance and power devices caused by midpoint voltage imbalance.

[0174] 2) By unbundling the switching states of the three-phase bridge arms and individually sorting and optimizing the switching state of each phase, this invention reduces the number of switching cycles and achieves smooth switching. This optimization avoids the large common-mode voltage amplitude caused by switching state jumps in traditional SVPWM, effectively suppressing leakage current.

[0175] 3) By optimizing the output voltage vector sequence, the use of small vectors with large common-mode voltage (such as PPO, ONN, etc.) is avoided, further reducing the change rate of the common-mode voltage, thereby significantly reducing the generation of leakage current.

[0176] In a preferred embodiment of the present invention, in order to fully verify the effectiveness of the proposed method, we constructed a Figure 2 The simulation model with the same system structure is shown, and two different modulation strategies are used for comparative analysis.

[0177] Modulation strategy I adopts a relatively basic scheme, that is, only the zero vector and two large vectors in the six sectors are used as the output voltage vectors. The combination vectors listed in Table 2 are not introduced, and the arm switch state sequence after unbundling is not optimized.

[0178] Modulation strategy II is an improvement on strategy I. It not only introduces the combination vectors in Table 2 (taking the first group as an example) to enhance the active control capability of the midpoint voltage, but also fine-tunes the switch state sequence of the bridge arm after unbundling.

[0179] In order to simulate the actual application scenario, this embodiment sets the simulation condition of the photovoltaic microgrid system and off-grid operation. In the main circuit, the capacitance of the upper and lower capacitors on the DC side is set to 6800uF, and the parasitic capacitance C PV2 with C PV1 The values of are approximately equal, both 30nF. The output filter uses an LCL structure, with specific parameters: L1 = 600uH, C = 9uF, and L2 = 300uH. In the simulation model, a DC voltage source on the DC side simulates the output of the photovoltaic storage device. The specific operating conditions are set as follows: the photovoltaic storage module transmits power to the grid via an NPC three-level converter, the DC side output voltage is constant at 750V, the initial voltages of the upper and lower capacitors are set to 400V and 350V, respectively, and the active current reference command is set to 30A (amplitude).

[0180] Under this operating condition, modulation strategy I was first used for simulation tests, and waveforms of the upper and lower capacitor voltages, common-mode voltage, leakage current, and output current were plotted. As shown in Figure 8(a), the upper and lower capacitor voltages remain largely near their initial values. This is primarily due to the lack of a midpoint voltage regulation mechanism in modulation strategy I, which results in an inability to achieve effective midpoint voltage balance, consistent with theoretical analysis. Figure 8(b) shows the output current waveform of the NPC three-level converter. The simulation results show that the output current amplitude is completely consistent with the reference set value.

[0181] Furthermore, Figure 9 shows the common-mode voltage waveform of the NPC three-level converter, where Figure 9(a) shows the common-mode voltage waveform when modulation strategy I is adopted, and Figure 9(b) shows the waveform of the magnified area in Figure 9(a). dc / 3 fluctuates up and down. This is because modulation strategy I does not optimize the bridge arm switch state sequence, resulting in the output voltage vector containing a small vector with a large common mode voltage amplitude, which is consistent with theoretical analysis. Figure 10 The leakage current waveform of the NPC three-level converter is given. The figure shows that the maximum leakage current is slightly greater than 0.1A, but still meets the requirements of the national standard.

[0182] Under the same working conditions, we adopted modulation strategy II for simulation test and presented the waveforms of upper and lower capacitor voltage, common mode voltage, leakage current, bridge arm line voltage and output current. As shown in Figure 11 (a), the upper and lower capacitor voltage gradually stabilized at V dc The results show that the midpoint voltage is approximately 0.5V / 2 (i.e., 375V), with minimal fluctuation. This simulation result strongly demonstrates that even when the initial capacitor voltage values are inconsistent, Modulation Strategy II can still accurately adjust the midpoint voltage to ensure it remains in a balanced state. Compared with Figure 8(a), the superiority of Modulation Strategy II in midpoint voltage balance control is fully demonstrated.

[0183] Figure 11 (b) shows the output current waveform of the NPC three-level converter. The simulation results show that the amplitude of the output current is completely consistent with the preset reference value, further verifying the effectiveness of modulation strategy II. In addition, Figure 12 shows the common-mode voltage waveform of the NPC three-level converter. As can be seen from the figure, the common-mode voltage only contains 0, ± U dc Compared with Figure 9, the results show that modulation strategy II is more effective than modulation strategy I in terms of common-mode voltage suppression.

[0184] Figure 13 The leakage current waveform of the NPC three-level converter is given. The figure shows that the maximum leakage current is less than 0.1A, which fully meets the requirements of the national standard. Figure 10 In comparison, modulation strategy II also shows superior performance in leakage current suppression.

[0185] In summary, the proposed modulation strategy II not only has excellent active midpoint voltage control capabilities, but also effectively suppresses leakage current while ensuring high-quality output waveforms. These advantages make modulation strategy II extremely valuable in the application of NPC three-level converters.

[0186] The above-described embodiments merely illustrate several embodiments of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0187] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for controlling the midpoint voltage and suppressing the leakage current of a three-level converter based on SVPWM, characterized in that: include: Based on the NPC three-level converter topology, a basic output voltage vector of the NPC three-level converter is defined, a space voltage vector diagram of the NPC three-level converter is drawn, and the space voltage vector diagram of the NPC three-level converter is divided into a plurality of sectors; wherein the basic output voltage vector includes a large vector, a medium vector, a small vector, and a zero vector; Analyze the impact of each sector's small vector on the midpoint voltage. Combine small vectors with small vectors, and small vectors with the midpoint vector, to form two types of combined vectors. Ensure that the sum of the midpoint currents generated by each combined vector within a cycle is zero, thus obtaining the first constraint. With the zero vector and the large vector as fixed output vectors, the action time of the large vector and the zero vector in each sector is calculated based on the volt-second balance principle. When introducing the combined vector to synthesize the spatial voltage vector, the action time of each switch state in each phase arm is ensured to remain unchanged before and after the introduction of the combined vector, thus obtaining the second constraint condition. Based on the relationship between the time variation of the small vector action and the degree of midpoint voltage imbalance and the direction of active power flow, a third constraint condition is established; Unbind the switching states of the three-phase bridge arms, and sort and optimize the switching states of each phase bridge arm separately to suppress leakage current; Combining the first constraint, the second constraint, the third constraint and the optimized switch state sequence, the action time of the basic output voltage vector in each sector is solved to generate the drive signal of the switch tube of each phase bridge arm.

2. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 1, wherein: The basic output voltage vector of the NPC three-level converter is defined based on the NPC three-level converter topology, including: The NPC three-level converter includes phase a, phase b, and phase c bridge arms. Each phase bridge arm contains four switching transistors and a pair of clamping diodes. The four switching transistors and the pair of clamping diodes are connected to the midpoint between the DC side upper capacitor and the DC side lower capacitor. The voltage at the midpoint between the DC side upper capacitor and the DC side lower capacitor is the midpoint voltage. Each phase bridge arm has three switching state outputs: P, O, and N. If the first and second switching tubes of the bridge arm are turned on at the same time, it is represented by P; if the second and third switching tubes of the bridge arm are turned on at the same time, it is represented by O; if the third and fourth switching tubes of the bridge arm are turned on at the same time, it is represented by N. Based on the three switching states P, O, and N of each phase bridge arm, 27 different switching state combinations of the three-phase bridge arm are obtained. Each switching state combination corresponds to a basic output voltage vector; among them: Zero vector: The voltage vector with zero amplitude in the NPC three-level converter, represented as OOO; Small vector: voltage vector with small amplitude in NPC three-level converter, including but not limited to POO and ONN; Medium vector: a voltage vector with an amplitude between the large vector and the small vector, including but not limited to PON and OPN; Large vector: The voltage vector with the largest amplitude in the NPC three-level converter, including but not limited to PPN and PNN.

3. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 2, characterized in that: The method of drawing a spatial voltage vector diagram of an NPC three-level converter includes: Considering the impact of midpoint voltage imbalance, the midpoint voltage imbalance degree λ is defined as: Where, V dc1 、 V dc2 and V dc Represent the DC side upper capacitor voltage, DC side lower capacitor voltage and total voltage respectively; Plot the spatial voltage vector diagram for λ>0, λ=0, and λ<0.

4. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 3, characterized in that: The calculation of the action time of the large vector and the zero vector in each sector according to the volt-second balance principle includes: For sector I, according to the volt-second balance principle, we get: Where, V r represents the space voltage vector, T s is the switching period, V pnn represents the voltage corresponding to the large vector PNN, V ppn represents the voltage corresponding to the large vector PPN, V ooo Represents the voltage corresponding to the zero vector OOO, t I_1 is the action time of the large vector PNN in sector I, t I_2 is the action time of the large vector PPN in sector I, t I_0 is the action time of zero vector OOO in sector I; V α 、 V β They represent the voltages of the two phases in the stationary coordinate system, j is an imaginary unit; For other sectors, the same method as sector 1 is used to calculate the action time of large vectors and zero vectors in the sector.

5. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 4, characterized in that: The first constraint condition is obtained by ensuring that the sum of the midpoint currents generated by each combination vector in one cycle is zero, including: In order to maintain the balance of the midpoint voltage and ensure that the sum of the midpoint currents generated by all combination vectors in one cycle is zero, the first constraint condition is: the action time of each combination vector is equal.

6. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 5, characterized in that: When introducing the combined vector to synthesize the space voltage vector, it is ensured that the action time of each switch state of each phase bridge arm remains unchanged before and after the introduction of the combined vector, and the second constraint condition is obtained, including: A combination vector is introduced into the fixed output voltage vector sequence to synthesize the space voltage vector; To ensure the stability of the output voltage after the combination vector is introduced, it is necessary to ensure that the P, O, and N switching state action time of each phase bridge arm remains unchanged before and after the combination vector is introduced. Therefore, the second constraint condition is: the switching state action time of each phase bridge arm remains unchanged before and after the combination vector is introduced; For sector 1, the expression of the second constraint is: Where, t 10 、 t 11 、 t 12 、 t 13 、 t 14 and t 15 They respectively represent the corresponding action times of the basic output voltage vectors OOO, PNN, PPN, PPO, PON and OPN in sector 1; for other sectors, the action times of the basic output voltage vectors also have a constraint relationship as expressed in the second constraint condition.

7. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 6, wherein: The third constraint condition is established based on the relationship between the time variation of the small vector action and the degree of midpoint voltage imbalance and the direction of active power flow, including: λ is used to represent the degree of midpoint voltage imbalance. When λ>0, the voltage of the upper capacitor on the DC side is greater than the voltage of the lower capacitor on the DC side; when λ<0, the voltage of the upper capacitor on the DC side is less than the voltage of the lower capacitor on the DC side. Kpower is used to represent the direction of active power flow. Kpower>0 means that the active power flows from the DC side of the converter to the AC side. Kpower<0 means that the active power flows from the AC side of the converter to the DC side. Kpower=0 means that there is no active power flow. The small vector of the NPC three-level converter generates a midpoint current, which in turn affects the midpoint voltage. When the voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side are inconsistent, the midpoint voltage becomes unbalanced. By controlling the action time of the small vector, the voltage of the upper capacitor on the DC side and the voltage of the lower capacitor on the DC side can be adjusted to bring the midpoint voltage into a balanced state. The expression of the third constraint is: Where, t is the time variation of the small vector action, k dc_P and k dc_I are the proportional and integral adjustment coefficients of the PI controller respectively; Sign is the direction of active power flow; s is the complex frequency variable in the Laplace transform.

8. The method for controlling the neutral point voltage and suppressing the leakage current of a three-level converter based on SVPWM according to claim 1, wherein: The step of unbundling the switch states of the three-phase bridge arms and individually sorting and optimizing the switch states of each phase bridge arm to suppress leakage current includes: Unbind the switch states of the three-phase bridge arms, and sort the switch states of each phase bridge arm independently; According to the switching state action time of each phase bridge arm, the switching sequence of the switching state is optimized to reduce the number of switching times; By optimizing the switching state sequence, the vectors that generate common-mode voltage amplitudes exceeding a preset threshold are avoided, thereby reducing the rate of change of the common-mode voltage and suppressing leakage current.

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