Biphase pulse circuit and high-frequency pulse therapeutic apparatus

Abstract

The invention provides a double-phase pulse circuit and a high-frequency pulse therapeutic apparatus, and relates to the technical field of medical instruments, and the double-phase pulse circuit comprises a booster circuit, N groups of pulse modulation isolation transformation circuits, an amplitude-limiting current-limiting circuit, a cascade circuit, a double-phase wave modulation circuit and a main controller, the boost circuit performs pulse modulation and boost processing on the output DC voltage of the target DC power supply to obtain an initial pulse voltage signal; n groups of pulse modulation isolation transformation circuits respectively perform isolation boosting processing on the initial pulse voltage signals to obtain N high-voltage pulse signals; the amplitude-limiting current-limiting circuit performs amplitude-limiting current-limiting processing on the N high-voltage pulse signals to obtain N high-voltage square-wave pulse signals; performing cascade processing on the N high-voltage square-wave pulse signals to obtain a target square-wave pulse signal; and performing dual-phase modulation on the target square wave pulse signal to obtain a target dual-phase pulse signal. According to the technical scheme, the effect of improving the safety of the double-phase pulse circuit is achieved.

Description

Technical Field

[0001] The present application relates to the technical field of medical devices, and in particular to a biphasic pulse circuit and a high-frequency pulse therapeutic apparatus. Background Art

[0002] High-frequency pulse therapy device, commonly known as nanosecond therapy device, is a non-thermal tumor ablation device, belonging to Class III medical device. It is based on the principle of irreversible electroporation, using strong pulsed electric field to create nano-scale micropores in tumor cells in the target area, causing cell apoptosis, and achieving the purpose of effectively treating tumors without damaging blood vessels, bile ducts, pancreatic ducts, nerves and other tissues in the treatment area. Since the therapy device needs to generate a pulsed electric field of sufficient intensity per unit area to achieve irreversible electroporation of cells, the intensity of the therapeutic electric field should be adjusted according to the actual size of the patient's application part, because a real-time voltage regulation circuit is required to achieve the best treatment effect.

[0003] The high-frequency pulse therapy devices currently on the market mainly use high-voltage capacitors to charge and then control the switch through the IGBT switch tube to achieve pulse output. The advantage of this implementation method is that the structure is simple. Due to the high voltage resistance of the IGBT, high-voltage pulses at the microsecond level can be easily obtained. However, due to the slow response speed of the IGBT, it is difficult to obtain high-voltage pulses at the nanosecond level. In addition, the high-voltage IGBT control module is relatively complex, which in turn affects the complexity of the two-phase pulse circuit, and the output pulse cannot be adjusted. In addition, since the high-voltage capacitor is directly in contact with the patient through the IGBT to discharge, the patient is at risk of being electrocuted by the excessive amount of electricity in the high-voltage capacitor. Therefore, it is particularly important to provide a two-phase pulse circuit with higher safety. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a biphasic pulse circuit and a high-frequency pulse therapeutic device.

[0005] In the first aspect, the present application provides a two-phase pulse circuit, including: a boost circuit, N groups of pulse modulation isolation transformer circuits, an amplitude limiting and current limiting circuit, a cascade circuit, a two-phase wave modulation circuit, and a main controller, wherein the boost circuit is electrically connected to the output end of the target DC power supply, and the boost circuit is used to perform pulse modulation and boost processing on the output DC voltage of the target DC power supply to obtain an initial pulse voltage signal; the output end of the boost circuit is electrically connected to the input end of each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits, and each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits respectively isolates, boosts and pulse modulates the initial pulse voltage signal to obtain a group of high-voltage pulse signals, wherein a group of high-voltage pulse signals includes N high-voltage pulse signals, and each group of pulse modulation isolation transformer The circuit outputs a high-voltage pulse signal accordingly, where N is a positive integer greater than or equal to 1; the output end of the N groups of pulse modulation isolation transformer circuits is electrically connected to the input end of the limiting and current limiting circuit, wherein the limiting and current limiting circuit is used to perform limiting and current limiting processing on the N high-voltage pulse signals respectively to obtain N high-voltage square wave pulse signals; the output end of the limiting and current limiting circuit is electrically connected to the input end of the cascade circuit, and the cascade circuit is used to perform cascade processing on the N high-voltage square wave pulse signals to obtain a target square wave pulse signal; the output end of the cascade circuit is electrically connected to the input end of the dual-phase wave modulation circuit, wherein the dual-phase wave modulation circuit is used to perform dual-phase modulation on the target square wave pulse signal to obtain a target dual-phase pulse signal; the main controller is electrically connected to the boost circuit, the N groups of pulse modulation isolation transformer circuits, the limiting and current limiting circuit and the dual-phase wave modulation circuit.

[0006] Optionally, the boost circuit includes: a first PWM controller, a boost transformer, a first MOS tube, a second MOS tube, a fuse, a first rectifier bridge, an energy storage capacitor group, a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a second diode, a first capacitor, and a second capacitor, wherein the first PWM controller is used to generate a first PWM control signal and a second PWM control signal, wherein the first PWM control signal is used to control the on and off of the first MOS tube, and the second PWM control signal is used to control the on and off of the second MOS tube, and the first PWM control signal and the second PWM control signal are both square wave signals of a first preset frequency, and the first PWM controller is electrically connected to the main controller; the drain of the first MOS tube is connected to the first end of the first winding of the primary side of the boost transformer, the second end of the first winding of the primary side of the boost transformer is electrically connected to the output end of the target DC power supply through the fuse, the gate of the first MOS tube is electrically connected to the first complementary output end of the first PWM controller through the first resistor, the source of the first MOS tube is connected to the first ground end, the gate of the first MOS tube is also connected to the first ground end through the second resistor, the first complementary output end of the first PWM controller is electrically connected to the negative pole of the first diode, and the first diode The positive electrode of the first PWM controller is electrically connected to the first ground terminal, wherein the first complementary output terminal of the first PWM controller is used to output the first PWM control signal; the drain of the second MOS tube is connected to the first end of the second winding of the primary side of the step-up transformer, the second end of the second winding of the primary side of the step-up transformer is electrically connected to the second end of the first winding of the primary side of the step-up transformer, the gate of the second MOS tube is electrically connected to the second complementary output terminal of the first PWM controller through the third resistor, the source of the second MOS tube is connected to the first ground terminal, the gate of the second MOS tube is also connected to the first ground terminal through the fourth resistor, and the second The complementary output terminal is electrically connected to the negative electrode of the second diode, and the positive electrode of the second diode is electrically connected to the first ground terminal, wherein the second complementary output terminal of the first PWM controller is used to output a second PWM control signal; the second end of the first winding of the primary side of the step-up transformer is electrically connected to the first ground terminal through the first capacitor, the first end of the secondary side of the step-up transformer is electrically connected to the first input terminal of the first rectifier bridge, the second end of the secondary side of the step-up transformer is electrically connected to the second input terminal of the first rectifier bridge through the second capacitor, the energy storage capacitor group is connected to the output terminal of the first rectifier bridge, and the output terminal of the first rectifier bridge is used to output an initial pulse voltage signal.

[0007] Optionally, the energy storage capacitor group includes: a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, wherein the third capacitor is a high-frequency electrolytic capacitor, and the fourth capacitor is a non-polar capacitor.

[0008] Optionally, the i-th group of pulse modulation isolation transformer circuits is any group of pulse modulation isolation transformer circuits among the N groups of pulse modulation isolation transformer circuits, and the i-th group of pulse modulation isolation transformer circuits includes: a second PWM controller, a first driver chip, a third MOS tube, a fourth MOS tube, an isolation transformer, a second rectifier bridge, a filter circuit, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein the second PWM controller is used to generate a third PWM control signal and a fourth PWM control signal, and the second PWM controller is electrically connected to the main controller; the first complementary output end of the second PWM controller and the second complementary output end of the second PWM controller are respectively electrically connected to the first input pin of the first driver chip and the second input pin of the first driver chip, the first output pin of the first driver chip and the second output pin of the first driver chip are respectively used to output a first drive control signal and a second drive control signal, wherein the first drive control signal is used to control the on and off of the third MOS tube, and the second drive control signal is used to control the on and off of the fourth MOS tube, the third PWM control signal and the fourth PWM control signal are both square wave signals of a second preset frequency, and the first complementary output end of the second PWM controller is electrically connected to the first input pin of the first driver chip and the second input pin of the first driver chip. The output end and the second complementary output end of the second PWM controller are used to output a third PWM control signal and a fourth PWM control signal respectively; the first output pin of the first driver chip is electrically connected to the gate of the third MOS tube through the fifth resistor, the gate of the third MOS tube is electrically connected to the first ground terminal through the sixth resistor, the source of the third MOS tube is electrically connected to the first ground terminal, and the drain of the third MOS tube is electrically connected to the first end of the primary side of the isolation transformer; the second output pin of the first driver chip is electrically connected to the gate of the fourth MOS tube through the seventh resistor, and the gate of the fourth MOS tube is electrically connected to the first ground terminal. The first ground terminal is electrically connected to the eighth resistor, the source of the fourth MOS tube is electrically connected to the first ground terminal, the drain of the fourth MOS tube is electrically connected to the second end of the primary side of the isolation transformer, and the primary side tap of the isolation transformer is used to input an initial pulse voltage signal; the secondary side of the isolation transformer is electrically connected to the input end of the second rectifier bridge, the output end of the second rectifier bridge is electrically connected to the input end of the filter circuit, and the output end of the filter circuit is used to output the i-th high-voltage pulse signal, wherein a group of high-voltage pulse signals includes the i-th high-voltage pulse signal, and i is a positive integer greater than or equal to 1 and less than or equal to N.

[0009] Optionally, the amplitude limiting and current limiting circuit includes: a bus isolation buffer, N voltage regulating and current limiting modules, wherein a group of communication buses is electrically connected to a group of bus input terminals corresponding to each of the N voltage regulating and current limiting modules through the bus isolation buffer; the high-voltage signal input terminal of the j-th voltage regulating and current limiting module among the N voltage regulating and current limiting modules is used to input the j-th high-voltage pulse signal, and the pulse output terminal of the j-th voltage regulating and current limiting module is used to output the j-th high-voltage square wave pulse signal, wherein the N high-voltage pulse signals include the j-th high-voltage pulse signal, and the N high-voltage square wave pulse signals include The jth high-voltage square wave pulse signal, the jth voltage regulating and current limiting module is any one of the N voltage regulating and current limiting modules, the jth voltage regulating and current limiting module is used to perform amplitude limiting and current limiting processing on the jth high-voltage pulse signal, j is a positive integer greater than or equal to 1 and less than or equal to N; the serial data output end of the jth voltage regulating and current limiting module is electrically connected to the serial data input end of the j+1th voltage regulating and current limiting module, and the serial data input end of the 1st voltage regulating and current limiting module is connected to the serial signal input bus in the target communication bus, and the target communication bus includes a group of communication buses.

[0010] Optionally, the j-th voltage regulation and current limiting module includes: a second driver chip, an LED array, an optocoupler array, a voltage regulator array, a third diode, a first voltage regulator diode, a second voltage regulator diode, a first insulated gate bipolar transistor, a first transistor, a ninth resistor, and a tenth resistor, wherein the second driver chip includes M output channels, the second driver chip is used to convert the serial input signal into M parallel switch signals, the LED array includes M LEDs, the optocoupler array includes M optocouplers, and the voltage regulator array includes M voltage regulator diodes, where M is a positive integer greater than 1; the k-th output channel corresponds to the k-th LED, a kth optocoupler and a kth Zener diode, wherein the kth output channel is any one of the M output channels, the M LEDs include the kth LED, the M optocouplers include the kth optocoupler, the M Zener diodes include the kth Zener diode, and k is a positive integer greater than or equal to 1 and less than or equal to M; the kth output channel is electrically connected to the cathode of the kth LED, the input end of the kth optocoupler is connected between the anode of the kth LED and the working power supply end, and the kth Zener diode is connected in parallel to the output end of the kth optocoupler; when k=1, the cathode of the first Zener diode is connected to the cathode of the first Zener diode; The cathodes of the three diodes are electrically connected, the anode of the third diode is electrically connected to the gate of the first insulated gate bipolar transistor, and the anode of the first Zener diode is electrically connected to the cathode of the second Zener diode; when k>1, the cathode of the kth Zener diode is electrically connected to the anode of the k-1th Zener diode, and the anode of the kth Zener diode is electrically connected to the cathode of the k+1th Zener diode; the anode of the Mth Zener diode is connected to the second ground terminal through the first Zener diode; the ninth resistor is connected between the gate of the first insulated gate bipolar transistor and the collector of the first insulated gate bipolar transistor, The anode of the second zener diode is electrically connected to the emitter of the first insulated gate bipolar transistor, the cathode of the second zener diode is electrically connected to the gate of the first insulated gate bipolar transistor, the collector of the first transistor is electrically connected to the gate of the first insulated gate bipolar transistor, the base of the first transistor is electrically connected to the emitter of the first insulated gate bipolar transistor, and the tenth resistor is connected between the base of the first transistor and the emitter of the first transistor; wherein, the collector of the first insulated gate bipolar transistor is used to input the jth high-voltage pulse signal, and the emitter of the first transistor is used to output the jth high-voltage square wave pulse signal.

[0011] Optionally, the dual-phase wave modulation circuit includes: a third PWM controller, a third drive chip, a first isolated gate driver, a second isolated gate driver, a third isolated gate driver, a fourth isolated gate driver, a first silicon carbide switch tube, a second silicon carbide switch tube, a third silicon carbide switch tube, a fourth silicon carbide switch tube, a duty cycle adjustment module, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein the main controller is electrically connected to the resistor pin of the oscillator of the third PWM controller through the duty cycle adjustment module, the third PWM controller is used to generate a fifth PWM control signal and a sixth PWM control signal, and the main controller adjusts the duty cycle of the fifth PWM control signal and the sixth PWM control signal through the duty cycle adjustment module. The first complementary output terminal of the third PWM controller and the second complementary output terminal of the third PWM controller are electrically connected to the first input pin of the third driver chip and the second input pin of the third driver chip respectively, and the first output pin of the third driver chip and the second output pin of the third driver chip are respectively used to output the third drive control signal and the fourth drive control signal, wherein the fifth PWM control signal and the sixth PWM control signal are both square wave signals with a preset duty cycle, the first complementary output terminal of the third PWM controller and the second complementary output terminal of the third PWM controller are respectively used to output the fifth PWM control signal and the sixth PWM control signal, and the third driver chip is a dual-channel gate driver chip for the fifth PWM control signal. The output of the control signal and the sixth PWM control signal is enabled and controlled; the first output pin of the third driver chip is electrically connected to the in-phase input terminal of the first isolated gate driver and the in-phase input terminal of the fourth isolated gate driver respectively, the inverting input terminal of the first isolated gate driver and the inverting input terminal of the fourth isolated gate driver are both grounded, the Miller clamp pin of the first isolated gate driver is electrically connected to the gate of the first silicon carbide switch tube, the gate output pin of the first isolated gate driver is electrically connected to the gate of the first silicon carbide switch tube through an eleventh resistor, the Miller clamp pin of the fourth isolated gate driver is electrically connected to the gate of the fourth silicon carbide switch tube, and the gate output pin of the fourth isolated gate driver is electrically connected to the gate of the fourth silicon carbide switch tube through a fourteenth resistor. The gate of the silicon switch tube is electrically connected; the second output pin of the third driver chip is electrically connected to the non-inverting input terminal of the second isolated gate driver and the non-inverting input terminal of the third isolated gate driver respectively, the inverting input terminal of the second isolated gate driver and the inverting input terminal of the third isolated gate driver are both grounded, the Miller clamp pin of the second isolated gate driver is electrically connected to the gate of the second silicon carbide switch tube, the gate output pin of the second isolated gate driver is electrically connected to the gate of the second silicon carbide switch tube through a twelfth resistor, the Miller clamp pin of the third isolated gate driver is electrically connected to the gate of the third silicon carbide switch tube, and the gate output pin of the third isolated gate driver is electrically connected to the gate of the third silicon carbide switch tube through a thirteenth resistor;The source of the first silicon carbide switch tube is electrically connected to the drain of the second silicon carbide switch tube, the source of the second silicon carbide switch tube is connected to the third ground terminal, the source of the third silicon carbide switch tube is electrically connected to the drain of the fourth silicon carbide switch tube, the source of the fourth silicon carbide switch tube is connected to the third ground terminal, and the drain of the first silicon carbide switch tube and the drain of the third silicon carbide switch tube are both used to input the target square wave pulse signal; the source of the first silicon carbide switch tube is used as the positive output terminal of the biphase pulse circuit to output the positive phase pulse signal, and the source of the third silicon carbide switch tube is used as the negative output terminal of the biphase pulse circuit to output the negative phase pulse signal, wherein the target biphase pulse signal includes a positive phase pulse signal and a negative phase pulse signal. ;

[0012] Optionally, the duty cycle adjustment module adopts one of the following adjustment methods: an adjustable potentiometer method; a digital potentiometer adjustment method; a digital switch array series resistance method.

[0013] Optionally, the dual-phase wave modulation circuit further includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a third Zener diode, a fourth Zener diode, a fifth Zener diode, and a sixth Zener diode, wherein the negative output power supply voltage pin of the first isolated gate driver is connected to the first power supply through the fifth capacitor and the fifteenth resistor, wherein the fifth capacitor and the fifteenth resistor are connected in series, and the negative output power supply voltage pin of the first isolated gate driver is also connected to the second ground terminal The positive electrode of the third zener diode is electrically connected to the negative output power supply voltage pin of the first isolated gate driver, the connection point of the fifth capacitor and the fifteenth resistor is electrically connected to the negative electrode of the third zener diode, the negative electrode of the third zener diode is also electrically connected to the source of the first silicon carbide switch tube, the positive output power supply voltage pin of the first isolated gate driver is electrically connected to the source of the first silicon carbide switch tube through the sixth capacitor, the sixteenth resistor is connected between the positive output power supply voltage pin of the first isolated gate driver and the first power supply, and the seventh capacitor is connected between the first power supply and the second ground terminal; the negative output power supply voltage pin of the second isolated gate driver is connected to the second power supply through the eighth capacitor and the seventeenth resistor, wherein the eighth capacitor and the seventeenth resistor are connected in series, The negative output power supply voltage pin of the second isolated gate driver is also connected to the second ground terminal, the anode of the fourth voltage regulator diode is electrically connected to the negative output power supply voltage pin of the second isolated gate driver, the connection point of the eighth capacitor and the seventeenth resistor is electrically connected to the negative electrode of the fourth voltage regulator diode, the negative electrode of the fourth voltage regulator diode is also electrically connected to the source electrode of the second silicon carbide switch tube, the positive output power supply voltage pin of the second isolated gate driver is electrically connected to the source electrode of the second silicon carbide switch tube through the ninth capacitor, the eighteenth resistor is connected between the positive output power supply voltage pin of the second isolated gate driver and the second power supply, the tenth capacitor is connected between the second power supply and the second ground terminal; the negative output power supply voltage pin of the third isolated gate driver is electrically connected to the negative output power supply voltage pin of the third isolated gate driver through the eleventh capacitor and the nineteenth resistor The eleventh capacitor and the nineteenth resistor are connected in series, the negative output power supply voltage pin of the third isolated gate driver is also connected to the second ground terminal, the anode of the fifth voltage regulator diode is electrically connected to the negative output power supply voltage pin of the third isolated gate driver, the connection point of the eleventh capacitor and the nineteenth resistor is electrically connected to the negative electrode of the fifth voltage regulator diode, the negative electrode of the fifth voltage regulator diode is also electrically connected to the source of the third silicon carbide switch tube, the positive output power supply voltage pin of the third isolated gate driver is electrically connected to the source of the third silicon carbide switch tube through the twelfth capacitor, the twentieth resistor is connected between the positive output power supply voltage pin of the third isolated gate driver and the third power supply, and the thirteenth capacitor is connected between the third power supply and the second ground terminal;The negative output power supply voltage pin of the fourth isolated gate driver is connected to the fourth power supply through the fourteenth capacitor and the twenty-first resistor, wherein the fourteenth capacitor and the twenty-first resistor are connected in series, the negative output power supply voltage pin of the fourth isolated gate driver is also connected to the second ground terminal, the anode of the sixth voltage zener diode is electrically connected to the negative output power supply voltage pin of the fourth isolated gate driver, the connection point of the fourteenth capacitor and the twenty-first resistor is electrically connected to the negative electrode of the sixth voltage zener diode, the negative electrode of the sixth voltage zener diode is also electrically connected to the source of the fourth silicon carbide switch tube, the positive output power supply voltage pin of the fourth isolated gate driver is electrically connected to the source of the fourth silicon carbide switch tube through the fifteenth capacitor, the twenty-second resistor is connected between the positive output power supply voltage pin of the fourth isolated gate driver and the fourth power supply, and the sixteenth capacitor is connected between the fourth power supply and the second ground terminal. ;

[0014] In a second aspect, the present application also provides a high-frequency pulse therapeutic device, comprising the biphasic pulse circuit described in any of the preceding items.

[0015] In summary, one or more technical solutions provided by the present application have at least the following technical effects or advantages: 1) Through the isolation transformer circuit, the stability and safety of the system are improved, and through the limiting and current limiting circuit, the high-voltage pulse signal can be effectively limited and current limited to protect the circuit and equipment to ensure that it operates within a safe range; 2) Each group of pulse modulation isolation transformer circuits can be controlled individually, and each voltage regulation and current limiting module is also individually controllable, avoiding the problem that the two-phase pulse circuit in the related technology cannot involve the limiting circuit; 3) Through the cooperation of the duty cycle adjustment module and the PWM controller, the duty cycle of the two-phase pulse signal is accurately adjusted, which improves the flexibility and adaptability of the circuit; 4) The SiC control chip provides a negative voltage drive circuit to ensure that the silicon carbide switch tube can quickly reach the required negative pressure level when it is turned off, thereby speeding up the shutdown speed and reducing energy loss during the switching process; and providing a fast discharge path during fast shutdown. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a framework diagram of a biphasic pulse circuit provided in an embodiment of the present application; Figure 2 It is a schematic diagram of a boost circuit provided in an embodiment of the present application; Figure 3 It is a schematic diagram of a pulse modulation isolation transformer circuit provided in an embodiment of the present application; Figure 4 This is a schematic diagram of an amplitude limiting and current limiting circuit provided in an embodiment of the present application; Figure 5 It is a schematic diagram of a single voltage regulating and current limiting module provided in an embodiment of the present application; Figure 6It is a schematic diagram of a dual-phase wave modulation circuit provided in an embodiment of the present application; Figure 7 It is a principle block diagram of a high-voltage biphasic pulse generating circuit provided in an embodiment of the present application; Figure 8 It is a principle block diagram of an amplitude limiting and current limiting circuit provided in an embodiment of the present application; Fig. 9 It is a principle block diagram of a pulse width modulation circuit provided in an embodiment of the present application; Fig.10 This is an example diagram of a high-voltage square wave pulse provided in an embodiment of the present application; Fig.11 This is an example diagram of a modulated biphasic pulse wave provided in an embodiment of the present application; Fig.12 This is a set of example diagrams of biphasic pulse wave waveforms provided in an embodiment of the present application.

[0017] Description of reference numerals: The first resistor-R1, the second resistor-R2, the third resistor-R3, the fourth resistor-R4, the fifth resistor-R5, the sixth resistor-R6, the seventh resistor-R7, the eighth resistor-R8, the ninth resistor-R9, the tenth resistor-R10, the eleventh resistor-R11, the twelfth resistor-R12, the thirteenth resistor-R13, the fourteenth resistor-R14, the fifteenth resistor-R15, the sixteenth resistor-R16, the seventeenth resistor-R17, the eighteenth resistor-R18, the nineteenth resistor-R19, the twentieth resistor-R20, the twentieth resistor-R21, The first resistor R21, the twenty-second resistor R22, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the fourteenth capacitor C14, the fifteenth capacitor C15, the sixteenth capacitor C16, the first Zener diode ZD1, the second Zener diode ZD2, the The third Zener diode - ZD3, the fourth Zener diode - ZD4, the fifth Zener diode - ZD5, the sixth Zener diode - ZD6, the first PWM controller - U1, the second PWM controller - U2, the third PWM controller - U3, the first driver chip - IC1, the second driver chip - IC2, the third driver chip - IC3, the first isolated gate driver - GD1, the second isolated gate driver - GD2, the third isolated gate driver - GD3, the fourth isolated gate driver - GD4, the first silicon carbide switch tube - V1, the Second silicon carbide switch tube - V2, third silicon carbide switch tube - V3, fourth silicon carbide switch tube - V4, first triode - B1, first insulated gate bipolar transistor - IGBT1, first diode - D1, second diode - D2, third diode - D3, first MOS tube - Q1, second MOS tube - Q2, third MOS tube - Q3, fourth MOS tube - Q4, first rectifier bridge - BR1, second rectifier bridge - BR2, fuse - F1, step-up transformer - T1, isolation transformer - T2, bus isolation buffer - IB1. DETAILED DESCRIPTION

[0018] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0019] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0020] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0021] The present application provides a biphasic pulse circuit, referring to Figure 1 , Figure 1 It is a framework diagram of a two-phase pulse circuit provided in an embodiment of the present application, including: a boost circuit, N groups of pulse modulation isolation transformer circuits, a limiting current limiting circuit, a cascade circuit, a two-phase wave modulation circuit, and a main controller, wherein the boost circuit is electrically connected to the output end of the target DC power supply, and the boost circuit is used to perform pulse modulation and boost processing on the output DC voltage of the target DC power supply to obtain an initial pulse voltage signal; the output end of the boost circuit is electrically connected to the input end of each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits, and each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits performs isolation boost and pulse modulation processing on the initial pulse voltage signal respectively to obtain a group of high-voltage pulse signals, wherein a group of high-voltage pulse signals includes N high-voltage pulse signals, and each group of pulse modulation isolation transformer circuits The transformer circuit outputs a high-voltage pulse signal correspondingly, where N is a positive integer greater than or equal to 1; the output end of the N groups of pulse modulation isolation transformer circuits is electrically connected to the input end of the limiting and current limiting circuit, wherein the limiting and current limiting circuit is used to perform limiting and current limiting processing on the N high-voltage pulse signals respectively to obtain N high-voltage square wave pulse signals; the output end of the limiting and current limiting circuit is electrically connected to the input end of the cascade circuit, and the cascade circuit is used to perform cascade processing on the N high-voltage square wave pulse signals to obtain a target square wave pulse signal; the output end of the cascade circuit is electrically connected to the input end of the dual-phase wave modulation circuit, wherein the dual-phase wave modulation circuit is used to perform dual-phase modulation on the target square wave pulse signal to obtain a target dual-phase pulse signal; the main controller is electrically connected to the boost circuit, the N groups of pulse modulation isolation transformer circuits, the limiting and current limiting circuit and the dual-phase wave modulation circuit.

[0022] In the above embodiments, the output voltage of the DC power supply can be effectively modulated and boosted by the boost circuit to provide the required initial pulse voltage signal; each group of pulse signals can be modulated and boosted independently by N groups of pulse modulation isolation transformer circuits, and the independence of each group of pulse signals can be ensured by the pulse modulation isolation transformer circuit to avoid mutual interference, improve the stability and safety of the system, and reduce the risk of electrical accidents; the high-voltage pulse signal can be effectively limited and current-limited by the limiting and current-limiting circuit to protect the circuit and equipment and ensure that it works within a safe range; the directly output high-voltage pulse signal may damage the subsequent circuit or equipment due to excessive amplitude or unstable current. The introduction of the limiting and current-limiting circuit ensures that the amplitude and current of each high-voltage pulse signal are within a safe and controllable range, protecting the stable operation of the entire system, and the limiting and current-limiting circuit ensures that the amplitude and current of the high-voltage pulse signal are within a reasonable range, improving the quality of the signal and protecting the safety of subsequent circuits and equipment; a single pulse signal is often difficult to meet the needs of complex application scenarios. Through the cascade circuit and the two-phase wave modulation circuit, the circuit realizes the integration and two-phase modulation of multiple high-voltage pulse signals, and can modulate the square wave pulse signal into the target two-phase pulse signal to meet the needs of specific applications, greatly increasing the diversity and flexibility of the output signal. The output voltage of the original DC power supply can be roughly adjusted through the boost circuit, and a more suitable initial pulse voltage signal can be provided. For example, the output voltage of the DC power supply is 0-36V. Taking 24V as an example, the amplitude of the initial pulse voltage signal obtained after the boost circuit is 60-300V. Taking 300V as an example, the initial pulse voltage signal is isolated, boosted and pulse modulated by N groups of pulse modulation isolation transformer circuits to obtain a group of high-voltage pulse signals, that is, N high-voltage pulse signals. For example, the voltage amplitude of each high-voltage pulse signal is 1200V (or other values), and then the N high-voltage pulse signals are respectively limited and current-limited by the limiting and current-limiting circuit to obtain N high-voltage square wave pulse signals. For example, after the limiting and current-limiting processing The high-voltage square wave pulse signal can be a square wave pulse signal of 200V-1100V, which can be flexibly adjusted to obtain the required square wave pulse voltage signal, avoiding the problem of unadjustable voltage of the two-phase pulse signal in the related technology. For example, the related technology may only obtain a fixed 1200V square wave pulse signal; because 1200V may not meet the needs of high-voltage pulses in some applications, N high-voltage square wave signals can also be cascaded to obtain the target square wave pulse signal, that is, to obtain a higher voltage pulse signal, for example, a 3300V (or 5000V, or other) high-voltage pulse signal can be obtained; then, the target square wave pulse signal is bi-phase modulated to obtain a target bi-phase pulse signal, that is, an isolated high-voltage bi-phase pulse signal.

[0023] In an optional embodiment, if Figure 2 As shown, the boost circuit includes: a first PWM controller U1, a boost transformer T1, a first MOS tube Q1, a second MOS tube Q2, a fuse F1, a first rectifier bridge BR1, an energy storage capacitor group, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2, wherein the first PWM controller U1 is used to generate a first PWM control signal and a second PWM control signal, wherein the first PWM control signal is used to control the on and off of the first MOS tube Q1, and the second PWM control signal is used to control the on and off of the second MOS tube Q2, and the first PWM control signal and the second PWM control signal are both The first PWM controller U1 is electrically connected to the main controller; the drain of the first MOS tube Q1 is connected to the first end of the first winding of the primary side of the step-up transformer T1, the second end of the first winding of the primary side of the step-up transformer T1 is electrically connected to the output end of the target DC power supply through the fuse F1, the gate of the first MOS tube Q1 is electrically connected to the first complementary output end of the first PWM controller U1 through the first resistor R1, the source of the first MOS tube Q1 is connected to the first ground end, the gate of the first MOS tube Q1 is also connected to the first ground end through the second resistor R2, the first complementary output end of the first PWM controller U1 is electrically connected to the cathode of the first diode D1, and the first The anode of the diode D1 is electrically connected to the first ground terminal, wherein the first complementary output terminal of the first PWM controller U1 is used to output the first PWM control signal; the drain of the second MOS tube Q2 is connected to the first end of the second winding of the primary side of the boost transformer T1, the second end of the second winding of the primary side of the boost transformer T1 is electrically connected to the second end of the first winding of the primary side of the boost transformer T1, the gate of the second MOS tube Q2 is electrically connected to the second complementary output terminal of the first PWM controller U1 through the third resistor R3, the source of the second MOS tube Q2 is connected to the first ground terminal, the gate of the second MOS tube Q2 is also connected to the first ground terminal through the fourth resistor R4, and the second The complementary output terminal is electrically connected to the negative electrode of the second diode D2, and the positive electrode of the second diode D2 is electrically connected to the first ground terminal, wherein the second complementary output terminal of the first PWM controller U1 is used to output a second PWM control signal; the second end of the first winding of the primary side of the boost transformer T1 is electrically connected to the first ground terminal through the first capacitor C1, the first end of the secondary side of the boost transformer T1 is electrically connected to the first input terminal of the first rectifier bridge BR1, the second end of the secondary side of the boost transformer T1 is electrically connected to the second input terminal of the first rectifier bridge BR1 through the second capacitor C2, the energy storage capacitor group is connected to the output terminal of the first rectifier bridge BR1, and the output terminal of the first rectifier bridge BR1 is used to output an initial pulse voltage signal.

[0024] In the above embodiment, the first PWM controller U1 outputs a push-pull control signal to control the switching of the first MOS transistor Q1 and the second MOS transistor Q2, thereby controlling the output voltage of the step-up transformer T1. The step-up transformer T1 performs a first step-up conversion on the output voltage of the output end of the target DC power supply, and then performs rectification processing through the first rectifier bridge BR1 to obtain an initial pulse voltage signal. It should be noted that the first step-up conversion is a coarse adjustment of the DC voltage output by the original target DC power supply, and the obtained initial pulse voltage signal is not a flat square wave. For example, the DC voltage output by the target DC power supply is 24V (or other values), and the voltage amplitude of the initial pulse voltage signal can be 60-300V. The above-mentioned first preset frequency can be 100kHz (or other frequencies). Energy storage is performed by connecting an energy storage capacitor group in parallel to the output end of the first rectifier bridge BR1. Because the instantaneous output power of the high-voltage end is very large and the duration is short, energy storage needs to be provided. Through precise PWM control and optimized circuit design, the boost circuit can efficiently increase the voltage of the target DC power supply to the required level and output a stable initial pulse voltage signal; the setting of components such as fuse F1 and diode effectively prevents damage to the circuit due to abnormal conditions such as overcurrent and overvoltage, thereby improving the reliability and safety of the circuit. Optionally, the input end of the first PWM controller U1 can adjust the output first PWM control signal and second PWM control signal through a DAC and a comparator, such as Figure 2 As shown, the input terminals of the DAC and the comparator can be connected to the feedback signal VREF. For example, two voltage-dividing resistors are set at the output terminal of the boost circuit to feed back the output voltage. The output first PWM control signal and the second PWM control signal are adjusted by the comparator to adjust the output voltage (such as Figure 2 VS in the figure), the main controller can be a single-chip microcomputer. For example, the single-chip microcomputer outputs a 0-5V voltage regulation signal through a DAC and compares it with the sampled feedback signal to control the output voltage. That is, the main controller adjusts the switching frequency of the first PWM controller through the DAC and the comparator circuit and then adjusts the output voltage of the secondary of the first MOS tube Q1 and the second MOS tube Q2 to control the boost transformer T1, so as to achieve coarse adjustment of the output pulse voltage. Figure 2 The commonly used peripheral configuration circuits of the first PWM controller U1 are also included, which will not be described in detail here.

[0025] In an optional embodiment, if Figure 2 As shown, the energy storage capacitor group includes: a third capacitor C3 and a fourth capacitor C4, the third capacitor C3 and the fourth capacitor C4 are connected in parallel, wherein the third capacitor C3 is a high-frequency electrolytic capacitor, and the fourth capacitor C4 is a non-polar capacitor.

[0026] In the above embodiment, the third capacitor C3 can be a large-capacity high-frequency low-impedance capacitor, and the fourth capacitor C4 can be a small-capacity chip ceramic capacitor, that is, the low-voltage direct current (such as 24V) is converted into a higher voltage (60-300V) direct current through the boosting process of the boost transformer T1 and the rectification process of the first rectifier bridge BR1, and then stored in the energy storage capacitor group. In the pulse circuit, an effective energy storage and rapid release mechanism is required to support the generation and transmission of the pulse signal. By connecting the high-frequency electrolytic capacitor (the third capacitor C3) and the non-polar capacitor (the fourth capacitor C4) in parallel, a more stable voltage support can be provided, and the impact of voltage fluctuations on the circuit can be reduced. The energy storage capacitor group can better adapt to the needs of high-frequency pulse signals and improve the frequency response and stability of the circuit. High-frequency electrolytic capacitors have better performance in the high-frequency band. The use of non-polar capacitors can reduce electromagnetic interference in the circuit and improve the overall performance and stability of the circuit, while non-polar capacitors can remain stable in a wider frequency range. By combining the use of high-frequency electrolytic capacitors and non-polar capacitors, the advantages of both can be combined to extend the overall life of the energy storage capacitor group and improve the reliability of the circuit. By using a combination of multiple capacitors, we can meet the circuit performance requirements while optimizing the selection based on the cost characteristics of various capacitors, thereby reducing the overall cost. This combination method enables the energy storage capacitor bank to achieve a better balance between performance, life, reliability and cost.

[0027] In an optional embodiment, if Figure 3As shown, the i-th group of pulse modulation isolation transformer circuits is any group of pulse modulation isolation transformer circuits among the N groups of pulse modulation isolation transformer circuits, and the i-th group of pulse modulation isolation transformer circuits includes: a second PWM controller U2, a first driving chip IC1, a third MOS tube Q3, a fourth MOS tube Q4, an isolation transformer T2, a second rectifier bridge BR2, a filter circuit, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, wherein the second PWM controller U2 is used to generate a third PWM control signal and a fourth PWM control signal, and the second PWM controller U2 is electrically connected to the main controller; the second PWM controller U2 The first complementary output terminal and the second complementary output terminal of the second PWM controller U2 are electrically connected to the first input pin of the first driver chip IC1 and the second input pin of the first driver chip IC1, respectively. The first output pin of the first driver chip IC1 and the second output pin of the first driver chip IC1 are respectively used to output the first drive control signal and the second drive control signal, wherein the first drive control signal is used to control the on and off of the third MOS tube Q3, and the second drive control signal is used to control the on and off of the fourth MOS tube Q4. The third PWM control signal and the fourth PWM control signal are both square wave signals of the second preset frequency. The first output pin of the first driver chip IC1 and the second output pin of the first driver chip IC1 are respectively used to output the first drive control signal and the second drive control signal. A complementary output terminal and a second complementary output terminal of the second PWM controller U2 are used to output a third PWM control signal and a fourth PWM control signal respectively; a first output pin of the first driver chip IC1 is electrically connected to the gate of the third MOS tube Q3 through a fifth resistor R5, the gate of the third MOS tube Q3 is electrically connected to the first ground terminal through a sixth resistor R6, the source of the third MOS tube Q3 is electrically connected to the first ground terminal, and the drain of the third MOS tube Q3 is electrically connected to the first end of the primary side of the isolation transformer T2; a second output pin of the first driver chip IC1 is electrically connected to the gate of the fourth MOS tube Q4 through a seventh resistor R7, and the fourth MO The gate of the S tube Q4 is electrically connected to the first ground terminal through the eighth resistor R8, the source of the fourth MOS tube is electrically connected to the first ground terminal, the drain of the fourth MOS tube is electrically connected to the second end of the primary side of the isolation transformer T2, and the primary side tap of the isolation transformer T2 is used to input the initial pulse voltage signal; the secondary side of the isolation transformer T2 is electrically connected to the input end of the second rectifier bridge BR2, the output end of the second rectifier bridge BR2 is electrically connected to the input end of the filter circuit, and the output end of the filter circuit is used to output the i-th high-voltage pulse signal, wherein a group of high-voltage pulse signals includes the i-th high-voltage pulse signal, and i is a positive integer greater than or equal to 1 and less than or equal to N.

[0028] In the above embodiment, the initial pulse voltage signal is isolated, boosted and pulse modulated by N groups of pulse modulation isolation transformer circuits to obtain N high-voltage pulse signals. For each group of pulse modulation isolation transformer circuits, the second PWM controller U2 is used to generate a third PWM control signal and a fourth PWM control signal. The first driver chip IC1 is used to buffer the third PWM control signal and the fourth PWM control signal. After the buffering process of the first driver chip IC1, the third MOS tube Q3 and the fourth MOS tube Q4 are switched. In practical applications, the first driver chip IC1 can also be omitted. The second PWM controller U2 is used to output a push-pull control signal to switch the third MOS tube Q3 and the fourth MOS tube Q4. After the boosting process of the isolation transformer T2, the rectification process of the second rectifier bridge BR2 and the filtering process of the filtering circuit, a relatively smooth high-voltage pulse signal is obtained. Each group of pulse modulation isolation transformer circuits outputs a corresponding high-voltage pulse signal. For example, the transformation ratio of the isolation transformer T2 is 1:4. Assuming that the output voltage of the aforementioned boost circuit is 300V, the isolation transformer T2 can output a high-voltage pulse of 1200V. By introducing the isolation transformer T2, electrical isolation between the primary and secondary sides is achieved, which effectively prevents problems such as high-voltage crosstalk and ground potential difference, and improves the safety and reliability of the circuit; the third and fourth PWM control signals are generated by the second PWM controller U2, and the MOS tube is precisely controlled by the first driver chip IC1, so as to achieve precise modulation of the high-voltage pulse signal. This control method enables the waveform, frequency and amplitude of the pulse signal to be flexibly adjusted as needed; through reasonable circuit design, such as using a filter circuit to smooth the pulse signal, signal distortion, noise and jitter are reduced. At the same time, the use of the isolation transformer T2 also helps to improve the stability and reliability of the signal. Each group of pulse modulation isolation transformer circuits can output pulse signals of different voltages because each group can be controlled separately. The pulse modulation isolation transformer circuit in this embodiment can be used as an independent module and reused in a two-phase pulse circuit (i.e., N groups of circuits). This modular design not only simplifies the circuit design, but also improves the scalability and maintainability of the circuit. Figure 3 The second PWM controller U2 and the first driving chip IC1 also include the commonly used peripheral configuration circuits, which will not be described in detail here.

[0029] In an optional embodiment, if Figure 4As shown, the amplitude limiting and current limiting circuit includes: a bus isolation buffer IB1, N voltage regulating and current limiting modules, wherein a group of communication buses is electrically connected to a group of bus input terminals corresponding to each of the N voltage regulating and current limiting modules through the bus isolation buffer IB1; the high-voltage signal input terminal of the j-th voltage regulating and current limiting module among the N voltage regulating and current limiting modules is used to input the j-th high-voltage pulse signal, and the pulse output terminal of the j-th voltage regulating and current limiting module is used to output the j-th high-voltage square wave pulse signal, wherein the N high-voltage pulse signals include the j-th high-voltage pulse signal, the N high-voltage square wave pulse signal The signal includes the jth high-voltage square wave pulse signal, the jth voltage regulating and current limiting module is any one of the N voltage regulating and current limiting modules, the jth voltage regulating and current limiting module is used to limit the amplitude and current of the jth high-voltage pulse signal, j is a positive integer greater than or equal to 1 and less than or equal to N; the serial data output end of the jth voltage regulating and current limiting module is electrically connected to the serial data input end of the j+1th voltage regulating and current limiting module, the serial data input end of the 1st voltage regulating and current limiting module is connected to the serial signal input bus in the target communication bus, and the target communication bus includes a group of communication buses.

[0030] In the above embodiment, the high-voltage pulse signal is preprocessed by the voltage regulating and current limiting module to ensure the stability and safety of the signal during transmission. The signal on the communication bus often needs to be isolated from other systems or modules to prevent mutual interference and damage. The use of the bus isolation buffer IB1 realizes the effective isolation of the signal and protects the subsequent circuit from abnormal conditions such as bus voltage fluctuations and short circuits. The bus isolation buffer is equivalent to a serial controller, such as an SPI serial controller. A set of serial buses includes BUS_SDI, BUS_CLK, BUS_LE and BUS_OE, where SDI is the serial data input, Figure 4 Each voltage regulating and current limiting module is an isolated current limiting circuit regulated by serial communication. Figure 4HV1~HVn represents the aforementioned high-voltage pulse signal, PULSE1~PULSEn represents the high-voltage square wave pulse signal obtained by current limiting and amplitude limiting adjustment. Optionally, two or more high-voltage square wave pulse signals can be selected for cascading to obtain the target square wave pulse signal. By designing N voltage regulating and current limiting modules and connecting different high-voltage pulse signal sources as needed, the circuit has high flexibility and scalability, and can adapt to the high-voltage pulse processing requirements in different application scenarios. The data synchronization and transmission between the voltage regulating and current limiting modules are realized through the serial data interface, which improves the integration and control accuracy of the entire circuit, and enables the circuit to respond to external commands and control signals more accurately. The dual protection of the bus isolation buffer and the voltage regulating and current limiting module effectively prevents mutual interference between signals and damage to circuit components, and enhances the stability and safety of the entire system. The modular design allows the system to flexibly configure the number and type of voltage regulating and current limiting modules according to actual needs to meet the high-voltage pulse processing requirements in different application scenarios. The data synchronization and transmission between the modules are realized through the serial data interface, which simplifies the system control logic and improves the response speed and control accuracy of the system.

[0031] In an optional embodiment, if Figure 5As shown, the j-th voltage regulating and current limiting module includes: a second driver chip IC2, an LED array, an optocoupler array, a voltage regulator array, a third diode D3, a first voltage regulator diode ZD1, a second voltage regulator diode ZD2, a first insulated gate bipolar transistor IGBT1, a first transistor B1, a ninth resistor R9, and a tenth resistor R10, wherein the second driver chip IC2 includes M output channels, the second driver chip IC2 is used to convert a serial input signal into a parallel M-way switch signal, the LED array includes M LEDs, the optocoupler array includes M optocouplers, and the voltage regulator array includes M voltage regulator diodes, where M is a positive integer greater than 1; the k-th output channel corresponds to the k-th LED, a kth optocoupler and a kth Zener diode, wherein the kth output channel is any output channel of the M output channels, the M LEDs include the kth LED, the M optocouplers include the kth optocoupler, the M Zener diodes include the kth Zener diode, and k is a positive integer greater than or equal to 1 and less than or equal to M; the kth output channel is electrically connected to the cathode of the kth LED, the input end of the kth optocoupler is connected between the anode of the kth LED and the working power supply end, and the kth Zener diode is connected in parallel to the output end of the kth optocoupler; when k=1, the cathode of the first Zener diode is electrically connected to the cathode of the third diode D3, and the third diode D The positive electrode of the kth Zener diode is electrically connected to the positive electrode of the k-1th Zener diode, and the positive electrode of the kth Zener diode is electrically connected to the negative electrode of the k+1th Zener diode; the positive electrode of the Mth Zener diode is connected to the second ground terminal through the first Zener diode ZD1; the ninth resistor R9 is connected between the gate of the first insulated gate bipolar transistor IGBT1 and the collector of the first insulated gate bipolar transistor IGBT1, and the positive electrode of the second Zener diode ZD2 is electrically connected to the negative electrode of the first insulated gate bipolar transistor IGBT1. The emitter of the first insulated gate bipolar transistor IGBT1 is electrically connected, the cathode of the second zener diode ZD2 is electrically connected to the gate of the first insulated gate bipolar transistor IGBT1, the collector of the first triode B1 is electrically connected to the gate of the first insulated gate bipolar transistor IGBT1, the base of the first triode B1 is electrically connected to the emitter of the first insulated gate bipolar transistor IGBT1, and the tenth resistor R10 is connected between the base of the first triode B1 and the emitter of the first triode B1; wherein, the collector of the first insulated gate bipolar transistor IGBT1 is used to input the jth high-voltage pulse signal, and the emitter of the first triode B1 is used to output the jth high-voltage square wave pulse signal.

[0032] In the above embodiment, the second driver chip IC2 is a serial-to-parallel driver chip, for example, the serial input signal is converted into a parallel M-way switch signal, which is used to control the M-way LEDs in the LED array, and then control the corresponding optocoupler to be turned on or off, and then control whether the corresponding voltage-regulating diode is short-circuited, so as to limit the aforementioned high-voltage pulse signal, that is, by converting the SPI serial signal into a parallel LED switch signal, and by turning on the optocoupler to short-circuit the corresponding voltage-regulating diode, the purpose of voltage regulation (or limiting) is achieved. After the high-voltage pulse signal is stabilized by the first insulated gate bipolar transistor IGBT1 and the second voltage-regulating diode ZD2, it is limited by the current limiting circuit composed of the first transistor B1 and the tenth resistor R10 to obtain a high-voltage square wave pulse signal. Each voltage regulating and current limiting module is also controlled separately, that is, each voltage regulating and current limiting module can output a high-voltage square wave pulse signal of different voltages. However, the two-phase pulse circuit in the related art cannot be designed with a limiting circuit. In the embodiment of the present application, the jth voltage regulating and current limiting module is taken as an example. In fact, each voltage regulating and current limiting module is limited and processed in a similar way. Figure 5 As shown, the second driver chip IC2 converts the serial input signal into 8 parallel switch signals, for example, Figure 5 The voltage regulator of the Zener diode connected in parallel to each optocoupler output terminal is 100V. As long as one Zener diode is short-circuited, the output voltage of the limiting circuit will decrease by 100V, and the voltage regulator of ZD1 is 200V. Therefore, Figure 5 The limiting circuit can achieve the purpose of outputting a voltage of 200-1100V. The second driver chip IC2 converts the serial input signal into a parallel M-way switch signal to achieve multi-way precise control of the high-voltage pulse signal. The combination of the LED array, the optocoupler array and the Zener diode array realizes the electrical isolation and protection of the high-voltage pulse signal. As non-contact switching elements, LED and optocoupler can effectively isolate the high-voltage signal from the low-voltage control signal to prevent the high-voltage pulse from damaging the control circuit. The Zener diode is used to limit the voltage and protect the subsequent circuit from overvoltage shock. Through the series connection of the Zener diode array, a multi-stage voltage clamping structure is formed, which can step down and stabilize the high-voltage pulse signal step by step. This design helps to reduce the fluctuation range of the high-voltage pulse signal and improve the stability and reliability of the signal. The insulated gate bipolar transistor (IGBT) is used as the main switching element, combined with the drive circuit composed of the first transistor B1, to achieve fast response and efficient conversion of the high-voltage pulse signal. IGBT has the advantages of fast switching speed and large carrying current, which can meet the high-performance requirements of the high-voltage pulse circuit for the switching element. Figure 5 The figure also includes some peripheral configuration circuits commonly used by the second driver chip IC2, which will not be described in detail here.

[0033] In an optional embodiment, if Figure 6As shown, the dual-phase wave modulation circuit includes: a third PWM controller U3, a third driving chip IC3, a first isolated gate driver GD1, a second isolated gate driver GD2, a third isolated gate driver GD3, a fourth isolated gate driver GD4, a first silicon carbide switch tube V1, a second silicon carbide switch tube V2, a third silicon carbide switch tube V3, a fourth silicon carbide switch tube V4, a duty cycle adjustment module, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14, wherein the main controller is electrically connected to the resistor pin of the oscillator of the third PWM controller U3 through the duty cycle adjustment module. The third PWM controller U3 is electrically connected to the first input pin of the third driver chip IC3 and the second input pin of the third driver chip IC3 respectively. The first output pin of the third driver chip IC3 and the second output pin of the third driver chip IC3 are electrically connected to the fifth PWM control signal and the sixth PWM control signal respectively. The third PWM controller U3 is used to generate the fifth PWM control signal and the sixth PWM control signal. The main controller adjusts the duty cycle of the fifth PWM control signal and the sixth PWM control signal through the duty cycle adjustment module. The first complementary output terminal of the third PWM controller U3 and the second complementary output terminal of the third PWM controller U3 are electrically connected to the first input pin of the third driver chip IC3 and the second input pin of the third driver chip IC3 respectively. The first output pin of the third driver chip IC3 and the second output pin of the third driver chip IC3 are electrically connected to the third drive control signal and the fourth drive control signal respectively. The fifth PWM control signal and the sixth PWM control signal are both square wave signals with a preset duty cycle. The first complementary output terminal of the third PWM controller U3 and the second complementary output terminal of the third PWM controller U3 are electrically connected to the first in-phase input terminal of the first isolated gate driver GD1 and the fourth in-phase input terminal of the fourth isolated gate driver GD4 respectively. The inverting input terminal of the first isolated gate driver GD1 and the inverting input terminal of the fourth isolated gate driver GD4 are both grounded, the Miller clamp pin of the first isolated gate driver is electrically connected to the gate of the first silicon carbide switch tube, the gate output pin of the first isolated gate driver GD1 is electrically connected to the gate of the first silicon carbide switch tube V1 through the eleventh resistor R11, the Miller clamp pin of the fourth isolated gate driver GD4 is electrically connected to the gate of the fourth silicon carbide switch tube V4, and the gate output pin of the fourth isolated gate driver GD4 is electrically connected to the gate of the fourth silicon carbide switch tube V4 through the fourteenth resistor R14;The second output pin of the third driver chip IC3 is electrically connected to the non-inverting input terminal of the second isolated gate driver GD2 and the non-inverting input terminal of the third isolated gate driver GD3 respectively, the inverting input terminal of the second isolated gate driver GD2 and the inverting input terminal of the third isolated gate driver GD3 are both grounded, the Miller clamp pin of the second isolated gate driver GD2 is electrically connected to the gate of the second silicon carbide switch tube V2, the gate output pin of the second isolated gate driver GD2 is electrically connected to the gate of the second silicon carbide switch tube V2 through a twelfth resistor R12, the Miller clamp pin of the third isolated gate driver GD3 is electrically connected to the gate of the third silicon carbide switch tube V3, and the gate output pin of the third isolated gate driver GD3 is electrically connected to the gate of the third silicon carbide switch tube V3 through a thirteenth resistor R13. The gate of the first silicon carbide switch tube V1 is electrically connected to the drain of the second silicon carbide switch tube V2, the source of the second silicon carbide switch tube V2 is connected to the third ground terminal, the source of the third silicon carbide switch tube V3 is electrically connected to the drain of the fourth silicon carbide switch tube V4, the source of the fourth silicon carbide switch tube V4 is connected to the third ground terminal, the drain of the first silicon carbide switch tube V1 and the drain of the third silicon carbide switch tube V3 are both used to input the target square wave pulse signal; the source of the first silicon carbide switch tube V1 is used as the positive output terminal of the two-phase pulse circuit to output the positive phase pulse signal, and the source of the third silicon carbide switch tube V3 is used as the negative output terminal of the two-phase pulse circuit to output the negative phase pulse signal, wherein the target two-phase pulse signal includes a positive phase pulse signal and a negative phase pulse signal. ;

[0034] In the above embodiment, the main controller adjusts the duty cycle of the fifth PWM control signal and the sixth PWM control signal output by the third PWM controller U3 through the duty cycle adjustment module, so that the fifth PWM control signal and the sixth PWM control signal are both square wave signals with a preset duty cycle, that is, the two-phase wave modulation circuit includes a pulse width adjustment circuit, and the switching frequency is adjustable, for example, 500ns-1us. Through the cooperation of the duty cycle adjustment module and the third PWM controller U3, the duty cycle of the two-phase pulse signal is accurately adjusted, thereby improving the flexibility and adaptability of the circuit; the third driver chip IC3 is a dual-channel gate driver chip, and each channel has an enable function for enabling and controlling the output of the fifth PWM control signal and the sixth PWM control signal. For example, the OUTB signal can be selectively cut off, and only half of the bridge arm can be opened, converting the two-phase wave function into a single-phase pulse output, which is controlled by the first silicon carbide switch tube V1, the second silicon carbide switch tube V2, and the third silicon carbide switch tube. V3 and the fourth silicon carbide switch tube V4 form a full-bridge circuit, that is, the input target square wave pulse signal is inverted into a two-phase pulse wave through a silicon carbide (or SiC) full bridge. In the embodiment of the present application, each of the above-mentioned silicon carbide switch tubes adopts a silicon carbide switch tube with a withstand voltage of more than 3300V, and the switching speed is fast, which can reach tens of nanoseconds. The high-speed switching capability and low on-resistance of the silicon carbide switch tube reduce the switching loss and conduction loss of the circuit, and improve the efficiency of the circuit; the first isolated gate driver GD1, the second isolated gate driver GD2, the third isolated gate driver GD3 and the fourth isolated gate driver GD4 can also be called SiC control chips, which are used to control the corresponding silicon carbide switch tubes, wherein the Miller clamp pins of each isolated gate driver are used to prevent the SiC from being mistakenly turned on during high-frequency switching, that is, to prevent the power switch from being mistakenly turned on. The target square wave pulse signal can be converted into a two-phase pulse through the two-phase wave modulation circuit of the embodiment of the present application, and the pulse width of the two-phase pulse is adjustable, and the pulse width can reach 500-1000ns. The biphasic pulse circuit needs to be able to output both positive and negative phase pulse signals at the same time to meet the needs of specific application scenarios. Figure 6As shown, by controlling the enable terminal (such as ENB) of the third driver chip IC3, the single-phase and dual-phase pulse outputs can be switched. The dual-phase wave modulation circuit realizes the modulation of the high-voltage square wave pulse signal and generates the required dual-phase pulse signal by cleverly designing the combination of the third PWM controller U3, the third driver chip IC3, the isolated gate driver and the silicon carbide switch tube. In the process of generating the dual-phase pulse signal, the duty cycle is an important parameter, which directly affects the width and shape of the pulse signal. The circuit is connected to the oscillator resistor pin of the third PWM controller through the duty cycle adjustment module, allowing the main controller to accurately adjust the duty cycle of the PWM control signal, thereby realizing flexible control of the dual-phase pulse signal characteristics; the silicon carbide switch tube has high-speed switching capability and good electrical isolation performance, and is suitable for high-voltage and high-frequency pulse circuits. The circuit uses silicon carbide switching tubes as switching elements, combined with isolated gate drivers to achieve efficient and reliable control of the switching tubes, while ensuring the safety of the circuit; the third driver chip IC3, as a dual-channel gate driver chip, enables the output of the PWM control signal, optimizes the waveform and timing of the drive signal, ensures that the silicon carbide switching tube can accurately and quickly respond to the control signal, and improves the stability and reliability of the circuit.

[0035] In an optional embodiment, the duty cycle adjustment module adopts one of the following adjustment methods: an adjustable potentiometer method; a digital potentiometer adjustment method; a digital switch array series resistance method.

[0036] In the above embodiment, the aforementioned target square wave pulse signal is subjected to bi-phase modulation through a bi-phase wave modulation circuit. The modulation method inverts the target square wave pulse signal into a bi-phase pulse group composed of multiple bi-phase nanosecond pulses through the above third PWM controller U3 with adjustable duty cycle. The duty cycle adjustment method can be implemented by an adjustable potentiometer, a digital potentiometer adjustment, or a digital switch array series resistor method. Different duty cycle adjustment methods not only improve the performance and accuracy of the bi-phase pulse circuit, but also enhance its automation, programmability, and anti-interference capabilities, meeting the diverse needs in different application scenarios.

[0037] In an optional embodiment, if Figure 6As shown, the biphasic wave modulation circuit also includes: a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a twenty-second resistor R22, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a fourteenth capacitor C14, a fifteenth capacitor C15, a sixteenth capacitor C16, a third voltage zener diode ZD3, a fourth voltage zener diode ZD4, a fifth voltage zener diode ZD5, a sixth voltage zener diode The negative output power supply voltage pin of the first isolated gate driver GD1 is connected to the first power supply through the fifth capacitor C5 and the fifteenth resistor R15, wherein the fifth capacitor C5 and the fifteenth resistor R15 are connected in series, the negative output power supply voltage pin of the first isolated gate driver GD1 is also connected to the second ground terminal, the anode of the third Zener diode ZD3 is electrically connected to the negative output power supply voltage pin of the first isolated gate driver GD1, the connection point of the fifth capacitor C5 and the fifteenth resistor R15 is electrically connected to the cathode of the third Zener diode ZD3, and the cathode of the third Zener diode ZD3 is also electrically connected to the source of the first silicon carbide switch tube V1. The positive output power supply voltage pin of the first isolated gate driver GD1 is electrically connected to the source of the first silicon carbide switch tube V1 through the sixth capacitor C6, the sixteenth resistor R16 is connected between the positive output power supply voltage pin of the first isolated gate driver GD1 and the first power supply, and the seventh capacitor C7 is connected between the first power supply and the second ground terminal; the negative output power supply voltage pin of the second isolated gate driver GD2 is connected to the second power supply through the eighth capacitor C8 and the seventeenth resistor R17, wherein the eighth capacitor C8 and the seventeenth resistor R17 are connected in series, the negative output power supply voltage pin of the second isolated gate driver GD2 is also connected to the second ground terminal, and the fourth stabilizer The positive electrode of the voltage-stabilizing diode ZD4 is electrically connected to the negative output power supply voltage pin of the second isolated gate driver GD2, the connection point of the eighth capacitor C8 and the seventeenth resistor R17 is electrically connected to the negative electrode of the fourth voltage-stabilizing diode ZD4, the negative electrode of the fourth voltage-stabilizing diode ZD4 is also electrically connected to the source electrode of the second silicon carbide switch tube V2, the positive output power supply voltage pin of the second isolated gate driver GD2 is electrically connected to the source electrode of the second silicon carbide switch tube V2 through the ninth capacitor C9, the eighteenth resistor R18 is connected between the positive output power supply voltage pin of the second isolated gate driver GD2 and the second power supply, and the tenth capacitor C10 is connected between the second power supply and the second ground terminal;The negative output power supply voltage pin of the third isolated gate driver GD3 is connected to the third power supply through the eleventh capacitor C11 and the nineteenth resistor R19, wherein the eleventh capacitor C11 and the nineteenth resistor R19 are connected in series, the negative output power supply voltage pin of the third isolated gate driver GD3 is also connected to the second ground terminal, the anode of the fifth Zener diode ZD5 is electrically connected to the negative output power supply voltage pin of the third isolated gate driver GD3, the connection point between the eleventh capacitor C11 and the nineteenth resistor R19 is electrically connected to the negative electrode of the fifth Zener diode ZD5, the negative electrode of the fifth Zener diode ZD5 is also electrically connected to the source of the third silicon carbide switch tube V3, the positive output power supply voltage pin of the third isolated gate driver GD3 is electrically connected to the source of the third silicon carbide switch tube V3 through the twelfth capacitor C12, the twentieth resistor R20 is connected between the positive output power supply voltage pin of the third isolated gate driver GD3 and the third power supply, and the thirteenth capacitor C13 is connected between the third power supply and the second ground terminal; the fourth The negative output power supply voltage pin of the isolated gate driver GD4 is connected to the fourth power supply through the fourteenth capacitor C14 and the twenty-first resistor R21, wherein the fourteenth capacitor C14 and the twenty-first resistor R21 are connected in series, the negative output power supply voltage pin of the fourth isolated gate driver GD4 is also connected to the second ground terminal, the anode of the sixth voltage zener diode ZD6 is electrically connected to the negative output power supply voltage pin of the fourth isolated gate driver GD4, the connection point of the fourteenth capacitor C14 and the twenty-first resistor R21 is electrically connected to the negative electrode of the sixth voltage zener diode ZD6, the negative electrode of the sixth voltage zener diode ZD6 is also electrically connected to the source of the fourth silicon carbide switch tube V4, the positive output power supply voltage pin of the fourth isolated gate driver GD4 is electrically connected to the source of the fourth silicon carbide switch tube V4 through the fifteenth capacitor C15, the twenty-second resistor R22 is connected between the positive output power supply voltage pin of the fourth isolated gate driver GD4 and the fourth power supply, and the sixteenth capacitor C16 is connected between the fourth power supply and the second ground terminal. ;

[0038] In the above embodiment, each isolated gate driver (or SiC control chip) is also configured with a negative voltage drive circuit, and each isolated gate driver has a negative output power supply voltage pin, for example, through a first power supply (such as Figure 6+VA1 in the figure), the fifteenth resistor R15, and the fifth capacitor C5 form a negative voltage drive circuit. When the first silicon carbide switch tube V1 is turned off, the negative voltage capacitor (such as the fifth capacitor) provides negative voltage. The negative voltage drive circuit ensures that the first silicon carbide switch tube V1 can quickly reach the required negative voltage level when it is turned off, thereby accelerating the turn-off speed and reducing energy loss during the switching process; and each silicon carbide switch tube (or SiC switch tube) has its own body diode, or leakage diode, which provides a fast leakage path when it is turned off quickly, that is, the embodiment of the present application provides separate negative voltage control for each SiC switch tube. Silicon carbide (SiC) switch tubes perform well in high-frequency and high-power applications, but their turn-off process needs to be fast and stable. Traditional driving methods may not be able to provide enough negative voltage to ensure that the switch tube is completely and quickly turned off, especially in high-voltage scenarios; by configuring a negative voltage drive circuit on each isolated gate driver, a stable negative voltage can be provided when it is turned off, ensuring that the silicon carbide switch tube can be turned off quickly and reliably, reducing the turn-off time and switching loss; such as Figure 6 As shown, the voltages of the first power supply (such as +VA1), the second power supply (such as +VA2), the third power supply (such as +VA3) and the fourth power supply (such as +VA4) can be equal or different, for example, they can all be 24V (or other voltages). The negative voltage that the SiC control chip in the embodiment of the present application can provide is -5V to -3V.

[0039] The present application also provides a high-frequency pulse therapeutic apparatus, comprising the biphasic pulse circuit described in any of the aforementioned embodiments.

[0040] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0041] An embodiment of the present application provides a high-voltage biphasic pulse generating circuit for a high-frequency pulse therapy device. High-voltage biphasic pulses are realized by adopting high-voltage silicon carbide and a dedicated driving circuit. In addition, a high-voltage amplitude limiting and current limiting circuit and a pulse width adjustment circuit based on isolated serial communication are designed to realize the output waveform required by the high-frequency pulse therapy device.

[0042] An isolated steep pulse therapeutic device capable of outputting a bi-phase pulse width adjustable nanosecond pulse wave. Figure 7 is a principle block diagram of a high voltage biphasic pulse generating circuit provided in an embodiment of the present application, wherein the amplitude limiting and current limiting circuit is constructed as follows Figure 8 As shown, the pulse width modulation circuit is composed of Fig. 9 The working principle of the high voltage biphase pulse generating circuit is as follows. Figure 7As shown, a boost circuit is used to convert low-voltage DC power into DC power of appropriate voltage of 60-300V and then store it in a storage capacitor group composed of large-capacity high-frequency low-impedance capacitors and small-capacity chip ceramic capacitors, such as Figure 2 As shown, the main controller adjusts the PWM controller (such as Figure 2 The switching frequency of the first PWM controller U1 in the circuit is adjusted to adjust the output voltage of the secondary of the switch tube control transformer, so as to achieve a rough adjustment of the output pulse voltage (the rough adjustment can avoid excessive voltage reduction of the IGBT tube of the limiting circuit). The stored electrical energy is then converted into high-voltage pulses through an isolated boost circuit, such as Figure 3 As shown in the figure, the maximum high voltage pulse output by the example circuit is 1200V. The duration of the high voltage pulse is controlled by the main controller through the control pin of the PWM controller, which is generally 50-200us. Figure 4 After modulation by the amplitude limiting and current limiting circuit, a high voltage square wave pulse is formed. Figure 4 IB1 in the figure is a bus isolation buffer. The limiting circuit can use serial communication. After connecting multiple LED driver chips in series, a certain algorithm is used to set the output pulse voltage. The output voltage can be cascaded to obtain a higher high-voltage square wave pulse. For example, the maximum output of a single high-voltage pulse is 1200V. Two cascades can obtain a 2400V high-voltage square wave pulse. Figure 5 As shown, the limiting circuit mainly drives an LED array through an LED driver group controlled by a serial communication. Each LED in the array is connected in series with an optocoupler, and a 100V withstand voltage Zener is short-circuited on the other side of the optocoupler. When the optocoupler is turned on, the Zener is short-circuited, and the output of the limiting circuit decreases by 100V. When the optocoupler is turned off, the Zener works normally and the output voltage increases by 100V. The high-voltage pulse is stabilized by the first insulated gate bipolar transistor IGBT1 and then output through the current limiting circuit composed of the first transistor B1 and the tenth resistor R10. The output high-voltage square wave pulse is Figure 6 The bi-phase modulation is carried out. The modulation method uses a PWM controller with adjustable duty cycle to invert the high-voltage square wave pulse into a bi-phase pulse group composed of multiple bi-phase nanosecond pulses. The duty cycle adjustment method can be achieved by using an adjustable potentiometer, a digital potentiometer or a digital switch array series resistor. Finally, the bi-phase high-voltage pulse is transmitted to the application part through the electrode. The bi-phase inverter switch tube uses a sic switch tube with a withstand voltage of more than 3300V, and the switching speed is in the tens of nanoseconds. At the same time, the controller part has a special negative voltage circuit for shutdown (negative voltage capacitor provides negative voltage when shutting down) and a fast shutdown design (the control chip provides a fast discharge path), which ensures the realization of nano-level bi-phase pulse waves. Fig.10 It is a high voltage square wave pulse output after limiting. Fig.11It is a modulated two-phase high-voltage pulse. First, two high-voltage square wave pulses are cascaded, and then a two-phase nanosecond pulse output of more than 2000V is achieved by adjusting the duty cycle and two-phase inversion. Fig.12 It is a specific waveform of a set of biphasic pulse waves.

[0043] Compared with the related art, the embodiments of the present application have at least the following technical effects: 1) The isolated high-frequency pulse output is adopted, which is safer than the traditional high-frequency pulse method based on the discharge of the charging capacitor switch tube; 2) By adopting high-voltage silicon carbide and a dedicated drive circuit, the voltage amplitude of the single-channel high-voltage two-phase pulse is increased to 3300V. The isolated high-frequency pulse output circuit originally designed based on a single-channel 1200V switch tube requires 4 sets of circuits to be superimposed for the timing 5000V high-frequency pulse output. After the new design is adopted, only 2 sets are needed to achieve it, which greatly simplifies the topology structure and control difficulty of the isolated high-frequency pulse output circuit; 3) The isolated amplitude limiting and current limiting circuit that can be adjusted by serial communication can realize high-frequency and high-voltage pulse square wave output; 4) Specially designed high-voltage silicon carbide drive circuit and pulse width adjustment circuit are used to realize nanosecond high-voltage two-phase pulses.

[0044] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification, those skilled in the art will easily think of other embodiments of the present disclosure.

[0045] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A biphase pulse circuit, characterized in that: include: Boosting circuit, N groups of pulse modulation isolation transformer circuits, amplitude limiting and current limiting circuits, cascade circuits, dual-phase wave modulation circuits, main controller, among which, The boost circuit is electrically connected to the output end of the target DC power supply, and the boost circuit is used to perform pulse modulation and boost processing on the output DC voltage of the target DC power supply to obtain an initial pulse voltage signal; The output end of the boost circuit is electrically connected to the input end of each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits, and each group of pulse modulation isolation transformer circuits in the N groups of pulse modulation isolation transformer circuits performs isolation boosting and pulse modulation processing on the initial pulse voltage signal to obtain a group of high-voltage pulse signals, wherein the group of high-voltage pulse signals includes N high-voltage pulse signals, and each group of pulse modulation isolation transformer circuits outputs a corresponding high-voltage pulse signal, and N is a positive integer greater than or equal to 1; The output end of the N groups of pulse modulation isolation transformer circuits is electrically connected to the input end of the amplitude limiting and current limiting circuit, wherein the amplitude limiting and current limiting circuit is used to perform amplitude limiting and current limiting processing on the N high-voltage pulse signals respectively to obtain N high-voltage square wave pulse signals; The output end of the amplitude limiting and current limiting circuit is electrically connected to the input end of the cascade circuit, and the cascade circuit is used to perform cascade processing on the N high-voltage square wave pulse signals to obtain a target square wave pulse signal; The output end of the cascade circuit is electrically connected to the input end of the bi-phase wave modulation circuit, wherein the bi-phase wave modulation circuit is used to perform bi-phase modulation on the target square wave pulse signal to obtain a target bi-phase pulse signal; The main controller is electrically connected to the boost circuit, the N groups of pulse modulation isolation transformer circuits, the amplitude limiting and current limiting circuit, and the dual-phase wave modulation circuit.

2. The biphasic pulse circuit according to claim 1, characterized in that: The boost circuit includes: a first PWM controller, a boost transformer, a first MOS tube, a second MOS tube, a fuse, a first rectifier bridge, an energy storage capacitor group, a first resistor, a second resistor, a third resistor, a fourth resistor, a first diode, a second diode, a first capacitor, and a second capacitor, wherein: The first PWM controller is used to generate a first PWM control signal and a second PWM control signal, wherein the first PWM control signal is used to control the on and off of the first MOS tube, and the second PWM control signal is used to control the on and off of the second MOS tube, and the first PWM control signal and the second PWM control signal are both square wave signals of a first preset frequency, and the first PWM controller is electrically connected to the main controller; The drain of the first MOS transistor is connected to the first end of the first winding of the primary side of the step-up transformer, the second end of the first winding of the primary side of the step-up transformer is electrically connected to the output end of the target DC power supply through the fuse, the gate of the first MOS transistor is electrically connected to the first complementary output end of the first PWM controller through the first resistor, the source of the first MOS transistor is connected to the first ground end, the gate of the first MOS transistor is also connected to the first ground end through the second resistor, the first complementary output end of the first PWM controller is electrically connected to the negative electrode of the first diode, and the positive electrode of the first diode is electrically connected to the first ground end, wherein the first complementary output end of the first PWM controller is used to output the first PWM control signal; The drain of the second MOS transistor is connected to the first end of the second winding of the primary side of the step-up transformer, the second end of the second winding of the primary side of the step-up transformer is electrically connected to the second end of the first winding of the primary side of the step-up transformer, the gate of the second MOS transistor is electrically connected to the second complementary output terminal of the first PWM controller through the third resistor, the source of the second MOS transistor is connected to the first ground terminal, the gate of the second MOS transistor is also connected to the first ground terminal through the fourth resistor, the second complementary output terminal of the first PWM controller is electrically connected to the negative electrode of the second diode, and the positive electrode of the second diode is electrically connected to the first ground terminal, wherein the second complementary output terminal of the first PWM controller is used to output the second PWM control signal; The second end of the first winding of the primary side of the step-up transformer is electrically connected to the first ground terminal through the first capacitor, the first end of the secondary side of the step-up transformer is electrically connected to the first input terminal of the first rectifier bridge, the second end of the secondary side of the step-up transformer is electrically connected to the second input terminal of the first rectifier bridge through the second capacitor, the energy storage capacitor group is connected to the output terminal of the first rectifier bridge, and the output terminal of the first rectifier bridge is used to output the initial pulse voltage signal.

3. The biphasic pulse circuit according to claim 2, characterized in that: The energy storage capacitor group includes: a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, wherein the third capacitor is a high-frequency electrolytic capacitor, and the fourth capacitor is a non-polar capacitor.

4. The biphasic pulse circuit according to claim 1, characterized in that: The i-th group of pulse modulation isolation transformer circuits is any group of pulse modulation isolation transformer circuits among the N groups of pulse modulation isolation transformer circuits, and the i-th group of pulse modulation isolation transformer circuits includes: a second PWM controller, a first driving chip, a third MOS tube, a fourth MOS tube, an isolation transformer, a second rectifier bridge, a filter circuit, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor, wherein: The second PWM controller is used to generate a third PWM control signal and a fourth PWM control signal, and the second PWM controller is electrically connected to the main controller; The first complementary output terminal of the second PWM controller and the second complementary output terminal of the second PWM controller are electrically connected to the first input pin of the first driver chip and the second input pin of the first driver chip respectively, the first output pin of the first driver chip and the second output pin of the first driver chip are used to output a first driving control signal and a second driving control signal respectively, wherein the first driving control signal is used to control the on-off of the third MOS tube, the second driving control signal is used to control the on-off of the fourth MOS tube, the third PWM control signal and the fourth PWM control signal are both square wave signals of a second preset frequency, and the first complementary output terminal of the second PWM controller and the second complementary output terminal of the second PWM controller are used to output the third PWM control signal and the fourth PWM control signal respectively; The first output pin of the first driving chip is electrically connected to the gate of the third MOS transistor through the fifth resistor, the gate of the third MOS transistor is electrically connected to the first ground terminal through the sixth resistor, the source of the third MOS transistor is electrically connected to the first ground terminal, and the drain of the third MOS transistor is electrically connected to the first end of the primary side of the isolation transformer; The second output pin of the first driving chip is electrically connected to the gate of the fourth MOS transistor through the seventh resistor, the gate of the fourth MOS transistor is electrically connected to the first ground terminal through the eighth resistor, the source of the fourth MOS transistor is electrically connected to the first ground terminal, the drain of the fourth MOS transistor is electrically connected to the second end of the primary side of the isolation transformer, and the primary side tap of the isolation transformer is used to input the initial pulse voltage signal; The secondary side of the isolation transformer is electrically connected to the input end of the second rectifier bridge, the output end of the second rectifier bridge is electrically connected to the input end of the filter circuit, and the output end of the filter circuit is used to output the i-th high-voltage pulse signal, wherein the group of high-voltage pulse signals includes the i-th high-voltage pulse signal, and i is a positive integer greater than or equal to 1 and less than or equal to N.

5. The biphasic pulse circuit according to claim 1, characterized in that: The amplitude limiting and current limiting circuit comprises: a bus isolation buffer, N voltage regulating and current limiting modules, wherein: A group of communication buses is electrically connected to a group of bus input terminals corresponding to each of the N voltage regulating and current limiting modules through the bus isolation buffer; The high-voltage signal input end of the j-th voltage regulating and current limiting module among the N voltage regulating and current limiting modules is used to input the j-th high-voltage pulse signal, and the pulse output end of the j-th voltage regulating and current limiting module is used to output the j-th high-voltage square wave pulse signal, wherein the N high-voltage pulse signals include the j-th high-voltage pulse signal, the N high-voltage square wave pulse signals include the j-th high-voltage square wave pulse signal, the j-th voltage regulating and current limiting module is any one of the N voltage regulating and current limiting modules, and the j-th voltage regulating and current limiting module is used to perform amplitude limiting and current limiting processing on the j-th high-voltage pulse signal, and j is a positive integer greater than or equal to 1 and less than or equal to N; The serial data output end of the j-th voltage regulating and current limiting module is electrically connected to the serial data input end of the j+1-th voltage regulating and current limiting module, and the serial data input end of the 1st voltage regulating and current limiting module is connected to the serial signal input bus in the target communication bus, and the target communication bus includes the group of communication buses.

6. The biphasic pulse circuit according to claim 5, characterized in that: The j-th voltage regulating and current limiting module includes: a second driving chip, an LED array, an optical coupler array, a voltage regulator array, a third diode, a first voltage regulator diode, a second voltage regulator diode, a first insulated gate bipolar transistor, a first transistor, a ninth resistor, and a tenth resistor, wherein the second driving chip includes M output channels, and the second driving chip is used to convert a serial input signal into M parallel switch signals, the LED array includes M LEDs, the optical coupler array includes M optical couplers, and the voltage regulator array includes M voltage regulator diodes, and M is a positive integer greater than 1; The kth output channel corresponds to the kth LED, the kth optocoupler and the kth Zener diode, wherein the kth output channel is any one of the M output channels, the M LEDs include the kth LED, the M optocouplers include the kth optocoupler, the M Zener diodes include the kth Zener diode, and k is a positive integer greater than or equal to 1 and less than or equal to M; The kth output channel is electrically connected to the cathode of the kth LED, the input end of the kth optocoupler is connected between the anode of the kth LED and the working power supply end, and the kth voltage regulator diode is connected in parallel to the output end of the kth optocoupler; When k=1, the cathode of the first Zener diode is electrically connected to the cathode of the third diode, the anode of the third diode is electrically connected to the gate of the first insulated gate bipolar transistor, and the anode of the first Zener diode is electrically connected to the cathode of the second Zener diode; when k>1, the cathode of the kth Zener diode is electrically connected to the anode of the k-1th Zener diode, and the anode of the kth Zener diode is electrically connected to the cathode of the k+1th Zener diode; the anode of the Mth Zener diode is connected to the second ground terminal through the first Zener diode; The ninth resistor is connected between the gate of the first insulated gate bipolar transistor and the collector of the first insulated gate bipolar transistor, the anode of the second zener diode is electrically connected to the emitter of the first insulated gate bipolar transistor, the cathode of the second zener diode is electrically connected to the gate of the first insulated gate bipolar transistor, the collector of the first transistor is electrically connected to the gate of the first insulated gate bipolar transistor, the base of the first transistor is electrically connected to the emitter of the first insulated gate bipolar transistor, and the tenth resistor is connected between the base of the first transistor and the emitter of the first transistor; Among them, the collector of the first insulated gate bipolar transistor is used to input the j-th high-voltage pulse signal, and the emitter of the first transistor is used to output the j-th high-voltage square wave pulse signal.

7. The biphasic pulse circuit according to claim 1, characterized in that: The dual-phase wave modulation circuit includes: a third PWM controller, a third driving chip, a first isolated gate driver, a second isolated gate driver, a third isolated gate driver, a fourth isolated gate driver, a first silicon carbide switch tube, a second silicon carbide switch tube, a third silicon carbide switch tube, a fourth silicon carbide switch tube, a duty cycle adjustment module, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor, wherein: The main controller is electrically connected to the resistor pin of the oscillator of the third PWM controller through the duty cycle adjustment module, the third PWM controller is used to generate a fifth PWM control signal and a sixth PWM control signal, and the main controller adjusts the duty cycle of the fifth PWM control signal and the sixth PWM control signal through the duty cycle adjustment module; The first complementary output terminal of the third PWM controller and the second complementary output terminal of the third PWM controller are electrically connected to the first input pin of the third driver chip and the second input pin of the third driver chip respectively, and the first output pin of the third driver chip and the second output pin of the third driver chip are respectively used to output a third drive control signal and a fourth drive control signal, wherein the fifth PWM control signal and the sixth PWM control signal are both square wave signals with a preset duty cycle, and the first complementary output terminal of the third PWM controller and the second complementary output terminal of the third PWM controller are respectively used to output the fifth PWM control signal and the sixth PWM control signal, and the third driver chip is a dual-channel gate driver chip, which is used to enable the output of the fifth PWM control signal and the sixth PWM control signal; The first output pin of the third driver chip is electrically connected to the non-inverting input terminal of the first isolated gate driver and the non-inverting input terminal of the fourth isolated gate driver respectively, the inverting input terminal of the first isolated gate driver and the inverting input terminal of the fourth isolated gate driver are both grounded, the Miller clamp pin of the first isolated gate driver is electrically connected to the gate of the first silicon carbide switch tube, the gate output pin of the first isolated gate driver is electrically connected to the gate of the first silicon carbide switch tube through the eleventh resistor, the Miller clamp pin of the fourth isolated gate driver is electrically connected to the gate of the fourth silicon carbide switch tube, and the gate output pin of the fourth isolated gate driver is electrically connected to the gate of the fourth silicon carbide switch tube through the fourteenth resistor; The second output pin of the third driver chip is electrically connected to the non-inverting input terminal of the second isolated gate driver and the non-inverting input terminal of the third isolated gate driver respectively, the inverting input terminal of the second isolated gate driver and the inverting input terminal of the third isolated gate driver are both grounded, the Miller clamp pin of the second isolated gate driver is electrically connected to the gate of the second silicon carbide switch tube, the gate output pin of the second isolated gate driver is electrically connected to the gate of the second silicon carbide switch tube through the twelfth resistor, the Miller clamp pin of the third isolated gate driver is electrically connected to the gate of the third silicon carbide switch tube, and the gate output pin of the third isolated gate driver is electrically connected to the gate of the third silicon carbide switch tube through the thirteenth resistor; The source of the first silicon carbide switch tube is electrically connected to the drain of the second silicon carbide switch tube, the source of the second silicon carbide switch tube is connected to the third ground terminal, the source of the third silicon carbide switch tube is electrically connected to the drain of the fourth silicon carbide switch tube, the source of the fourth silicon carbide switch tube is connected to the third ground terminal, and the drain of the first silicon carbide switch tube and the drain of the third silicon carbide switch tube are both used to input the target square wave pulse signal; The source of the first silicon carbide switching tube serves as the positive output terminal of the bi-phase pulse circuit, and is used to output a positive phase pulse signal. The source of the third silicon carbide switching tube serves as the negative output terminal of the bi-phase pulse circuit, and is used to output a negative phase pulse signal. The target bi-phase pulse signal includes the positive phase pulse signal and the negative phase pulse signal.

8. The biphasic pulse circuit according to claim 7, characterized in that: The duty cycle adjustment module adopts one of the following adjustment methods: Adjustable potentiometer method; digital potentiometer adjustment method; digital switch array series resistance method.

9. The biphasic pulse circuit according to claim 7, characterized in that: The dual-phase wave modulation circuit also includes: a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a third Zener diode, a fourth Zener diode, a fifth Zener diode, and a sixth Zener diode, wherein: The negative output power supply voltage pin of the first isolated gate driver is connected to the first power supply through the fifth capacitor and the fifteenth resistor, wherein the fifth capacitor and the fifteenth resistor are connected in series, the negative output power supply voltage pin of the first isolated gate driver is also connected to the second ground terminal, the anode of the third voltage regulator diode is electrically connected to the negative output power supply voltage pin of the first isolated gate driver, the connection point between the fifth capacitor and the fifteenth resistor is electrically connected to the negative electrode of the third voltage regulator diode, the negative electrode of the third voltage regulator diode is also electrically connected to the source of the first silicon carbide switch tube, the positive output power supply voltage pin of the first isolated gate driver is electrically connected to the source of the first silicon carbide switch tube through the sixth capacitor, the sixteenth resistor is connected between the positive output power supply voltage pin of the first isolated gate driver and the first power supply, and the seventh capacitor is connected between the first power supply and the second ground terminal; The negative output power supply voltage pin of the second isolated gate driver is connected to the second power supply through the eighth capacitor and the seventeenth resistor, wherein the eighth capacitor and the seventeenth resistor are connected in series, the negative output power supply voltage pin of the second isolated gate driver is also connected to the second ground terminal, the anode of the fourth voltage regulator diode is electrically connected to the negative output power supply voltage pin of the second isolated gate driver, the connection point between the eighth capacitor and the seventeenth resistor is electrically connected to the negative electrode of the fourth voltage regulator diode, the negative electrode of the fourth voltage regulator diode is also electrically connected to the source of the second silicon carbide switch tube, the positive output power supply voltage pin of the second isolated gate driver is electrically connected to the source of the second silicon carbide switch tube through the ninth capacitor, the eighteenth resistor is connected between the positive output power supply voltage pin of the second isolated gate driver and the second power supply, and the tenth capacitor is connected between the second power supply and the second ground terminal; The negative output power supply voltage pin of the third isolated gate driver is connected to the third power supply through the eleventh capacitor and the nineteenth resistor, wherein the eleventh capacitor and the nineteenth resistor are connected in series, the negative output power supply voltage pin of the third isolated gate driver is also connected to the second ground terminal, the anode of the fifth voltage regulator diode is electrically connected to the negative output power supply voltage pin of the third isolated gate driver, the connection point of the eleventh capacitor and the nineteenth resistor is electrically connected to the negative electrode of the fifth voltage regulator diode, the negative electrode of the fifth voltage regulator diode is also electrically connected to the source of the third silicon carbide switch tube, the positive output power supply voltage pin of the third isolated gate driver is electrically connected to the source of the third silicon carbide switch tube through the twelfth capacitor, the twentieth resistor is connected between the positive output power supply voltage pin of the third isolated gate driver and the third power supply, and the thirteenth capacitor is connected between the third power supply and the second ground terminal; The negative output power supply voltage pin of the fourth isolated gate driver is connected to the fourth power supply through the fourteenth capacitor and the twenty-first resistor, wherein the fourteenth capacitor and the twenty-first resistor are connected in series, the negative output power supply voltage pin of the fourth isolated gate driver is also connected to the second ground terminal, the anode of the sixth voltage regulator diode is electrically connected to the negative output power supply voltage pin of the fourth isolated gate driver, the connection point of the fourteenth capacitor and the twenty-first resistor is electrically connected to the negative electrode of the sixth voltage regulator diode, the negative electrode of the sixth voltage regulator diode is also electrically connected to the source of the fourth silicon carbide switch tube, the positive output power supply voltage pin of the fourth isolated gate driver is electrically connected to the source of the fourth silicon carbide switch tube through the fifteenth capacitor, the twenty-second resistor is connected between the positive output power supply voltage pin of the fourth isolated gate driver and the fourth power supply, and the sixteenth capacitor is connected between the fourth power supply and the second ground terminal.

10. A high-frequency pulse therapeutic apparatus, characterized in that: A biphasic pulse circuit comprising any one of claims 1 to 9.

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