Wireless charging based on sine / square wave hybrid reconfigurable radio frequency waveform

Abstract

A digital power amplifier for driving an RFID antenna with an antenna signal of a substantially sinusoidal output current. The digital power amplifier comprises switching means configured to switch at least one of the 2 * W driver blocks from a contributing mode to a non-contributing mode in which the driver block does not contribute a charge increment to the output current to adjust the amplitude and / or waveform of the output signal. This makes it possible to reduce the power transmitted in the magnetic field emitted by the RFID antenna without the need for digital waveform-forming bit combination with a digital control of high-frequency processing. This reduces the power demand of the digital power amplifier.

Description

Technical Field

[0001] The invention relates to a digital power amplifier that drives an RFID antenna using an antenna signal. Background Art

[0002] Wireless charging is used for a variety of different portable devices, such as mobile phones or headphones. The two headphones must be placed in a storage box with a power supply device, which includes one or two RFID antennas to generate and transmit the power supply device's magnetic field to wirelessly charge the two headphones. In some of these systems, the power supply device only transmits a magnetic field, while some newer systems include a feedback loop from the portable device to the power supply device to adjust the power of the magnetic field to transmit more or less output power.

[0003] For example, such a system is described in European patent application number 22167055.7 (filed on April 7, 2022), which describes a system based on NFC Forum TM Technical Specification Version 1.0 of Wireless Charging is as follows. The power supply device 1 is a reader called a "poller" and includes an antenna that transmits a magnetic field with a frequency of 13.56MHz and a sinusoidal waveform of a carrier signal. The portable device is a tag called a "listener" and includes an antenna that is exposed to the magnetic field emitted by the power supply device. An adaptation or matching circuit matches the impedance of the output pin of the antenna to the input pin of a rectifier that uses a bridge rectifier to rectify the antenna signal and provide a DC voltage. The charging stage of the portable device is used to charge the battery of the portable device. The charging stage includes a charger IC that requires a power supply voltage of 5V+ / -10%, and a DC / DC converter is used to convert the DC voltage provided by the rectifier to an appropriate input voltage at the input pin of the charging stage. The battery is a lithium-ion battery that needs to be charged by the charging stage at different charging currents and charging voltages for different time periods. The charging stage also includes a digital control stage that generates power adjustment information in the event that the input voltage at the input pin and / or the charging current for charging the battery is too low or too high. This power adjustment information is provided by the digital control stage to the Cless communication stage that complies with the NFC communication protocol to transmit the power adjustment information to the power supply device. Through this feedback loop from the portable device to the power supply device, the charging stage can request more or less power in the magnetic field provided by the power supply device. The increase or decrease of power in the magnetic field is achieved by a higher or lower amplitude or a different waveform of the carrier signal of the magnetic field.

[0004] Currently, there are two different NFC power amplifier topologies for power supply devices, one using a square wave followed by filtering, and the other using a full sine wave synthesis as disclosed in EP 3 182 585 B1. Power supply devices operating on the square wave principle produce a fundamental wave of the 13.56MHz carrier frequency, but also produce odd harmonics. These harmonics must be filtered out using a passive filter. When transmitting the high powers required for wireless charging, the resistance of the inductor within the filter results in high heat losses, as the resistive losses are proportional to the square of the current.

[0005] The power amplifier disclosed in EP 3 182 585 B1 includes W driver blocks connected to a first output pin of the power amplifier and another W driver blocks connected to a second output pin of the power amplifier. Each of these parallel arranged driver blocks includes a level shifter and a buffer or an inverter and a series capacitor, which is loaded to a charging stage according to the waveform of the signal to be output at the first and second output pins. These parallel capacities of all driver blocks are loaded through a specific charging stage, the clock frequency of which is M times the transmission frequency of the magnetic field used to wirelessly charge the battery of the portable device. The sum of the charges in these charging stages is provided at the first and second output pins, and the output current of the power amplifier is realized. The advantage of using such a power amplifier as a shaping stage in the transmitter stage of the power supply device is that only the bit combination at the input pin of the driver block needs to be adjusted to switch between different waveforms provided at the output pin of the driver stage. Therefore, switching between waveforms such as sine, sawtooth or rectangular is easy and very energy-saving. Any other waveform can be achieved by simply changing the bit combination at the input pin of the driver block. Thus, the full sinusoidal synthesis by a power amplifier disclosed in EP 3182 585 B1 uses a capacitive DC to AC converter to construct a substantially sinusoidal output current which can pass directly through a matching circuit to the RFID antenna. This is more efficient at high powers than a square wave generating power amplifier, but is less efficient at lower amplitudes and lower powers of the antenna signal. Summary of the invention

[0006] An object of the present invention is to provide a digital power amplifier and a power supply device and a system of a portable device having such a digital power amplifier for wirelessly powering a load of a portable device, which enables efficient power transmission and power adjustment.

[0007] This object is achieved by a digital power amplifier according to claim 1 and a system according to claim 6 .

[0008] The digital power amplifier according to the present invention comprises a switching device configured to switch at least one of the 2×W driver blocks from a contributing mode to a non-contributing mode in which the driver block does not contribute an increment of charge to the output current to adjust the amplitude and / or waveform of the output signal. This makes it possible to reduce the power transmitted in the magnetic field emitted by the RFID antenna without employing digital wave-forming bit combinations performed by a digital control section with high frequency processing. This reduces the power requirements of the digital power amplifier.

[0009] It is further advantageous if the digital control is constructed to reduce the output power of an antenna signal having a substantially sinusoidal output current by symmetrically switching those of the 2×W driver blocks in a stepwise manner to a non-contributing mode which is capable of cutting off the highest amplitudes of the positive and negative half-waves of the substantially sinusoidal output current and each step converting the waveform of the substantially sinusoidal output voltage into an output voltage which is increasingly substantially square-wave. As a result, such a digital power amplifier produces a substantially sinusoidal output current at high power amplitudes, thereby eliminating the need for external passive filtering. However, as the required output power decreases, the output becomes more trapezoidal until at low powers it becomes indistinguishable from a square wave. As the power decreases, the proportion of harmonics in the carrier does increase, but since the carrier amplitude is decreasing, the absolute harmonic energy content remains low enough that external filtering is not required.

[0010] Advantageously, a digital waveform forming bit pattern is stored in the memory of the digital control section to generate a basic sinusoidal output current, and / or a clipping value of a switching code for a switching device of the digital control section is stored to gradually reduce or increase the output power of the antenna signal. The use of this stored information enables the generation of different waveforms of the output signal using a digital power amplifier, and the power of the output signal and the magnetic field can be gradually reduced based on the reduced power requirements of the high-frequency digital control section. This memory storing information for the digital power amplifier operates at 13.56MHz and enables the generation of the basic sinusoidal output current to be hard-coded, thereby simplifying it and reducing the power required to generate it. A typical generation of a basic sinusoidal output current based on a 26nm process will consume 3mA, and a solution with a memory and a stored lookup table will consume less than 1mA.

[0011] The generation of the sine wave can be shared between multiple power amplifiers. This is particularly important in true wireless stereo applications where two power amplifiers are needed to support independent charging of two wireless listeners. Since the sine wave lookup (W signals) does not need to be synchronized on every clock cycle, the synchronization between the modulator and the power amplifier is reduced. The power amplifiers themselves are responsible for synchronizing the required amplitude at each power amplifier zero crossing.

[0012] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.It will be appreciated by those skilled in the art that the various embodiments may be combined. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A power supply device with a digital power amplifier according to the system of the present invention is shown, which is used for wirelessly charging a battery of a portable device.

[0014] Figure 2 Show according to Figure 1 Time diagram of the output voltage of the digital power amplifier of the system.

[0015] Figure 3 The upper part shows Figure 1 The output voltage at the transmission output pin of a digital power amplifier integrated circuit is cut off in different steps to reduce the output power. Figure 3 The lower portion shows the essentially sinusoidal output current of the antenna signal, which is an antenna inductor filtered version of the output voltage at the transmit output pin.

[0016] Figure 4 A comparison of the output power efficiency of the digital power amplifier of the prior art and the present invention is shown.

[0017] Figure 5 The figure shows the comparison of the spurious-free dynamic range of the antenna output current of the digital power amplifier of the prior art and the present invention in terms of output power.

[0018] Figure 6 Show Figure 1 Spectra of the antenna output current for three different output power levels of the power amplifier.

[0019] Figure 7 Show Figure 1 The thermometer encoder of the power amplifier has a symmetrical clipping of the waveform. DETAILED DESCRIPTION

[0020] Figure 1 The power supply device 1 of the system 2 according to the first embodiment of the present invention is shown. The system 2 also includes two portable headphones for the left and right ears of the user, which are Figure 1 Such a system 2 can be used in various use cases where two or more antennas with the same or different power levels are required. Each earphone comprises an antenna connected via a matching circuit to an integrated circuit powered by the battery of the earphone. The integrated circuit of the earphone is constructed to harvest energy from the magnetic field generated by the power supply device 1, which is implemented in the storage box of the earphone, for wirelessly powering the batteries of the two earphones.

[0021] The power supply device 1 includes an integrated circuit 3, a first digital power amplifier 4 and a second digital power amplifier 5. The integrated circuit 3 is composed of Figure 1 The integrated circuit 3 further comprises a first transmission output pin 8 and a second transmission output pin 9 to provide an output signal OS from the first digital power amplifier 4, and a third transmission output pin 10 and a fourth transmission output pin 11 to provide an output signal OS from the second digital power amplifier 5. A first adaptation circuit 12 of discrete components is connected to the first transmission output pin 8 and the second transmission output pin 9, and is constructed to match the impedance and adapt the output signal OS to feed the first RFID antenna 6 with a substantially sinusoidal output current I having a transmission resonance frequency of 13.56 MHz. A second adaptation circuit 13 of discrete components is connected to the third transmission output pin 10 and the fourth transmission output pin 11, and is constructed to match the impedance and adapt the output signal OS to feed the second RFID antenna 7 with a substantially sinusoidal output current I having a transmission resonance frequency of 13.56 MHz. From a more technical perspective, the digital power amplifiers 4 and 5 provide charge increments which add up to a sinusoidal output current as will be explained below.

[0022] The integrated circuit 3 and the digital power amplifiers 4 and 5 further comprise a digital control section 14 for the first digital power amplifier 4, which has W waveform forming contacts 15 to output a digital waveform forming bit pattern, where W=2^(number of amplitude resolution bits N), in the present embodiment N=6. The clock frequency of the digital waveform forming bit pattern is M times the transmission resonance frequency, where the oversampling rate is M, in the present embodiment M=64. The clock frequency of M=64 in the present embodiment is 64×13.56 MHz=867.84 MHz. The number N defines the resolution or number of different amplitudes, and the number M of the oversampling rate defines the time resolution or division of one cycle of the basic sinusoidal output current with the transmission resonance frequency of 13.56 MHz, with which the first digital power amplifier 4 drives the first RFID antenna 6. In principle, the higher the numbers W and M, the better and smoother the form of the basic sinusoidal output current I of the antenna signal AS. Any other numbers / resolutions W and M can also be used. M=64 provides a phase resolution of 360 / 64 degrees (approximately 6 degrees).

[0023] Figure 2 Show according to Figure 1An example of a substantially sinusoidal output voltage U of the antenna signal OS generated by the first digital power amplifier 4 compared to a perfect sinusoid SIN, the maximum amplitude may be within a half period of the transmission resonance frequency at the RFID antenna 6. Such a resonant output voltage U may be in the range of 100 volts peak-to-peak, or even higher.

[0024] The digital control section 14 includes a memory 16 for storing a lookup table of digital waveform forming bit combinations of W waveform forming contacts 15 to generate a basic sinusoidal output current and gradually reduce or increase the output power of the antenna based on different clipping values. To achieve this, a table is stored in the memory 16, which contains M time instances, each time instance having a digital waveform forming bit combination of W data bits "0" and "1". The digital control section 14 also includes a wave generator 17, which is constructed to output a digital waveform forming bit combination of M data bits "0" or "1" at the W waveform forming contacts 15 to convert the data bit "0" or "1" into a basic sinusoidal output current I of the antenna signal AS. In this embodiment, a bus width of N=6 from the memory 16 to the wave generator 17 is used according to the amplitude resolution bit. In another embodiment of the present invention, only M / 2 time instances of the W waveform forming bit combinations are stored, and the time axis symmetric part is generated by the wave generator 17.

[0025] The first digital power amplifier 4 includes a plurality of 2×W driver blocks 18, half of which are connected to one of the W waveform forming contacts 15 via a first contact 19 and to the first transmission output pin 8 via a second contact 20. The other half of the 2×W driver blocks 18 are connected to one of the W waveform forming contacts 15 via their first contact 19 and to the second transmission output pin 9 via their second contact 20. The driver blocks 18 are constructed to provide charge increments of a basic sinusoidal output current I to the first transmission output pin 8 and the second transmission output pin 9. This means that each driver block 18, if driven with a bit "1" in the digital waveform forming bit pattern, adds a charge increment to the transmission output pin 8 or 9 to drive, for example, 5 mA in one clock cycle. All these charge increments add up to form a basic sinusoidal output current I, for example, a maximum of N×5mA=320mA. Higher or lower increments are also possible.

[0026] This design of the integrated circuit 3 includes the advantage that the output signal OS at the first and second transmission output pins 8 and 9 enables an analog signal in the form of an antenna signal AS that is close to a perfect sinusoid SIN to meet the spurious emission levels required by regulations to avoid noise in other frequency ranges. Therefore, compared to prior art integrated circuits that use a square wave and filter it to achieve a substantially sinusoidal output current, no external filter means are required in the adaptation device 12. In addition, advantageously, the digital control section 14 can digitally program the waveform of the substantially sinusoidal output current I and the output signal OS to achieve precise output power modulation.

[0027] These driver blocks 18 connected to the first transmission output pin 8 via their second contact 20 comprise an AND gate 22, and another W driver blocks 18 comprise a NAND gate 26, the gates 22 and 26 forming a logic unit and connected to the first contact 19 and thus to the waveform forming contact 15 via one of their input pins. The gating function of the AND gate 22 and the NAND gate 26 will be explained below. All 2×W driver blocks also comprise a level shifter 24, which shifts the voltage of the waveform forming contact 15 to a higher voltage, in particular to a voltage at least twice as high. In the disclosed embodiment, the driver block 18 receives an input signal in the range of 0 volts to 1.8 volts at its first contact 19 and shifts it to an output signal in the range of 0 volts to 5 volts at the output of the level shifter 24. The level shifter 24 converts the low voltage domain of the digital control part 14 into a high voltage analog domain, which is fed to the output pins 8 and 9.

[0028] Those driver blocks 18 connected to the second transmission output pin 9 via the second contact 20 comprise a NAND gate 26 for inverting the potential of the voltage provided by the waveform forming contact 15. This enables the generation of complementary output signals to have a differential signal chain.

[0029] Each driver block 18 further comprises a series capacitor C which is arranged between the level shifter 24 and the second contact 20 and is fed with the voltage of the level shifter 24. This allows the charge increment of each driver block 18 to add up to a positive half-wave of the driver block 18 connected to the first transmission output pin 8 and a negative half-wave of the driver block 18 connected to the second transmission output pin 9, with a substantially sinusoidal output current I. The typical capacity of the capacitors C is 5 pF each, but can also be lower or higher.

[0030] The integrated circuit 3 is implemented in CMOS technology and advantageously the series capacitor C is implemented by a metal-oxide-metal capacitor using the capacitive effect of the connection lines within the integrated circuit 3. This enables good integration of the series capacitor C within the integrated circuit 3 and allows high output voltages.

[0031] In principle, all driver blocks 18 are always on, even when no digital waveform shaping bit is output at the waveform shaping contact 15. This enables the resonant tuning to be maintained and prevents overvoltages on the driver blocks 18. The outputs of the driver blocks 18 may also contain diode clamps to ensure that there is no overvoltage. The number of driver blocks 18 used in combination with the pulse width of the digital waveform shaping bit defines the output power of the power amplifier 4.

[0032] The integrated circuit 3 of the system 2 comprises a second digital power amplifier 5, which is constructed in the same way as the first digital power amplifier 4 described above. Advantageously, both digital power amplifiers 4 and 5 are part of the system 2 of the power supply device 1 and share the same digital control section 14, which reduces chip area and costs. Since they are implemented on one integrated circuit 3, their components have no temperature differences that could lead to different output OS, which is a great advantage.

[0033] The digital control section 14 further includes a first switching device 27 and a second switching device 28 of the present invention, the first switching device 27 being constructed to adjust the amplitude and / or waveform of the output signal OS of the first digital power amplifier 4, and the second switching device 28 being constructed to adjust the amplitude and / or waveform of the output signal OS of the second digital power amplifier 5. The first switching device 27 is constructed to switch at least four of the 2×W driver blocks 18 from a contribution mode to a non-contribution mode, in which the driver block 18 does not contribute to the charge increment of the output current I. The first switching device 27 selectively switches or permits / prohibits each of the 2×W driver blocks 18 to enter a contribution mode or a non-contribution mode. In the non-contribution mode, the driver block 18 is disconnected from the waveform forming contact 15 or does not contribute, and its capacitance C is not loaded independently of the bit "1" or bit "0" of its associated digital waveform forming bit contact 15. This makes it possible to reduce the power transmitted to the headset in the magnetic field emitted by the RFID antenna 6 without using a digital waveform forming bit combination of the digital control section 14 processed with a high-frequency clock of 867.84 MHz. Both of these (no loading of the capacity C and no need for processing by the digital control unit 14 ) reduce the power requirement of the first digital power amplifier 4 .

[0034] The digital control section 14 further comprises a second switching device 28 which is constructed to switch between the contributing mode and the non-contributing mode or to enable / disable the 2×W driver blocks 18 of the second digital power amplifier 5. This provides the advantage that the power transmitted from the first digital power amplifier 4 via the first antenna 6 to the first earphone of the system 2 can be manipulated to be different and independent from the power transmitted from the second digital power amplifier 5 via the second antenna 7 to the second earphone of the system 2. Communicates with wireless headsets, and one of the two headsets must have The receiver loads the battery of this earphone, the battery of the other earphone is loaded more. Therefore, the battery of one earphone may need to be charged with a different power to fully charge them at the same time. This possibility of charging each earphone with a different power in the magnetic field of the RFID antennas 6 and 7 can reduce the total charging time of the earphones, which is an essential feature.

[0035] In order to switch between the contributing mode and the non-contributing mode or to enable / disable, the first and second switching means 27 and 28 include an amplitude stage 29 and a thermometer encoder 30. The amplitude stage 29 receives synchronization and other information from the digital control section 14 via the wave generator 17, including information about the step size (resolution N) to which extent the maximum output power of the substantially sinusoidal output current I should be reduced. This operates the thermometer encoder 30 to generate a switching code 31 to selectively switch or enable / disable each of the 2×W driver blocks 18 to the contributing mode or the non-contributing mode. Using a thermometer code or a unary code, a simple switching (enabling / disabling) can be achieved, but other codes can also be used to selectively connect or disconnect the driver stage 18. The thermometer encoder 30 is connected to the second input pins of the AND gate 22 and the NAND gate 26 and provides its switching code 31 as a second input signal. This means that the output of the digital waveform forming contact 15 provided to the AND gate 22 of the driver block 18 contributes only when the switching code 31 provided to the AND gate 22 of the driver block 18 is bit "1". It may facilitate a transition from bit "0" to bit "1" or from bit "1" to bit "0". The same is true for the NAND gate 26, but in reverse, where the switching code 31 must provide a bit "0" to switch or permit the driver block 18 to its contributing mode to enable the contribution of the digital waveform forming contact 15 at the NAND gate 26. For those driver blocks 18 that are switched or disabled to their non-contributing mode, the second contact 20 is clamped to a fixed voltage, high VD or low VS. The thermometer encoder 30 ensures that the waveform is clipped symmetrically, as shown in FIG. Figure 7 Amplitude resolution and clipping can be defined independently, so for example a bit width of 4 bits at the output of amplitude level 29 provides 16 levels of amplitude resolution, while a bit width of 5 bits provides 32 levels. Let's deal with this one.

[0036] The first and second switching means 27 and 28 are constructed to reduce the charge increment provided at the output pins 8 and 9, which cuts off the higher amplitude of the output signal OS and reduces the amplitude of the antenna signal AS with the substantially sinusoidal output current I ( Figure 3This is achieved by symmetrically switching those of the 2×W driver blocks 18 stepwise to a non-contributory mode capable of reducing the amount of charge supplied to the first transmission output pin 8 and the second transmission output pin 9 and cutting off the highest amplitudes of the positive and negative half-waves of the substantially sinusoidal output voltage U ( Figure 3 The driver block 18 switched to its non-contribution mode is symmetrically clamped to different clamping voltages VD and VS by the first switching device 27 and the second switching device 28. By reducing the output power of the power amplifier 4, the output voltage U of the output signal OS becomes more and more a basic square wave waveform, which is a low EMI problem with regard to unwanted higher harmonics, because the amplitude is already very low and the amplitude of the harmonics no longer interferes.

[0037] Figure 4 A prior art power amplifier and Figure 1 3 . Efficiency line 32 shows the efficiency of a power amplifier based on the square wave principle, but without the additional filtering required for EMI. Efficiency line 33 shows the efficiency of a power amplifier disclosed in EP 3 182 585 B1. Efficiency line 34 shows the efficiency of a power amplifier based on the square wave principle. Figure 1 The efficiency of the power amplifiers 4 and 5 of the power supply device 1, which converts from a SIN waveform to a square waveform using a hybrid method when reducing the output power. Figure 4 The efficiency line 32 of the square wave principle in is higher than the efficiency line 34, but the square wave principle has loss due to filtering, which further reduces the efficiency of the square wave principle and provides better overall efficiency for the power amplifiers 4 and 5 of the present invention.

[0038] Figure 5 A prior art power amplifier and Figure 1 The spurious-free dynamic range SFDR (such as Figure 6 35 shows the output power of the power amplifier based on the square wave principle. SFDR line 36 shows the output power of the power amplifier disclosed in EP 3 182 585 B1. SFDR line 37 shows the output power of the power amplifier according to Figure 1 The output power of the power amplifiers 4 and 5 of the power supply device 1 is converted from a SIN waveform to a square waveform using a hybrid method when reducing the output power. This hybrid method of the present invention has better harmonics than the square wave principle and is converted to the same harmonic content as the power amplifier disclosed in EP 3 182 585 B1.

[0039] Figure 6 The spectrum of power amplifiers 4 and 5 at different output power levels is shown, which indicates Figure 5The antenna current spectra for the three output power data points in SFDR line 37. Figure 6 Show Figure 5 The spectral line 38 with harmonics at the 0.2W output power data point shows that the SFDR is about 36.9dB. The spectral line 39 shows Figure 5 The spectrum of the 0.8W output power data point has a SFDR of approximately 40.4dB. Spectrum line 40 shows Figure 5 The spectrum of the 2W output power data point, the SFDR is about 77.2dB.

[0040] In accordance with Figure 1 In the system 2 of the embodiment, the digital control section 14 is constructed to use the same digital waveform forming bit combination on the waveform forming contact 15 for all W driver blocks 18 of the two digital power amplifiers 4 and 5. In addition, the digital control section 14 is constructed to use the same or different switching codes 31 for the two switching devices 27 and 28 of the power amplifiers 4 and 5, so as to be able to output the same power to the two portable headphones, or to output a larger power to one of the two portable headphones. This makes it possible to achieve the advantage of customizing the output power for charging according to the power requirements of the two batteries of the headphones.

[0041] In another embodiment of the present invention, the 2×W driver blocks of each of the two power amplifiers share the same level shifter 24 to shift the voltage provided at the waveform forming contact 15 to a higher voltage when the AND gate and the NAND gate are in the high voltage domain. This reduces complexity and chip area.

[0042] The advantages of the invention are explained by the application of wireless charging of two earphones, but the invention can also be used for any other wireless charging or power supply application. In addition, additional digital power amplifiers can be added to the system and power supply device to enable more antennas to be powered with independent magnetic fields with less or more output power.

[0043] With the power amplifier disclosed in EP 3 182 585 B1, the waveform of the antenna signal AS can be adjusted as needed to output a SIN waveform or a triangular waveform or a square waveform. According to the invention described herein, the amplitude and power of the selected waveform can be reduced in an effective manner as described above. In some embodiments of the present invention, the waveform, amplitude and power of the antenna signal AS can be adjusted by switching some driver blocks to a non-contributing mode.

Claims

1. A digital power amplifier for driving an RFID antenna with an antenna signal of an output current, the digital power amplifier comprising: An integrated circuit having a first transmission output pin and a second transmission output pin (9) for providing an output signal; an adaptation circuit of discrete components connected to the first transmission output pin and the second transmission output pin for adapting the output signal and feeding a substantially sinusoidal output current having a transmission resonant frequency to the RFID antenna; a digital control section having W waveform forming contacts for outputting a digital waveform forming bit pattern having a clock frequency M times the transmission resonant frequency; 2×W driver blocks, each driver block is connected to one of the waveform forming contacts via a first contact, and W of them are connected to the first transmission output pin via a second contact, and another W of them are connected to the second transmission output pin via their second contacts, and these driver blocks are constructed to provide a charge increment of the substantially sinusoidal output current to the first transmission output pin and the second transmission output pin, wherein The digital control unit comprises: A switching device, which is constructed to manipulate the logic unit in each of the driver blocks to make at least four driver blocks of the 2×W driver blocks of the digital power amplifier enter a non-contributing mode from a contributing mode, in which the driver block does not contribute a charge increment to the output current to adjust the amplitude and / or waveform of the output signal, wherein the digital control unit is constructed to reduce the output power of the antenna signal with the basic sinusoidal output current by stepwise and symmetrically making those driver blocks of the 2×W driver blocks enter the non-contributing mode, wherein the non-contributing mode allows the highest amplitudes of the positive half-wave and the negative half-wave of the basic sinusoidal output current to be cut off, and each step converts the waveform of the basic sinusoidal output voltage into an increasingly basic square wave output voltage. 2 . The digital power amplifier according to claim 1 , wherein the switching device is constructed to cause at least four of the 2×W driver blocks to enter the non-contributing mode from a waveform-forming contact point thereof. 3 . The digital power amplifier of claim 1 , wherein the digital control section is configured to provide information to the switching device to selectively permit or prohibit each of the 2×W driver blocks from entering the contributing mode or the non-contributing mode. 4 . The digital power amplifier according to claim 3 , wherein the switching device generates a switching code using a thermometer encoder to selectively permit or prohibit each of the 2×W driver blocks from entering the contributing mode or the non-contributing mode.

5. A digital power amplifier according to claim 1, wherein the digital control unit includes a memory, which is used to store a lookup table of bit combinations of the digital waveform to generate the basic sinusoidal output current, and / or store the clipping value of the switching code of the switching device to gradually reduce or increase the output power of the antenna signal.

6. A system comprising a power supply device and at least one portable device, for wirelessly powering a load of the portable device, the power supply device comprising: At least two digital power amplifiers according to any one of claims 1 to 5, wherein each of the digital power amplifiers drives an independent RFID antenna, and wherein the at least two digital power amplifiers share the same digital control section.

7. A system according to claim 6, wherein the digital control section is constructed to use the same digital waveform to form a bit combination for the 2×W driver blocks of each of the two digital power amplifiers, and wherein the digital control section is constructed to use the same or different switching codes for two switching devices of the power amplifier to allow the same power to be output to both of the two portable devices, or more power to be output to one of the two portable devices.

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