A sub-nanosecond square-wave pulse generator

Abstract

This application discloses a sub-nanosecond square wave pulse generator, which includes: a clock source unit, a control logic unit, a high-speed switch, a pre-driver and amplifier unit, and an output unit. Among them, the output end of the clock source unit is connected to the input end of the control logic unit, and the clock source unit is used for; the output end of the control logic unit is connected to the control end of the high-speed switch circuit, and the control logic unit is used for; the output end of the high-speed switch is connected to the input end of the pre-driver and amplifier unit, and the pre-driver and amplifier unit is used for; the output end of the pre-driver and amplifier unit is connected to the input end of the output unit, and the output unit is used for further processing the amplified and conditioned pulse signal to output a sub-nanosecond square wave pulse. This application can obtain a sub-nanosecond square wave pulse with high precision.

Description

Technical Field

[0001] This application relates to a pulse generator, and more particularly to a sub - nanosecond square - wave pulse generator. Background Art

[0002] Existing square - wave pulse generators usually have difficulty achieving sub - nanosecond pulse - width accuracy and maintaining good signal integrity. In addition, at high frequencies, the rise time and fall time of the signal have a significant impact on the pulse shape. Therefore, for sub - nanosecond applications, these two parameters must be ensured to be as small as possible. Summary of the Invention

[0003] Aiming at the deficiencies in the prior art, the purpose of this application is to provide a sub - nanosecond square - wave pulse generator, which can obtain high - quality sub - nanosecond square - wave pulses with steep edges.

[0004] To achieve the above purpose, this application provides the following technical solutions:

[0005] A sub - nanosecond square - wave pulse generator, the generator includes: a clock source unit, a control logic unit, a high - speed switch, a pre - driver and amplifier unit, and an output unit. Among them, the clock source unit is used to provide a clock signal for the generation of sub - nanosecond square - wave pulses; the control logic unit is used to set the parameters of the sub - nanosecond square - wave pulses and generate control signals based on these parameters; the high - speed switch is used to perform fast switching based on the control signals to generate pulse signals with steep edges; the pre - driver and amplifier unit is used to amplify and condition the pulse signals with steep edges; the output unit is used to further process the amplified and conditioned pulse signals to output sub - nanosecond square - wave pulses; the protection unit is used to provide protection for the output unit.

[0006] Optionally, the clock source unit includes: an atomic clock, a temperature - controlled crystal oscillator, a first phase - locked loop, a second phase - locked loop, an adder, a first operational amplifier, and an output driver. Among them, the input end of the first phase - locked loop is connected to the output end of the atomic clock, the input end of the second phase - locked loop is connected to the output end of the temperature - controlled crystal oscillator, the output end of the first phase - locked loop is connected to the first input end of the adder, the output end of the second phase - locked loop is connected to the second input end of the adder, the output end of the adder is connected to the non - inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the input end of the output driver, and the output end of the output driver is connected to the input end of the control logic unit; the clock source unit further includes a temperature compensation circuit, and the temperature compensation circuit is connected to the inverting input end of the first operational amplifier.

[0007] Optionally, the temperature compensation circuit includes a temperature sensor and a heating or cooling element.

[0008] Optionally, the pre-driving and amplifying unit includes: a first capacitor, a second operational amplifier, a voltage dividing network, a matching network, a gate driver, and a power MOSFET. Wherein, a first end of the first capacitor is connected to an output end of the high-speed switch, a second end of the first capacitor is connected to a non-inverting input end of the second operational amplifier, the voltage dividing network is disposed between an inverting input end and an output end of the second operational amplifier, an output end of the second operational amplifier is connected to an input end of the gate driver through the matching network, an output end of the gate driver is connected to a gate of the power MOSFET, a source of the power MOSFET is connected to a third ground terminal, and a drain of the power MOSFET is connected to the protection unit.

[0009] Optionally, the output unit includes: a first filtering and voltage stabilizing module, a second filtering and voltage stabilizing module, a signal conditioning module, a signal processing module, and an output module. Wherein, the first filtering and voltage stabilizing module is configured to provide a stable power supply signal and filter out noise in the power supply signal; the second filtering and voltage stabilizing module is configured to further purify the power supply signal; the signal conditioning module is configured to condition the amplified and conditioned pulse signal; the signal processing module is configured to convert the conditioned pulse signal into a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width; and the signal output module is configured to output a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width.

[0010] Optionally, the first filtering and voltage stabilizing module includes: a first low-dropout regulator, a fifth resistor, a first transistor, a second inductor, and a fourth capacitor. Wherein, a first end of the fifth resistor is connected to a base of the first transistor to form a first node, a second end of the fifth resistor is connected to an input end of the first low-dropout regulator; an output end of the first low-dropout regulator is connected to a first end of the second inductor; a second end of the second inductor is connected to a -5V power supply; a first end of the fourth capacitor is connected to the output end of the first low-dropout regulator, a second end of the fourth capacitor is connected to a seventh ground terminal; a collector of the first transistor is connected to a sixth ground terminal, and an emitter of the first transistor is connected to a first input end of the signal conditioning module to form a second node.

[0011] Optionally, the second filtering and voltage stabilizing module includes: a second low-dropout regulator, a ninth capacitor, and a third inductor. Wherein, an input end of the second low-dropout regulator is connected to a +5V power supply through the third inductor, an output end of the second low-dropout regulator is connected to a first input end of the signal processing module to form an eighth node; a first end of the ninth capacitor is connected to the input end of the second low-dropout regulator, and a second end of the ninth capacitor is connected to an eighth ground terminal.

[0012] Optionally, the signal conditioning module includes: a second transistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, and a switch. Among them, the first end of the sixth resistor serves as the first input end of the signal conditioning module and is connected to the second node, and the second end of the sixth resistor is connected to the first input end of the signal processing module to form a fourth node; the emitter of the second transistor is connected to the second node, the base of the second transistor is connected to the first end of the ninth resistor to form a fifth node, and the collector of the second transistor is connected to the second input end of the signal processing module to form a third node; the second end of the ninth resistor is connected to the third node through the eighth resistor; the first end of the fifth capacitor is connected to the fifth node, and the second end of the fifth capacitor is connected to the sixth ground terminal through the switch; the first end of the tenth resistor is connected to the first node, and the second end of the tenth resistor is connected to the first end of the sixth capacitor; the second end of the sixth capacitor is connected to the sixth ground terminal through the switch.

[0013] Optionally, the signal processing module includes: a third transistor, a fourth transistor, a seventh resistor, a seventh capacitor, an eighth capacitor, an eleventh resistor, a tenth capacitor, and an eleventh capacitor. Among them, the base of the third transistor serves as the second input end of the signal processing module and is connected to the third node, the collector of the third transistor is connected to the sixth ground terminal, and the emitter of the third transistor is connected to the base of the fourth transistor; the emitter of the fourth transistor is connected to the first end of the eleventh resistor to form a sixth node; the second end of the eleventh resistor serves as the first input end of the signal processing module and is connected to the fourth node; the collector of the fourth transistor is connected to the first end of the seventh capacitor to form a seventh node; the second end of the seventh capacitor is connected to the first input end of the signal output module to form an eighth node; the eighth capacitor is connected in parallel across both ends of the seventh capacitor; the first end of the tenth capacitor is connected to the fourth node, and the second end of the tenth capacitor is connected to the sixth ground terminal; the first end of the eleventh capacitor is connected to the fourth node, and the second end of the eleventh capacitor is connected to the sixth ground terminal.

[0014] Optionally, the signal output module includes: a fifth transistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor. Among them, the emitter of the fifth transistor is connected to the sixth node, and the collector of the fifth transistor is connected to the first end of the twelfth resistor; the second end of the twelfth resistor serves as the first input end of the signal output module and is connected to the eighth node; the base of the fifth transistor is connected to the first end of the thirteenth resistor to form a ninth node; the second end of the thirteenth resistor is connected to the output end of the output unit; the first end of the fourteenth resistor is connected to the ninth node, and the second end of the fourteenth resistor is connected to the fourth node.

[0015] Compared with the prior art, the beneficial effects brought by the present application are as follows:

[0016] By integrating a high-precision clock source unit, a flexible control logic unit, a high-speed switch, a fine pre-drive and amplification unit, an optimized output unit, and a comprehensive protection unit, the present application can achieve the efficient generation and precise control of sub-nanosecond square-wave pulses. The present application can not only ensure that the pulses have extremely high time resolution and stability, but also effectively filter out noise and interference, ensuring the purity and integrity of the signals. In addition, the multi-level protection mechanism significantly improves the reliability and anti-interference ability of the system, enabling the entire pulse generator to operate stably in a complex and changeable electrical environment, and finally output high-quality sub-nanosecond square-wave pulses with steep edges. Description of the Drawings

[0017] Figure 1 is a schematic circuit structure diagram of a sub-nanosecond square-wave pulse generator provided by an embodiment of the present application;

[0018] Figure 2 is Figure 1 a schematic circuit structure diagram of the clock source unit in a sub-nanosecond square-wave pulse generator shown in

[0019] Figure 3 is Figure 1 a schematic circuit structure diagram of the pre-drive and amplification unit in a sub-nanosecond square-wave pulse generator shown in

[0020] Figure 4 is Figure 1 a schematic circuit structure diagram of the protection unit in a sub-nanosecond square-wave pulse generator shown in

[0021] Figure 5 is Figure 1 a schematic circuit structure diagram of the output unit in a sub-nanosecond square-wave pulse generator shown in

[0022] The description of the reference numerals in the drawings is as follows:

[0023] 1. Clock source unit; 11. Atomic clock; 12. Temperature-controlled crystal oscillator; 13. First phase-locked loop; 14. Second phase-locked loop; 15. Adder; 16. Amplifier; 17. Output driver; 18. Temperature compensation circuit; 2. Control logic unit; 3. High-speed switch; 4. Pre-drive and amplification unit; 41. Voltage division network; 42. Matching network; 43. Gate driver; 44. Power MOSFET; 5. Protection unit; 6. Output unit; 61. First filter and voltage regulator module; 62. Second filter and voltage regulator module; 63. Signal conditioning module; 64. Signal processing module; 65. Signal output module. Detailed Embodiments

[0024] Specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although specific embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.

[0025] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different terms to refer to the same component. The specification and claims do not use the difference in terms as a way to distinguish components, but use the difference in the functions of components as the criterion for distinction. As mentioned throughout the specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "including but not limited to". The subsequent description of the specification is the preferred implementation mode for implementing the present application, but the description is for the purpose of the general principles of the specification and is not used to limit the scope of the present application. The protection scope of the present application is defined by the appended claims.

[0026] For ease of understanding of the embodiments of the present application, the following will further explain with specific embodiments as examples in conjunction with the accompanying drawings, and each accompanying drawing does not constitute a limitation on the embodiments of the present application.

[0027] Figure 1 is a schematic structural diagram of a sub-nanosecond square wave pulse generator proposed in an exemplary embodiment of the present application, as Figure 1 shown, the sub-nanosecond square wave pulse generator includes: a clock source unit 1, a control logic unit 2, a high-speed switch 3, a pre-drive and amplification unit 4, and an output unit 6. Among them, the clock source unit 1 is used to provide a clock signal for the generation of sub-nanosecond square wave pulses; the control logic unit 2 is used to set the parameters of the sub-nanosecond square wave pulses and generate control signals based on these parameters; the high-speed switch 3 is used to perform fast switching based on the control signals to generate pulse signals with steep edges; the pre-drive and amplification unit 4 is used to amplify and condition the pulse signals with steep edges; the output unit 6 is used to further process the amplified and conditioned pulse signals to output sub-nanosecond square wave pulses.

[0028] The present application can obtain high-quality sub-nanosecond square wave pulses with steep edges by integrating a high-precision clock source unit, a flexible control logic unit, a high-speed switch, a fine pre-drive and amplification unit, an optimized output unit, and a comprehensive protection unit.

[0029] This application is of great practical significance by obtaining high-quality sub-nanosecond square-wave pulses. For example, high-quality sub-nanosecond square-wave pulses can significantly improve the resolution and accuracy of radar systems. Among them, a short pulse width means higher time resolution, which can provide more detailed target details in radar images. The steep edge of the pulse helps to accurately measure the distance of the target, especially in applications with a high dynamic range. Another example is that in materials science and non-destructive testing, high-quality short pulses can more accurately detect tiny defects or cracks inside materials. By analyzing the pulse reflection or transmission characteristics, the physical properties of the materials can be deeply understood.

[0030] In another exemplary embodiment, as Figure 2 shown, the clock source unit 1 includes: an atomic clock 11, a temperature-controlled crystal oscillator 12, a first phase-locked loop 13, a second phase-locked loop 14, an adder 15, a first operational amplifier 16, and an output driver 17. Among them, the input end of the first phase-locked loop 13 is connected to the output end of the atomic clock 11, the input end of the second phase-locked loop 14 is connected to the output end of the temperature-controlled crystal oscillator 12, the output end of the first phase-locked loop 13 is connected to the first input end of the adder 15, the output end of the second phase-locked loop 14 is connected to the second input end of the adder 15, the output end of the adder 15 is connected to the non-inverting input end of the first operational amplifier 16, the output end of the first operational amplifier 16 is connected to the input end of the output driver 17, and the output end of the output driver 17 is connected to the input end of the control logic unit 2; the clock source unit 1 further includes a temperature compensation circuit 18 (including a temperature sensor and a heating or cooling element, the heating element includes any one of a resistance heater, a thermistor, and an electrothermal film, and the cooling element includes any one of a Peltier effect cooler, a fan, and a heat sink), and the temperature compensation circuit 18 is connected to the inverting input end of the first operational amplifier 16.

[0031] In this embodiment, the atomic clock 11 operates based on the resonance frequencies of specific atoms (such as cesium, rubidium, etc.), and can maintain its timing accuracy for a long time without significant drift, so that the clock source unit 1 can maintain extremely high time accuracy for a long time. The oven-controlled crystal oscillator 12 can provide a very stable frequency output in the short term. By placing the oven-controlled crystal oscillator 12 in a temperature-controlled environment, the oven-controlled crystal oscillator 12 can minimize the impact of temperature on frequency stability, thus providing better short-term frequency stability than ordinary crystal oscillators. The function of the first phase-locked loop 13 is to lock the extremely stable and accurate frequency signal provided by the atomic clock 11 at a specific frequency. The first phase-locked loop 13 adjusts the output frequency of its internal oscillator to match the frequency and phase of the frequency signal of the atomic clock 11. The first phase-locked loop 13 continuously adjusts the frequency of its internal oscillator through a feedback mechanism until its output signal is completely synchronized with the frequency and phase of the atomic clock 11. In addition, the first phase-locked loop 13 can also filter out the noise and interference of the frequency signal output by the atomic clock 11, thereby improving the signal quality.

[0032] Similarly, the second phase-locked loop 14 is used to ensure that the output frequency of its internal oscillator is synchronized with the signal frequency and phase generated by the oven-controlled crystal oscillator 12.

[0033] The signals output by the atomic clock 11 and the oven-controlled crystal oscillator 12 are respectively adjusted by the first phase-locked loop 13 and the second phase-locked loop 14 and then sent to the adder 15 for merging processing, so that an accurate and stable clock signal can be generated based on the long-term stability of the atomic clock 11 and the short-term stability of the oven-controlled crystal oscillator 12, thereby providing a solid foundation for generating square wave pulses with sub-nanosecond accuracy.

[0034] It should be noted that the adder 15 merges and outputs two signals from the first phase-locked loop 13 and the second phase-locked loop 14. This output signal is often weak. By setting a first operational amplifier 16 after the adder 15, the intensity of this output signal can be enhanced to ensure that it has sufficient amplitude to drive the output driver 17.

[0035] It should also be noted that although the first operational amplifier 16 can enhance the intensity of the output signal, its current driving ability is limited. The output driver 17 can provide stronger current driving ability to ensure that the signal can be transmitted to the subsequent circuit without loss of intensity. In addition, for high-speed signals (such as sub-nanosecond pulses), fast rise and fall times are required. The output driver 17 is usually designed with fast response characteristics to accelerate the edge transition of high-speed signals, thus helping to generate clear and accurate pulse shapes.

[0036] Further, it should be noted that the clock source unit 1 is configured with a temperature compensation circuit 18 because: the change in temperature will affect the operating frequencies of the crystal oscillator and the phase-locked loop, resulting in frequency drift, which will in turn cause signal distortion or increased delay, especially in high-speed signal processing. By introducing the temperature compensation circuit 18 in this application, it helps the first operational amplifier 16 reduce the gain change or bias point drift caused by temperature, ensuring that the signal can maintain good linearity and signal-to-noise ratio throughout the operating temperature range, so as to ensure that the clock source unit 1 can provide a highly accurate and stable clock signal even in different temperature environments, and further support the generation of high-quality sub-nanosecond square wave pulses.

[0037] In another exemplary embodiment, the high-speed switching circuit uses GaN (gallium nitride) or SiC (silicon carbide) transistors.

[0038] In this embodiment, since the transistors of these two materials have higher carrier mobilities and lower on-resistances. Among them, the high carrier mobility of GaN and SiC transistors means that electrons or holes can move through the semiconductor material faster under the action of an electric field. Therefore, when a control signal is applied, it can support an extremely fast switching speed, theoretically reaching the sub-nanosecond level. In addition, the lower on-resistance means less energy loss in the on-state of the transistor and can complete the state transition in a shorter time, which helps to reduce the switching time, making the rise time and fall time of the pulse signal shorter, that is, the edge is steeper.

[0039] In another exemplary embodiment, the control logic unit uses an FPGA.

[0040] In this embodiment, the FPGA is used to programmatically set various parameters of the output pulse, such as pulse width, repetition rate, etc., and control the work of subsequent stages according to these parameters. The FPGA is also responsible for synchronizing all internal operations with the clock source. First, the FPGA is synchronized with the clock source unit to ensure that all internal operations can be carried out based on a very precise time reference. Based on the above-set pulse parameters, the FPGA will generate a series of control signals according to a preset algorithm or logic, and these control signals are used to precisely control the working state of the high-speed switch, that is, to determine when to turn on and off the switch, so as to form a pulse sequence with a specific width and interval.

[0041] It should be noted that since the control logic unit uses an FPGA, the output terminal of the output driver in the clock source unit can be specifically connected to the global clock input pin (such as GCLK0) of the control logic unit, and the control terminal of the high-speed switch can be connected to the I / O pin (such as GPIO_0) of the control logic unit.

[0042] In another exemplary embodiment, as Figure 3 shown, the pre-driving and amplifying unit 4 includes: a first capacitor C1, a second operational amplifier U2, a gate driver 43, and a power MOSFET 44. Among them, the first end of the first capacitor C1 is connected to the output end of the high-speed switch, the second end of the first capacitor C1 is connected to the non-inverting input end of the second operational amplifier U2, a voltage dividing network 41 is provided between the inverting input end and the output end of the second operational amplifier U2, the output end of the second operational amplifier U2 is connected to the input end of the gate driver 43 through a matching network 42, the output end of the gate driver 43 is connected to the gate of the power MOSFET 44, the source of the power MOSFET 44 is connected to the third ground terminal GND3, and the drain of the power MOSFET 44 is connected to the protection unit 5.

[0043] In this embodiment, the first capacitor C1 serves as a coupling capacitor in the pre-driving and amplifying unit 4. Its main function is to block the DC component and only allow the AC signal to pass through, so as to ensure that the signal transmitted to the second operational amplifier U2 does not contain any unnecessary DC bias.

[0044] The second operational amplifier U2 and the voltage dividing network 41 constitute a negative feedback amplifier. The voltage dividing network 41 is connected between the inverting input end and the output end of the second operational amplifier U2 to form a voltage feedback loop, which helps to stabilize the gain of the second operational amplifier and improve the linearity. The second operational amplifier U2 amplifies the signal received from the first capacitor C1 and adjusts the output voltage level according to the ratio set by the voltage dividing network 41.

[0045] The output of the second operational amplifier U2 is connected to the input end of the gate driver 43 after passing through the matching network 42. The matching network 42 is used to ensure impedance matching between the signal source and the load, thereby reducing reflection and improving signal integrity. The gate driver 43 is responsible for converting the control signal provided by the second operational amplifier U2 into a driving signal sufficient to quickly turn on or off the power MOSFET 44. The power MOSFET 44 serves as the final switching element, and its gate receives the signal from the gate driver 43. When the gate of the power MOSFET 44 receives sufficient voltage, the MOSFET conducts, allowing current to flow from the power supply to the load. Since the power MOSFET 44 has a low on-resistance, it can effectively amplify the signal provided by the previous stage to generate the required output pulse.

[0046] As Figure 3As shown, the voltage dividing network 41 includes a first resistor R1 and a second resistor R2. Among them, the first end of the first resistor R1 is connected to the output end of the second operational amplifier U2, the second end of the first resistor R1 is connected to the inverting input end of the second operational amplifier U2, the first end of the second resistor R2 is connected to the second end of the first resistor R1, and the second end of the second resistor R2 is connected to the first ground terminal GND1.

[0047] The matching network 42 includes a third resistor R3, a first inductor L1, and a second capacitor C2. Among them, the first end of the third resistor R3 is connected to the output end of the second operational amplifier U2, the second end of the third resistor R3 is connected to the input end of the gate driver 43 through the first inductor L1, the first end of the second capacitor C2 is connected to the second end of the third resistor R3, and the second end of the second capacitor C2 is connected to the second ground terminal GND2.

[0048] The pre-driving and amplifying unit 4 realizes highly precise amplification and conditioning of the input signal (i.e., a pulse signal with steep edges) by precisely configuring the voltage dividing network 41 and the programmable second operational amplifier U2, and can ensure that the output pulse strictly meets the expected requirements in terms of shape and amplitude. This module uses the second operational amplifier U2 in combination with the matching network 42 and the gate driver 43, which can not only adjust the gain and frequency response according to specific application requirements, but also effectively convert the amplified control signal into a driving level sufficient to quickly switch the power MOSFET 44. This design ensures an extremely short delay from receiving the input signal to generating the output pulse, which is crucial for achieving sub-nanosecond rise and fall times. Specifically, the high gain and wide bandwidth characteristics of the second operational amplifier U2 support fast signal processing, while the matching network 42 optimizes the signal transmission efficiency and reduces reflection losses. The gate driver 43 further accelerates the switching speed of the power MOSFET 44, enabling it to complete the state switching within nanoseconds or even sub-nanoseconds, thereby generating high-quality square wave pulses with steep edges.

[0049] In another exemplary embodiment, as Figure 5As shown, the output unit includes: a first filter and voltage regulator module, a second filter and voltage regulator module, a signal conditioning module, a signal processing module, and a signal output module. Among them, the first filter and voltage regulator module is used to provide a stable power supply signal and filter out the noise in the power supply signal; the second filter and voltage regulator module is used to further purify the power supply signal; the signal conditioning module is used to condition the amplified and conditioned pulse signal; the signal processing module is used to convert the conditioned pulse signal into a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width; the signal output module is used to output a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width.

[0050] In another exemplary embodiment, the first filter and voltage regulator module 61 includes: a first low dropout regulator LDO1, a fifth resistor R5, a first transistor T1, a second inductor L2, and a fourth capacitor C4. Among them, the first end of the fifth resistor R5 is connected to the base of the first transistor T1 to form a first node N1, the second end of the fifth resistor R5 is connected to the input end of the first low dropout regulator LDO1, the output end of the first low dropout regulator LDO1 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to the -5V power supply, the first end of the fourth capacitor C4 is connected to the output end of the first low dropout regulator LDO1, the second end of the fourth capacitor C4 is connected to the seventh ground terminal GND7, the collector of the first transistor T1 is connected to the sixth ground terminal GND6, and the emitter of the first transistor T1 is connected to the first input end of the signal conditioning module to form a second node N2.

[0051] In this embodiment, the first low dropout regulator LDO1 is used to provide a stable voltage output. Even if the input voltage fluctuates within a certain range, the output voltage can still be maintained stable.

[0052] The fifth resistor R5 serves as a current limiting resistor. It is used to limit the current flowing into the base of the first transistor T1 and helps set the operating point of the first transistor T1. In addition, the fifth resistor R5 also participates in forming a part of the feedback path to ensure the output stability of the first low dropout regulator.

[0053] The second inductor L2 and the fourth capacitor C4 together constitute an LC filter, which is used to filter out the high-frequency noise or interference in the power supply signal provided by the -5V power supply and ensure the purity of the power supply signal. In addition, the fourth capacitor C4 also acts as a bypass capacitor. It can quickly respond to transient current demands, absorb voltage fluctuations, and thus maintain a smoother DC voltage output.

[0054] In another exemplary embodiment, the second filtering and voltage stabilizing module 62 includes: a second low dropout regulator LDO2, a ninth capacitor C9, and a third inductor L3. Among them, the input end of the second low dropout regulator LDO2 is connected to the +5V power supply through the third inductor L3. The output end of the second low dropout regulator LDO2 is connected to the first input end of the signal processing module to form an eighth node N8. The first end of the ninth capacitor C9 is connected to the input end of the second low dropout regulator LDO2, and the second end of the ninth capacitor C9 is connected to an eighth ground terminal GND8.

[0055] In this embodiment, the operating principle of the second filtering and voltage stabilizing module is similar to that of the first filtering and voltage stabilizing module, which will not be elaborated here. The difference is that the second filtering and voltage stabilizing module is used to filter and stabilize the +5V power supply.

[0056] In another exemplary embodiment, the signal conditioning module 63 includes: a second transistor T2, a sixth resistor R6, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a sixth capacitor C6, and a switch S. Among them, the first end of the sixth resistor R6 serves as the first input end of the signal conditioning module and is connected to the second node N2. The second end of the sixth resistor R6 is connected to the first input end of the signal processing module to form a fourth node N4. The emitter of the second transistor T2 is connected to the second node N2. The base of the second transistor T2 is connected to the first end of the ninth resistor R9 to form a fifth node N5. The collector of the second transistor T2 is connected to the second input end of the signal processing module to form a third node N3. The second end of the ninth resistor R9 is connected to the third node N3 through the eighth resistor R8. The first end of the fifth capacitor C5 is connected to the fifth node N5. The second end of the fifth capacitor C5 is connected to a sixth ground terminal GND6 through the switch S. The first end of the tenth resistor R10 is connected to the first node N1. The second end of the tenth resistor R10 is connected to the first end of the sixth capacitor C6. The second end of the sixth capacitor C6 is connected to the sixth ground terminal GND6 through the switch S.

[0057] In this embodiment, the input pulse signal enters the signal conditioning module from the second node N2 through the sixth resistor R6 and is transmitted to the emitter of the second transistor T2. The base of the second transistor T2 is grounded through the ninth resistor R9 and the fifth capacitor C5, and at the same time the base is also indirectly connected to the third node N3 through the ninth resistor R9 and the eighth resistor R8, thus forming a local feedback loop. This feedback mechanism can help stabilize the operating point of the second transistor T2 and set the gain, thereby reducing the gain fluctuation of the second transistor T2 caused by temperature changes or other factors. The ninth resistor R9 and the eighth resistor R8 together form a voltage divider network for adjusting the voltage of the base of the second transistor T2 relative to its emitter, optimizing the conduction state of the second transistor T2, thereby affecting the conduction degree of the second transistor T2, so that the input signal can be amplified under optimal conditions (through the voltage divider network composed of the ninth resistor R9 and the eighth resistor R8, a stable DC voltage can be provided for the base of the second transistor T2 without relying on the input signal. This DC voltage determines the quiescent operating point (Q point) of the second transistor T2. Appropriate setting of the quiescent operating point helps ensure that the second transistor T2 maintains a stable operating state over the entire operating temperature range. In addition, the voltage divider network not only determines the quiescent operating point of the second transistor T2, but also affects the AC gain of the second transistor T2. When the second transistor T2 is in the linear amplification region, its gain is mainly determined by the base current and the emitter resistance. By adjusting the ratio of the ninth resistor R9 and the eighth resistor R8, the voltage applied to the base can be precisely controlled, thereby indirectly controlling the base current and further affecting the gain. By adjusting the ratio of R9 and R8, the voltage applied to the base of T2 can be precisely controlled. Further, a higher base voltage will cause more current to flow into the second transistor T2, increasing its conduction degree; vice versa. Therefore, by appropriately selecting the values of these two resistors, the conduction degree of the second transistor T2 can be flexibly adjusted as needed to adapt to different application requirements. If the base voltage is too high or too low, the second transistor T2 may enter the saturation region or the cut-off region, resulting in serious signal distortion or even inability to amplify the signal normally. Through reasonable design of the voltage divider network, it can be ensured that the second transistor T2 is always in the optimal conduction state, neither over-saturated nor cut-off, thus ensuring accurate signal amplification). When the second transistor T2 conducts, current flows from the collector to the emitter. During this process, the input signal is amplified, and the amplified signal is output to the second input terminal of the signal processing module through the third node N3. The fifth capacitor C5 plays a coupling role here to ensure that only AC signals can reach the base of the second transistor T2 to avoid any unnecessary DC offset. The sixth capacitor C6 can further filter out unwanted high-frequency noise to ensure signal quality.The switch S can be used to control whether to ground the fifth capacitor C5 and the sixth capacitor C6, depending on the requirements of specific application scenarios. For example, in some cases, it may be necessary to turn off these capacitors to change the behavior of the circuit or for debugging.

[0058] The signal conditioning module utilizes local feedback (a voltage-divider network formed by the ninth resistor R9 and the eighth resistor R8), which can effectively reduce the gain fluctuations of the second transistor T2 caused by temperature changes or other factors, thereby improving the stability of the output signal of the second transistor T2.

[0059] In summary, through the collaborative work of the above components, the signal conditioning module realizes the effective amplification, filtering, and necessary conditioning of the received pulse signal, and can ensure that the purity and intensity of the pulse signal meet the requirements of subsequent processing.

[0060] In another exemplary embodiment, the signal processing module 64 includes: a third transistor T3, a fourth transistor T4, a seventh resistor R7, a seventh capacitor C7, an eighth capacitor C8, an eleventh resistor R11, a tenth capacitor C10, and an eleventh capacitor C11. Among them, the base of the third transistor T3 is connected to the third node N3 as the second input terminal of the signal processing module, the collector of the third transistor T3 is connected to the sixth ground terminal GND6, the emitter of the third transistor T3 is connected to the base of the fourth transistor T4, the emitter of the fourth transistor T4 is connected to the first end of the eleventh resistor R11 to form a sixth node N6, the second end of the eleventh resistor R11 is connected to the fourth node N4 as the first input terminal of the signal processing module, the collector of the fourth transistor T4 is connected to the first end of the seventh capacitor C7 to form a seventh node N7, the second end of the seventh capacitor C7 is connected to the first input terminal of the signal output module to form an eighth node, the eighth capacitor C8 is connected in parallel across the two ends of the seventh capacitor C7, the first end of the tenth capacitor C10 is connected to the fourth node N4, the second end of the tenth capacitor C10 is connected to the sixth ground terminal GND6, the first end of the eleventh capacitor C11 is connected to the fourth node N4, and the second end of the eleventh capacitor C11 is connected to the sixth ground terminal GND6.

[0061] In this embodiment, the third transistor T3 and the fourth transistor T4 form a cascaded amplifier. The input signal enters the base of the third transistor T3 through the third node N3. The third transistor T3 serves as the first-stage amplifier, whose collector is connected to the sixth ground terminal GND6, and the emitter is connected to the base of the fourth transistor (T4). The fourth transistor T4 serves as the second-stage amplifier, whose emitter is connected to the fourth node N4 through the eleventh resistor R11 to form the sixth node N6. This two-stage amplification structure can significantly improve the gain and contribute to signal shaping, making the generated square-wave pulse clearer and steeper.

[0062] The seventh capacitor C7 and the eighth capacitor C8 are connected in parallel between the collector of the fourth transistor T4 and the first input terminal of the signal output module. Their main functions are to filter out high-frequency noise and smooth the signal edges, thereby generating a purer square-wave pulse. In addition, the seventh capacitor C7 and the eighth capacitor C8 can also be used to help stabilize the output signal and prevent instability or distortion caused by transient response. The tenth capacitor C10 and the eleventh capacitor C11 are respectively connected from the fourth node N4 to the sixth ground terminal. The tenth capacitor C10 and the eleventh capacitor C11, as bypass capacitors, help remove the noise in the power supply, ensure that the signal processing module can work in a clean power supply environment, and avoid the influence of power supply fluctuations on the signal quality.

[0063] In summary, by adopting the two-stage amplification structure composed of the third transistor T3 and the fourth transistor T4, the signal processing module can significantly enhance the intensity and clarity of the input signal, ensuring that the generated square-wave pulse has steep rising and falling edges. After the input signal enters the base of the third transistor T3 through the third node N3 for preliminary amplification, it is further enhanced and shaped by the fourth transistor T4 and finally output to the signal output module. The seventh capacitor C7 and the eighth capacitor C8 connected in parallel between the collector of the fourth transistor T4 and the signal output module effectively filter out high-frequency noise and smooth the signal edges, ensuring the purity and stability of the pulse. In addition, the tenth capacitor C10 and the eleventh capacitor C11, as bypass capacitors, remove the noise in the power supply, ensuring that the signal processing process is carried out in a clean power supply environment and avoiding the influence of power supply fluctuations on the signal quality. This tightly coupled design enables the signal processing module to accurately convert the amplified signal into a high-quality square-wave pulse that meets the accuracy requirements of the sub-nanosecond level.

[0064] In another exemplary embodiment, the signal output module 65 includes: a fifth transistor T5, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14. Among them, the emitter of the fifth transistor T5 is connected to the sixth node N6, the collector of the fifth transistor T5 is connected to the first end of the twelfth resistor R12, the second end of the twelfth resistor R12 serves as the first input terminal of the signal output module and is connected to the eighth node N8, the base of the fifth transistor T5 is connected to the first end of the thirteenth resistor R13 to form a ninth node N9, the second end of the thirteenth resistor R13 is connected to the output terminal OUT of the output module, the first end of the fourteenth resistor R14 is connected to the ninth node N9, and the second end of the fourteenth resistor R14 is connected to the fourth node N4.

[0065] In this embodiment, the input signal enters the emitter of the fifth transistor T5 from the sixth node N6. The fifth transistor T5 acts as a switch or buffer, its collector is connected to the eighth node N8 through the twelfth resistor R12, the base of the fifth transistor T5 is connected to the ninth node N9 through the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is directly connected to the output terminal OUT of the output module. This configuration allows the fifth transistor T5 to quickly respond to changes in the base voltage and adjust its conduction state, thereby precisely controlling the signal transmission. The fourteenth resistor R14 is connected between the ninth node N9 and the fourth node N4), which can help stabilize the base voltage of the fifth transistor T5 and provide an additional feedback path to ensure the stability of signal transmission.

[0066] By using the fifth transistor T5 as a high-speed switch and combining appropriate resistor and capacitor configurations, the signal output module can ensure that the generated square-wave pulse has very steep rising and falling edges.

[0067] In summary, the signal output module closely cooperates with the pre-stage signal processing module to ensure that each link from signal amplification, shaping to final output can complete the task efficiently and accurately, thereby realizing the generation of high-quality sub-nanosecond square-wave pulses.

[0068] In another exemplary embodiment, the pulse generator further includes a protection unit 5, such as Figure 4As shown, the protection unit 5 includes a transient voltage suppression diode D, a fourth resistor R4, a solid-state switch, a common-mode choke CMC, a ferrite bead FB, a first bidirectional diode TVS1, a second bidirectional diode TVS2, and a third capacitor C3. Among them, the first end of the fourth resistor R4 is connected to the drain of the power MOSFET, the second end of the fourth resistor R4 is connected to the first end of the first bidirectional diode TVS1 through the solid-state switch, the second end of the first bidirectional diode TVS1 is connected to the first end of the ferrite bead FB through the common-mode choke CMC, the second end of the ferrite bead FB is connected to the first end of the third capacitor C3, and the first end of the first bidirectional diode TVS1 is connected to the fourth ground terminal GND4. The second end of the third capacitor C3 is connected to the signal input terminal IN of the output module 6, and the second end of the third capacitor C3 is connected to the fifth ground terminal GND5. The second bidirectional diode TVS2 is connected in parallel across the two ends of the first bidirectional diode TVS1, and the transient voltage suppression diode D is connected in parallel across the two ends of the ferrite bead FB.

[0069] In this embodiment, the transient voltage suppression diode D, the first bidirectional diode TVS1, and the second bidirectional diode TVS2 work together to quickly conduct when a transient overvoltage is detected, so as to clamp the voltage within a safe range. This fast response mechanism can effectively protect the subsequent circuit from the impact of momentary high voltage. The first bidirectional diode TVS1 and the second bidirectional diode TVS2 can share the current in the overvoltage event through parallel connection, which means that the entire protection circuit can handle a larger peak pulse current (IPP), thereby improving the protection ability against high-energy transient events. If one of the TVS diodes fails or ages, the other can still continue to provide protection. This redundant design increases the overall reliability of the protection unit. In some cases, the parallel connection of two TVS diodes can achieve a lower effective clamping voltage because when the two TVS diodes conduct simultaneously, the total dynamic resistance will decrease, resulting in a lower clamping voltage, which can further protect the subsequent circuit from high-voltage impact.

[0070] The fourth resistor R4 can limit the maximum current passing through the solid-state switch to prevent damage caused by excessive current. The solid-state switch can quickly cut off or restore the circuit connection as needed, providing an additional safety barrier for the circuit.

[0071] The common-mode choke CMC and the ferrite bead FB work together to suppress electromagnetic interference from the external environment. Among them, the common-mode choke CMC mainly filters common-mode noise in the low-frequency to medium-frequency range and can generate a reverse magnetic field through its internal coil to cancel the common-mode current. The ferrite bead FB exhibits high impedance in the high-frequency band and can absorb and consume high-frequency noise energy to ensure the purity of the signal path. Since the two play roles in different frequency bands respectively, various frequencies of noise in a complex electrical environment (including common-mode noise, differential-mode noise, and high-frequency noise, etc.) can be effectively filtered, ensuring the purity of the transmitted signal, reducing signal distortion, and thus ensuring that the generated sub-nanosecond square-wave pulse has a steep rising edge and falling edge, meeting the high-precision requirements. Therefore, compared with a single bead, by connecting the common-mode choke CMC and the ferrite bead FB in parallel to work together, the present application can provide a wider noise suppression range, thereby maximizing the accuracy of the square-wave pulse.

[0072] The third capacitor C3 is used as a bypass capacitor and is placed at the signal input terminal IN of the output module to help filter high-frequency noise in the power supply, ensure that the signal entering the output module is as pure as possible, and reduce the possibility of distortion and interference.

[0073] The above components together constitute a multi-level protection network. From transient voltage suppression, current limiting, electromagnetic interference suppression to high-frequency noise filtering, each link cooperates closely, thereby providing comprehensive protection measures for the power transmission unit.

[0074] It should be noted that the solid-state switch can be, for example, a MOSFET. The gate of the MOSFET is connected to the timer TM, the source of the MOSFET is connected to the second end of the fourth resistor R4, and the drain of the MOSFET is connected to the first end of the first bidirectional diode TVS1. In addition, the fourth resistor R4 is a thermistor, and the third capacitor C3 is a ceramic capacitor. By using a MOSFET as the solid-state switch, through its excellent high-speed switching ability and extremely low on-resistance (Rds(on)), fast and precise control of the current path is achieved. This design enables the MOSFET to quickly cut off the circuit connection when an abnormal situation is detected, preventing overcurrent or overvoltage from damaging the subsequent sensitive circuits and ensuring that the system can operate efficiently and stably under various working conditions.

[0075] Thermistors have the property of changing their resistance values with temperature changes. This not only enables them to effectively limit the maximum current during the startup phase or under overload conditions, avoiding damage caused by excessive current, but also allows them to self-adjust according to temperature changes, providing an additional temperature compensation function. This dual role significantly enhances the robustness and safety of the system, especially in high-power or high-temperature environments.

[0076] At the same time, the third capacitor C3 is selected as a ceramic capacitor. With its excellent high-frequency filtering performance and low equivalent series resistance (ESR) and equivalent series inductance (ESL), it can efficiently remove high-frequency noise in the power supply, ensuring the purity of the signal path. The ceramic capacitor can also quickly provide additional charge during transient events (such as sudden changes in power supply voltage) to maintain voltage stability, thus preventing the impact of transient voltage fluctuations on the system. This property is particularly crucial for applications that require high precision and high reliability, ensuring that the sub-nanosecond square-wave pulses output by the pulse generator have steep rising and falling edges, reducing the possibility of distortion and interference.

[0077] In summary, this combination not only greatly improves the overall reliability of the pulse generator but also ensures its stable operation in a complex electrical environment. Through the precise control of MOSFETs, the current limiting and temperature compensation of thermistors, and the efficient filtering of ceramic capacitors, the entire generator can generate high-quality and high-precision sub-nanosecond square-wave pulses, thus meeting the strict requirements for high-precision time bases and signal integrity in modern high-tech fields.

[0078] The above embodiments are only for illustrating the technical concept and features of the present application, and their purpose is to enable those skilled in the art to understand the content of the present application and implement it accordingly, and shall not be used to limit the protection scope of the present application. Any equivalent changes or modifications made according to the spirit and essence of the present application shall be covered within the protection scope of the present application.

Claims

1. A sub-nanosecond square-wave pulse generator, characterized in that The generator includes: a clock source unit, a control logic unit, a high-speed switch, a pre-drive and amplification unit, a protection unit, and an output unit, where the clock source unit is used to provide a clock signal for the generation of sub-nanosecond square wave pulses; the control logic unit is used to set the parameters of the sub-nanosecond square wave pulses and generate a control signal based on the parameters; the high-speed switch is used to perform fast switching based on the control signal to generate a pulse signal with steep edges; the pre-drive and amplification unit is used to amplify and condition the pulse signal with steep edges; the output unit is used to further process the amplified and conditioned pulse signal to output sub-nanosecond square wave pulses; the protection unit is used to provide protection for the output unit; the clock source unit includes: an atomic clock, a temperature-controlled crystal oscillator, a first phase-locked loop, a second phase-locked loop, an adder, a first operational amplifier, and an output driver, where the input end of the first phase-locked loop is connected to the output end of the atomic clock, the input end of the second phase-locked loop is connected to the output end of the temperature-controlled crystal oscillator, the output end of the first phase-locked loop is connected to the first input end of the adder, the output end of the second phase-locked loop is connected to the second input end of the adder, the output end of the adder is connected to the non-inverting input end of the first operational amplifier, the output end of the first operational amplifier is connected to the input end of the output driver, the output end of the output driver is connected to the input end of the control logic unit; the clock source unit further includes a temperature compensation circuit, and the temperature compensation circuit is connected to the inverting input end of the first operational amplifier; the pre-drive and amplification unit includes: a first capacitor, a second operational amplifier, a voltage-dividing network, a matching network, a gate driver, and a power MOSFET, where the first end of the first capacitor is connected to the output end of the high-speed switch, the second end of the first capacitor is connected to the non-inverting input end of the second operational amplifier, the voltage-dividing network is arranged between the inverting input end and the output end of the second operational amplifier, the output end of the second operational amplifier is connected to the input end of the gate driver through the matching network, the output end of the gate driver is connected to the gate of the power MOSFET, the source of the power MOSFET is connected to a third ground terminal, the drain of the power MOSFET is connected to the protection unit.

2. The sub-nanosecond square-wave pulse generator according to claim 1, characterized in that The temperature compensation circuit includes a temperature sensor and a heating or cooling element.

3. The sub-nanosecond square wave pulse generator according to claim 1, characterized in that, The output unit includes: a first filtering and voltage stabilizing module, a second filtering and voltage stabilizing module, a signal conditioning module, a signal processing module, and a signal output module, where the first filtering and voltage stabilizing module is used to provide a stable power signal supply and filter out the noise in the power signal; the second filtering and voltage stabilizing module is used to further purify the power signal; the signal conditioning module is used to condition the amplified and conditioned pulse signal; the signal processing module is used to convert the conditioned pulse signal into sub-nanosecond square wave pulses with steep edges and accurate pulse widths; The signal output module is used to output a sub-nanosecond square wave pulse with a steep edge and an accurate pulse width.

4. The sub-nanosecond square-wave pulse generator according to claim 3, characterized in that, The first filtering and voltage regulation module includes: A first low-dropout regulator, a fifth resistor, a first transistor, a second inductor, and a fourth capacitor. Among them, the first end of the fifth resistor is connected to the base of the first transistor to form a first node, and the second end of the fifth resistor is connected to the input end of the first low-dropout regulator; The output end of the first low-dropout regulator is connected to the first end of the second inductor; The second end of the second inductor is connected to the -5V power supply; The first end of the fourth capacitor is connected to the output end of the first low-dropout regulator, and the second end of the fourth capacitor is connected to the seventh ground terminal; The collector of the first transistor is connected to the sixth ground terminal, and the emitter of the first transistor is connected to the first input end of the signal conditioning module to form a second node.

5. The sub-nanosecond square-wave pulse generator according to claim 3, characterized in that, The second filtering and voltage regulation module includes: A second low-dropout regulator, a ninth capacitor, and a third inductor. Among them, the input end of the second low-dropout regulator is connected to the +5V power supply through the third inductor, and the output end of the second low-dropout regulator is connected to the first input end of the signal processing module to form an eighth node; The first end of the ninth capacitor is connected to the input end of the second low-dropout regulator, and the second end of the ninth capacitor is connected to the eighth ground terminal.

6. The sub-nanosecond square wave pulse generator according to claim 4, wherein The signal conditioning module includes: A second transistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fifth capacitor, a sixth capacitor, and a switch. Among them, the first end of the sixth resistor serves as the first input end of the signal conditioning module and is connected to the second node, and the second end of the sixth resistor is connected to the first input end of the signal processing module to form a fourth node; The emitter of the second transistor is connected to the second node, the base of the second transistor is connected to the first end of the ninth resistor to form a fifth node, and the collector of the second transistor is connected to the second input end of the signal processing module to form a third node; The second end of the ninth resistor is connected to the third node through the eighth resistor; The first end of the fifth capacitor is connected to the fifth node, and the second end of the fifth capacitor is connected to the sixth ground terminal through the switch; The first end of the tenth resistor is connected to the first node, and the second end of the tenth resistor is connected to the first end of the sixth capacitor; The second end of the sixth capacitor is connected to the sixth ground terminal through the switch.

7. The sub-nanosecond square-wave pulse generator according to claim 6, wherein The signal processing module includes: A third transistor, a fourth transistor, a seventh resistor, a seventh capacitor, an eighth capacitor, an eleventh resistor, a tenth capacitor, and an eleventh capacitor. Among them, the base of the third transistor serves as the second input end of the signal processing module and is connected to the third node, the collector of the third transistor is connected to the sixth ground terminal, and the emitter of the third transistor is connected to the base of the fourth transistor; The emitter of the fourth transistor is connected to the first end of the eleventh resistor to form a sixth node; The second end of the eleventh resistor serves as the first input end of the signal processing module and is connected to the fourth node; The collector of the fourth transistor is connected to the first end of the seventh capacitor to form a seventh node; The second end of the seventh capacitor is connected to the first input end of the signal output module to form an eighth node; The eighth capacitor is connected in parallel across the two ends of the seventh capacitor; The first end of the tenth capacitor is connected to the fourth node, and the second end of the tenth capacitor is connected to the sixth ground terminal; The first end of the eleventh capacitor is connected to the fourth node, and the second end of the eleventh capacitor is connected to the sixth ground terminal.

8. A sub-nanosecond square-wave pulse generator according to claim 7, characterized in that, The signal output module includes: A fifth transistor, a twelfth resistor, a thirteenth resistor, and a fourteenth resistor. Among them, the emitter of the fifth transistor is connected to the sixth node, and the collector of the fifth transistor is connected to the first end of the twelfth resistor; The second end of the twelfth resistor serves as the first input end of the signal output module and is connected to the eighth node; The base of the fifth transistor is connected to the first end of the thirteenth resistor to form a ninth node; The second end of the thirteenth resistor is connected to the output end of the output unit; The first end of the fourteenth resistor is connected to the ninth node, and the second end of the fourteenth resistor is connected to the fourth node.

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