Signal delay adjustment method, signal delay adjustment device and storage medium

Abstract

The present application provides a signal delay adjustment method, a signal delay adjustment device, and a storage medium, which are applied to the chip field; the method includes: obtaining an initial delay value and an initial test result of a gear in a delay line; performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; the target delay value includes a reference delay value and a first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and a unit time interval; based on the target delay value and the updated test result, determining the target gear, and controlling the delay line to adjust to the target gear. This method can adjust the signal delay of the chip to reduce the bit error rate.

Description

Technical Field

[0001] The present application relates to the field of chips, and more specifically, to a signal delay adjustment method, a signal delay adjustment device, and a storage medium. Background Art

[0002] To achieve high-bandwidth, low-latency transmission between chips, high-speed data transmission requires precise control of data and clock signals at both the transmitter and receiver. To ensure stable data sampling, the receiver's sampling clock and data must maintain a certain phase relationship. Multi-chip interconnects often use a clock-associated scheme to help the receiver accurately recover data from the clock signal transmitted by the transmitter.

[0003] Currently, transceivers often require various delays to adjust the phase relationship between clock and data. The adjustable ranges of the delay unit are then iterated and tested to find the optimal sampling range. However, this method of iterating through each range assumes that the relationship between delay and range is linear or uniformly distributed. However, in actual implementation, there may be large nonlinear jumps between different delay ranges, making simple iterative methods unable to accurately locate the optimal sampling window. This can cause a deviation between the detection results and the actual situation, reducing the reliability of data sampling at the receiving end and increasing the bit error rate. Therefore, how to adjust the signal delay of the chip to reduce the bit error rate has become an urgent problem to be solved. Summary of the Invention

[0004] The present application provides a signal delay adjustment method, a signal delay adjustment device and a storage medium. The method can adjust the signal delay of a chip to reduce the bit error rate.

[0005] In a first aspect, a signal delay adjustment method is provided, which is applied to a chip; the method comprises:

[0006] Obtain the initial delay value and initial test results of the gear in the delay line;

[0007] Performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; wherein the number of the target delay values ​​is greater than the number of the initial delay values;

[0008] updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; wherein the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; and the reference delay value is determined based on the first delay value and a unit time interval;

[0009] Based on the target delay value and the updated test result, a target gear position is determined, and the delay line is controlled to be adjusted to the target gear position.

[0010] The above technical solution obtains the initial delay value and initial test result of the gear in the delay line; performs data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; updates the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value; the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to adjust to the target gear; which is different from the prior art in which the delay unit is determined. Compared with traversing and detecting the adjustable gears of the element to find the optimal sampling gear, the present application, through a comprehensive analysis of the gear detection results in different UIs, can update the invalid value in the current UI (the target detection result corresponding to the first delay value) when an invalid value appears in one UI but is not an invalid value in another UI, and obtain an updated detection result of the target delay value, thereby avoiding sampling inaccuracy caused by invalid values ​​in a single UI. Based on the updated detection results, the target gear is determined, which can ensure that the target gear is the optimal sampling phase position, thereby realizing reliable sampling of data, thereby reducing the bit error rate of the communication link under high-speed transmission, and improving the overall communication quality and system stability.

[0011] In addition, the method in this application is compatible with a variety of high-speed interconnection scenarios. Whether it is die-to-die (D2D) interconnection in a multi-chip package or a high-speed interface within a single chip, it can directly utilize the existing delay line hardware structure and only requires mapping and compensation algorithm implementation at the firmware or software level. The development and deployment costs are relatively low, and it has high portability and practical value.

[0012] In conjunction with the first aspect, in some possible implementations, updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value includes:

[0013] Determining whether a target test result corresponding to the reference delay value is a valid value;

[0014] If it is a valid value, determining the target test result corresponding to the reference delay value as the updated test result corresponding to the first delay value;

[0015] If it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

[0016] The above technical solution determines whether the target test result corresponding to the reference delay value is a valid value; if it is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; if it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value; this solution takes into account the actual situation that the delay adjustment range of the chip is greater than the length of one UI. Through comprehensive analysis of the gear detection results in different UIs, a "dead zone" area can appear in one UI, but when the other UI is a valid area, the "dead zone" area is compensated, which can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby improving the flexibility of the sampling clock phase selection and ensuring the accuracy of the target gear.

[0017] In combination with the first aspect and the above implementation manner, in some possible implementation manners, determining the target gear position based on the target delay value and the updated test result includes:

[0018] Traversing the update test results to determine a maximum sampling window;

[0019] selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window;

[0020] The target gear is determined based on the target sampling delay value.

[0021] The above technical solution traverses the updated test results, determines the maximum sampling window, selects the target sampling delay value from the target delay value based on the maximum sampling window, and determines the target gear position based on the target sampling delay value; by compensating the target test result of the target delay value and determining the updated test result, the number of invalid values ​​corresponding to the target delay value can be effectively reduced; on this basis, the target sampling delay value is determined in combination with the maximum sampling window in the target delay value, which can ensure the accuracy of the target sampling delay value and thus ensure the accuracy of the target gear position.

[0022] In combination with the first aspect and the above implementation manner, in some possible implementation manners, the method further includes: determining whether the starting delay value in the target delay value is within the candidate sampling window;

[0023] The selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window includes:

[0024] If the starting delay value is within the candidate sampling window, determining the target sampling delay value based on a first window length of the candidate sampling window and a second window length of the maximum sampling window;

[0025] If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0026] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value. By combining whether there is a candidate sampling window at the starting delay value in the target delay value, when there is a candidate sampling window, the target sampling delay value is comprehensively determined by combining the candidate sampling window and the maximum sampling window. This avoids the omission of the optimal sampling window due to the length of the sampling window when the optimal sampling window is located at the starting delay value, thereby ensuring the accuracy of the optimal sampling window positioning, thereby ensuring the accuracy of the target sampling delay value.

[0027] In combination with the first aspect and the foregoing implementation, in some possible implementations, determining the target sampling delay value based on the first window length of the candidate sampling window and the second window length of the maximum sampling window includes:

[0028] Determining a reference window length based on the second window length; wherein the reference window length is greater than or equal to half of the second window length;

[0029] If the first window length is less than or equal to the reference window length, determining the central delay value of the maximum sampling window as the target sampling delay value;

[0030] If the first window length is greater than the reference window length, a delay value that is a difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0031] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window; if the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the starting delay value is within the candidate sampling window, the reference window length is determined based on the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value; by An inference mechanism is proposed for the relationship between the candidate sampling window starting from the starting delay value of the target delay value and the gear position. Due to the finite width of the eye diagram, when a valid sampling window (candidate sampling window) is detected starting from 0 (the starting delay value of the target delay value) and the length of the candidate sampling window is greater than the reference window length, the candidate sampling window is the optimal sampling window in the target delay value. On this basis, the target sampling delay value is determined, which can reduce the dependence on the nonlinear relationship between the gear position and the delay value and the invalid value area corresponding to the target delay value, ensure the accuracy of the target sampling delay value, and thus improve the accuracy of the target gear position and reduce the bit error rate.

[0032] In combination with the first aspect and the above implementation, in some possible implementations, performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value includes:

[0033] Determining a target common divisor of the initial delay value;

[0034] Performing data expansion processing on the initial delay value with the target common divisor as a step size to obtain the target delay value;

[0035] Based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

[0036] The above technical solution performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0037] In combination with the first aspect and the above implementation manner, in some possible implementation manners, determining the target test result corresponding to the target delay value based on the initial test result and the initial delay value includes:

[0038] Determining a target difference between a first initial delay value and a second initial delay value; wherein the first initial delay value and the second initial delay value are used to indicate any adjacent delay values ​​of the initial delay values;

[0039] If the target difference is less than or equal to the preset difference, determining the reference test result as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; wherein the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value;

[0040] If the target difference is greater than a preset difference, an invalid value is determined as a target test result corresponding to the target delay value between the first initial delay value and the second initial delay value.

[0041] The above technical solution determines the target difference between the first initial delay value and the second initial delay value; if the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value, and the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; thereby, when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value can be directly supplemented, and the target detection result corresponding to the delay value with a smaller gap can be estimated; if the target difference is greater than the preset difference, the invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, the "dead zone" of the chip's adjustable delay is accurately determined by the target difference between the delay values; on this basis, the target detection result in the "dead zone" area is compensated to improve the capture capability of the sampling window, thereby improving the accuracy of the target gear.

[0042] In combination with the first aspect and the above implementations, in some possible implementations, obtaining the initial delay value of the gear in the delay line includes:

[0043] Determine the target unit for the initial gear;

[0044] Obtaining the accumulated delay value of the target unit and a second delay value corresponding to the initial gear position;

[0045] The sum of the accumulated delay value and the second delay value is determined as the initial delay value corresponding to the initial gear position; wherein the initial gear position is used to indicate any gear position in the delay line.

[0046] The above technical solution obtains the accumulated delay value of the target unit where the initial gear is located and the second delay value corresponding to the initial gear, and determines the sum of the accumulated delay value and the second delay value as the initial delay value corresponding to the initial gear; by determining the initial delay value of the initial gear in the delay value, the gear domain is converted to the time domain, and the mapping relationship between the gear and the delay value can be accurately determined.

[0047] In the second aspect, a signal delay adjustment device is provided, comprising a memory and a processor, the memory being used to store executable program code; the processor being used to call and run the executable program code from the memory, so that the signal delay adjustment device executes the signal delay adjustment method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0048] In a third aspect, a computer-readable storage medium is provided, which stores a computer program code. When the computer program code runs on a computer, the computer executes the signal delay adjustment method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0049] In a fourth aspect, a computer program product is provided, comprising: a computer program code, which, when executed on a computer, enables the computer to execute the signal delay adjustment method in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a schematic flow chart of a signal delay adjustment method provided in an embodiment of the present application;

[0051] Figure 2 is a schematic flow chart of a data expansion method provided in an embodiment of the present application;

[0052] Figure 3 This is a schematic diagram of the corresponding relationship between a delay value and a detection result provided in an embodiment of the present application;

[0053] Figure 4 is a schematic flow chart of a method for determining a target gear position provided in an embodiment of the present application;

[0054] Figure 5 This is a structural diagram of a signal delay adjustment device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will clearly and thoroughly describe the technical solutions in this application in conjunction with the accompanying drawings. In the description of the embodiments of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more than two.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0057] It is understandable that when transmitting data between chips at high speed, achieving high bandwidth and low latency, precise control of data and clock signals is required at both the transmitter and receiver. To ensure stable data sampling, the sampling clock at the receiver must maintain a certain phase relationship with the data.

[0058] In related technologies, multi-chip interconnects often use a clock-associated approach to help the receiver accurately recover data from the clock signal transmitted by the transmitter. However, in actual implementation, various delays are often required within the transceiver to adjust the phase relationship between the clock and data, and the adjustable taps of the delay line are traversed and tested to find the optimal sampling tap. This method of traversing each tap assumes that the relationship between delay and tap is linear or uniformly distributed. However, in actual implementation, there may be large nonlinear jumps between different delay taps, making it impossible for a simple traversal method to accurately locate the optimal sampling window. This can cause a deviation between the detection results and the actual situation, thereby reducing the reliability of receiving a single pair of data samples and increasing the bit error rate.

[0059] It should be noted that the gear position in the delay line is used to adjust the delay amount, that is, different gear positions in the delay line correspond to different delay amounts.

[0060] In multi-chip interconnect architectures, an embedded clock (Embedded Clock) solution is often used to ensure data and clock synchronization. This solution sends the clock signal from the transmitter along with the data to the receiver, where the appropriate sampling clock is recovered. Accurate data sampling at the receiver typically requires fine-grained adjustment of the phase relationship between the internal clock and data within the transceiver. Therefore, one or more adjustable delay lines are often implemented in hardware, allowing the arrival time of the clock or data to be altered by selecting different discrete "gears."

[0061] However, in actual implementation, the delay line does not exhibit linear increments between gears, especially when there are significant jumps between adjacent gears. Simply traversing the gears will result in an inability to accurately locate the optimal sampling gear, leading to a higher bit error rate.

[0062] In view of this, the present application provides a signal delay adjustment method, a signal delay adjustment device and a storage medium. The method can adjust the signal delay of the chip to reduce the bit error rate. Figure 1 This is a schematic flowchart of a signal delay adjustment method provided in an embodiment of the present application.

[0063] For example, Figure 1 The signal delay adjustment method shown is applied to the chip.

[0064] For example, Figure 1 As shown, the signal delay adjustment method 100 includes the following processes:

[0065] S110, obtaining the initial delay value and initial test result of the gear in the delay line.

[0066] For example, in a multi-chip interconnection architecture, the microcontroller unit (MCU) of the main control chip in the multi-chip usually acts as the controller to control the signal delay adjustment process. Each chip has a transmitting end and a receiving end. The MCU controls the multi-chip to start initialization, that is, any two chips start sending the first stage signal, and the process of the receiving end is controlled by the MCU, thereby completing the signal delay adjustment.

[0067] For example, a chip may appear in different forms in different application scenarios. For example, it may appear as a chip in a chip application scenario, as a bare die in a bare die application scenario, and as a chiplet (or chiplet) in a chiplet application scenario.

[0068] For example, the transmit clock and associated clock for all lanes on the transmitter side are output from the same internal phase-locked loop. Specifically, the clock signal is distributed to the transmit clock and each lane by the clock distribution unit. The receiver side receives the associated clock, which, after entering the chip, also passes through different clock distribution units and enters different lanes to serve as the sampling clock for each channel. This ensures that the clock signals of all channels on the transmitter and receiver side have the same clock source, ensuring clock synchronization.

[0069] In addition, each channel is equipped with an adjustable delay line, which can make fine delay adjustments to the clock signal, thereby adjusting the phase relationship between the sampling clock and data.

[0070] As you can understand, a delay line is a component or device used to control the delay time of an electrical signal. It can delay the arrival of an input signal by a certain amount of time before outputting it. A delay line has multiple settings, each corresponding to a different delay value.

[0071] Exemplarily, the initial delay value and initial test result of the gear position in the delay line are obtained. The delay line includes multiple gear positions, each of which corresponds to an initial delay value. That is, the delay line can adjust the delay value of the control signal by adjusting the gear position. Each gear position corresponds to an initial test result of the communication link, and the initial test result is used to indicate the communication quality of the communication link. It is understandable that the gear position in the delay line has a corresponding relationship with the initial delay value, that is, each gear position corresponds to an initial delay value. The gear position in the delay line has a corresponding relationship with the initial test result, that is, each gear position corresponds to an initial test result, and each initial delay value corresponds to an initial test result.

[0072] For example, the initial test result may be a bit error rate detection result of the communication link. When the bit error rate of the communication link is less than or equal to a preset bit error rate, the initial test result corresponding to the gear position is determined to be 1; when the bit error rate of the communication link is greater than the preset bit error rate, the initial test result corresponding to the gear position is determined to be 0. It will be understood that the initial test result shown above is only one possible application method in actual applications. The specific representation method of the initial test result can be determined based on actual circumstances and is not specifically limited here.

[0073] S120 , performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value.

[0074] Exemplarily, the number of target delay values ​​is greater than the number of initial delay values, the number of target test results is greater than the number of initial test results, and each target delay value in the target delay values ​​corresponds to a target test result.

[0075] Exemplarily, a target common divisor of the initial delay value is determined, and data expansion processing is performed on the initial delay value with the target common divisor as a step size to obtain a target delay value, and based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

[0076] For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps; the initial test results include test result 0 corresponding to 0ps, test result 1 corresponding to 1.1ps, test result 1 corresponding to 2.2ps, test result 1 corresponding to 3.3ps, test result 1 corresponding to 4.4ps, test result 1 corresponding to 5.5ps, test result 1 corresponding to 6.6ps, test result 0 corresponding to 7.7ps, and test result 0 corresponding to 12.7.

[0077] Furthermore, data expansion processing is performed on the initial delay value to obtain target delay values ​​including 0ps, 0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps...12.1ps, 12.2ps, 12.3ps, 12.4ps, 12.5ps, 12.6ps, and 12.7ps. In addition, each target delay value corresponds to a target detection result.

[0078] Illustratively, the target detection results corresponding to delay values ​​within the target delay values ​​that overlap with the initial delay values ​​are equal to the initial detection results corresponding to the initial delay values. For example, the target detection result for a target delay value of 2.2 ps is the initial detection result 1 corresponding to the initial delay value of 2.2 ps. The target detection results corresponding to delay values ​​within the target delay values ​​that do not overlap with the initial delay values ​​are determined by reference to the initial detection results of adjacent initial delay values. For example, the target detection results corresponding to target delay values ​​from 2.3 ps to 3.2 ps are 1 (the initial detection result corresponding to the initial delay value of 2.2 ps, or the initial detection result corresponding to the initial delay value of 3.3 ps).

[0079] Of course, if the target difference between adjacent initial delay values ​​is greater than a preset difference, the target detection results corresponding to the delay values ​​between the adjacent initial delay values ​​are determined to be invalid values. For example, the invalid value can be represented by 2. For example, if the target difference between the target delay values ​​of 7.8 ps and 12.6 ps is greater than 1.1 ps, the target detection results corresponding to the target delay values ​​of 7.8 ps to 12.6 ps are all determined to be invalid values.

[0080] Optionally, the preset difference may be 1.1 ps.

[0081] Optionally, the target detection result includes a valid value and an invalid value, and the valid value can be 0 or 1.

[0082] The above technical solution performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0083] S130 , updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value.

[0084] Exemplarily, the target delay value includes a reference delay value and a first delay value; the target test result corresponding to the first delay value is an invalid value; and the reference delay value is determined by the first delay value and the unit time interval.

[0085] For example, a unit interval (UI) is the length of one bit period of a signal, and the length of a UI is half the signal period. Specifically, the length of the UI is determined based on the signal transmission rate, i.e., the length of the UI = 1 / (2f), where f is the signal transmission rate.

[0086] It should be noted that the frequency of modern high-speed interfaces is very high, and the chip's delay adjustment range often exceeds the length of a single UI. If the delay line experiences a large jump or "dead zone," it may be impossible to find the ideal sampling point in some UIs, but stable sampling can be achieved in another UI. If you rely solely on test results in a single UI, you may ignore more feasible sampling intervals, thus losing the opportunity to further optimize reception quality. A "dead zone" refers to an area within a certain UI where poor signal quality (such as low signal amplitude, high noise, severe jitter, etc.) makes it impossible to accurately sample or detect valid data. The target test result corresponding to the target delay value in the "dead zone" is invalid.

[0087] To avoid the problem of not finding the ideal sampling point for test results under a single UI, "dead zone" detection results can be compensated across UIs. Specifically, if a "dead zone" appears within the current UI range but not in another UI, the detection results of multiple UIs are combined and interpolated or compensated to improve the capture of the sampling window.

[0088] It can be understood that the delay value in the “dead zone” area is the first delay value.

[0089] Exemplarily, the target delay value includes a reference delay value and a first delay value. The reference delay value is a delay value that is n UIs apart from the first delay value. Because the first delay value is within the "dead zone," the target test result corresponding to the first delay value is invalid, while the target test result corresponding to the reference delay value may be a valid value (0 or 1). Of course, the target test result corresponding to the reference delay value may also be invalid. Furthermore, by performing comprehensive compensation based on the test results of multiple UIs, the target test result corresponding to the target delay value can be updated to obtain an updated test result corresponding to the target delay value.

[0090] S140 , determining a target gear position based on the target delay value and the updated test result, and controlling the delay line to adjust to the target gear position.

[0091] For example, a sampling window is determined based on updated test results, a target sampling delay value is selected from the target delay values ​​based on the sampling window, a target gear is determined based on the target sampling delay value, and the delay line is controlled to adjust to the target gear. This avoids offsets caused by nonlinear or uneven distributions, accurately maps continuous delay values ​​measured or calculated in real time to the nearest discrete gear (target gear), and facilitates configuration and implementation in hardware systems.

[0092] It is understandable that when the target gear is determined, the target gear is set to the communication link of the receiving chip to obtain the optimal sampling phase setting, thereby adjusting the signal delay of the chip, improving the stability of the link and reducing the bit error rate.

[0093] Exemplarily, the test results are traversed and updated to determine a maximum sampling window, and based on the maximum sampling window, a target sampling delay value is selected from the target delay values, and based on the target sampling delay value, a target gear is determined.

[0094] In one example, when determining the updated test results corresponding to the target delay value, the maximum sampling window in the target delay value is determined by traversing the updated test results, and the central delay value of the maximum sampling window is determined. The central delay value is determined as the target sampling delay value, and then the target gear corresponding to the target sampling delay value is determined.

[0095] Exemplarily, the center delay value is used to indicate the delay value corresponding to the center position of the maximum sampling window.

[0096] The above technical solution traverses the updated test results, determines the maximum sampling window, selects the target sampling delay value from the target delay value based on the maximum sampling window, and determines the target gear position based on the target sampling delay value; by compensating the target test result of the target delay value and determining the updated test result, the number of invalid values ​​corresponding to the target delay value can be effectively reduced; on this basis, the target sampling delay value is determined in combination with the maximum sampling window in the target delay value, which can ensure the accuracy of the target sampling delay value and thus ensure the accuracy of the target gear position.

[0097] In order to improve the accuracy of the target sampling delay value, it should also be considered whether the candidate sampling window starting from 0 is the optimal sampling window. Due to the effectiveness of the eye width of the eye diagram, when the candidate sampling window is larger than half of the maximum sampling window, the candidate sampling window is the optimal sampling window in the eye diagram.

[0098] In another example, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value in the target delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value in the target delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value, and the target gear is determined based on the target sampling delay value.

[0099] For example, determine whether there is a candidate sampling window starting from 0 in the target delay value. When there is no candidate sampling window starting from 0 in the target delay value, the maximum sampling window in the target delay value is the optimal sampling window, and the central delay value of the maximum sampling window is determined as the target sampling delay value; when there is a candidate sampling window starting from 0 in the target delay value, the optimal sampling window between the candidate sampling window and the maximum sampling window is determined according to the length of the candidate sampling window and the length of the maximum sampling window. On this basis, the target sampling delay value is determined, thereby determining the target gear position, which can ensure the accuracy of the target gear position.

[0100] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window. If the starting delay value is within the candidate sampling window, the target sampling delay value is determined based on the first window length of the candidate sampling window and the second window length of the maximum sampling window. If the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value. By combining whether there is a candidate sampling window at the starting delay value in the target delay value, when there is a candidate sampling window, the target sampling delay value is comprehensively determined by combining the candidate sampling window and the maximum sampling window. This avoids the omission of the optimal sampling window due to the length of the sampling window when the optimal sampling window is located at the starting delay value, thereby ensuring the accuracy of the optimal sampling window positioning, thereby ensuring the accuracy of the target sampling delay value.

[0101] Furthermore, if the starting delay value in the target delay value is within the candidate sampling window, the reference window length is determined based on the second window length, and the reference window length is greater than or equal to half of the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0102] For example, when there is a candidate sampling window starting from 0 in the target delay value, half of the maximum sampling window length is determined as the reference window length, and it is determined whether the first window length of the candidate sampling window is greater than the reference window length. When the first window length of the candidate sampling window is less than or equal to the reference window length, the maximum sampling window is determined to be the optimal sampling window, and the center delay value of the maximum sampling window is determined as the target sampling delay value; when the first window length of the candidate sampling window is greater than the reference window length, the candidate sampling window is determined to be the optimal sampling window, and the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value, thereby ensuring the accuracy of the target sampling delay value on the basis of ensuring the accuracy of the optimal sampling window positioning.

[0103] The above technical solution obtains the initial delay value and initial test result of the gear in the delay line; performs data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; updates the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value; the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to adjust to the target gear; which is different from the prior art in which the delay unit is determined. Compared with traversing and detecting the adjustable gears of the element to find the optimal sampling gear, the present application, through a comprehensive analysis of the gear detection results in different UIs, can update the invalid value in the current UI (the target detection result corresponding to the first delay value) when an invalid value appears in one UI but is not an invalid value in another UI, and obtain an updated detection result of the target delay value, thereby avoiding sampling inaccuracy caused by invalid values ​​in a single UI. Based on the updated detection results, the target gear is determined, which can ensure that the target gear is the optimal sampling phase position, thereby realizing reliable sampling of data, thereby reducing the bit error rate of the communication link under high-speed transmission, and improving the overall communication quality and system stability.

[0104] In addition, the method in this application is compatible with a variety of high-speed interconnection scenarios. Whether it is die-to-die (D2D) interconnection in a multi-chip package or a high-speed interface within a single chip, it can directly utilize the existing delay line hardware structure and only requires mapping and compensation algorithm implementation at the firmware or software level. The development and deployment costs are relatively low, and it has high portability and practical value.

[0105] Compared with the prior art method of traversing the gears one by one to find the optimal sampling gear, the present application maps the link information from the gear domain to the absolute time domain (determines the initial delay value of the gear in the delay line and performs data expansion processing), and compensates the link detection results of the "dead zone" area in the absolute time domain after data expansion processing through the link detection results corresponding to other UIs, thereby realizing data compensation for the situation where a "dead zone" area appears in one UI but is a valid area in another UI, and can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby obtaining an updated test result of the target delay value; on this basis, the situation where a candidate window exists in the initial phase is judged (the candidate sampling window starting from 0 in the target delay value is judged), ensuring the accuracy of the optimal sampling window, improving the accuracy of the optimal sampling point (target sampling delay value), and thus achieving reliable sampling of data and improving the overall communication quality and system stability.

[0106] It should be noted that the method of the following embodiment can be used as Figure 1 The refinement of step S110 in the illustrated embodiment.

[0107] Exemplarily, all gears in the delay line are traversed to determine the initial test results of the communication link corresponding to each gear. Specifically, taking the delay line adjusted to an initial gear (the initial gear is any gear in the delay line) as an example, the test results of the communication link corresponding to the initial gear are determined, and the bit error rate of the communication link within a preset time period is determined. When the bit error rate of the communication link within the preset time period is less than or equal to the preset bit error rate, the initial test result of the initial gear is determined to be 1; when the bit error rate of the communication link within the preset time period is greater than the preset bit error rate, the initial test result of the initial gear is determined to be 0.

[0108] Exemplarily, all gears in the delay line are traversed to determine the initial delay value corresponding to each gear. Specifically, a target unit for the initial gear is determined, the cumulative delay value of the target unit and the second delay value corresponding to the initial gear are obtained, and the sum of the cumulative delay value and the second delay value is determined as the initial delay value corresponding to the initial gear.

[0109] It should be noted that the initial gear is used to indicate any gear in the delay line. Due to the limitation of the delay line structure, every 8 gears form a structural unit, and the overall delay value corresponding to each structural unit is the same; for example, the overall delay value can be 12ps.

[0110] For example, the expression of the initial delay value can be expressed as follows:

[0111]

[0112] Wherein, n represents the initial gear position; Indicates the initial delay corresponding to the initial gear; Indicates that n / 8 is rounded down to the nearest integer and is used to calculate the target unit of the initial gear; t represents the overall delay value of the structural unit; n mod 8 represents the remainder when n is divided by 8 (range 0 to 7); Indicates a table lookup operation, and selects the corresponding second delay value according to the remainder. For example, when When , the corresponding second delay value is t3.

[0113] When determining the target unit of the initial gear, the cumulative delay value of the target unit is determined by multiplying the target unit and the overall delay value of the structural unit ( ); and determine the second delay value corresponding to the initial gear according to the table lookup operation, and determine the sum of the accumulated delay value and the second delay value as the initial delay value corresponding to the initial gear.

[0114] The above technical solution obtains the cumulative delay value of the target unit where the initial gear is located and the second delay value in the target unit, and determines the sum of the cumulative delay value and the second delay value as the initial delay value corresponding to the initial gear; by determining the initial delay value of the initial gear in the delay value, the gear domain is converted to the time domain, and the mapping relationship between the gear and the delay value can be accurately determined.

[0115] Figure 2 This is a schematic flowchart of a data expansion method provided in an embodiment of the present application.

[0116] For example, Figure 2 As shown, the data expansion method 200 includes the following processes S210-S260, and steps S210-S260 can be used as Figure 1 The refinement of step S120 in the illustrated embodiment.

[0117] S210: Determine a target common divisor of the initial delay value.

[0118] Exemplarily, when the initial delay value is determined, an initial common divisor of the initial delay value is determined, and a target common divisor is obtained by selecting from the initial common divisors.

[0119] Optionally, the target common divisor may be the greatest common divisor of the initial delay values, or the target common divisor may be the least common divisor of the initial delay values. The target common divisor may be determined based on actual conditions and is not specifically limited here.

[0120] S220 , performing data expansion processing on the initial delay value with the target common divisor as a step size to obtain a target delay value.

[0121] For example, by performing data expansion on the initial delay values ​​with the target common divisor as a step size, target delay values ​​can be obtained, and the number of target delay values ​​is greater than the number of initial delay values. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps, and 12.7ps, and the initial delay values ​​are expanded with a step size of 0.1ps to obtain target delay values ​​including 0ps, 0.1ps, 0.2ps, 0.3ps ... 12.5ps, 12.6ps, and 12.7ps.

[0122] Furthermore, the initial delay value is subjected to data expansion processing with the target common divisor as a step size to obtain the target delay value, and then the target test result corresponding to the target delay value is determined based on the initial test result and the initial delay value.

[0123] The above technical solution performs data expansion processing on the initial delay value with the target common divisor of the initial delay value as the step size to obtain the target delay value, and determines the target test result corresponding to the target delay value based on the initial test result and the initial delay value; by performing data expansion on the initial delay value, the nonlinear jump position of the delay value can be accurately determined, and on this basis, the accuracy of determining the optimal sampling window can be improved, thereby improving the accuracy of the target gear position.

[0124] S230: Determine a target difference between the first initial delay value and the second initial delay value.

[0125] Exemplarily, the first initial delay value and the second initial delay value are used to indicate any adjacent delay values ​​among the initial delay values, and a target difference between the first initial delay value and the second initial delay value is determined. The target difference is used to indicate the absolute value of the difference between the first initial delay value and the second initial delay value. For example, if the initial delay values ​​include 0 ps, ​​1.1 ps, 2.2 ps, 3.3 ps, 4.4 ps, 5.5 ps, 6.6 ps, 7.7 ps, and 12.7 ps, and the first initial delay value is 1.1 ps and the second initial delay value is 2.2 ps, then the target difference is 1.1.

[0126] S240, determining whether the target difference is greater than a preset difference; if not, executing S250; if so, executing S260.

[0127] Optionally, the preset difference may be 1.1, 1.2, etc. The preset difference may be determined according to actual conditions and is not specifically limited here.

[0128] Exemplarily, a target difference between the first initial delay value and the second initial delay value is determined, and whether the target difference is greater than a preset difference is determined, so that when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value is supplemented; when the target difference is greater than the preset difference, an invalid value is determined as the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value.

[0129] S250: Determine the reference test result as a target test result corresponding to a target delay value between the first initial delay value and the second initial delay value.

[0130] Exemplarily, the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value. For example, the reference test result is the initial test result corresponding to the first initial delay value; or the reference test result is the initial test result corresponding to the second initial delay value.

[0131] Exemplarily, when the target difference is less than or equal to the preset difference, the reference test result is determined as the target detection result corresponding to the target delay value between the first initial delay value and the second initial delay value. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps and 12.7ps, the first initial delay value is 1.1ps, the second initial delay value is 2.2ps, and the target difference is equal to the preset difference. The reference test result is the initial test result corresponding to the first initial delay value; when the expansion step is 0.1, the target delay value between the first initial delay value and the second initial delay value includes 1.2ps. , 1.3ps, 1.4ps, 1.5ps, 1.6ps, 1.7ps, 1.8ps, 1.9ps, 2ps and 2.1ps, when the initial test result corresponding to the first initial delay value is 1, the target test results corresponding to the target delay values ​​between the first initial delay value and the second initial delay value (1.2ps, 1.3ps, 1.4ps, 1.5ps, 1.6ps, 1.7ps, 1.8ps, 1.9ps, 2ps and 2.1ps) are all 1.

[0132] S260: Determine the invalid value as a target test result corresponding to a target delay value between the first initial delay value and the second initial delay value.

[0133] Exemplarily, when the target difference is greater than a preset difference, an invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value. For example, the initial delay values ​​include 0ps, 1.1ps, 2.2ps, 3.3ps, 4.4ps, 5.5ps, 6.6ps, 7.7ps, and 12.7ps, the first initial delay value is 7.7ps, the second initial delay value is 12.7ps, and the target difference is greater than the preset difference. The reference test result is the initial test result corresponding to the first initial delay value. When the expansion step size is 0.1, the target delay values ​​between the first initial delay value and the second initial delay value include 7.8ps, 7.9ps, 8ps, 8.1ps, ..., 12.7ps. In this case, the target test results corresponding to the target delay values ​​between the first initial delay value and the second initial delay value (7.8ps, 7.9ps, 8ps, 8.1ps, ..., 12.7ps) are all invalid values.

[0134] The above technical solution determines the target difference between the first initial delay value and the second initial delay value; if the target difference is less than or equal to the preset difference, the reference test result is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value, and the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; thereby, when the target difference is less than or equal to the preset difference, the target detection result corresponding to the target delay value can be directly supplemented, and the target detection result corresponding to the delay value with a smaller gap can be estimated; if the target difference is greater than the preset difference, the invalid value is determined as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, the "dead zone" of the chip's adjustable delay is accurately determined by the target difference between the delay values; on this basis, the target detection result in the "dead zone" area is compensated to improve the capture capability of the sampling window, thereby improving the accuracy of the target gear.

[0135] Figure 3 This is a schematic diagram of the corresponding relationship between a delay value and a detection result provided in an embodiment of the present application.

[0136] For example, Figure 3 (a) in the figure shows the corresponding relationship between the initial delay value and the initial detection result. Figure 3 (b) in FIG. 5 is a schematic diagram showing the corresponding relationship between the target delay value and the target detection result.

[0137] For example, Figure 3 The correspondence between the delay value and the detection result is explained based on the correspondence between the time axis of the delay value and the detection result on the time axis.

[0138] For example, Figure 3As shown in (a), the gears of the delay line include 0, 1, 2, 3, 4, 5, 6, 7 and 8; the initial delay value corresponding to gear 0 is 0ps, the initial delay value corresponding to gear 1 is 1.1ps, the initial delay value corresponding to gear 2 is 2.2ps, the initial delay value corresponding to gear 3 is 3.3ps, the initial delay value corresponding to gear 4 is 4.4ps, the initial delay value corresponding to gear 5 is 5.5ps, the initial delay value corresponding to gear 6 is 6.6ps, and the initial delay value corresponding to gear 7 is 7.7. ps, the initial delay value corresponding to gear 8 is 12.7ps; the initial detection result of the communication link in gear 0 is 0, the initial detection result of the communication link in gear 1 is 1, the initial detection result of the communication link in gear 2 is 1, the initial detection result of the communication link in gear 3 is 1, the initial detection result of the communication link in gear 4 is 1, the initial detection result of the communication link in gear 5 is 1, the initial detection result of the communication link in gear 6 is 1, the initial detection result of the communication link in gear 7 is 0, and the initial detection result of the communication link in gear 8 is 0.

[0139] For example, Figure 3 As shown in (b), the initial delay value is expanded with a step size of 0.1, and the target delay values ​​include 0ps, 0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps...12.1ps, 12.2ps, 12.3ps, 12.4ps, 12.5ps, 12.6ps, 12.7ps. The target delay value includes the initial delay value. Any adjacent delay value in the initial delay value is used as a reference point. Any adjacent delay value in the initial delay value is the first initial delay value. The target difference between the first initial delay value and the second initial delay value is determined, and whether the target difference is greater than a preset difference is determined. When the target difference is less than or equal to the preset difference, the initial detection result corresponding to the smaller delay value between the first initial delay value and the second initial delay value is determined as the target detection result of the target delay value between the first initial delay value and the second initial delay value; when the target difference is greater than the preset difference, the invalid value is determined as the target detection result of the target delay value between the first initial delay value and the second initial delay value.

[0140] For example, the preset difference is 1.1, and the target detection result of the target delay value between 0ps and 1.1ps (0.1ps, 0.2ps, 0.3ps, 0.4ps, 0.5ps, 0.6ps, 0.7ps, 0.8ps, 0.9ps, 1ps) is determined to be 0 (the initial detection result corresponding to 0); the target detection result of the target delay value between 1.1ps and 2.2ps is determined to be 1 (the initial detection result corresponding to 1.1ps); the target detection result of the target delay value between 2.2ps and 3.3ps is determined to be 1 (the initial detection result corresponding to 2.2ps). the target detection result for the target delay value between 3.3ps and 4.4ps is determined to be 1 (the initial detection result corresponding to 3.3ps); the target detection result for the target delay value between 4.4ps and 5.5ps is determined to be 1 (the initial detection result corresponding to 4.4ps); the target detection result for the target delay value between 5.5ps and 6.6ps is determined to be 1 (the initial detection result corresponding to 5.5ps); the target detection result for the target delay value between 6.6ps and 7.7ps is determined to be 1 (the initial detection result corresponding to 6.6ps).

[0141] The difference between 7.7 ps and 12.7 ps is greater than the preset difference of 1.1, so the target detection result for the target delay value between 7.7 ps and 12.7 ps is determined to be 2 (an invalid value). It is understood that setting the invalid value to 2 is only one possible method in practical applications. The specific method for representing the invalid value can be determined based on actual circumstances and is not specifically limited here.

[0142] It should be noted that the method of the following embodiment can be used as Figure 1 The refinement of step S130 in the illustrated embodiment.

[0143] Exemplarily, determine whether the target test result corresponding to the reference delay value is a valid value. When the target detection result corresponding to the reference delay value is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; when the target detection result corresponding to the reference delay value is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

[0144] It can be understood that the target delay value includes the reference delay value and the first delay value; the delay value in the "dead zone" area is the first delay value, and the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval, and the reference delay value is a delay value with a length of n UIs separated from the first delay value, and the target detection result corresponding to the reference delay value may be a valid value (0 or 1). Of course, the target detection result corresponding to the reference delay value may also be an invalid value.

[0145] Exemplarily, when the target detection result is a valid value, the target detection result can be 0, or the target detection result can be 1; when the target detection result is an invalid value, the current target delay value is used to indicate that the delay line cannot accurately detect a valid result, resulting in the target detection result being an invalid value.

[0146] It should be noted that compensation is performed through the detection results of multiple UIs to update the target detection result corresponding to the target delay value, and then the updated detection result corresponding to the target delay value is obtained. The number of sampling windows in the updated detection result may be greater than the number of sampling windows in the target detection result.

[0147] Specifically, for the first delay value in the "dead zone" area, determine whether the target detection result corresponding to the reference delay value that is n UIs away from the first delay value is a valid value. When the target detection result corresponding to the reference delay value is a valid value, the target detection result corresponding to the reference delay value is determined as the updated detection result corresponding to the first delay value. When the target detection result corresponding to the reference delay value is an invalid value, the target detection result corresponding to the first delay value is determined as the updated detection result corresponding to the first delay value. For the third delay value in the valid area (the area of ​​the target delay value excluding the "dead zone"), the target detection result corresponding to the third delay value is determined as the updated detection result corresponding to the third delay value.

[0148] The above technical solution determines whether the target test result corresponding to the reference delay value is a valid value; if it is a valid value, the target test result corresponding to the reference delay value is determined as the updated test result corresponding to the first delay value; if it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value; this solution takes into account the actual situation that the delay adjustment range of the chip is greater than the length of one UI. Through comprehensive analysis of the gear detection results in different UIs, a "dead zone" area can appear in one UI, but when the other UI is a valid area, the "dead zone" area is compensated, which can avoid the sampling inaccuracy caused by the "dead zone" area in a single UI, thereby improving the flexibility of the sampling clock phase selection and ensuring the accuracy of the target gear.

[0149] Figure 4 This is a schematic flowchart of a method for determining a target gear provided in an embodiment of the present application.

[0150] For example, Figure 4 As shown, the target gear determination method 400 includes the following processes S410-S480, and steps S410-S480 can be used as Figure 1 The refinement of step S140 in the illustrated embodiment.

[0151] S410, traverse and update the test results to determine the maximum sampling window.

[0152] Exemplarily, when the updated test results corresponding to the target delay value are determined, the updated test results are traversed to determine the initial sampling windows, and the largest one among the initial sampling windows is determined as the maximum sampling window.

[0153] Exemplarily, the maximum sampling window is used to indicate a sampling window with the largest window length in the initial sampling windows.

[0154] It can be understood that the sampling window refers to the optimal time interval selected by the receiver for capturing data within a UI.

[0155] S420 , determining whether the starting delay value in the target delay value is within the candidate sampling window; if not, executing S430 ; if so, executing S440 .

[0156] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value is within the candidate sampling window, it indicates that the starting delay value exists in the sampling window.

[0157] Exemplarily, the candidate sampling window is used to indicate a sampling window in the target delay value.

[0158] It's important to note that in digital communications, an eye diagram is a graphical representation used to assess signal quality. An eye diagram is formed by superimposing signal waveforms from multiple bit periods, giving it the appearance of an eye, hence the name. The eye width refers to the horizontal size of the eye opening, or the distance from the left to the right side of the eye. The eye width reflects the signal's temporal stability and timing tolerance. A larger eye width means more time margin around the sampling point, making it easier for the receiver to capture the signal at the correct time, thereby improving communication reliability.

[0159] Exemplarily, the sampling window can be located at any position in the eye diagram. Since the length of the sampling window is limited by the width of the eye diagram, by determining whether the starting delay value is within the candidate sampling window and confirming the candidate sampling window, the candidate sampling window where the starting delay value is located is avoided from being ignored, thereby ensuring the accuracy of the target sampling delay value.

[0160] S430: Determine the central delay value of the maximum sampling window as the target sampling delay value.

[0161] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value in the target delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0162] Exemplarily, the center delay value is used to indicate the delay value at the center position of the maximum sampling window. Specifically, the center position of the maximum sampling window is determined, and the delay value at the center position is determined as the center delay value.

[0163] S440: Determine a reference window length based on the second window length.

[0164] Exemplarily, it is determined whether the starting delay value in the target delay value is within the candidate sampling window. When the starting delay value in the target delay value is within the candidate sampling window, the reference window length is determined based on the second window length of the maximum sampling window.

[0165] For example, half of the second window length of the maximum sampling window is determined as the reference window length.

[0166] S450, determine whether the first window length is greater than the reference window length; if not, execute S460; if so, execute S470.

[0167] Exemplarily, based on the second window length of the maximum sampling window, the reference window length is determined, it is determined whether the first window length of the candidate sampling window is greater than the reference window length, and the target sampling delay value is determined based on the comparison result of the first window length of the candidate sampling window and the reference window length.

[0168] S460: Determine the central delay value of the maximum sampling window as the target sampling delay value.

[0169] Exemplarily, when the first window length of the candidate sampling window is less than or equal to the reference window length, the central delay value of the maximum sampling window is determined as the target sampling delay value.

[0170] S470 : Determine the difference between the upper edge delay value of the candidate sampling window and the reference window length as the target sampling delay value.

[0171] Exemplarily, when the first window length of the candidate sampling window is greater than the reference window length, the difference delay value between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

[0172] It should be noted that the candidate sampling window includes an upper edge delay value and a lower edge delay value, and the upper edge delay value is greater than the lower edge delay value. The delay value of the difference between the upper edge delay value of the candidate sampling window and the reference window length is a starting delay value greater than the target delay value and less than the delay value of the upper edge delay value.

[0173] For example, the candidate sampling window is [0, 1.1 ps], the upper edge delay value of the candidate sampling window is 1.1 ps, the lower edge delay value of the candidate sampling window is 0, and when the reference window length is 0.5 ps, the target sampling delay value is 0.6 ps.

[0174] S480: Determine a target gear position based on the target sampling delay value.

[0175] Exemplarily, when the target sampling delay value is determined, the target sampling delay value is converted into a gear position to obtain a target gear position.

[0176] It is understandable that the target sampling delay value is used to indicate the optimal sampling point in the target delay value; however, adjusting the delay value through the delay line cannot accurately adjust it to the optimal sampling point. Therefore, by determining the gear position closest to the optimal sampling point and determining the gear position as the target gear position, the control delay value is adjusted to the target gear position. This can ensure that the adjusted communication link has a lower bit error rate during data transmission, while improving communication quality and system stability.

[0177] For example, the target gear position can be expressed as follows:

[0178]

[0179] Among them, Tap represents the target gear position, represents the target sampling delay value; t represents the overall delay value of the structural unit; Express Round down to the nearest integer, used to calculate the target sampling delay value. Indicates mapping continuous value x to discrete labels The closest value in ; for example, when x is closest to hour, The value of ; Indicates table lookup operation, select the corresponding value gear according to the remainder. For example, when , the corresponding numerical gear is 3.

[0180] When determining the target sampling delay value, the large structural unit of the target sampling delay value is determined by the overall delay value of the structural unit ( ), each large structure unit contains 8 gears. The total number of gears accumulated before the large structure unit is determined by multiplying the large structure unit by 8; and the number of gears in the structure unit where the target sampling delay value is located is determined according to the table lookup operation, and the sum of the total number of gears and the number of gears in the structure unit is determined as the target gear corresponding to the target sampling delay value.

[0181] The above technical solution determines whether the starting delay value in the target delay value is within the candidate sampling window; if the starting delay value is outside the candidate sampling window, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the starting delay value is within the candidate sampling window, the reference window length is determined based on the second window length; if the first window length is less than or equal to the reference window length, the center delay value of the maximum sampling window is determined as the target sampling delay value; if the first window length is greater than the reference window length, the difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value; by An inference mechanism is proposed for the relationship between the candidate sampling window starting from the starting delay value of the target delay value and the gear position. Due to the finite width of the eye diagram, when a valid sampling window (candidate sampling window) is detected starting from 0 (the starting delay value of the target delay value) and the length of the candidate sampling window is greater than the reference window length, the candidate sampling window is the optimal sampling window in the target delay value. On this basis, the target sampling delay value is determined, which can reduce the dependence on the nonlinear relationship between the gear position and the delay value and the invalid value area corresponding to the target delay value, ensure the accuracy of the target sampling delay value, and thus improve the accuracy of the target gear position and reduce the bit error rate.

[0182] It should be understood that the above examples are intended to help those skilled in the art understand the embodiments of the present application, and are not intended to limit the embodiments of the present application to the specific numerical values ​​or specific scenarios illustrated. Those skilled in the art can obviously make various equivalent modifications or variations based on the above examples, and such modifications or variations also fall within the scope of the embodiments of the present application.

[0183] Combined with the above Figures 1 to 4 The signal delay adjustment method provided by the embodiment of the present application is described in detail; Figure 5 The signal delay adjustment device embodiment of the present application is described in detail. It should be understood that the signal delay adjustment device in the embodiment of the present application can execute the various methods of the aforementioned embodiments of the present application, that is, the specific working processes of the following various products can refer to the corresponding processes in the aforementioned method embodiments.

[0184] Figure 5 This is a structural diagram of a signal delay adjustment device provided in an embodiment of the present application.

[0185] For example, Figure 5 As shown, the signal delay adjustment device 500 includes: a memory 510 and a processor 520, wherein the memory 510 stores an executable program code 530, and the processor 520 is used to call and execute the executable program code 530 to perform a signal delay adjustment method.

[0186] Exemplarily, the memory 510 can be used to store relevant programs of the signal delay adjustment method provided in the embodiment of the present application; the processor 520 can call the relevant programs of the signal delay adjustment method stored in the memory 510 to execute the signal delay adjustment method of the embodiment of the present application; for example, obtain the initial delay value and initial test result of the gear in the delay line; perform data expansion processing on the initial delay value and the initial test result to obtain the target delay value and the target test result corresponding to the target delay value; wherein, the number of target delay values ​​is greater than the number of initial delay values; based on the target test result corresponding to the reference delay value, the target test result corresponding to the first delay value is updated to obtain an updated test result of the target delay value; wherein, the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; the reference delay value is determined based on the first delay value and the unit time interval; based on the target delay value and the updated test result, the target gear is determined, and the delay line is controlled to be adjusted to the target gear.

[0187] This embodiment can divide the functional modules according to the above-mentioned method example. For example, each functional module can be mapped to a specific functional module, or two or more functions can be integrated into a single processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used.

[0188] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0189] When an integrated unit is employed, the device may include a processing module and a storage module. The processing module may be a processor or controller that implements or executes the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processing (DSP) and a microprocessor, and the storage module may be a memory.

[0190] In addition, the device provided in the embodiments of the present application can specifically be a chip, component or module, and the chip may include a connected processor and memory; wherein the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute a signal delay adjustment method provided in the above embodiment.

[0191] The present application also provides a computer-readable storage medium, which stores computer program code. When the computer program code runs on a computer, the computer executes the above-mentioned related method steps to implement a signal delay adjustment method provided by the above-mentioned embodiment. Among them, computer-readable storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, Digital Video Discs (DVDs), Compact Disc Read-Only Memory (CD-ROMs), microdrives and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAMs), Erasable Programmable Read-Only Memory (EPROMs), Electrically Erasable Programmable Read-Only Memory (EEPROMs), Dynamic Random Access Memory (DRAMs), Video Random Access Memory (VRAMs), flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.

[0192] The present application also provides a computer program product. When the computer program product is run on a computer, it enables the computer to execute the above-mentioned related steps to implement a signal delay adjustment method provided by the above embodiment.

[0193] Among them, the computer-readable storage medium, computer program product or chip provided in this application is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0194] Through the description of the above implementation methods, technical personnel in the relevant field can understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0195] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0196] The above content is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A signal delay adjustment method, characterized in that: The method is applied to a chip; the method comprises: Obtain the initial delay value and initial test results of the gear in the delay line; Performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value; wherein the number of the target delay values ​​is greater than the number of the initial delay values; updating the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain an updated test result of the target delay value; wherein the target delay value includes the reference delay value and the first delay value; the target test result corresponding to the first delay value is an invalid value; and the reference delay value is determined based on the first delay value and a unit time interval; Determining a target gear position based on the target delay value and the updated test result, and controlling the delay line to adjust to the target gear position; The step of determining the target gear position based on the target delay value and the updated test result includes: Traversing the update test results to determine a maximum sampling window; selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window; The target gear is determined based on the target sampling delay value.

2. The method according to claim 1, characterized in that The updating of the target test result corresponding to the first delay value based on the target test result corresponding to the reference delay value to obtain the updated test result of the target delay value includes: Determining whether a target test result corresponding to the reference delay value is a valid value; If it is a valid value, determining the target test result corresponding to the reference delay value as the updated test result corresponding to the first delay value; If it is an invalid value, the target test result corresponding to the first delay value is determined as the updated test result corresponding to the first delay value.

3. The method according to claim 1, characterized in that The method further comprises: Determining whether a starting delay value in the target delay value is within a candidate sampling window; The selecting a target sampling delay value from the target delay values ​​based on the maximum sampling window includes: If the starting delay value is within the candidate sampling window, determining the target sampling delay value based on a first window length of the candidate sampling window and a second window length of the maximum sampling window; If the starting delay value is outside the candidate sampling window, the central delay value of the maximum sampling window is determined as the target sampling delay value.

4. The method according to claim 3, characterized in that The determining the target sampling delay value based on the first window length of the candidate sampling window and the second window length of the maximum sampling window includes: Determining a reference window length based on the second window length; wherein the reference window length is greater than or equal to half of the second window length; If the first window length is less than or equal to the reference window length, determining the central delay value of the maximum sampling window as the target sampling delay value; If the first window length is greater than the reference window length, a delay value that is a difference between the upper edge delay value of the candidate sampling window and the reference window length is determined as the target sampling delay value.

5. The method according to claim 1, wherein The performing data expansion processing on the initial delay value and the initial test result to obtain a target delay value and a target test result corresponding to the target delay value includes: Determining a target common divisor of the initial delay value; Performing data expansion processing on the initial delay value with the target common divisor as a step size to obtain the target delay value; Based on the initial test result and the initial delay value, a target test result corresponding to the target delay value is determined.

6. The method according to claim 5, characterized in that The determining, based on the initial test result and the initial delay value, a target test result corresponding to the target delay value includes: Determining a target difference between a first initial delay value and a second initial delay value; wherein the first initial delay value and the second initial delay value are used to indicate any adjacent delay values ​​of the initial delay values; If the target difference is less than or equal to the preset difference, determining the reference test result as the target test result corresponding to the target delay value between the first initial delay value and the second initial delay value; wherein the reference test result is the initial test result corresponding to the first initial delay value or the initial test result corresponding to the second initial delay value; If the target difference is greater than a preset difference, an invalid value is determined as a target test result corresponding to the target delay value between the first initial delay value and the second initial delay value.

7. The method according to claim 1, characterized in that The step of obtaining the initial delay value of the gear in the delay line includes: Determine the target unit for the initial gear; Obtaining the accumulated delay value of the target unit and a second delay value corresponding to the initial gear position; The sum of the accumulated delay value and the second delay value is determined as the initial delay value corresponding to the initial gear position; wherein the initial gear position is used to indicate any gear position in the delay line.

8. A signal delay adjustment device, characterized in that: include: a memory for storing executable program code; A processor is configured to call and run the executable program code from the memory, so that the signal delay adjustment device performs the signal delay adjustment method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed, the signal delay adjustment method according to any one of claims 1 to 7 is implemented.

Images