All-digital phase discrimination method, phase discriminator and fractional all-digital phase-locked loop circuit

Abstract

The present invention discloses a full-digital phase discrimination method, a phase discriminator and a fractional full-digital phase-locked loop circuit. In the full-digital phase discrimination method and the phase discriminator, a measurement method combining coarse and fine measurements is adopted, effectively reducing the requirement for the range of the time measurement circuit; moreover, the first count value part utilizes the oscillation period counting and period stability of the ring oscillator to ensure the large dynamic range and linearity of phase measurement; the second count value part utilizes the non-correlation between the oscillation signal period and the reference clock period, measures and averages multiple edges of the oscillation signal to avoid dead zones in time measurement, realizes interpolation of the delay chain, breaks through the unit delay limitation, and effectively improves the measurement accuracy; in addition, the fractional full-digital phase-locked loop circuit provided with a phase discriminator can realize phase discrimination with a large dynamic range without a traditional digital time converter, reduces the non-linearity of phase measurement, has a more concise overall architecture, is easy for full-digital integration, and effectively improves the performance.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to an all-digital phase discrimination method, a phase discriminator, and a fractional all-digital phase-locked loop circuit. Background Art

[0002] A phase-locked loop (PLL) is a circuit used to generate stable and accurate clock signals and maintain phase synchronization, and has wide applications in the fields of wireless communication, clock synthesis, data recovery, etc.

[0003] Traditional PLLs mainly consist of a phase discriminator (PD), a charge pump (CP), a loop filter (LF), and a voltage-controlled oscillator (VCO). Although analog PLLs have low phase noise, they are sensitive to process variations and temperature changes, have complex designs, and are difficult to achieve high integration in modern complementary metal-oxide-semiconductor (CMOS) processes. In addition, analog PLLs have limitations in programmability and are difficult to meet the requirements of modern digital systems for flexible frequency adjustment.

[0004] To overcome the limitations of analog PLLs, digital PLLs (DPLLs) have gradually developed. DPLLs use digital circuits to replace traditional analog filters and charge pumps, enhancing programmability, improving process compatibility, and reducing sensitivity to environmental factors. However, DPLLs still rely on analog VCOs and have not achieved full digitization.

[0005] All-digital phase-locked loops (ADPLLs) have further developed on the basis of DPLLs, replacing all analog modules in the PLL structure, including VCOs and phase discriminators, with digital circuits to achieve higher programmability, lower power consumption, and higher process migration capabilities. ADPLLs mainly consist of a divider, a digital phase discriminator (DPD), a digital loop filter (DLF), and a digitally controlled oscillator (DCO). Among them, the DCO is directly controlled by digital signals, replacing the analog VCO, making the ADPLL more easily integrated into modern digital systems.

[0006] The Fractional-N All-Digital Phase-Locked Loop (Fractional-N ADPLL) is an important branch of ADPLL. The Fractional-N ADPLL realizes fractional frequency division through digital control, improving the flexibility of frequency adjustment and making it widely used in fields such as 5G communication (the fifth-generation mobile communication technology) and high-precision clock generation. Traditionally, the Fractional-N ADPLL uses a multi-mode divider (MMDIV) and a time-to-digital converter (TDC) to achieve fractional frequency division. Among them, the MMDIV makes the average frequency of the feedback signal reach the required fractional multiple by periodically switching the integer division coefficient, and the TDC is responsible for measuring the phase error and providing feedback regulation. However, this solution has the following problems:

[0007] (1) The TDC needs to have a large dynamic range: Due to the large periodic phase error generated by the MMDIV, the TDC must be able to measure a wide range of phase deviations, resulting in increased power consumption and higher requirements for linearity.

[0008] (2) The quantization noise of the TDC affects the system performance: The resolution of the TDC is limited, and the quantization error will cause the overall phase noise of the phase-locked loop to deteriorate and increase the output clock jitter.

[0009] To reduce the dynamic range requirement of the TDC and improve the system performance, in recent years, the mainstream design has adopted the scheme of MMDIV, digital time converter (DTC) and TDC. As a programmable delay unit, the DTC makes fine phase adjustment to the feedback signal, thus reducing the range of phase error that the TDC needs to measure. However, although the MMDIV, DTC and TDC scheme effectively reduces the dynamic range requirement of the TDC, the nonlinearity of the DTC and the dead zone problem of the TDC still restrict the performance of the Fractional-N ADPLL. The key technical challenges it faces are mainly manifested in the following two aspects:

[0010] (1) The linearity problem of the DTC: The DTC is composed of cascaded delay units, and its delay accuracy is affected by process deviation, temperature drift and power supply fluctuation, resulting in the accumulation of nonlinear errors. The traditional all-digital delay chain architecture is difficult to maintain high-precision time control, and the nonlinear errors are difficult to optimize. Therefore, the mainstream DTC design usually uses analog circuits to improve linearity, but this increases the design complexity and power consumption.

[0011] (2) TDC dead zone problem: Limited by its finite time resolution, when the phase error is less than the minimum resolution of the TDC, the output of the TDC remains unchanged, resulting in the PLL being unable to correctly adjust the phase and affecting the phase-locking effect. This dead zone problem directly affects the phase noise performance of the Fractional-N ADPLL, which is particularly prominent in high-precision clock synthesis applications. Therefore, it is necessary to further optimize the TDC design to improve the measurement accuracy.

[0012] In view of this, the present invention is specifically proposed. Summary of the Invention

[0013] The object of the present invention is to provide a fully digital phase discrimination method, a phase discriminator and a fractional fully digital phase-locked loop circuit, which can ensure the large dynamic range and linearity of phase measurement, avoid the dead zone problem in time measurement, realize the interpolation of the delay chain, break through the unit delay limit, effectively improve the measurement accuracy, and the fractional fully digital phase-locked loop circuit can achieve large dynamic range phase discrimination without a traditional digital time converter, reduce the non-linearity of phase measurement, the overall architecture is more concise, easy for full digital integration, and the performance is effectively improved.

[0014] The object of the present invention is achieved by the following technical solutions:

[0015] A fully digital phase discrimination method includes:

[0016] When the edge of the input fractional division signal is detected, start oscillating to generate an oscillation signal until the edge of the reference clock signal is detected and stop, and count the edges of the oscillation loop signal to obtain the first count value of phase measurement;

[0017] Delay the oscillation signal through a delay chain. When the edge of the reference clock signal is detected, record the state code value on the delay chain. After encoding and non-linear correction of the state code value, obtain the second count value of phase measurement;

[0018] Combine the first count value and the second count value of phase measurement with the quantization compensation signal of the input frequency divider to generate a phase error quantity.

[0019] A phase discriminator for implementing the foregoing fully digital phase discrimination method includes: a ring oscillator, a time measurement circuit based on a delay chain, and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and both the ring oscillator and the time measurement circuit based on the delay chain are connected to the output encoder; wherein:

[0020] The ring oscillator is configured to start oscillating to generate an oscillation signal when the edge of the input fractional division signal is detected, stop until the edge of the reference clock signal is detected, and count the edges of the oscillation ring signal to obtain a first count value for phase measurement;

[0021] The time measurement circuit based on a delay chain is configured to delay the oscillation signal through the delay chain, record the state code value on the delay chain when the edge of the reference clock signal is detected, and obtain a second count value for phase measurement after encoding and non-linear correction of the state code value;

[0022] The output encoder is configured to combine the first count value and the second count value of the phase measurement with the input divider quantization compensation signal to generate a phase error amount.

[0023] A fractional all-digital phase-locked loop circuit includes: a digitally controlled oscillator, a multi-mode divider, the aforementioned phase detector, and a digital loop filter, which are connected in sequence to form a loop; wherein:

[0024] The digitally controlled oscillator is configured to generate a clock frequency signal according to the input digital control signal;

[0025] The divider is configured to perform fractional division on the clock frequency signal generated by the digitally controlled oscillator, output a fractional division signal, and a corresponding divider quantization compensation signal to the phase detector;

[0026] The phase detector is configured to output a phase error amount according to the input fractional division signal and the divider quantization compensation signal;

[0027] The digital loop filter is configured to digitally filter the phase error signal and generate a digital control signal output to the digitally controlled oscillator.

[0028] As can be seen from the technical solutions provided by the present invention described above, in the all-digital phase discrimination process, the method of obtaining the first count value for phase measurement is the coarse measurement method, and the method of obtaining the second count value is the fine measurement method. The combination of the two can effectively reduce the requirements for the range of the time measurement circuit. Moreover, the first count value part utilizes the oscillation period counting and period stability to ensure the large dynamic range and linearity of the phase measurement. The second count value part utilizes the irrelevance between the oscillation signal period and the reference clock period, measures and averages multiple edges of the oscillation signal, avoids the dead zone problem in time measurement, realizes the interpolation of the delay chain, breaks through the unit delay limit, and effectively improves the measurement accuracy. In addition, the corresponding fractional all-digital phase-locked loop circuit does not require a traditional digital time conversion unit and is suitable for all-digital implementation. Compared with the traditional time-to-digital converter-based scheme, while ensuring large-dynamic-range phase discrimination, the present invention utilizes the oscillation period to improve linearity. Generally speaking, the present invention adopts a more concise digital structure, improves the accuracy of the phase discriminator, and optimizes the overall performance of the phase-locked loop while improving the accuracy of the phase discriminator. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0030] Figure 1 It is a flowchart of an all-digital phase discrimination method provided by an embodiment of the present invention;

[0031] Figure 2 It is a schematic diagram of a phase discriminator provided by an embodiment of the present invention;

[0032] Figure 3 It is a schematic diagram of a fractional all-digital phase-locked loop circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0034] First, the following explanations will be given for the terms that may be used in this article:

[0035] Descriptions with terms such as "comprising", "including", "containing", "having" or other similar semantics shall be construed as non-exclusive inclusion. For example, including a technical feature element (such as raw materials, components, ingredients, carriers, dosage forms, materials, dimensions, parts, components, mechanisms, devices, steps, processes, methods, reaction conditions, processing conditions, parameters, algorithms, signals, data, products or articles, etc.) shall be construed as not only including the explicitly listed technical feature element, but also including other technical feature elements well-known in the art that are not explicitly listed.

[0036] The term "consisting of" means excluding any technical feature element that is not explicitly listed. If this term is used in a claim, then this term will make the claim a closed type, making it not contain technical feature elements other than the explicitly listed ones, except for conventional impurities related thereto. If this term only appears in a sub-clause of a claim, then it only limits the elements explicitly listed in that sub-clause, and the elements recorded in other sub-clauses are not excluded from the overall claim.

[0037] Unless otherwise clearly specified or limited, terms such as "connected" and "coupled" shall be understood in a broad sense. For example: it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this text can be understood according to specific circumstances.

[0038] The following provides a detailed description of a full-digital phase discrimination method, a phase discriminator, and a fractional full-digital phase-locked loop circuit provided by the present invention. The content not described in detail in the embodiments of the present invention belongs to the prior art well-known to those of ordinary skill in the art. For those conditions not specified in the embodiments of the present invention, they are carried out according to the conventional conditions in the art or the conditions recommended by the manufacturer. For the reagents or instruments not specified in the production manufacturer in the embodiments of the present invention, they are all conventional products that can be obtained through commercial purchase.

[0039] Embodiment 1

[0040] The embodiment of the present invention provides a full-digital phase discrimination method, which converts the measurement of the phase difference into the measurement of the state of a ring oscillator circuit, as Figure 1 shown, and mainly includes the following steps:

[0041] Step 1: When the edge of the input fractional division signal is detected, start oscillating to generate an oscillation signal until the edge of the reference clock signal is detected and stop, and count the edges of the oscillation ring signal to obtain the first count value of the phase measurement.

[0042] In the embodiments of the present invention, the oscillation period of a ring oscillator (RO) is used as a unit to quantify the phase error and achieve coarse measurement. The first count value can also be referred to as coarse count. The stability of the oscillation period of the ring oscillator ensures the linearity and stability of phase quantization in a large dynamic range.

[0043] Exemplarily, when the rising edge of the fractional division signal is detected, oscillation starts from the 0 phase and stops until the rising edge of the reference clock signal is detected.

[0044] Exemplarily, the counting of the edges of the oscillation ring signal includes: separately counting the rising edge and the falling edge of the oscillation signal to avoid metastability. Of course, in practical applications, other counting methods can also be used, which will not be elaborated in the present invention.

[0045] Step 2: Delay the oscillation signal through a delay chain. When the edge of the reference clock signal is detected, record the status code value on the delay chain. After encoding and non-linear correction of the status code value, obtain the second count value of the phase measurement.

[0046] Preferably, the encoding and non-linear correction of the status code value include: first preprocessing the status code value (for example, bubble elimination); then, performing multiple edge position detections, including 1 / 0 or 0 / 1 state jumps, and encoding the status code values at the detected edge positions to obtain the encoded edge code values; and then performing non-linear correction on the encoded edge code values.

[0047] In the embodiments of the present invention, the average value of the non-linearly corrected edge code values can be used as the second count value of the phase measurement.

[0048] In the embodiments of the present invention, after the coarse count measurement in this part of the measurement, the remaining phase amount less than one oscillation signal period can be referred to as fine measurement, and the phase quantization accuracy can be improved by the high-precision delay unit in the delay chain. Moreover, by utilizing the non-correlation between the oscillation period of the ring oscillator and the TDC reference clock period, and combining multiple oscillation signal edges (such as simultaneously measuring the rising and falling edges) for time measurement and averaging, the dead zone problem in time measurement is effectively avoided, the interpolation of the delay chain is realized, the unit delay limit is broken through, and the measurement accuracy is effectively improved.

[0049] Step 3: Combine the first count value and the second count value of the phase measurement with the input frequency divider quantization compensation signal to generate a phase error amount.

[0050] Preferably, the calculation process here is: perform phase normalization operations on the first count value and the second count value respectively, and then sum them with the input frequency divider quantization compensation signal to generate a phase error amount.

[0051] Exemplarily, according to the specific range of the second count value, a suitable first count value (the count value of the rising or falling edge of the oscillation pulse) can be selected to effectively avoid the impact of metastability.

[0052] In the embodiments of the present invention, the combination manner of the fine measurement and the foregoing coarse measurement reduces the requirement for the range of the time measurement circuit (only needs to cover one oscillation period of the ring oscillator).

[0053] Embodiment 2

[0054] The embodiments of the present invention further provide a phase detector, which is mainly used to implement the all-digital phase discrimination method provided in the foregoing embodiments, as Figure 2 shown, which mainly includes: a ring oscillator (Ring Oscillator, RO), a time measurement circuit based on tapped-delay lines (TDL), and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and both the ring oscillator and the time measurement circuit based on the delay chain are connected to the output encoder, and this phase detector is called RO-TDL-DPD.

[0055] The ring oscillator is used to start oscillating to generate an oscillation signal when detecting the edge of the input fractional division signal, and stop until detecting the edge of the reference clock signal, and count the edges of the oscillation ring signal to obtain the first count value for phase measurement (which can be called the coarse count).

[0056] The time measurement circuit based on the delay chain is used to delay the oscillation signal through the delay chain, record the state code value on the delay chain when detecting the edge of the reference clock signal, and obtain the second count value for phase measurement (which can be called the fine count) after encoding and non-linear correction of the state code value.

[0057] The output encoder is used to combine the first count value and the second count value for phase measurement with the quantization compensation signal of the input frequency divider to generate a phase error amount.

[0058] As Figure 2 shown, the ring oscillator includes: an oscillation ring and an oscillation ring edge counter connected in sequence; wherein: the oscillation ring is used to start oscillating to generate an oscillation signal when detecting the edge of the input fractional division signal, and stop until detecting the edge of the reference clock signal; the oscillation ring edge counter is used to count the edges of the oscillation ring signal to obtain the first count value for phase measurement.

[0059] This part of the ring oscillator is mainly used to implement step 1 in the foregoing embodiments. Considering that the relevant measurement process has been introduced in the foregoing embodiments, it will not be elaborated here.

[0060] AsFigure 2 As shown, the time measurement circuit based on a delay chain includes: a delay chain, a delay chain sampling module, and a data processing module connected in sequence; where: the delay chain is used to delay an oscillation signal; the delay chain sampling module is used to record the state code value on the delay chain when detecting the edge of a reference clock signal; the data processing module is used to perform encoding and non-linear correction on the state code value to obtain a second count value for phase measurement.

[0061] This part of the time measurement circuit based on a delay chain is mainly used to implement step 2 in the foregoing embodiment. The remaining phase error less than one oscillation period of the ring oscillator is measured by the time measurement circuit based on a delay chain. Considering that the relevant measurement process has been introduced in the foregoing embodiment, it will not be elaborated here.

[0062] Similarly, the specific calculation process involved in the output encoder can be referred to the introduction in the foregoing embodiment, and will not be elaborated here.

[0063] Embodiment III

[0064] An embodiment of the present invention provides a fractional-N all-digital phase-locked loop (Fractional-N ADPLL) circuit, as Figure 3 shown, which mainly includes: a digitally controlled oscillator (DCO), a multi-mode frequency divider (MMDIV), a phase detector, and a digital loop filter, which are connected in sequence to form a loop.

[0065] The digitally controlled oscillator is used to generate a clock frequency signal according to an input digital control signal.

[0066] The frequency divider is used to perform fractional division on the clock frequency signal generated by the digitally controlled oscillator, output a fractional division signal, and a corresponding frequency divider quantization compensation signal to the phase detector.

[0067] The phase detector is used to output a phase error quantity according to the input fractional division signal and the frequency divider quantization compensation signal. The phase detector here is the phase detector provided in the foregoing embodiment, and the method provided in the foregoing embodiment is used to generate the phase error quantity and output it to the digital loop filter.

[0068] The digital loop filter is used to digitally filter the phase error signal, combine a control algorithm (for example, a proportional-integral-derivative control algorithm) to generate a digital control signal output to the digitally controlled oscillator, and finally achieve frequency locking.

[0069] In the above-mentioned fractional all-digital phase-locked loop circuit provided by the embodiment of the present invention, a phase detector for realizing all-digital phase discrimination is provided, and the phase error is quantified by the cycle count of the ring oscillator to realize high-dynamic-range phase discrimination. At the same time, based on the high-precision time measurement of the delay chain, combined with multi-edge measurement averaging and non-linear correction, the resolution limitation of the delay unit of the delay chain is broken through. In addition, by utilizing the non-correlation between the oscillation period of the ring oscillator and the reference clock signal, the influence of the dead zone effect in time measurement can be effectively reduced.

[0070] The above-mentioned fractional all-digital phase-locked loop circuit provided by the present invention does not require a digital time converter and is suitable for all-digital implementation. In comparison, while ensuring large-dynamic-range phase discrimination, the present invention utilizes the oscillation period of the ring oscillator to improve linearity. Overall, the present invention adopts a more concise digital structure, which improves the accuracy of the phase detector and optimizes the overall performance of the phase-locked loop while enhancing the overall performance of the phase-locked loop.

[0071] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background art part of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art.

Claims

1. A fully digital phase discrimination method, characterized in that, Comprising: When detecting the edge of the input fractional division signal, start oscillating to generate an oscillation signal until detecting the edge of the reference clock signal and stop, and count the edges of the oscillation ring signal to obtain the first count value for phase measurement; wherein, the counting of the edges of the oscillation ring signal includes: counting the rising edge and the falling edge of the oscillation signal respectively; Delay the oscillation signal through a delay chain. When detecting the edge of the reference clock signal, record the status code value on the delay chain. After encoding and non-linear correction of the status code value, obtain the second count value for phase measurement; Combine the first count value and the second count value for phase measurement with the input divider quantization compensation signal to generate a phase error quantity, including: performing phase normalization operations on the first count value and the second count value respectively, and then summing them with the input divider quantization compensation signal to generate a phase error quantity.

2. The all-digital phase discrimination method according to claim 1, wherein The encoding and non-linear correction of the status code value includes: First, preprocess the status code value; then, perform multiple edge position detections, and encode the status code values at the detected edge positions to obtain the encoded edge code values; and then perform non-linear correction on the encoded edge code values.

3. A phase discriminator, characterized in that, Used to implement the all-digital phase discrimination method described in any one of claims 1 to 2, including: a ring oscillator, a time measurement circuit based on a delay chain, and an output encoder; the ring oscillator is connected to the time measurement circuit based on the delay chain, and both the ring oscillator and the time measurement circuit based on the delay chain are connected to the output encoder; wherein: The ring oscillator is used to start oscillating to generate an oscillation signal when detecting the edge of the input fractional division signal, until detecting the edge of the reference clock signal and stop, and count the edges of the oscillation ring signal to obtain the first count value for phase measurement; The time measurement circuit based on the delay chain is used to delay the oscillation signal through the delay chain, record the status code value on the delay chain when detecting the edge of the reference clock signal, and obtain the second count value for phase measurement after encoding and non-linear correction of the status code value; The output encoder is used to combine the first count value and the second count value for phase measurement with the input divider quantization compensation signal to generate a phase error quantity.

4. A phase discriminator according to claim 3, characterized in that The ring oscillator includes: an oscillation ring and an oscillation ring edge counter connected in sequence; wherein: The oscillation ring is used to start oscillating to generate an oscillation signal when detecting the edge of the input fractional division signal, until detecting the edge of the reference clock signal and stop; The oscillation ring edge counter is used to count the edges of the oscillation ring signal to obtain the first count value for phase measurement.

5. The phase discriminator according to claim 3, characterized in that The time measurement circuit based on the delay chain includes: a delay chain, a delay chain sampling module, and a data processing module connected in sequence; wherein: The delay chain is used to delay the oscillation signal; The delay chain sampling module is used to record the status code value on the delay chain when detecting the edge of the reference clock signal; The data processing module is used to obtain the second count value for phase measurement after encoding and non-linear correction of the status code value.

6. A decimal all-digital phase-locked loop circuit, characterized in that, Comprising: A numerically controlled oscillator, a multi-mode frequency divider, a phase detector according to any one of claims 3 to 5, and a digital loop filter are connected in sequence to form a loop; wherein: The numerically controlled oscillator is configured to generate a clock frequency signal according to an input digital control signal; The frequency divider is configured to perform fractional division on the clock frequency signal generated by the numerically controlled oscillator, output a fractional division signal, and a corresponding frequency divider quantization compensation signal to the phase detector; The phase detector is configured to output a phase error quantity according to the input fractional division signal and the frequency divider quantization compensation signal; The digital loop filter is configured to perform digital filtering on the phase error signal and generate a digital control signal output to the numerically controlled oscillator.

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