Phase-locked loop circuits, clock generators, chips and electronic devices

Abstract

The present disclosure relates to a phase-locked loop circuit, a clock generator, a chip and an electronic device. The phase-locked loop circuit mainly includes: a phase-frequency detector, which is used to generate a phase-detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; a proportional path module, which is used to generate a first control current according to the phase-detection output signal; an integral path module, which is used to generate a second control current according to the phase-detection output signal; a current-controlled oscillation module, which is used to generate a clock output signal according to the first control current and the second control current; and a feedback frequency divider, which is used to obtain a feedback clock signal by dividing the clock output signal. The present disclosure combines the advantages of an analog charge pump phase-locked loop and a fully digital phase-locked loop, and is helpful to achieve the generation of a high-performance clock with a smaller area, higher bandwidth, more stable loop and lower quantization noise, and is helpful to achieve the applicability of the phase-locked loop to high bandwidth requirements, and is helpful to reduce quantization noise, and theoretically achieve unconditional stability of the phase-locked loop.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a phase-locked loop circuit, a clock generator, a chip and an electronic device. Background Art

[0002] Phase-Locked Loop (PLL) is a widely used synchronous circuit in integrated circuits, mainly used to synchronize clock signals to ensure the accuracy and stability of data transmission. In SoC (System on Chip), PLL is usually used as a clock generator to provide clocks for various modules in SoC. High-performance, low-area, and flexible configuration PLL has become an indispensable core module of modern high-performance SoC.

[0003] In the related technology, phase-locked loops include analog phase-locked loops and digital phase-locked loops. Both analog phase-locked loops and digital phase-locked loops have corresponding disadvantages. For example, analog phase-locked loops have problems such as large PVT (process, voltage, temperature) changes, difficulty in further miniaturization, small frequency modulation range, and large loop parameter fluctuations. Digital phase-locked loops have problems such as large circuit structure area in some parts, time-consuming design, difficulty in transplantation, difficulty in suppressing quantization noise, and loop stability being easily affected by PVT changes. Summary of the invention

[0004] In view of this, the present disclosure provides a phase-locked loop circuit, a clock generator, a chip and an electronic device to help achieve the applicability of the phase-locked loop to high bandwidth requirements, help reduce quantization noise, and theoretically achieve unconditional stability of the phase-locked loop.

[0005] According to one aspect of an embodiment of the present disclosure, a phase-locked loop circuit is provided, comprising:

[0006] A phase frequency detector, used for receiving a reference clock signal and a feedback clock signal, and generating a phase detection output signal according to the phase of the reference clock signal and the phase of the feedback clock signal;

[0007] A proportional path module, coupled to the phase frequency detector, for receiving the phase detection output signal, and generating a first control current according to the phase detection output signal, wherein the proportional path module does not include passive components;

[0008] An integral path module, coupled to the phase frequency detector, for receiving the phase detection output signal and generating a second control current according to the phase detection output signal;

[0009] a current-controlled oscillation module, coupled to the proportional path module and the integral path module, configured to receive the first control current and the second control current, and generate a clock output signal according to the first control current and the second control current;

[0010] The feedback frequency divider is coupled to the current controlled oscillation module and the frequency and phase detector, and is used for receiving the clock output signal and obtaining the feedback clock signal by dividing the frequency of the clock output signal.

[0011] In one possible implementation, the proportional path module includes:

[0012] The first digital-to-analog converter is coupled to the phase frequency detector and the current controlled oscillation module, and is used for generating the first control current according to the phase detection output signal.

[0013] In one possible implementation manner, the phase-comparison output signal includes an up signal and a down signal;

[0014] The first digital-to-analog converter generates the first control current of different magnitudes according to the level of the upper signal and the level of the lower signal.

[0015] In a possible implementation manner, when both the upper signal and the lower signal are at low levels, the magnitude of the first control current is a reference output current value preset by the first digital-to-analog converter;

[0016] When the upper signal is at a high level and the lower signal is at a low level, the magnitude of the first control current is twice the value of the reference output current;

[0017] When the upper signal is at a low level and the lower signal is at a high level, the magnitude of the first control current is 0.

[0018] In one possible implementation, the integral path module includes:

[0019] A Bang-Bang phase detector, coupled to the phase frequency detector, for receiving the phase detection output signal, and generating an early-late signal according to the phase detection output signal;

[0020] a digital loop filter, coupled to the Bang-Bang phase detector, for receiving the early-late signal and generating a filter control signal according to the early-late signal; and

[0021] The second digital-to-analog converter is coupled to the digital loop filter, and is used for receiving the filtering control signal, and generating the second control current of different magnitudes according to the magnitude of the filtering control signal.

[0022] In a possible implementation manner, the integral path module further includes:

[0023] a differential integral modulator, coupled between the digital loop filter and the second digital-to-analog converter, and configured to modulate the filter control signal to obtain a modulated filter signal;

[0024] The filtering control signal received by the second digital-to-analog converter is the modulated filtering signal obtained by modulation by the differential integral modulator.

[0025] In one possible implementation, the current controlled oscillation module includes:

[0026] an adder, coupled to the proportional path module and the integral path module, configured to receive the first control current and the second control current, and add the first control current and the second control current to obtain a current control signal;

[0027] The current controlled oscillator is coupled to the adder and is used for receiving the current control signal and generating the clock output signal according to the current control signal.

[0028] In a possible implementation manner, the phase-locked loop circuit further includes:

[0029] a coarse adjustment calibration module, coupled to the current controlled oscillation module, for generating a coarse adjustment current, wherein the coarse adjustment current is used to determine a target frequency range of the clock output signal;

[0030] Wherein, the current-controlled oscillation module further generates the clock output signal according to the first control current, the second control current and the coarse adjustment current.

[0031] According to another aspect of an embodiment of the present disclosure, a clock generator is provided, comprising the phase-locked loop circuit as described in any one of the above items.

[0032] According to another aspect of an embodiment of the present disclosure, a chip is provided, comprising the phase-locked loop circuit as described in any one of the above items.

[0033] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, comprising the chip as described above.

[0034] It can be seen from the above scheme that the phase-locked loop circuit, clock generator, chip and electronic device disclosed in the present invention adopt a dual-path architecture of a proportional path module and an integral path module, and can flexibly optimize the design of the proportional path and the integral path respectively. Among them, the first control current is generated by using the first digital-to-analog converter in the proportional path module based on the phase difference detection of the reference clock signal and the feedback clock signal, which continues the behavior of the linear phase detection in the charge pump phase-locked loop and eliminates the main quantization noise in the full digital phase-locked loop (the quantization noise introduced by the time digital converter and the proportional path). The integral path module adopts the digital loop filter in the full digital phase-locked loop, which greatly reduces the area of ​​the loop filter, avoids the charge leakage problem of the capacitor used in the analog phase-locked loop, and reduces the dependence of the analog filter RC value used in the analog phase-locked loop on the process PVT change, which is easy to transplant between different processes. The gain of the digital loop filter in the integral path module is usually small, so that the quantization noise of the integral path is very small, usually to the extent of being negligible. The loop of the phase-locked loop circuit disclosed in the present invention is an over-damped system, which is approximately a first-order system, so that the loop is unconditionally stable, and thus its bandwidth design can be greater than the limit required by the usual phase-locked loop design. The phase-locked loop circuit disclosed in the present invention combines the advantages of an analog charge pump phase-locked loop and a fully digital phase-locked loop, and is helpful to achieve the generation of a high-performance clock with a smaller area, higher bandwidth, more stable loop, and lower quantization noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of a typical charge pump phase-locked loop structure in the related art;

[0036] Figure 2 It is a schematic structural diagram of a typical all-digital phase-locked loop based on a time-to-digital converter in the related art;

[0037] Figure 3 is a schematic structural diagram of a phase-locked loop circuit according to an exemplary embodiment;

[0038] Figure 4 is a schematic diagram of a specific circuit structure of an application scenario of a phase-locked loop circuit according to an embodiment of the present disclosure;

[0039] Figure 5 is a timing diagram of various signals in a proportional path module according to an exemplary embodiment;

[0040] Fig. 6A It is a schematic diagram of the transfer function image of the frequency and phase detector;

[0041] Figure 6B It is a schematic diagram of the transfer function image of the Bang-Bang phase detector;

[0042] Figure 7Schematic diagram of a small signal model of a phase-locked loop circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0045] The phase-locked loop achieves phase locking through a feedback loop. There are two typical phase-locked loop architectures in integrated circuit design, one is the analog charge pump (CP) phase-locked loop (also called CPPLL), and the other is the full digital phase-locked loop based on the time to digital converter (TDC) (also called TDC-based ADPLL).

[0046] Figure 1 Schematic diagram of a typical charge pump phase-locked loop in the related art. Figure 1 As shown in Figure 1, phase locking requires a reference clock signal ref, which is usually a clock from a high-precision crystal oscillator (XO). The phase difference between the reference clock signal ref and the feedback clock signal div is detected by a phase detector (PD).

[0047] If the feedback clock signal div lags behind the reference clock signal ref, for example Figure 1 In the timing diagram in the upper right corner, the phase of div(t) reflecting the feedback clock signal div lags behind ref(t) reflecting the reference clock signal ref. t represents time. In the phase detector, the U (Up) signal ( Figure 1 The Q output signal of the upper D flip-flop in the phase detector is high, the charging switch of the charge pump in the phase detector is turned on, and the charge pump passes the current I e (t) Charge the analog loop filter (ALF), where Figure 1As shown, the analog loop filter is mainly composed of capacitors and resistors. Charging the analog loop filter means charging the capacitors therein, thereby increasing the output voltage Vtune(t) of the analog loop filter, which increases the frequency of the output signal out of the voltage-controlled oscillator (VCO) connected to the output end of the analog loop filter, thereby increasing the phase accumulation of the output signal out. The output signal out passes through a frequency divider (FD) to obtain a feedback clock signal div, wherein MC is the main clock signal of the input frequency divider. The feedback clock signal div enters the phase detector. Because the phase accumulation of the output signal out increases, the phase accumulation of the feedback clock signal div increases accordingly, thereby reducing the phase difference between the feedback clock signal div and the reference clock signal ref.

[0048] If the feedback clock signal div is ahead of the reference clock signal ref in phase detector, the D (Down) signal ( Figure 1 The output signal of the Q end of the D flip-flop at the bottom of the phase detector is high level, the discharge switch of the charge pump in the phase detector is turned on, the charge pump is discharged, and then the output voltage Vtune(t) of the analog loop filter decreases, so that the frequency of the voltage-controlled oscillator output signal out decreases, and then the phase accumulation of the output signal out decreases. Because the phase accumulation of the output signal out decreases, the phase accumulation of the feedback clock signal div decreases accordingly, and then the phase difference between the feedback clock signal div and the reference clock signal ref decreases.

[0049] The charge pump phase-locked loop is adjusted continuously until the phase difference between the feedback clock signal div and the reference clock signal ref approaches 0, achieving phase locking. At this time, the voltage-controlled oscillator outputs a stable clock signal frequency.

[0050] Figure 2 FIG. 1 is a schematic diagram of a typical all-digital phase-locked loop based on a time-to-digital converter in the related art. Figure 2 As shown, Figure 1Compared with the charge pump phase-locked loop shown in the figure, the most important difference of the fully digital phase-locked loop based on the time-to-digital converter is that the phase detector is replaced by the time-to-digital converter, which changes the phase detection control from a linear analog behavior to a quantized digital behavior. The phase difference information between the reference clock signal ref and the feedback clock signal div is converted into a first digital control code e[k] by the time-to-digital converter. The first digital control code e[k] is further converted into a second digital control code tw[k] by controlling the digital loop filter. The second digital control code tw[k] is output to the digitally controlled oscillator (Digitally Controlled Oscillator, DCO). If the value of the second digital control code tw[k] increases, the frequency of the output signal out of the digitally controlled oscillator increases. If the value of the second digital control code tw[k] decreases, the frequency of the output signal out of the digitally controlled oscillator decreases. At the same time, Figure 1 Compared with the charge pump phase-locked loop shown in the figure, the analog loop filter is replaced by a digital loop filter. Since the digital loop filter no longer contains the passive components in the analog loop filter, the occupied area of ​​the loop filter in the chip is effectively reduced. In addition, the digital loop filter can also benefit from the miniaturization of the integrated circuit process. Compared with the charge pump phase-locked loop, the full digital phase-locked loop based on the time-to-digital converter is easier to be miniaturized with the advancement of the integrated circuit process because there are no passive components.

[0051] Both the charge pump phase-locked loop and the all-digital phase-locked loop based on the time-to-digital converter have their own shortcomings.

[0052] The analog loop filter in the charge pump phase-locked loop uses on-chip passive components such as resistors and capacitors ( Figure 1 As shown in the figure, there are problems such as large occupied area, large PVT (Process, Voltage, Temperature) variation, capacitor charge leakage, etc., and it is difficult to benefit from the miniaturization of integrated circuit technology; because the power supply voltage of current integrated circuits is relatively lower and lower, the range of the output voltage Vtune(t) of the charge pump in the charge pump phase-locked loop is limited, which in turn limits the frequency modulation range of the clock signal and makes it impossible to adapt to the wide frequency range of the clock signal; the frequency response curve of the voltage-controlled oscillator in the charge pump phase-locked loop is strongly nonlinear, which makes the loop parameter fluctuation range larger.

[0053] The design of the time-to-digital converter in the all-digital phase-locked loop based on the time-to-digital converter is time-consuming, and the time-to-digital converter is usually large in area and consumes a lot of power. Especially for the phase-locked loop that can adapt to a wide frequency range, the design of the time-to-digital converter is more difficult. Transplanting the time-to-digital converter between different processes is almost equivalent to redesigning it. The in-band noise of the all-digital phase-locked loop based on the time-to-digital converter is also limited by the accuracy of the time-to-digital converter, and the accuracy of the time-to-digital converter is very sensitive to the change of PVT, and the in-band noise is difficult to effectively control.

[0054] In addition, from the perspective of automatic control theory, charge pump phase-locked loops and all-digital phase-locked loops based on time-to-digital converters are both second-order or third-order systems. Regardless of whether they are second-order or third-order systems, their bandwidth selection is limited and the loop stability is easily affected by PVT changes.

[0055] In view of this, the embodiments of the present disclosure provide a phase-locked loop circuit, a clock generator, a chip and an electronic device to help achieve the applicability of the phase-locked loop to high bandwidth requirements, and help reduce quantization noise, and theoretically achieve unconditional stability of the phase-locked loop.

[0056] Figure 3 FIG. 1 is a schematic diagram showing a structure of a phase-locked loop circuit according to an exemplary embodiment. Figure 3 As shown, the phase-locked loop circuit of the embodiment of the present disclosure mainly includes a frequency detector 1, a proportional path module 2, an integral path module 3, a current control oscillation module 4 and a feedback divider 5. Among them, the frequency detector 1 is used to receive a reference clock signal ref and a feedback clock signal div, and generate a phase detection output signal according to the phase of the reference clock signal ref and the phase of the feedback clock signal div. The proportional path module 2 is coupled to the frequency detector 1, and is used to receive the phase detection output signal, and generate a first control current iprop according to the phase detection output signal. The integral path module 3 is coupled to the frequency detector 1, and is used to receive the phase detection output signal, and generate a second control current iint according to the phase detection output signal. The current control oscillation module 4 is coupled to the proportional path module 2 and the integral path module 3, and is used to receive the first control current iprop and the second control current iint, and generate a clock output signal fout according to the first control current iprop and the second control current iint. The feedback divider 5 is coupled to the current control oscillation module 4 and the frequency detector 1, and is used to receive the clock output signal fout, and obtain the feedback clock signal div by dividing the clock output signal fout.

[0057] Among them, the proportional path module 2 is mainly used to quickly adjust and track the phase change of the reference clock signal ref, and the integral path module 3 is mainly used to adjust the frequency of the clock output signal fout to make the feedback clock signal div consistent with the frequency of the reference clock signal ref.

[0058] In the exemplary embodiment, the proportional path module 2 does not include passive devices. In this way, it is helpful to reduce the area of ​​the phase-locked loop circuit, reduce PVT changes, eliminate the capacitance charge leakage problem of passive devices, and benefit from the miniaturization of integrated circuit technology. For example, the proportional path module 2 can be composed of digital circuit elements and analog transistor elements and no passive devices are used in the proportional path module 2. For example, the current source circuit in the proportional path module 2 can be constructed by analog transistor elements and the control circuit for controlling the current size in the proportional path module 2 can be constructed by digital circuit elements.

[0059] Figure 4 is a schematic diagram of a specific circuit structure of an application scenario of the phase-locked loop circuit of the embodiment of the present disclosure, combined with Figure 3 , Figure 4 As shown, in the exemplary embodiment, the proportional path module 2 includes a first digital-to-analog converter 201. The first digital-to-analog converter 201 is coupled to the phase frequency detector 1 and the current control oscillation module 4, and is used to generate a first control current iprop according to the phase detection output signal. Because the first digital-to-analog converter 201 is located in the proportional path module 2, the first digital-to-analog converter 201 can also be called a proportional path digital-to-analog converter (Proportional Digital to Analog Convertor, PDAC) in the embodiment of the present disclosure. In the exemplary embodiment, the first digital-to-analog converter 201 does not include passive devices. In this way, it is helpful to reduce the area of ​​the phase-locked loop circuit, reduce PVT changes, eliminate the problem of capacitive charge leakage of passive devices, and benefit from the miniaturization of integrated circuit technology. For example, the first digital-to-analog converter 201 can be composed of digital circuit elements and analog transistor elements, and no passive devices are used in the first digital-to-analog converter 201. For example, the current source circuit in the first digital-to-analog converter 201 can be constructed by analog transistor elements, and the control circuit for controlling the current size in the first digital-to-analog converter 201 can be constructed by digital circuit elements.

[0060] Combination Figure 3 , Figure 4 As shown, in the exemplary embodiment, the phase detection output signal includes an up signal up and a down signal dn. The first digital-to-analog converter 201 generates first control currents iprop of different magnitudes according to the levels of the up signal up and the down signal dn.

[0061] In an illustrative embodiment, the first digital-to-analog converter 201 may be configured as follows: when both the upper signal up and the lower signal dn are at a low level, the magnitude of the first control current iprop is a reference output current value (iprop_base) preset by the first digital-to-analog converter 201. When the upper signal up is at a high level and the lower signal dn is at a low level, the magnitude of the first control current iprop is twice the reference output current value (iprop_base); when the upper signal up is at a low level and the lower signal dn is at a high level, the magnitude of the first control current iprop is 0. It should be noted that those skilled in the art may use conventional active devices to perform corresponding designs of the circuit structure of the first digital-to-analog converter 201 according to the configuration function of the first digital-to-analog converter 201 in the embodiment of the present disclosure.

[0062] Figure 5 FIG. 1 is a timing diagram of various signals in a proportional path module according to an exemplary embodiment. Figure 5 As shown, the phase detector 1 compares the phases of the reference clock signal ref and the feedback clock signal div, and outputs the corresponding control signal (upper signal up / lower signal dn) according to the phase relationship and phase difference between the reference clock signal ref and the feedback clock signal div. In the exemplary embodiment, before the phase detection starts, the upper signal up and the lower signal dn are both 0, and the magnitude of the first control current iprop is the reference output current value iprop_base, wherein the reference output current value iprop_base is a set fixed value. Figure 5 As shown, if the phase of the feedback clock signal div lags behind the reference clock signal ref, the upper signal up output by the frequency detector 1 is at a high level. At this time, the magnitude of the first control current iprop is twice the reference output current value iprop_base. Then, the proportional path module 2 provides twice the reference output current value iprop_base to the current control oscillation module 4. Then, the current control oscillation module 4 will increase the frequency of its clock output signal fout due to the increase in current provided by the proportional path module 2. The frequency of the feedback clock signal div obtained after the clock output signal fout passes through the feedback divider 5 will also increase accordingly, thereby performing phase accumulation. Figure 5 As shown, if the phase of the feedback clock signal div is ahead of the reference clock signal ref, the lower signal dn output by the frequency detector 1 is at a high level. At this time, the magnitude of the first control current iprop is 0, and the output current of the proportional path module 2 is turned off. Furthermore, the current-controlled oscillation module 4 will reduce the frequency of its clock output signal fout due to the closure of the current provided by the proportional path module 2. The frequency of the feedback clock signal div obtained after the clock output signal fout passes through the feedback divider 5 will also be reduced accordingly, thereby slowing down the phase accumulation of the feedback clock signal div.

[0063] It can be seen from the above description that in the embodiment of the present disclosure, the phase compensation of the proportional path module 2 is performed based on the phase difference between the reference clock signal ref and the feedback clock signal div generated by the frequency detector 1. The larger the phase difference between the two, the more compensation is performed, and the smaller the phase difference, the less compensation is performed. This has the advantages of linear compensation like the charge pump phase-locked loop in the related art, and the phase compensation action is real-time. In the embodiment of the present disclosure, the first digital-to-analog converter 201 plays a role similar to that of the charge pump in the charge pump phase-locked loop of the analog architecture, thus continuing the linear phase detection behavior in the charge pump phase-locked loop, inheriting the advantages of the charge pump phase-locked loop, and also helping to avoid the main quantization noise in the full digital phase-locked loop (quantization noise introduced by the time-to-digital converter and its proportional path). Compared with the all-digital phase-locked loop based on a time digital converter in the related art, the phase-locked loop circuit of the embodiment of the present disclosure does not adopt the solution of a time digital converter but adopts a frequency detector 1 and the proportional path module 2 adopts the first digital-to-analog converter 201 of the above embodiment, thereby eliminating the quantization noise from the time digital converter to the digital loop filter 302 in the all-digital phase-locked loop based on a time digital converter from the root.

[0064] Combination Figure 3 , Figure 4 As shown, in the exemplary embodiment, the integral path module 3 mainly includes a Bang-Bang phase detector 301, a digital loop filter 302 and a second digital-to-analog converter 303. Among them, the Bang-Bang phase detector 301 is coupled to the frequency detector 1, and is used to receive the phase detection output signal, and generate an early / late signal according to the phase detection output signal. The digital loop filter 302 is coupled to the Bang-Bang phase detector 301, and is used to receive the early and late signals, and generate a filter control signal dlfout according to the early and late signals. The second digital-to-analog converter 303 is coupled to the digital loop filter 302, and is used to receive the filter control signal dlfout, and generates a second control current iint of different sizes according to the size of the filter control signal dlfout. Among them, because the second digital-to-analog converter 303 is located in the integral path module 3, and then in the embodiment of the present disclosure, the second digital-to-analog converter 303 can also be called an integral path digital-to-analog converter (Integral Digital to Analog Convertor, IDAC).

[0065] In an illustrative embodiment, the second digital-to-analog converter 303 does not include passive devices. In this way, it is helpful to reduce the area of ​​the phase-locked loop circuit, reduce PVT changes, eliminate the capacitance charge leakage problem of passive devices, and benefit from the miniaturization of integrated circuit technology. For example, the second digital-to-analog converter 303 can be composed of digital circuit elements and analog transistor elements and no passive devices are used in the second digital-to-analog converter 303. For example, the current source circuit in the second digital-to-analog converter 303 can be constructed by analog transistor elements and the control circuit for controlling the current size in the first digital-to-analog converter 201 can be constructed by digital circuit elements.

[0066] The Bang-Bang phase detector 301, also known as a Bang-Bang phase detector, is theoretically a mid-rise quantizer with infinite precision. Fig. 6A It is a schematic diagram of the transfer function image of the frequency and phase detector. Figure 6B This is a diagram of the transfer function of the Bang-Bang phase detector. First, Fig. 6A As shown, the output of the phase frequency detector has a linear characteristic. When the phase difference of the input signal is within one cycle, the output signal of the phase frequency detector will increase linearly as the phase difference of the input signal increases from small to large, such as Figure 6B As shown in the figure, in the Bang-Bang phase detector, when the input signal phase difference is greater than 0, the output signal is 1, and when the input signal phase difference is less than 0, the output signal is 0. The transmission function of the Bang-Bang phase detector is completely different from the transmission function characteristics of the frequency detector. Figure 4 As shown, if the Bang-Bang phase detector 301 is coupled after the frequency detector 1, the phase detection characteristics of the two can be combined to provide a control signal to the digital loop filter 302. Figure 4 As shown in FIG. 1 , when the phase of the feedback clock signal div lags behind the reference clock signal ref, the up signal up is 1, and the late signal late in the early-late signal output by the Bang-Bang phase detector 301 is 1. At this time, in the digital loop filter 302, the late signal late is 1, which represents "+1", and then the gain gain is multiplied by "+1", and the accumulator is combined with the filtering control signal dlfout ( Figure 4 Z -1(represented) is accumulated to obtain the filter control signal dlfout at the current moment, that is, the filter control signal dlfout at the current moment is the filter control signal dlfout at the previous moment plus the gain gain; when the phase of the feedback clock signal div is ahead of the reference clock signal ref, the lower signal dn is 1, and the early signal early in the early-late signal output by the Bang-Bang phase detector 301 is 1. At this time, in the digital loop filter 302, the early signal early is 1, which represents "-1", and then the gain gain is multiplied by "-1", and the filter control signal dlfout at the previous moment is accumulated through the accumulator to obtain the filter control signal dlfout at the current moment, that is, the filter control signal dlfout at the current moment is the filter control signal dlfout at the previous moment minus the gain gain. In the disclosed embodiment, the frequency detector 1 and the Bang-Bang phase detector 301 cooperate with the digital loop filter 302, and adjust the filter control signal dlfout as the phase difference between the reference clock signal ref and the feedback clock signal div changes continuously until the phase lock is achieved. In order to reduce the quantization noise of the proportional path module 2, in the exemplary embodiment, the value of the gain gain is set to a very small value. For example, the value of the gain gain can be set so that the proportion of the quantization noise of the phase-locked loop circuit of the embodiment of the present disclosure in the total noise is less than the value corresponding to the preset tolerance threshold. When the value of the gain gain is set to a certain value so that the proportion of the quantization noise of the phase-locked loop circuit of the embodiment of the present disclosure in the total noise is less than the preset tolerance threshold, it can be considered that the certain value is the very small value. Among them, the size of the tolerance threshold depends on the needs of the specific application. In the exemplary embodiment, the size of the tolerance threshold can be set to 10%. Based on this, when the quantization noise of the phase-locked loop circuit accounts for less than 10% of the total noise, it can be considered that the quantization noise is not the dominant factor in the noise generated by the phase-locked loop circuit.

[0067] In addition, in order to more flexibly control the gain of the integral path module 3 and further reduce the quantization noise in the integral path module 3, so as to reduce the design difficulty of the second digital-to-analog converter 303, the Figure 3 , Figure 4As shown, in the exemplary embodiment, the integral path module 3 further includes a differential integral modulator 304. The differential integral modulator 304 is coupled between the digital loop filter 302 and the second digital-to-analog converter 303, and is used to modulate the filter control signal dlfout to obtain a modulated filter signal dsmout, wherein the filter control signal dlfout received by the second digital-to-analog converter 303 is the modulated filter signal dsmout obtained by modulation of the differential integral modulator 304. In the exemplary embodiment, the modulated filter signal dsmout is the modulated filter control signal dlfout, based on which the second digital-to-analog converter 303 receives the modulated filter control signal dlfout. The differential integral modulator 304 implements gain control in the integral path, which helps to reduce the quantization noise in the integral path module 3, and further helps to reduce the design difficulty of the second digital-to-analog converter 303.

[0068] It can be seen that the integral path module 3 is designed using a digital method, for example, the digital loop filter 302 is designed using an accumulator-related digital circuit, so that the integral path module 3 retains the advantages of the digital phase-locked loop. Combined with the proportional path module 2, the phase-locked loop circuit of the embodiment of the present disclosure combines the advantages of the analog phase-locked loop and the digital phase-locked loop, which not only reduces the area of ​​the phase-locked loop circuit, but also benefits from the miniaturization of the integrated circuit process, and also helps to reduce the quantization noise of the phase-locked loop circuit.

[0069] Combination Figure 3 , Figure 4 As shown, in the exemplary embodiment, the current controlled oscillation module 4 includes an adder 401 and a current controlled oscillator 402. The adder 401 is coupled to the proportional path module 2 and the integral path module 3, and is used to receive the first control current iprop and the second control current iint, and add the first control current iprop and the second control current iint to obtain the current control signal iico. The current controlled oscillator 402 is coupled to the adder 401, and is used to receive the current control signal iico, and generate a clock output signal fout according to the current control signal iico. It can be seen that in the embodiment of the present disclosure, the clock output signal fout generated by the current controlled oscillator 402 is jointly controlled by the first control current iprop generated by the proportional path module 2 and the second control current iint generated by the integral path module 3, because the integral path module 3 and the proportional path module 2 combine the advantages of the analog phase-locked loop and the digital phase-locked loop, so that the clock output signal fout generated by the current controlled oscillator 402 based on the first control current iprop and the second control current iint is more accurate.

[0070] like Figure 4As shown, in the exemplary embodiment, the phase-locked loop circuit of the embodiment of the present disclosure may further include a coarse adjustment calibration module 6. The coarse adjustment calibration module 6 is coupled to the current control oscillation module 4, and is used to generate a coarse adjustment current icoarse, and the coarse adjustment current icoarse is used to determine the target frequency range of the clock output signal fout. Among them, the current control oscillation module 4 further generates the clock output signal fout according to the first control current iprop, the second control current iint and the coarse adjustment current icoarse. In the current control oscillation module 4, the adder 401 is also coupled to the coarse adjustment calibration module 6, and the adder 401 receives the coarse adjustment current icoarse in addition to the first control current iprop and the second control current iint, and adds the first control current iprop, the second control current iint and the coarse adjustment current icoarse to obtain the current control signal iico, so that the current control signal iico contains the components of the first control current iprop, the second control current iint and the coarse adjustment current icoarse.

[0071] In the exemplary embodiment, the coarse adjustment calibration module 6 does not include passive devices. In this way, it is helpful to reduce the area of ​​the phase-locked loop circuit, reduce PVT changes, eliminate the capacitance charge leakage problem of passive devices, and benefit from the miniaturization of integrated circuit technology. For example, the coarse adjustment calibration module 6 can be composed of digital circuit elements and analog transistor elements and no passive devices are used in the coarse adjustment calibration module 6. For example, the current source circuit in the coarse adjustment calibration module 6 can be constructed by analog transistor elements and the control circuit for controlling the current size in the coarse adjustment calibration module 6 can be constructed by digital circuit elements.

[0072] In an illustrative embodiment, the coarse adjustment calibration module 6 is implemented by a third digital-to-analog converter 601. Since the function of the third digital-to-analog converter 601 is to perform coarse adjustment calibration, the third digital-to-analog converter 601 may also be referred to as a coarse adjustment digital-to-analog converter (CDAC). In an illustrative embodiment, the third digital-to-analog converter 601 generates a coarse adjustment current icoarse according to the input related digital control signal. In an illustrative embodiment, the third digital-to-analog converter 601 does not include passive components. In this way, it is helpful to reduce the area of ​​the phase-locked loop circuit, reduce PVT changes, eliminate the problem of capacitive charge leakage of passive components, and benefit from the miniaturization of integrated circuit technology. For example, the third digital-to-analog converter 601 can be composed of digital circuit elements and analog transistor elements, and no passive components are used in the third digital-to-analog converter 601. For example, the current source circuit in the third digital-to-analog converter 601 can be constructed by analog transistor elements, and the control circuit for controlling the current size in the third digital-to-analog converter 601 can be constructed by digital circuit elements.

[0073] The coarse adjustment calibration module 6 is independent of the feedback loop of the phase-locked loop circuit, and its function is to use the generated coarse adjustment current icoarse to control the frequency band of the clock output signal fout of the current controlled oscillator 402 in the current controlled oscillation module 4. In the embodiment of the present disclosure, the coarse adjustment calibration module 6 can be used to set the frequency band range of various clock output signals fout of the phase-locked loop circuit.

[0074] The loop locking of the phase-locked loop circuit of the disclosed embodiment is mainly divided into two stages. The first stage is the open-loop coarse calibration stage, and the second stage is the closed-loop phase locking stage. In the open-loop coarse calibration stage, the proportional path module 2 and the integral path module 3 are disconnected, and the first control current iprop and the second control current iint are maintained as fixed default configuration values. The value of the coarse adjustment current icoarse is changed by inputting the code value of the digital control signal of the third digital-to-analog converter 601, thereby changing the frequency of the clock output signal fout of the current-controlled oscillator 402, and finding the frequency band closest to the target frequency. After the coarse calibration is completed, the code value of the digital control signal input to the third digital-to-analog converter 601 remains unchanged, and the proportional path module 2 and the integral path module 3 are closed. At this time, the feedback loop achieves precise phase locking through the phase detection and feedback compensation mechanism of the proportional path module 2 and the integral path module 3.

[0075] After open-loop coarse calibration and closed-loop phase locking, the coarse adjustment calibration module 6 and the integral path module 3 jointly determine the output frequency of the phase-locked loop circuit of the embodiment of the present disclosure, while the proportional path module 2 is mainly used for real-time phase compensation.

[0076] In addition to the advantages of high bandwidth and low quantization noise, the phase-locked loop circuit of the embodiment of the present disclosure also has the characteristic of unconditional stability. The following is explained by performing S-domain modeling analysis on the loop of the phase-locked loop circuit of the embodiment of the present disclosure.

[0077] Figure 7 is a schematic diagram of a small signal model of a phase-locked loop circuit according to an embodiment of the present disclosure. The small signal model is for Figure 4 The application scenario of the phase-locked loop circuit shown is obtained by S-domain modeling of the specific circuit. Figure 7Where: Kprop represents the gain of the first digital-to-analog converter 201; Kico_prop represents the gain of the current-controlled oscillator 402 due to the first control current iprop; Kint represents the gain of the digital loop filter 302; Kico_int represents the gain of the current-controlled oscillator 402 due to the second control current iint; 1 / N corresponds to the feedback divider 5, indicating that the feedback divider 5 divides the clock output signal fout by N; 1 / s corresponds to the current-controlled oscillator 402, which is an integrator in the frequency domain model, so 1 / s represents the integral of the current-controlled oscillator 402; φ ref Represents the phase of the reference clock signal ref; φ out Represents the phase of the clock output signal fout; φ div Represents the phase of the feedback clock signal div; φ e Represents the phase difference between the feedback clock signal div and the reference clock signal ref, which is reflected in the pulse width of the upper signal up and the lower signal dn, φ e A positive value represents a pulse that generates an up signal (the phase of the feedback clock signal div lags behind the reference clock signal ref), φ e A negative value represents a pulse of the down signal dn (the phase of the feedback clock signal div is ahead of the reference clock signal ref). Taking the above signal up and the first control current iprop as an example, Figure 5 As shown, the magnitude of the first control current iprop during the up signal pulse width is twice the reference output current value iprop_base. Therefore, the wider the up signal pulse width, the longer the duration of the first control current iprop, and thus the greater the phase compensation. This phase compensation is represented by Kico_prop.

[0078] from Figure 7 The small signal model of the phase-locked loop circuit of the embodiment of the present disclosure shown in the figure uses the relevant knowledge of control theory to obtain a closed-loop transfer function in the form of a standard second-order transfer function:

[0079]

[0080] Where ζ is the damping coefficient, expressed as:

[0081]

[0082] ω n is the natural frequency of the system (e.g., the phase-locked loop circuit of the embodiment of the present disclosure), which indicates the frequency of natural oscillation of the system without damping or external interference, ω n Also called loop bandwidth.

[0083] As mentioned above, in order to reduce the quantization noise of the integral path module 3, the gain is set to a very small value and the differential integral modulator 304 is introduced, so that the integral path gain In the embodiment of the present disclosure, the integral path gain can be achieved by setting the gain. Much smaller than the proportional path gain purpose, so as to obtain As a result (generally speaking, the phase-locked loop in the related art is a second-order system or a third-order system, and the damping coefficient of the phase-locked loop of the second-order system is usually around 1), the entire system of the phase-locked loop circuit of the embodiment of the present disclosure is an over-damped system, and the over-damped system is usually unconditionally stable. Based on this, the closed-loop transfer function of the loop can be further simplified as follows:

[0084]

[0085] Therefore, the phase-locked loop circuit of the embodiment of the present disclosure can be approximated as a first-order system. In this case, the loop bandwidth is:

[0086]

[0087] In practical applications, N is relatively fixed, so the above loop bandwidth formula shows that by adjusting the proportional path gain A larger loop bandwidth than that of a phase-locked loop in the related art can be achieved.

[0088] It can be seen from the above closed-loop transfer function that the phase-locked loop circuit of the embodiment of the present disclosure can be approximated as a first-order system, which theoretically guarantees the unconditional stability of the system. However, traditional phase-locked loops, including analog phase-locked loops and digital phase-locked loops, are usually second-order or third-order systems, and special care must be taken in the design of loop stability, and the phase margin under small signal analysis is usually required to be greater than 60°. In addition, since the phase-locked loop system is essentially a discrete-time nonlinear large signal system, the small signal analysis requires the phase-locked loop system to be approximated as a continuous system. Therefore, the premise of small signal analysis is to meet the discrete-to-continuous approximation condition, that is, the loop bandwidth must be less than 1 / 10 of the reference clock signal ref frequency. In order to ensure this approximation condition in engineering, the loop bandwidth is usually required to be less than 1 / 20 of the reference clock signal ref frequency. For example, in SoC, the typical frequency of the crystal oscillator clock is 25MHz, so the phase-locked loop bandwidth in the related art is at most about 1MHz. Generally speaking, in phase-locked loop design, the phase noise of the voltage-controlled oscillator is dominant, and the phase noise of the voltage-controlled oscillator presents a high-pass characteristic. The larger the bandwidth, the better the phase noise suppression effect of the voltage-controlled oscillator.

[0089] Since the phase-locked loop circuit of the embodiment of the present disclosure can be approximated as a first-order system, some restrictions in the traditional phase-locked loop do not need to be considered in the design of loop stability, that is, it is not restricted by the above-mentioned bandwidth selection. The loop bandwidth can be much larger than 1 / 20 of the reference clock signal ref frequency required in the engineering, which can more effectively suppress phase noise and improve the performance of the phase-locked loop.

[0090] In summary, the phase-locked loop circuit of the embodiment of the present disclosure adopts a dual-path architecture of a proportional path module and an integral path module, and can flexibly optimize the design of the proportional path and the integral path respectively. Among them, the first control current is generated by using the first digital-to-analog converter in the proportional path module to detect the phase difference based on the reference clock signal and the feedback clock signal, which continues the behavior of the linear phase detection in the charge pump phase-locked loop and eliminates the main quantization noise in the full digital phase-locked loop (the quantization noise introduced by the time digital converter and the proportional path). The integral path module adopts the digital loop filter in the full digital phase-locked loop, which greatly reduces the area of ​​the loop filter, avoids the charge leakage problem of the capacitor used in the analog phase-locked loop, and reduces the dependence of the analog filter RC (resistance and capacitance) value used in the analog phase-locked loop on the process PVT change, which is easy to transplant between different processes. The gain of the digital loop filter in the integral path module is usually small, so that the quantization noise of the integral path is very small, which can usually be ignored. The loop of the phase-locked loop circuit of the embodiment of the present disclosure is an over-damped system, which is approximately a first-order system, so that the loop is unconditionally stable, and thus its bandwidth design can be greater than the limit required by the usual phase-locked loop design. The phase-locked loop circuit of the embodiment of the present disclosure combines the advantages of an analog charge pump phase-locked loop and a fully digital phase-locked loop, and helps to achieve the generation of a higher-performance clock with a smaller area, higher bandwidth, more stable loop, and lower quantization noise.

[0091] In an exemplary embodiment, a clock generator is further provided, comprising the phase-locked loop circuit according to any one of the above embodiments.

[0092] In an exemplary embodiment, a chip is further provided, comprising the phase-locked loop circuit according to any one of the above embodiments.

[0093] In an illustrative embodiment, an electronic device is also provided, comprising the chip of the above embodiment.

[0094] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0095] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A phase-locked loop circuit, characterized in that: include: A phase frequency detector, used for receiving a reference clock signal and a feedback clock signal, and generating a phase detection output signal according to the phase of the reference clock signal and the phase of the feedback clock signal; A proportional path module, coupled to the phase frequency detector, for receiving the phase detection output signal, and generating a first control current according to the phase detection output signal, wherein the proportional path module is composed of digital circuit elements and analog transistor elements and does not include passive devices; An integral path module, coupled to the phase frequency detector, for receiving the phase detection output signal and generating a second control current according to the phase detection output signal; a current-controlled oscillation module, coupled to the proportional path module and the integral path module, configured to receive the first control current and the second control current, and generate a clock output signal according to the first control current and the second control current; The feedback frequency divider is coupled to the current controlled oscillation module and the frequency and phase detector, and is used for receiving the clock output signal and obtaining the feedback clock signal by dividing the frequency of the clock output signal.

2. The phase-locked loop circuit according to claim 1, characterized in that: The proportional path module comprises: The first digital-to-analog converter is coupled to the phase frequency detector and the current controlled oscillation module, and is used for generating the first control current according to the phase detection output signal.

3. The phase-locked loop circuit according to claim 2, characterized in that: The phase-comparison output signal includes an up signal and a down signal; The first digital-to-analog converter generates the first control current of different magnitudes according to the level of the upper signal and the level of the lower signal.

4. The phase-locked loop circuit according to claim 3, characterized in that: When both the upper signal and the lower signal are at low levels, the magnitude of the first control current is a reference output current value preset by the first digital-to-analog converter; When the upper signal is at a high level and the lower signal is at a low level, the magnitude of the first control current is twice the value of the reference output current; When the upper signal is at a low level and the lower signal is at a high level, the magnitude of the first control current is 0.

5. The phase-locked loop circuit according to claim 1, characterized in that: The integral path module comprises: A Bang-Bang phase detector, coupled to the phase frequency detector, for receiving the phase detection output signal, and generating an early-late signal according to the phase detection output signal; a digital loop filter, coupled to the Bang-Bang phase detector, for receiving the early-late signal and generating a filter control signal according to the early-late signal; and The second digital-to-analog converter is coupled to the digital loop filter, and is used for receiving the filtering control signal, and generating the second control current of different magnitudes according to the magnitude of the filtering control signal.

6. The phase-locked loop circuit according to claim 5, characterized in that: The integral path module also includes: a differential integral modulator, coupled between the digital loop filter and the second digital-to-analog converter, and configured to modulate the filter control signal to obtain a modulated filter signal; The filtering control signal received by the second digital-to-analog converter is the modulated filtering signal obtained by modulation by the differential integral modulator.

7. The phase-locked loop circuit according to claim 1, characterized in that: The current controlled oscillation module comprises: an adder, coupled to the proportional path module and the integral path module, configured to receive the first control current and the second control current, and add the first control current and the second control current to obtain a current control signal; The current controlled oscillator is coupled to the adder and is used for receiving the current control signal and generating the clock output signal according to the current control signal.

8. The phase-locked loop circuit according to claim 1, characterized in that: The phase-locked loop circuit also includes: a coarse adjustment calibration module, coupled to the current controlled oscillation module, for generating a coarse adjustment current, wherein the coarse adjustment current is used to determine a target frequency range of the clock output signal; Wherein, the current-controlled oscillation module further generates the clock output signal according to the first control current, the second control current and the coarse adjustment current.

9. A clock generator, characterized in that: Comprising the phase-locked loop circuit according to any one of claims 1 to 8.

10. A chip, characterized in that: Comprising the phase-locked loop circuit according to any one of claims 1 to 8.

11. An electronic device, characterized in that: Comprising the chip as claimed in claim 10.

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