Phase-locked loop locking detection circuit
By designing a phase-locked loop lock detection circuit based on timing and logic relationships, the problem of complex system design and high cost caused by the PLL lock detection circuit in the prior art requires an off-chip RC filter, and the PLL lock detection function with a simple structure, a small area, and no off-chip device is realized.
Patent Information
- Application Number
- CN202510000691.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-04-18
AI Technical Summary
In the prior art, the PLL lock detection circuit requires an off-chip RC filter, resulting in complex system design and high cost.
A phase-locked loop lock detection circuit is designed to realize PLL lock detection through reference clock circuit, feedback clock circuit, flip-flop and AND gate only through timing and logic relationships. It has a simple structure, small area and no off-chip devices are required.
The PLL lock detection function is realized, with a simple structure, small area and no off-chip devices required, which is conducive to saving system costs.
Smart Images
Figure CN119853678A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of circuit technology, and in particular to a phase-locked loop lock detection circuit and a phase-locked loop thereof. Background Art
[0002] Phase Locked Loop (PLL) clock sources are widely used in various electronic devices and systems. For example, PLL generates stable high-frequency signals, which is crucial in wireless communications, satellite communications, radar systems, RF test equipment, spectrum analyzers and other fields. Through PLL, functions such as digital signal processing, clock generation and frequency synthesis can be realized. In high-speed data transmission, PLL is used to extract the clock signal from the received data stream to ensure the correct sampling and processing of the data. This is especially important in digital communication systems to ensure accurate transmission and demodulation of data.
[0003] However, when the PLL works abnormally, such as being unable to lock stably or being unable to lock, how the system can quickly detect and respond becomes an important part of the system design. In order to ensure that the application system can quickly detect the abnormality of the PLL operation, the PLL usually uses a lock detection circuit to output the PLL lock state. Therefore, the PLL lock detection circuit has become an important module for providing PLL application systems with PLL working status detection.
[0004] At present, in many PLL application fields, it is found that the PLL circuit or PLL single chip will give a lock indication signal. For example, inside the chip, the PLL lock indication signal can participate in the working sequence inside the chip to reduce the confusion of the chip power-on sequence or reduce the working current.
[0005] In the prior art, the charge and discharge control signal of the charge pump is output from the PFD and then output to the chip port after passing through the NOR gate. Then, an off-chip RC filter is used to filter the signal to indicate the PLL lock. The disadvantage of this method is that it requires off-chip components to cooperate, which is not conducive to cost saving and increases the complexity of system design.
[0006] In order to solve the above problems, it is urgent to provide a phase-locked loop lock detection circuit and a phase-locked loop thereof. Summary of the invention
[0007] The purpose of the present invention is to provide a phase-locked loop lock detection circuit and a phase-locked loop thereof, so as to achieve the effect of simple structure, small area, no need for off-chip devices, and saving system cost.
[0008] To achieve this object, the present invention adopts the following technical solutions: A phase-locked loop lock detection circuit, comprising: A reference clock circuit, wherein an input terminal of the reference clock circuit inputs a reference clock signal, passes through a delay unit and is reversed once, and then outputs a reference signal; a first feedback clock circuit, wherein a feedback clock signal inputted into an input terminal of the first feedback clock circuit is inverted once and then outputted as a first feedback clock signal; A second feedback clock circuit, wherein a feedback clock inputted at an input end of the second feedback clock circuit outputs a second feedback clock signal after passing through two delay units and two inversions; a first flip-flop and a second flip-flop, the reference signal being output to the first flip-flop and the second flip-flop respectively, the first feedback clock signal being output to an input terminal of the first flip-flop, the second feedback clock signal being output to an input terminal of the second flip-flop, the output of the first flip-flop being a first output signal, and the output signal of the second flip-flop being a second output signal; and AND gate, the first output signal and the second output signal are both connected to the input end of the AND gate, the AND gate outputs a lock detection signal, when the first output signal and the second output signal are both high level, the AND gate outputs a lock detection signal of high level, then the phase-locked loop is locked, when one of the first output signal and the second output signal is low level, the AND gate outputs a lock detection signal of low level, then the phase-locked loop is unlocked.
[0009] As an optional scheme, the reference clock circuit includes a first delay unit and a first inverter, the reference clock signal is input into the input end of the first delay unit, the output end of the first delay unit is connected to the input end of the first inverter, and the output end of the first inverter outputs the reference clock signal.
[0010] As an optional solution, the first feedback clock circuit includes a second inverter, and the feedback clock signal input to the input end of the first feedback clock circuit passes through the second inverter to output the first feedback clock signal.
[0011] As an optional scheme, the second feedback clock circuit includes a second delay unit, a third delay unit, a third inverter and a fourth inverter. The feedback clock input to the input end of the second feedback clock circuit passes through the third inverter, the second delay unit, the third delay unit and the fourth inverter in sequence, and then outputs a second feedback clock signal.
[0012] As an optional scheme, the second feedback clock circuit includes a second delay unit, a third delay unit and a third inverter, the input end of the second delay unit is connected to the output end of the second inverter, the second delay unit, the third delay unit and the third inverter are connected in sequence, and the output end of the third inverter outputs the second feedback clock signal.
[0013] As an optional solution, both the first trigger and the second trigger use rising edges to sample input data.
[0014] As an optional solution, the input terminals of the reference clock circuit and the delay unit of the second feedback clock circuit can both be input with bias current adjustment control.
[0015] As an optional solution, the delay unit includes: The first branch includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the source and gate of the first NMOS tube and the gate of the second NMOS tube are connected to a power supply, the drains of the first NMOS tube and the second NMOS tube are respectively connected to the ground terminal, and the drain of the second NMOS tube is connected to the source of the first PMOS tube.
[0016] As an optional solution, the delay unit further includes: The second branch includes a third NMOS tube, a fourth NMOS tube, a second PMOS tube, a third PMOS tube, a fifth inverter, a sixth inverter, a first capacitor and a second capacitor. The fifth inverter and the sixth inverter are connected in sequence. The output end of the fifth inverter is a signal input end, and the output end is respectively connected to the input end of the sixth inverter and the first capacitor. The other end of the first capacitor is connected to the ground end. The output end of the sixth inverter is respectively connected to the external circuit and the second capacitor. The other end of the second capacitor is connected to the ground end. The two ends of the fifth inverter are respectively connected to the source of the third NMOS tube and the source of the second PMOS tube. The drain of the third NMOS tube is connected to the ground end. The gate of the third NMOS tube is connected to a negative voltage, and the gate of the second PMOS tube is connected to a positive voltage. The two ends of the sixth inverter are respectively connected to the source of the fourth NMOS tube and the source of the third PMOS tube. The drain of the fourth NMOS tube is connected to the ground end. The gate of the fourth NMOS tube is connected to a negative voltage, and the gate of the third PMOS tube is connected to a positive voltage.
[0017] As an optional solution, the fifth inverter includes a fifth NMOS tube and a fourth PMOS tube, the gates of the fifth NMOS tube and the fourth PMOS tube are connected in common to the input end of the fifth inverter, the source of the fifth NMOS tube is connected to the source of the fourth PMOS tube and is connected to the output end, the drain of the fifth NMOS tube is connected to the source of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the source of the second PMOS tube; The sixth inverter includes a sixth NMOS tube and a fifth PMOS tube, the gates of the sixth NMOS tube and the fifth PMOS tube are connected in common to the input end of the sixth inverter, the source of the sixth NMOS tube is connected to the source of the fifth PMOS tube and to the output end, the drain of the sixth NMOS tube is connected to the source of the fourth NMOS tube, and the drain of the fifth PMOS tube is connected to the source of the third PMOS tube.
[0018] The beneficial effects of the present invention are: The invention provides a phase-locked loop lock detection circuit, comprising a reference clock circuit, a first feedback clock circuit, a second feedback clock circuit, a first trigger, a second trigger and an AND gate. The reference clock signal is input to the input end of the reference clock circuit and outputs the reference signal after passing through a delay unit and a reversal. The feedback clock signal is input to the input end of the first feedback clock circuit and outputs the first feedback clock signal after passing through a reversal. The feedback clock signal is input to the input end of the second feedback clock circuit and outputs the second feedback clock signal after passing through two delay units and two reversals. The reference signal is output to the first trigger and the second trigger respectively. The first feedback clock signal is output to the input end of the first trigger, and the second feedback clock signal is output to the input end of the second trigger. The first trigger outputs a first output signal, and the second trigger outputs a second output signal. The first output signal and the second output signal are both connected to the input end of the AND gate. The AND gate outputs a lock detection signal. When the first output signal and the second output signal are both high level, the AND gate outputs a lock detection signal of a high level, and the phase-locked loop is locked. When one of the first output signal and the second output signal is low level, the AND gate outputs a lock detection signal of a low level, and the phase-locked loop is unlocked. The phase-locked loop lock detection circuit realizes the PLL lock detection circuit only through timing and logic relationship by using a delay unit, a trigger, an inverter and an AND gate. The structure is simple and the area is small, no external devices are required, and it is beneficial to save system cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.
[0020] Figure 1 Schematic diagram of a phase-locked loop lock detection circuit provided by an embodiment of the present invention Figure 1 ; Figure 2 is a working timing diagram of a phase-locked loop lock detection circuit provided by an embodiment of the present invention; Figure 3 Schematic diagram of a phase-locked loop lock detection circuit provided by an embodiment of the present invention Figure 2 ; Figure 4 Schematic diagram of a delay unit provided in an embodiment of the present invention.
[0021] The following are marked in the figure: 100-reference clock circuit; 110-first delay unit; 120-first inverter; 200-a first feedback clock circuit; 210-a second inverter; 300 - second feedback clock circuit; 310 - second delay unit; 320 - third delay unit; 330 - third inverter; 400 - first trigger; 500 - second trigger; 600 - AND gate. DETAILED DESCRIPTION
[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only partial structures related to the present invention are shown in the accompanying drawings, rather than the entire structure.
[0023] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the connection of the internal structures of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0024] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0025] In the description of this embodiment, the terms "upper", "lower", "left", "right" and other directions or positional relationships are based on the directions or positional relationships shown in the drawings, and are only for the convenience of description and simplification of operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.
[0026] like Figure 1 As shown, this embodiment provides a phase-locked loop lock detection circuit, which includes a reference clock circuit 100. The reference clock signal input to the input end of the reference clock circuit 100 is output after passing through a delay unit and a reverse. When the input reference clock signal is CLK_REF, after a delay time Wt, a reference signal CLK_REF_bar is output.
[0027] The phase-locked loop lock detection circuit also includes a first feedback clock circuit 200. The feedback clock signal input to the input end of the first feedback clock circuit 200 is inverted once and then outputs a first feedback clock signal. When the feedback clock signal is CLK_Fb, the output first feedback clock signal is Ck_fb_bar.
[0028] The phase-locked loop lock detection circuit also includes a second feedback clock circuit 300. The feedback clock input to the input end of the second feedback clock circuit 300 outputs a second feedback clock signal after two delay units and two inversions. When the feedback clock signal is CLK_Fb, the output second feedback clock signal is Ck_fb_2xdelay.
[0029] The phase-locked loop lock detection circuit also includes a first trigger 400 and a second trigger 500, reference signals are output to the first trigger 400 and the second trigger 500 respectively, a first feedback clock signal is output to the input end of the first trigger 400, a second feedback clock signal is output to the input end of the second trigger 500, the first trigger 400 outputs a first output signal, and the second trigger 500 outputs a second output signal. In the phase-locked loop lock detection circuit, the first trigger 400 input clock is the reference signal CLK_REF_bar, and the input data D port is Ck_fb_bar; the second trigger 500 input clock is the reference signal CLK_REF_bar, and the input data D port is Ck_fb_2xdelay.
[0030] The phase-locked loop lock detection circuit also includes an AND gate 600, the first output signal and the second output signal are both connected to the input end of the AND gate 600, and the AND gate 600 outputs a lock detection signal. When the first output signal and the second output signal are both high-level, the output lock detection signal is high-level, and the phase-locked loop is locked. When one of the first output signal and the second output signal is low-level, the output lock detection signal is low-level, and the phase-locked loop is unlocked.
[0031] See also Figure 1 and Figure 2 , when the phase of CLK_fb lags behind CLK_REF by △t, the phase difference between CLK_REF and CLK_fb is recorded as -△t. When the phase of CLK_fb leads CLK_REF by △t, the phase difference between CLK_REF and CLK_fb is recorded as △t. When the phase of CLK_fb lags behind CLK_REF by △t, the high level time margin of the first output signal is Wt-△t, and the high level time margin of the second output signal is Wt+△t. When the phase of CLK_fb leads CLK_REF by △t, the high level time margin of the first output signal is Wt+△t, and the high level time margin of the second output signal is Wt-△t.
[0032] Therefore, when the delay Wt of the lock window delay unit is less than the phase difference Δt between CLK_fb and CLK_REF, one of the first output signal or the second output signal will become low, causing the output lock detection signal Ldet to become low, thereby determining that the PLL loop is unlocked. When the delay Wt of the lock window delay unit is greater than the phase difference Δt between CLK_fb and CLK_REF and less than 0.5 CLK_REF cycle + Δt, the first output signal or the second output signal is high, causing the output lock detection signal Ldet to become high, thereby determining that the PLL loop is locked.
[0033] The phase-locked loop lock detection circuit realizes the PLL lock detection circuit only through timing and logic relationship by using a delay unit, a trigger, an inverter and an AND gate 600. The structure is simple and the area is small, no external devices are required, and the system cost is saved.
[0034] like Figure 1-Figure 3 As shown, further, the reference clock circuit 100 includes a first delay unit 110 and a first inverter 120, the reference clock signal is input to the input end of the first delay unit 110, the output end of the first delay unit 110 is connected to the input end of the first inverter, and the output end of the first inverter outputs the reference clock signal, thereby realizing the output of the reference clock signal.
[0035] The first feedback clock circuit 200 includes a second inverter 210 . The feedback clock signal input to the input end of the first feedback clock circuit 200 passes through the second inverter 210 and then outputs a first feedback clock signal.
[0036] In one embodiment, the second feedback clock circuit 300 includes a second delay unit 310, a third delay unit 320 and a third inverter 330, the input end of the second delay unit 310 is connected to the output end of the second inverter 210, the second delay unit 310, the third delay unit 320 and the third inverter 330 are connected in sequence, and the output end of the third inverter 330 outputs a second feedback clock signal. Through the first feedback clock and the second feedback clock circuit 300, a PLL lock indication circuit with a wide adjustment range is realized by using a delay unit with a wide delay range and a timing plus combinational logic. At the same time, the second feedback clock circuit 300 and the first feedback clock circuit 200 share the second inverter 210, which is conducive to further simplifying the structure and reducing costs.
[0037] The second feedback clock circuit 300 includes a second delay unit 310, a third delay unit 320, a third inverter 330 and a fourth inverter. The second feedback clock circuit 300 inputs a feedback clock which passes through the third inverter 330, the second delay unit 310, the third delay unit 320 and the fourth inverter in sequence and then outputs a second feedback clock signal. Through the first feedback clock and the second feedback clock circuit 300, a PLL lock indication circuit with a wide adjustment range is realized by using a delay unit with a wide delay range and a timing plus combinational logic.
[0038] Both the first flip-flop 400 and the second flip-flop 500 use rising edges to sample input data for comparison.
[0039] The input terminals of the delay units of the reference clock circuit 100 and the second feedback clock circuit 300 can both be input with bias current adjustment control, which is beneficial to adjust the charge and discharge current.
[0040] like Figure 4 As shown, further, the delay unit includes a first branch, the first branch includes a first NMOS tube mn1, a second NMOS tube mn2 and a first PMOS tube mp1, the source and gate of the first NMOS tube mn1, and the gate of the second NMOS tube mn2 are connected to the power supply, the drains of the first NMOS tube mn1 and the second NMOS tube mn2 are respectively connected to the ground terminal, and the drain of the second NMOS tube mn2 is connected to the source of the first PMOS tube mp1 to adjust the charging and discharging current of the current mirror.
[0041] In addition, the delay unit also includes a second branch, the second branch includes a third NMOS tube mn3, a fourth NMOS tube mn4, a second PMOS tube mp2, a third PMOS tube mp3, a fifth inverter, a sixth inverter, a first capacitor C and a second capacitor C1, the fifth inverter and the sixth inverter are connected in sequence, the output end of the fifth inverter is a signal input end, the output end is respectively connected to the input end of the sixth inverter and the first capacitor, the other end of the first capacitor is connected to the ground end, the output end of the sixth inverter is respectively connected to the external circuit and the second capacitor, and the other end of the second capacitor is connected to the ground end. The first and second PMOS tubes are connected to the ground terminal, the second and third NMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the second and third NMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the second and third NMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the second and third NMOS tubes are connected to the ground terminal, the second and third PMOS tubes are connected to the ground terminal, the third and fourth N ...
[0042] Specifically, the fifth inverter includes a fifth NMOS tube mn5 and a fourth PMOS tube mp4, the gates of the fifth NMOS tube mn5 and the fourth PMOS tube mp4 are connected to the input end of the fifth inverter, the source of the fifth NMOS tube mn5 is connected to the source of the fourth PMOS tube mp4 and to the output end, the drain of the fifth NMOS tube mn5 is connected to the source of the third NMOS tube mn3, and the drain of the fourth PMOS tube mp4 is connected to the source of the second PMOS tube mp2; The sixth inverter includes a sixth NMOS tube mn6 and a fifth PMOS tube mp5, the gates of the sixth NMOS tube mn6 and the fifth PMOS tube mp5 are connected to the input end of the sixth inverter, the source of the sixth NMOS tube mn6 is connected to the source of the fifth PMOS tube mp5 and is connected to the output end, the drain of the sixth NMOS tube mn6 is connected to the source of the fourth NMOS tube mn4, and the drain of the fifth PMOS tube mp5 is connected to the source of the third PMOS tube mp3.
[0043] In the above delay unit circuit, the input Clk_in is input to the inverter composed of mp4 and mn5. When clk_in is high, C is discharged through mn5 and mn3, and the discharge current Ib discharge time Tdis=C*Vdd / Ib. When clk_in is low, C is charged through mp2 and mp4, and the charging current Ib charging time Tc=C*Vdd / Ib.
[0044] The output of the inverter formed by mp4 and mn5 is connected to the inverter formed by mp5 and mn6. Similarly, when mp4 and mn5 output high level, C1 discharges through mn6 and mn4, and the discharge current Ib discharge time Tdis=C1*Vdd / Ib. When clk_in is low level, C1 is charged through mp3 and mp5, and the charging current Ib charging time Tc=C1*Vdd / Ib.
[0045] Through the above analysis, it can be seen that the delay time of the delay unit can be controlled by Ib. Ib can be controlled from nA level to uA level, and the corresponding locking delay unit window time Wt can meet the wide adjustment range of phase difference time from ns to us, which can meet the PLL lock detection function requirements with reference frequency as low as 48kHz and as high as 100MHz, and has strong versatility.
[0046] When the lock delay unit window time Wt is configured to be greater than the phase difference time between the reference clock and the feedback clock when the PLL is locked, the lock detection requirements of the PLLs with different reference frequencies can be met.
[0047] The phase-locked loop lock detection circuit uses a clock delay circuit and related logic to implement a PLL lock indication circuit with a wide adjustment range, which can provide accurate PLL lock status indication for the inside of a chip or a chip application system.
[0048] In summary, the phase-locked loop lock detection circuit in this embodiment compares the phase difference between the input reference clock and the feedback clock with the configured lock window time Wt, and when the phase difference is less than Wt, it is considered that the PLL is in a locked state and outputs a lock indication high level. The phase-locked loop lock detection circuit can meet the PLL lock detection function requirements with a reference frequency as low as 48kHz and as high as 100MHz, and has the advantages of simple structure, small area, no need for additional off-chip components, and strong versatility.
[0049] Note that the above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected, and the scope of the present invention to be protected is defined by the attached claims and their equivalents.
Claims
1. A phase-locked loop lock detection circuit, characterized in that: include: A reference clock circuit (100), wherein an input end of the reference clock circuit (100) inputs a reference clock signal, passes through a delay unit and is reversed once, and then outputs a reference signal; A first feedback clock circuit (200), wherein a feedback clock signal input to an input end of the first feedback clock circuit (200) is inverted once and then outputs a first feedback clock signal; A second feedback clock circuit (300), wherein a feedback clock input to an input end of the second feedback clock circuit (300) outputs a second feedback clock signal after passing through two delay units and two inversions; a first flip-flop (400) and a second flip-flop (500), the reference signal being output to the first flip-flop (400) and the second flip-flop (500) respectively, the first feedback clock signal being output to an input end of the first flip-flop (400), the second feedback clock signal being output to an input end of the second flip-flop (500), the output of the first flip-flop (400) being a first output signal, and the output signal of the second flip-flop (500) being a second output signal; and An AND gate (600), wherein the first output signal and the second output signal are both connected to an input end of the AND gate (600), and the AND gate (600) outputs a lock detection signal. When the first output signal and the second output signal are both at a high level, the AND gate (600) outputs a lock detection signal at a high level, and the phase-locked loop is locked; when one of the first output signal and the second output signal is at a low level, the AND gate (600) outputs a lock detection signal at a low level, and the phase-locked loop is unlocked.
2. The phase-locked loop lock detection circuit according to claim 1, characterized in that: The reference clock circuit (100) comprises a first delay unit (110) and a first inverter (120); the reference clock signal is input to the input end of the first delay unit (110); the output end of the first delay unit (110) is connected to the input end of the first inverter (120); and the reference clock signal is output to the output end of the first inverter (120).
3. The phase-locked loop lock detection circuit according to claim 1, characterized in that: The first feedback clock circuit (200) comprises a second inverter (210), and a feedback clock signal input to an input end of the first feedback clock circuit (200) passes through the second inverter (210) to output a first feedback clock signal.
4. The phase-locked loop lock detection circuit according to claim 1, characterized in that: The second feedback clock circuit (300) comprises a second delay unit (310), a third delay unit (320), a third inverter (330) and a fourth inverter; a feedback clock input to an input end of the second feedback clock circuit (300) passes through the third inverter (330), the second delay unit (310), the third delay unit (320) and the fourth inverter in sequence, and then outputs a second feedback clock signal.
5. The phase-locked loop lock detection circuit according to claim 3, characterized in that: The second feedback clock circuit (300) comprises a second delay unit (310), a third delay unit (320) and a third inverter (330); the input end of the second delay unit (310) is connected to the output end of the second inverter (210); the second delay unit (310), the third delay unit (320) and the third inverter (330) are connected in sequence; and the output end of the third inverter (330) outputs the second feedback clock signal.
6. The phase-locked loop lock detection circuit according to claim 1, characterized in that: The first flip-flop (400) and the second flip-flop (500) both use rising edges to sample input data.
7. The phase-locked loop lock detection circuit according to claim 1, characterized in that: The input ends of the delay units of the reference clock circuit (100) and the second feedback clock circuit (300) can both be input with bias current adjustment control.
8. The phase-locked loop lock detection circuit according to any one of claims 1 to 7, characterized in that: The delay unit comprises: The first branch includes a first NMOS tube, a second NMOS tube and a first PMOS tube, the source and gate of the first NMOS tube and the gate of the second NMOS tube are connected to a power supply, the drains of the first NMOS tube and the second NMOS tube are respectively connected to the ground terminal, and the drain of the second NMOS tube is connected to the source of the first PMOS tube.
9. The phase-locked loop lock detection circuit according to claim 8, characterized in that: The delay unit also includes: The second branch includes a third NMOS tube, a fourth NMOS tube, a second PMOS tube, a third PMOS tube, a fifth inverter, a sixth inverter, a first capacitor and a second capacitor. The fifth inverter and the sixth inverter are connected in sequence. The output end of the fifth inverter is a signal input end, and the output end is respectively connected to the input end of the sixth inverter and the first capacitor. The other end of the first capacitor is connected to the ground end. The output end of the sixth inverter is respectively connected to the external circuit and the second capacitor. The other end of the second capacitor is connected to the ground end. The two ends of the fifth inverter are respectively connected to the source of the third NMOS tube and the source of the second PMOS tube. The drain of the third NMOS tube is connected to the ground end. The gate of the third NMOS tube is connected to a negative voltage, and the gate of the second PMOS tube is connected to a positive voltage. The two ends of the sixth inverter are respectively connected to the source of the fourth NMOS tube and the source of the third PMOS tube. The drain of the fourth NMOS tube is connected to the ground end. The gate of the fourth NMOS tube is connected to a negative voltage, and the gate of the third PMOS tube is connected to a positive voltage.
10. The phase-locked loop lock detection circuit according to claim 9, characterized in that: The fifth inverter comprises a fifth NMOS tube and a fourth PMOS tube, the gates of the fifth NMOS tube and the fourth PMOS tube are connected in common to the input end of the fifth inverter, the source of the fifth NMOS tube is connected to the source of the fourth PMOS tube and is connected to the output end, the drain of the fifth NMOS tube is connected to the source of the third NMOS tube, and the drain of the fourth PMOS tube is connected to the source of the second PMOS tube; The sixth inverter includes a sixth NMOS tube and a fifth PMOS tube, the gates of the sixth NMOS tube and the fifth PMOS tube are connected in common to the input end of the sixth inverter, the source of the sixth NMOS tube is connected to the source of the fifth PMOS tube and to the output end, the drain of the sixth NMOS tube is connected to the source of the fourth NMOS tube, and the drain of the fifth PMOS tube is connected to the source of the third PMOS tube.