Analog-to-digital conversion circuit based on clock signal bootstrap module, chip and electronic device

Abstract

The present disclosure relates to the field of analog-to-digital conversion, and proposes an analog-to-digital conversion circuit based on a clock signal bootstrap module, a chip and an electronic device. The circuit comprises a clock signal bootstrap module, a conversion module and a feedback module. The power supply voltages of the clock signal bootstrap module, the conversion module and the feedback module are equal and less than or equal to a first threshold value. The clock signal bootstrap module is used to generate at least one pair of clock signals with a swing greater than the first threshold value, and output the clock signals to the conversion module to drive at least one unit in the conversion module. The conversion module is used to obtain a digital output signal according to an analog input signal and a feedback signal. The feedback module is used to generate the feedback signal according to the latest digital output signal and output the feedback signal to the conversion module. The analog-to-digital conversion circuit of the present disclosure has a smaller chip area and lower power consumption, and can realize high-quality analog-to-digital conversion at a low voltage.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of analog-to-digital conversion, and in particular to an analog-to-digital conversion circuit based on a clock signal bootstrap module, a chip and an electronic device. BACKGROUND

[0002] With the application and development of Internet of Things (IoT), it is indispensable to obtain real-time information and data from IoT devices. Power supply of IoT devices is an important aspect in IoT system design, as it directly affects the reliability, durability and cost of the devices. The power supply of IoT devices generally has battery power supply, solar power supply, cable power supply, wireless charging and energy harvesting (EH).

[0003] However, in some environments, the density of energy that can be harvested is often low, and the voltage that can be generated is also very low, so that the IoT device must work at a low voltage. This brings great challenges to the performance of some circuits (such as analog-to-digital conversion circuits) in IoT devices. Some prior art cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low, and although some analog-to-digital conversion circuits proposed by some prior art can maintain high-quality analog-to-digital conversion when the power supply voltage is low, they increase the power consumption and chip area occupied by the analog-to-digital conversion circuit. SUMMARY

[0004] Therefore, the present disclosure proposes an analog-to-digital conversion circuit based on a clock signal bootstrap module, a chip and an electronic device. The analog-to-digital conversion circuit of the present disclosure has a smaller chip area and lower power consumption, and can achieve high-quality analog-to-digital conversion at a low voltage.

[0005] According to an aspect of the present disclosure, an analog-to-digital conversion circuit based on a clock signal bootstrap module is provided, which includes a clock signal bootstrap module, a conversion module and a feedback module. The power supply voltages of the clock signal bootstrap module, the conversion module and the feedback module are equal and less than or equal to a first threshold value. The clock signal bootstrap module is configured to generate at least one pair of clock signals with a swing greater than the first threshold value, and output the clock signals to the conversion module to drive at least one unit in the conversion module. The conversion module is configured to obtain a digital output signal according to an analog input signal and a feedback signal. The feedback module is configured to generate the feedback signal according to the latest digital output signal and output the feedback signal to the conversion module.

[0006] In a possible implementation, the conversion module comprises a first chopping unit, a capacitive filter unit, a dead zone control unit, a voltage-to-current conversion unit, a second chopping unit, an integration unit, a quantization unit, an output unit, the analog input signal comprises a differential first input signal and a second input signal, the feedback signal comprises a differential first feedback signal and a second feedback signal, a first end of the first chopping unit receives the first input signal, a second end of the first chopping unit receives the second input signal, a third end of the first chopping unit is connected to a first end of the capacitive filter unit, and a fourth end of the first chopping unit is connected to a second end of the capacitive filter unit; a third end of the capacitive filter unit is connected to a first end of the dead zone control unit and a fourth end of the feedback module, a fourth end of the capacitive filter unit is connected to a second end of the dead zone control unit and a third end of the feedback module, the fourth end of the feedback module outputs the first feedback signal, and the third end of the feedback module outputs the second feedback signal; a third end of the dead zone control unit is connected to a first end of the voltage-to-current conversion unit, and a fourth end of the dead zone control unit is connected to a second end of the voltage-to-current conversion unit; a third end of the voltage-to-current conversion unit is connected to a first end of the second chopping unit, and a fourth end of the voltage-to-current conversion unit is connected to a second end of the second chopping unit; a third end of the second chopping unit is connected to a first end of the integration unit, and a fourth end of the second chopping unit is connected to a second end of the integration unit; a third end of the integration unit is connected to a first end of the quantization unit, and a fourth end of the integration unit is connected to a second end of the quantization unit; a third end of the quantization unit is connected to a first end of the output unit and a first end of the feedback module, and a fourth end of the quantization unit is connected to a second end of the output unit and a second end of the feedback module; and a third end of the output unit outputs the digital output signal.

[0007] In a possible implementation, the quantization unit is a time-domain quantization unit, and the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented by using digital circuits.

[0008] In a possible implementation, the clock signal is used to drive the first chopping unit, the dead zone control unit, and the second chopping unit.

[0009] In a possible implementation, the clock signal bootstrapping module comprises at least one clock signal bootstrapping unit connected in cascade, each clock signal bootstrapping unit outputs a pair of clock signals, the clock signal output by a preceding clock signal bootstrapping unit is input to a following clock signal bootstrapping unit, and the swing of the clock signal output by the following clock signal bootstrapping unit is higher than the swing of the clock signal output by the preceding clock signal bootstrapping unit.

[0010] In a possible implementation, a swing of a clock signal used to drive the dead-time control unit is greater than or equal to a second threshold, a swing of a clock signal used to drive the first and second chopping units is greater than or equal to a third threshold, and the second threshold is greater than the third threshold.

[0011] In a possible implementation, the feedback module includes a logic control unit, a third chopping unit, and a capacitive digital-to-analog conversion unit, a first end of the logic control unit is a first end of the feedback module, a second end of the logic control unit is a second end of the feedback module, a third end of the logic control unit is connected to a first end of the third chopping unit, and a fourth end of the logic control unit is connected to a second end of the third chopping unit; a third end of the third chopping unit is connected to a first end of the capacitive digital-to-analog conversion unit, and a fourth end of the third chopping unit is connected to a second end of the capacitive digital-to-analog conversion unit; a third end of the capacitive digital-to-analog conversion unit is a third end of the feedback module, and a fourth end of the capacitive digital-to-analog conversion unit is a fourth end of the feedback module.

[0012] In a possible implementation, the clock signal bootstrap unit comprises a first bootstrap sub-unit and a second bootstrap sub-unit, the first bootstrap sub-unit comprises a first transistor, a second transistor, a third transistor, a first capacitor, the second bootstrap sub-unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a second capacitor, a first electrode of the first transistor is connected to a first electrode of the second transistor and serves as a first input terminal of the first bootstrap sub-unit, a second electrode of the first transistor is connected to a first terminal of the first capacitor and serves as a second input terminal of the first bootstrap sub-unit, a third electrode of the first transistor is connected to a third electrode of the second transistor, a first electrode of the third transistor and serves as an output terminal of the first bootstrap sub-unit, a second electrode of the second transistor is connected to a second electrode of the third transistor, a second terminal of the first capacitor, a third electrode of the third transistor is connected to a power supply voltage; a first electrode of the fourth transistor is connected to a first electrode of the fifth transistor and serves as a first input terminal of the second bootstrap sub-unit, a second electrode of the fourth transistor is connected to a first terminal of the second capacitor and serves as a second input terminal of the second bootstrap sub-unit, a third electrode of the fourth transistor is connected to a third electrode of the fifth transistor, a first electrode of the sixth transistor and serves as an output terminal of the second bootstrap sub-unit, a second electrode of the fifth transistor is connected to a second electrode of the sixth transistor, a second terminal of the second capacitor, a third electrode of the sixth transistor is connected to a power supply voltage; the first input terminal of the second bootstrap sub-unit is connected to the second input terminal of the first bootstrap sub-unit and receives a first clock signal, the second input terminal of the second bootstrap sub-unit is connected to the first input terminal of the first bootstrap sub-unit and receives a second clock signal, the output terminal of the first bootstrap sub-unit outputs a third clock signal, and the output terminal of the second bootstrap sub-unit outputs a fourth clock signal; the first clock signal and the second clock signal are a pair of differential signals and serve as clock signals input to the clock signal bootstrap unit, and the third clock signal and the fourth clock signal are a pair of differential signals and serve as clock signals output from the clock signal bootstrap unit.

[0013] According to another aspect of the present disclosure, there is provided a chip comprising the analog-to-digital conversion circuit of any one of the above.

[0014] According to another aspect of the present disclosure, there is provided an electronic device comprising the chip of the above.

[0015] According to the analog-digital conversion circuit provided in the embodiment of the present disclosure, the clock signal bootstrap module is set, so that the clock signal with the swing higher than the first threshold value can be obtained when the power supply voltage is lower than the first threshold value, the conversion module is driven by the clock signal, the digital output signal is obtained by the conversion module according to the analog input signal and the feedback signal, and the feedback module generates the feedback signal according to the latest digital output signal and outputs the feedback signal to the conversion module, so that the high-quality analog-digital conversion is realized. In the analog-digital conversion circuit, only part of the units in the conversion module are driven by the clock signal with high swing, and the other units of the conversion module, the clock signal bootstrap module and the feedback module can still be powered by the power supply voltage lower than the first threshold value, so that the power consumption of the entire analog-digital conversion circuit is low. Moreover, the analog-digital conversion circuit does not involve voltage boosting, so that no additional charge storage is needed, no large-capacity capacitor needs to be set, and the chip area occupied is smaller. In conclusion, the analog-digital conversion circuit provided in the embodiment of the present disclosure occupies a smaller chip area and has lower power consumption, and can realize high-quality analog-digital conversion at low voltage.

[0016] Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0018] Figure 1 A schematic diagram showing that the energy harvesting system supplies power for the circuit in the Internet of Things device.

[0019] Figure 2 A working scheme of the ADC when the supply voltage is low is shown.

[0020] Figure 3 Another working scheme of the ADC when the supply voltage is low is shown.

[0021] Figure 4 An exemplary application scenario of the analog-digital conversion circuit according to the embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic diagram showing the structure of the analog-digital conversion circuit according to the embodiment of the present disclosure is shown.

[0023] Figure 6 A schematic diagram showing the structure of the clock signal bootstrap module according to the embodiment of the present disclosure is shown.

[0024] Figure 7 A schematic diagram showing the structure of the clock signal bootstrap unit according to the embodiment of the present disclosure is shown.

[0025] Figure 8A schematic diagram showing another structure of a clock signal bootstrap module according to an embodiment of the present disclosure is shown.

[0026] Figure 9a A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure is provided.

[0027] Figure 9b A schematic diagram showing the structure of a conversion module according to an embodiment of the present disclosure is provided.

[0028] Figure 10 A schematic diagram showing the structure of a feedback module according to an embodiment of the present disclosure is provided. Detailed Implementation

[0029] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0030] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0031] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0032] Figure 1 This diagram illustrates how an energy harvesting system powers circuitry in an IoT device.

[0033] like Figure 1 As shown, an energy harvesting system can harvest energy from an external energy source and convert it into a supply voltage (VDD) for output to data transceiver modules, digital signal processors (DSPs), analog-to-digital converters (ADCs), etc., in IoT devices. The energy density harvested by such a system is often less than 100 μW / cm³. 2 The corresponding output voltage is typically below 300mV. This voltage powers the ADC, DSP, and data transceiver modules in the system. For the ADC, achieving high-quality analog-to-digital conversion at such a low voltage is extremely difficult.

[0034] Figure 2 This illustrates one operating scheme for the ADC when the supply voltage is low.

[0035] As shown in Figure 2 , a DC-DC converter can be used to directly increase the low voltage VDD output by the energy harvesting system to a high voltage VDD' that can make the ADC work normally, and provide it as a power supply voltage. The ADC converts the input analog signal V IN into a digital signal D OUT and outputs it. However, this results in a significant increase in the overall power consumption of the ADC. In addition, when using a DC-DC converter to raise the voltage, an additional capacitor with a very large area needs to be added to the chip to store the charge, which increases the chip area and thus the cost of the chip.

[0036] Figure 3 Another working scheme of the ADC when the power supply voltage is low is shown.

[0037] As shown in Figure 3 , another method is to directly implement analog-to-digital conversion at the low voltage VDD output by the energy harvesting system by using some ADCs that can still work normally at low voltage, such as oversampling ADCs based on inverters, oversampling ADCs based on ring oscillators, and successive approximation register (SAR) ADCs based on carefully designed comparators, to convert the input analog signal V IN into a digital signal D OUT and output it. However, the circuit modules in these ADCs are often very sensitive to the power supply voltage, and the quality of analog-to-digital conversion fluctuates greatly. Moreover, the quality of analog-to-digital conversion at low voltage, such as conversion linearity and conversion accuracy, of these ADCs is significantly different from that of ADCs that perform analog-to-digital conversion at normal voltage.

[0038] In summary, some existing technologies cannot maintain high-quality analog-to-digital conversion when the power supply voltage is low. Although some existing technologies propose analog-to-digital conversion circuits that can maintain high-quality analog-to-digital conversion when the power supply voltage is low, they increase the power consumption and chip area occupied by the analog-to-digital conversion circuit. How to reduce the power consumption and chip area occupied by the analog-to-digital conversion circuit while maintaining high-quality analog-to-digital conversion has become a technical problem to be solved in the field.

[0039] Therefore, the present disclosure proposes an analog-to-digital conversion circuit based on a clock signal bootstrap module, a chip, and an electronic device. The analog-to-digital conversion circuit of the present disclosure occupies a smaller chip area and has lower power consumption, and can implement high-quality analog-to-digital conversion at low voltage.

[0040] Figure 4 An exemplary application scenario of the analog-to-digital conversion circuit according to an embodiment of the present disclosure is shown.

[0041] As shown in Figure 4 The electronic device can include an energy harvesting system and a chip. The analog-to-digital conversion circuit of the embodiments of the present disclosure can be arranged on the chip. The energy harvesting system can power the chip. The power supply voltage output by the energy harvesting system can be less than a first threshold value, that is, the energy harvesting system outputs an ultra-low voltage. The value of the first threshold value can be set according to the requirements of the application scenario, for example, set to 0.3V. The embodiments of the present disclosure do not limit the specific value of the first threshold value.

[0042] The analog-to-digital conversion circuit can receive an analog input signal to be converted, and output a digital output signal after analog-to-digital conversion.

[0043] The chip can further be provided with a data transceiver module (not shown) and a digital signal processor (not shown). The analog input signal can be a signal received by the data transceiver module, and then transmitted to the analog-to-digital conversion circuit by the data transceiver module. The digital output signal can be output to the DSP for processing, or can be transmitted to the data transceiver module, and then transmitted to other devices / modules by the data transceiver module. The embodiments of the present disclosure do not limit this.

[0044] Those skilled in the art should understand that if the electronic device itself carries a power supply, the chip can also be powered by the power supply. When the power supply is insufficient and outputs a voltage signal with a value less than the first threshold value, the analog-to-digital conversion circuit on the chip can also achieve high-quality analog-to-digital conversion. The embodiments of the present disclosure do not limit the source of power for the chip.

[0045] Figure 5 A schematic diagram showing the structure of the analog-to-digital conversion circuit according to the embodiments of the present disclosure.

[0046] As shown in Figure 5 In one possible implementation, the circuit includes a clock signal bootstrap module, a conversion module, and a feedback module, the power supply voltages of the clock signal bootstrap module, the conversion module, and the feedback module are equal and less than or equal to a first threshold value,

[0047] The clock signal bootstrap module is configured to generate at least one pair of clock signals with a swing greater than the first threshold value, and output the clock signals to the conversion module to drive at least one unit in the conversion module;

[0048] The conversion module is configured to obtain a digital output signal according to an analog input signal and a feedback signal;

[0049] The feedback module is configured to generate a feedback signal according to the latest digital output signal and output the feedback signal to the conversion module.

[0050] For example, the analog-to-digital conversion circuit can include a clock signal bootstrap module, a conversion module, and a feedback module, and all three modules are powered by a power supply voltage less than the first threshold value.

[0051] The clock signal bootstrapping module can generate at least one pair of clock signals with a swing greater than a first threshold value, and output the clock signals to the conversion module to drive at least one cell in the conversion module. The conversion module can include a plurality of cells, and some key cells can maintain high performance under the driving of the clock signals with high swing. In this case, the clock signals generated by the clock signal bootstrapping module can be used to drive these key cells.

[0052] The embodiments of the present disclosure do not limit the specific structure of the clock signal bootstrapping module and the conversion module, as long as the clock signal bootstrapping module and the conversion module can implement the above functions. Examples of the structure of the clock signal bootstrapping module, examples of the structure of the conversion module, and examples of the key cells are given below.

[0053] The analog-to-digital conversion process can include three main stages of voltage-to-current conversion, integration, and quantization, which can all be completed by the conversion module. Before entering the voltage-to-current conversion stage, the analog input signal can also be operated, such as chopping, to optimize the quality of the signal. When performing the voltage-to-current conversion operation, the higher the swing of the analog input signal, the greater the deviation of the final digital output signal. Therefore, the conversion module can use the feedback signal to adjust the swing of the analog input signal, and then perform voltage-to-current conversion, integration, quantization, and other operations on the adjusted analog input signal to obtain the digital output signal.

[0054] The analog input signal is periodically input to the conversion module, so the conversion module outputs the digital output signal more than once. The feedback signal can be generated by the feedback module according to the latest digital output signal. In this way, the accuracy of adjusting the analog-to-digital conversion process using the feedback signal can be improved. The embodiments of the present disclosure do not limit the specific structure of the feedback module, as long as the feedback module can implement the above functions. Examples of the structure of the feedback module are given below.

[0055] According to the analog-digital conversion circuit, the clock signal bootstrap module is arranged, so that the clock signal with the swing higher than the first threshold value can be obtained under the power supply voltage lower than the first threshold value, the conversion module is driven by the clock signal, the conversion module obtains the digital output signal according to the analog input signal and the feedback signal, and the feedback module generates the feedback signal according to the latest digital output signal and outputs the feedback signal to the conversion module, so that high-quality analog-digital conversion is realized. In the analog-digital conversion circuit, only part of units in the conversion module are driven by the clock signal with the high swing, and the other units of the conversion module, the clock signal bootstrap module and the feedback module can still be powered by the power supply voltage lower than the first threshold value, so that the power consumption of the analog-digital conversion circuit as a whole is low. Moreover, the analog-digital conversion circuit does not involve voltage boosting, so that additional charge storage is not needed, a large-capacity capacitor does not need to be arranged, and the chip area occupied by the analog-digital conversion circuit is smaller. In summary, the analog-digital conversion circuit according to the embodiment of the present disclosure occupies a smaller chip area and has lower power consumption, and can realize high-quality analog-digital conversion under low voltage.

[0056] Figure 6 A schematic diagram showing the structure of the clock signal bootstrap module according to the embodiment of the present disclosure is shown.

[0057] As shown in Figure 6 In a possible implementation, the clock signal bootstrap module includes at least one clock signal bootstrap unit in cascade, each clock signal bootstrap unit outputs a pair of clock signals, the output clock signal of the front-stage clock signal bootstrap unit is input to the rear-stage clock signal bootstrap unit as the input clock signal, and the swing of the output clock signal of the rear-stage clock signal bootstrap unit is higher than the swing of the output clock signal of the front-stage clock signal bootstrap unit.

[0058] For example, if the swing of the clock signal obtained by a single clock signal bootstrap unit can meet the driving requirement, the clock signal bootstrap module includes only one clock signal bootstrap unit. If the swing of the clock signal obtained by a single clock signal bootstrap unit cannot meet the driving requirement, the clock signal bootstrap module can include a plurality of clock signal bootstrap units in cascade, each clock signal bootstrap unit outputs a pair of clock signals, and the output clock signal of the front-stage clock signal bootstrap unit is input to the rear-stage clock signal bootstrap unit as the input clock signal. Since the clock signal bootstrap unit can improve the swing of the clock signal, the swing of the output clock signal of the rear-stage clock signal bootstrap unit is higher than the swing of the output clock signal of the front-stage clock signal bootstrap unit.

[0059] The circuit structure of each clock signal bootstrap unit can be the same or different. The embodiment of the present disclosure does not limit the specific structure of each clock signal bootstrap unit, as long as the number of the output clock signals of the front-stage clock signal bootstrap unit is consistent with the number of the input clock signals of the rear-stage clock signal bootstrap unit.

[0060] The high level of the first clock signal received by the first stage clock signal bootstrap unit can be equal to the power supply voltage, and the high level of the first clock signal received by the clock signal bootstrap units of the second stage and subsequent stages can be greater than the power supply voltage. In an ideal case, the high level of the clock signal output by the kth stage (k is a positive integer) clock signal bootstrap unit can be equal to k+1 times the power supply voltage.

[0061] In this way, the clock signal bootstrap circuit can output a clock signal that meets the requirements of the application scenario.

[0062] Figure 7 A schematic diagram showing the structure of a clock signal bootstrap unit according to an embodiment of the present disclosure.

[0063] As shown in Figure 7 In one possible implementation, the clock signal bootstrap unit includes a first bootstrap subunit 51 and a second bootstrap subunit 52, the first bootstrap subunit 51 includes a first transistor M1, a second transistor M2, a third transistor M3, a first capacitor C1, the second bootstrap subunit 52 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second capacitor C2,

[0064] The first pole m11 of the first transistor is connected to the first pole m21 of the second transistor and serves as the first input end w11 of the first bootstrap subunit, the second pole m12 of the first transistor is connected to the first end c11 of the first capacitor and serves as the second input end w12 of the first bootstrap subunit, the third pole m13 of the first transistor is connected to the third pole m23 of the second transistor, the first pole m31 of the third transistor and serves as the output end w13 of the first bootstrap subunit, the second pole m22 of the second transistor is connected to the second pole m32 of the third transistor, the second end c12 of the first capacitor, and the third pole m33 of the third transistor is connected to the power supply voltage VDD;

[0065] The first pole m41 of the fourth transistor is connected to the first pole m51 of the fifth transistor and serves as the first input end w21 of the second bootstrap subunit, the second pole m42 of the fourth transistor is connected to the first end c21 of the second capacitor and serves as the second input end w22 of the second bootstrap subunit, the third pole m43 of the fourth transistor is connected to the third pole m53 of the fifth transistor, the first pole m61 of the sixth transistor and serves as the output end w23 of the second bootstrap subunit, the second pole m52 of the fifth transistor is connected to the second pole m62 of the sixth transistor, the second end c22 of the second capacitor, and the third pole m63 of the sixth transistor is connected to the power supply voltage VDD;

[0066] The first input end w21 of the second bootstrap subunit is connected to the second input end w12 of the first bootstrap subunit, and receives the first clock signal CLK PThe second input end w22 of the second bootstrap unit is connected with the first input end w11 of the first bootstrap unit, and receives the second clock signal CLK N The output end w13 of the first bootstrap unit outputs the third clock signal CLK BSTP The output end w23 of the second bootstrap unit outputs the fourth clock signal CLK BSTN ;

[0067] The first clock signal CLK P and the second clock signal CLK N are a pair of differential signals and are clock signals input by the clock signal bootstrap unit, the third clock signal CLK BSTP and the fourth clock signal CLK BSTN are a pair of differential signals and are clock signals output by the clock signal bootstrap unit.

[0068] For example, the clock signal bootstrap unit can include a first bootstrap unit and a second bootstrap unit.

[0069] The first bootstrap unit can include a first transistor, a second transistor, a third transistor and a first capacitor.

[0070] The second bootstrap unit can include a fourth transistor, a fifth transistor, a sixth transistor and a second capacitor. The first transistor can be an N-channel transistor, the second transistor and the third transistor can be P-channel transistors. The fourth transistor can be an N-channel transistor, the fifth transistor and the sixth transistor can be P-channel transistors. The first pole of each transistor can be a gate, the second pole can be a source, and the third pole can be a drain.

[0071] Since the signal received by the first input end of the first bootstrap unit is the same as the signal received by the second input end of the second bootstrap unit, the first input end of the first bootstrap unit can be connected with the second input end of the second bootstrap unit, and together as an input end of the clock signal bootstrap unit. Since the signal received by the second input end of the first bootstrap unit is the same as the signal received by the first input end of the second bootstrap unit, the second input end of the first bootstrap unit can be connected with the first input end of the second bootstrap unit, and together as another input end of the clock signal bootstrap unit. The output end of the first bootstrap unit and the output end of the second bootstrap unit can be two output ends of the clock signal bootstrap circuit respectively.

[0072] The first clock signal CLK P may be a low-swing clock signal input from outside the clock signal bootstrap circuit, and the voltage value can be 0-V clk . V clk may be greater than or equal to the power supply voltage VDD, and the voltage value of the second clock signal CLK clkThe specific values of the clock signal are not limited. The clock signal self-boosting unit can further comprise a clock generator (not shown) for generating the first clock signal CLK P The second clock signal CLK N may be input from outside the clock signal self-boosting unit or generated by the clock signal self-boosting unit according to the first clock signal CLK P The disclosure embodiments are not limited to the source of the first clock signal CLK P and the second clock signal CLK N .

[0073] Since the first clock signal CLK P and the second clock signal CLK N are a pair of differential signals, the voltage value of the first clock signal CLK P is 0~V clk , so CLK P =0, CLK N =V clk , that is, when the first clock signal is at low level, the second clock signal is at high level. Similarly, CLK P =V clk , CLK N =0, that is, when the first clock signal is at high level, the second clock signal is at low level.

[0074] The relationship between the level of the third clock signal CLK BSTP and the first clock signal CLK P and the second clock signal CLK N is introduced below.

[0075] In one possible implementation, when the first clock signal CLK P is at low level, the second electrode m12 and the third electrode m13 of the first transistor are turned on, the second electrode m32 and the third electrode m33 of the third transistor are turned on, the second electrode m22 and the third electrode m23 of the second transistor are disconnected and the gate-source voltage is greater than or equal to 0, the power supply voltage VDD charges the first capacitor C1 through the third transistor, and the third clock signal CLK BSTP is at low level.

[0076] When the first clock signal CLK P is at high level, the second electrode m12 and the third electrode m13 of the first transistor are disconnected and the gate-source voltage is less than 0, the second electrode m32 and the third electrode m33 of the third transistor are disconnected, the second electrode m22 and the third electrode m23 of the second transistor are turned on, the first capacitor C1 is discharged, the third clock signal CLK BSTP is at high level and the level of the third clock signal CLK BSTP is greater than that of the first clock signal CLK PThe level;

[0077] First clock signal CLK P When the high level is equal to the power supply voltage, and the second and third terminals of the second transistor are disconnected, the gate-source voltage of the second transistor is equal to 0.

[0078] First clock signal CLK P When the high level is greater than the power supply voltage, the gate-source voltage of the second transistor is greater than 0 when the second and third terminals of the second transistor are disconnected.

[0079] See Figure 7 Because the first terminal C11 of the first capacitor receives the first clock signal CLK P Therefore, CLK P When = 0, the voltage at the first terminal C11 of the first capacitor is 0.

[0080] The first terminal m11 of the first transistor receives the second clock signal CLK. N The second terminal m12 of the first transistor receives the first clock signal CLK. P Therefore, CLK P When = 0, the voltage at the first terminal m11 of the first transistor is V. clk The voltage at the second terminal m12 is 0. The first transistor is an N-channel transistor, therefore its second terminal m12 and third terminal m13 are turned on. The third terminal m13 of the first transistor outputs the third clock signal CLK. BSTP Therefore, the third clock signal CLK BSTP The voltage value is also 0.

[0081] The first terminal m21 of the second transistor receives the second clock signal CLK. N Therefore, CLK P When = 0, the voltage at the first terminal m21 of the second transistor is V. clk The second transistor is a P-channel transistor, therefore the second terminal m22 and the third terminal m23 of the second transistor are disconnected.

[0082] The third transistor is a P-channel transistor and CLK BSTP =0, therefore the second terminal m32 and the third terminal m33 of the third transistor are turned on. At this time, the power supply voltage VDD charges the first capacitor C1 through the third transistor M3, so that the voltage at the second terminal c12 of the first capacitor C1 is VDD.

[0083] The second terminal C12 of the first capacitor C1 is connected to the second terminal m22 of the second transistor, therefore the voltage at the second terminal m22 of the second transistor is also VDD. Since VDD... clk The gate-source voltage of the second transistor is greater than or equal to the supply voltage VDD, therefore the gate-source voltage (VDD) is greater than or equal to the supply voltage VDD. clk-VDD) is greater than or equal to 0.

[0084] In this case, as long as V clk When the voltage is >VDD, the gate-source voltage of the second transistor will be greater than 0. In the case that the second transistor is a P-channel transistor, the leakage current of the second transistor will be greatly reduced.

[0085] In this way, when the first clock signal is high, the leakage current of the clock signal bootstrap circuit is reduced, thereby reducing the power consumption of the clock signal bootstrap circuit.

[0086] Similarly, CLK P =V clk At that time, the voltage at the first terminal C11 of the first capacitor is VDD. The first capacitor discharges, causing the voltage at the second terminal C12 of the first capacitor to reach VDD + V. clk .

[0087] CLK P =V clk CLK N =0, which is the first clock signal CLK P When it is high, the second clock signal CLK N It is a low level.

[0088] The first terminal m11 of the first transistor receives the second clock signal CLK. N The second terminal m12 of the first transistor receives the first clock signal CLK. P Therefore, CLK P =V clk At this time, the voltage at the first terminal m11 of the first transistor is 0, and the voltage at the second terminal m12 is V. clk The first transistor is an N-channel transistor, therefore the second terminal m12 and the third terminal m13 of the first transistor are disconnected.

[0089] The first terminal m21 of the second transistor receives the second clock signal CLK. N Therefore, CLK P =V clk At this time, the voltage at the first terminal m21 of the second transistor is 0. The second transistor is a P-channel transistor, therefore the second terminal m22 and the third terminal m23 of the second transistor are turned on.

[0090] The voltage across the second terminal C12 of the first capacitor is equal to VDD + V clk When the second and third terminals of the second transistor are conducting, and leakage current is not considered, the voltage between the third terminal m23 and the first terminal m31 of the second transistor is also equal to VDD + V. clk CLK BSTP =VDD+V clkThe third transistor is a P-channel transistor, so the second electrode m32 and the third electrode m33 of the third transistor are disconnected.

[0091] At this time, the voltage difference between the second electrode m12 and the third electrode m13 of the first transistor is VDD, so the first transistor has a leakage current. However, since the voltage of the first electrode m11 of the first transistor is equal to 0 and the voltage of the second electrode m12 is equal to V clk , the gate-source voltage of the first transistor is less than 0, which greatly reduces the leakage current of the first transistor in the case that the first transistor is an N-channel transistor.

[0092] The fourth clock signal CLK BSTN is introduced below. P N The relationship between the fourth clock signal CLK N and the first clock signal CLK BSTN and the second clock signal CLK N is introduced below.

[0093] In one possible implementation, when the second clock signal CLK N is at a low level, the second electrode m42 and the third electrode m43 of the fourth transistor are turned on, the second electrode m62 and the third electrode m63 of the sixth transistor are turned on, the second electrode m52 and the third electrode m53 of the fifth transistor are disconnected and the gate-source voltage is greater than or equal to 0, the power supply voltage charges the second capacitor C2 through the sixth transistor, and the fourth clock signal CLK BSTN is at a low level.

[0094] When the second clock signal CLK N is at a high level, the second electrode m42 and the third electrode m43 of the fourth transistor are disconnected and the gate-source voltage is less than 0, the second electrode m62 and the third electrode m63 of the sixth transistor are disconnected, the second electrode m52 and the third electrode m53 of the fifth transistor are turned on, the second capacitor is discharged, the fourth clock signal CLK BSTN is at a high level and the level of the fourth clock signal CLK BSTN is greater than the level of the second clock signal CLK N .

[0095] When the high level of the second clock signal CLK N is equal to the power supply voltage, the gate-source voltage of the fifth transistor is equal to 0 when the second electrode and the third electrode of the fifth transistor are disconnected.

[0096] When the high level of the second clock signal CLK N is greater than the power supply voltage, the gate-source voltage of the fifth transistor is less than 0 when the second electrode and the third electrode of the fifth transistor are disconnected.

[0097] Referring to Figure 7 , since the first end c21 of the second capacitor receives the second clock signal CLK N , and the first clock signal CLKP and the second clock signal CLK N is a pair of differential signals, so CLK N = 0, CLK P = V clk , the voltage of the first terminal c21 of the second capacitor is 0. The first pole m41 of the fourth transistor receives the first clock signal CLK P , and the second pole m42 of the fourth transistor receives the second clock signal CLK N , so CLK P = 0, CLK clk = V clk , the voltage of the first pole m41 of the fourth transistor is V BSTN , and the voltage of the second pole m42 is 0. The fourth transistor is an N-channel transistor, so the second pole m42 and the third pole m43 of the fourth transistor are turned on. The third pole m43 of the fourth transistor outputs the fourth clock signal CLK BSTN , so the voltage value of the fourth clock signal CLK BSTN is also 0.

[0098] The first pole m51 of the fifth transistor receives the first clock signal CLK P , so CLK P = V clk , the voltage of the first pole m51 of the fifth transistor is V clk . The fifth transistor is a P-channel transistor, so the second pole m52 and the third pole m53 of the fifth transistor are turned off.

[0099] The sixth transistor is a P-channel transistor and CLK BSTP = 0, so the second pole m62 and the third pole m63 of the sixth transistor are turned on. At this time, the power supply voltage VDD charges the second capacitor C2 through the sixth transistor, so that the voltage of the second terminal c22 of the second capacitor is VDD.

[0100] The second terminal c22 of the second capacitor is connected to the second pole m52 of the fifth transistor, so the voltage of the second pole m52 of the fifth transistor is also VDD. Since V clk is greater than or equal to the power supply voltage VDD, the gate-source voltage (V clk -VDD) of the fifth transistor is greater than or equal to 0.

[0101] In this case, as long as V clk > VDD, the gate-source voltage (V clk -VDD) of the fifth transistor is greater than 0, and in the case where the fifth transistor is a P-channel transistor, the leakage degree of the fifth transistor can be reduced.

[0102] Similarly, CLK PWhen VDD = 0, the voltage across the first terminal C21 of the second capacitor is VDD. The second capacitor discharges, causing the voltage across the second terminal C22 to reach VDD + VDD. clk .

[0103] CLK P =0 when CLK N =V clk The first terminal m41 of the fourth transistor receives the first clock signal CLK. P The second terminal m42 of the fourth transistor receives the second clock signal CLK. N Therefore, CLK P When the voltage is 0, the voltage at the first terminal m41 of the fourth transistor is 0, and the voltage at the second terminal m42 is V. clk The fourth transistor is an N-channel transistor, therefore the second terminal m42 and the third terminal m43 of the fourth transistor are disconnected.

[0104] The first terminal of the fifth transistor, m51, receives the first clock signal CLK. P Therefore, CLK P When the voltage is 0, the voltage at the first terminal m51 of the fifth transistor is 0. The fifth transistor is a P-channel transistor, therefore the second terminal m52 and the third terminal m53 of the fifth transistor are turned on.

[0105] The voltage across the second terminal C22 of the second capacitor is equal to VDD + V clk When the second terminal m52 and the third terminal m53 of the fifth transistor are conducting, and leakage current is not considered, the voltage between the third terminal m53 of the fifth transistor and the first terminal m61 of the sixth transistor is also equal to VDD + V. clk CLK BSTN =VDD+V clk The sixth transistor is a P-channel transistor, therefore the second terminal m62 and the third terminal m63 of the sixth transistor are disconnected.

[0106] At this point, the voltage difference between the second terminal m42 and the third terminal m43 of the fourth transistor is VDD, therefore, the fourth transistor has leakage current. However, since the voltage at the first terminal of the fourth transistor is 0 and the voltage at the second terminal is VDD, the fourth transistor has leakage current. clk Therefore, the gate-source voltage of the fourth transistor is less than 0, which greatly reduces the leakage current of the fourth transistor when the fourth transistor is an N-channel transistor.

[0107] In this way, regardless of whether the first clock signal is high or low, the leakage current of at least one transistor in the clock signal bootstrap unit is reduced, thereby reducing the power consumption of the clock signal bootstrap unit.

[0108] Since the clock signal self-boosting unit can output differential clock signals, the differential clock signals can drive devices with higher linearity, thus supporting devices with higher linearity in the conversion module and improving the performance of the analog-to-digital conversion circuit.

[0109] Those skilled in the art should understand that the embodiments of the present disclosure do not limit the type of each transistor, nor the type of each pole of each transistor, as long as the leakage of at least one transistor in the clock signal self-boosting unit is reduced regardless of whether the first clock signal is at a high level or a low level.

[0110] Figure 8 A schematic diagram showing another structure of the clock signal self-boosting module according to an embodiment of the present disclosure is shown.

[0111] As shown in Figure 8 The clock signal self-boosting unit further includes an inverter, the input end of the inverter is connected to the second input end w12 of the first self-boosting subunit and the first input end w21 of the second self-boosting subunit, the output end of the inverter is connected to the first input end w11 of the first self-boosting subunit and the second input end w22 of the second self-boosting subunit, and the second clock signal is generated by the inverter.

[0112] At this time, the input end of the inverter, the second input end of the first self-boosting subunit, and the first input end of the second self-boosting subunit can be collectively used as the input end of the clock signal self-boosting unit, and the output end of the first self-boosting subunit and the output end of the second self-boosting subunit can be used as two output ends of the clock signal self-boosting unit, respectively.

[0113] For example, if the clock signal self-boosting unit receives a single-ended clock signal (such as the first clock signal), an inverter can be added to the circuit structure of the clock signal self-boosting unit as shown in Figure 7 That is, the input end of the inverter is connected to the first end c11 of the first capacitor, the second pole m12 of the first transistor, the first pole m41 of the fourth transistor, and the first pole m51 of the fifth transistor, and the output end of the inverter is connected to the first end c21 of the second capacitor, the second pole m42 of the fourth transistor, the first pole m11 of the first transistor, and the first pole m21 of the second transistor.

[0114] In this case, the first clock signal is simultaneously input to the second input end of the first self-boosting subunit, the first input end of the second self-boosting subunit, and the input end of the inverter, the inverter can directly reverse the first clock signal to obtain the second clock signal, and then input the second clock signal to the first input end of the first self-boosting subunit and the second input end of the second self-boosting subunit.

[0115] In this way, the adaptability of the clock signal bootstrap unit to different application scenarios is improved.

[0116] Figure 9a and Figure 9b A schematic diagram showing the structure of a conversion module according to an embodiment of the disclosure is shown.

[0117] As Figure 9a and Figure 9b In one possible implementation, the conversion module includes a first chopping unit 10, a capacitive filter unit 20, a dead zone control unit 30, a voltage-current conversion unit 40, a second chopping unit 50, an integration unit 60, a quantization unit 70, an output unit 80,

[0118] The analog input signal includes a differential first input signal VINP and a second input signal VINN, and the feedback signal includes a differential first feedback signal VFP and a second feedback signal VFN,

[0119] The first end a1 of the first chopping unit receives the first input signal VINP, the second end a2 of the first chopping unit receives the second input signal VINN, the third end a3 of the first chopping unit is connected to the first end b1 of the capacitive filter unit, and the fourth end a4 of the first chopping unit is connected to the second end b2 of the capacitive filter unit;

[0120] The third end b3 of the capacitive filter unit is connected to the first end d1 of the dead zone control unit and the fourth end n4 of the feedback module, the fourth end b4 of the capacitive filter unit is connected to the second end d2 of the dead zone control unit and the third end n3 of the feedback module, the fourth end n4 of the feedback module outputs the first feedback signal VFP, and the third end n3 of the feedback module outputs the second feedback signal VFN;

[0121] The third end d3 of the dead zone control unit is connected to the first end e1 of the voltage-current conversion unit, and the fourth end d4 of the dead zone control unit is connected to the second end e2 of the voltage-current conversion unit;

[0122] The third end e3 of the voltage-current conversion unit is connected to the first end f1 of the second chopping unit, and the fourth end e4 of the voltage-current conversion unit is connected to the second end f2 of the second chopping unit;

[0123] The third end f3 of the second chopping unit is connected to the first end g1 of the integration unit, and the fourth end f4 of the second chopping unit is connected to the second end g2 of the integration unit;

[0124] The third terminal g3 of the integration unit is connected to the first terminal h1 of the quantization unit, the fourth terminal g4 of the integration unit is connected to the second terminal h2 of the quantization unit, the third terminal h3 of the quantization unit is connected to the first terminal j1 of the output unit and the first terminal n1 of the feedback unit, and the fourth terminal h4 of the quantization unit is connected to the second terminal j2 of the output unit and the second terminal n2 of the feedback unit.

[0125] The third terminal j3 of the output unit outputs the digital output signal DOUT.

[0126] For example, the conversion module may include a first chopper unit, a capacitor filter unit, a dead-time control unit, a voltage-to-current conversion unit, a second chopper unit, an integration unit, a quantization unit, and an output unit.

[0127] The first chopper unit can receive an external analog input signal. The analog input signal can be a differential signal, including a first input signal and a second input signal. In this case, the first chopper unit, the capacitor filter unit, the dead-time control unit, the voltage-to-current conversion unit, the second chopper unit, the integration unit, and the quantization unit each include two input terminals and two output terminals; the output unit may include two input terminals and one output terminal.

[0128] The first chopper unit receives a first input signal at its first end, a second input signal at its second end, outputs the signal VAP obtained by chopping the first input signal at its third end, and outputs the signal VAN obtained by chopping the second input signal at its fourth end.

[0129] like Figure 9b As shown, the first chopper unit may include switches S1-S4. The first terminal s11 of S1 is connected to the first terminal s31 of S3, serving as the first terminal of the first chopper unit. The second terminal s12 of S1 is connected to the first terminal s41 of S4, serving as the third terminal of the first chopper unit. The first terminal s21 of S2 is connected to the second terminal s42 of S4, serving as the second terminal of the first chopper unit. The second terminal s22 of S2 is connected to the second terminal s32 of S3, serving as the fourth terminal of the first chopper unit.

[0130] Those skilled in the art should understand that the first chopper unit can also be implemented using other structures, as long as it has chopping function and can chop the differential input signal to obtain the differential output signal. The embodiments of this disclosure do not limit the specific structure of the first chopper unit.

[0131] Signals VAP and VAN are output from the first chopper unit and then input to the first and second terminals of the capacitor filter unit, respectively. Figure 9bAs shown, the capacitor filter unit may include capacitor C3 and capacitor C4. One end of capacitor C3 serves as the first end of the capacitor filter unit, and the other end of capacitor C3 serves as the third end of the capacitor filter unit; one end of capacitor C4 serves as the second end of the capacitor filter unit, and the other end of capacitor C4 serves as the fourth end of the capacitor filter unit.

[0132] Capacitor C3 can be used to filter out interference components in signal VAP. Capacitor C4 can be used to filter out interference components in signal VAN. Since the third terminal of the capacitor filter unit is also connected to the fourth terminal of the feedback module, and the fourth terminal of the capacitor filter unit is also connected to the third terminal of the feedback module, the feedback signal output by the feedback module is a differential signal including a first feedback signal VFP and a second feedback signal VFN. The fourth and third terminals of the feedback module output the first feedback signal VFP and the second feedback signal VFN, respectively. Therefore, after the interference components in signal VAP are filtered out, the amplitude is adjusted by the first feedback signal VFP to obtain signal VBP, which is then output to the first terminal of the dead-zone control unit. After the interference components in signal VAN are filtered out, the amplitude is adjusted by the second feedback signal VFN to obtain signal VBN, which is then output to the second terminal of the dead-zone control unit.

[0133] like Figure 9b As shown, the dead-time control unit may include switches S5 and S6. One end of switch S5 serves as the first terminal of the dead-time control unit, and the other end serves as the third terminal. One end of switch S6 serves as the second terminal of the dead-time control unit, and the other end serves as the fourth terminal. The third terminal of the dead-time control unit is connected to the first terminal of the voltage-to-current conversion unit, and the fourth terminal is connected to the second terminal. After signals VBP and VBN enter the voltage-to-current conversion unit, they enter the voltage-to-current conversion stage described above. Therefore, switches S5 and S6 can be controlled to open for a short period each cycle (the cycle frequency can be the sampling frequency of the analog-to-digital conversion circuit) to prevent signals VBP and VBN from entering the voltage-to-current conversion unit, thereby optimizing the quality of the signal output by the voltage-to-current conversion unit (e.g., removing glitches from the signal output by the voltage-to-current conversion unit). The time period for controlling switches S5 and S6 to open can be set according to the application scenario requirements; this embodiment does not impose any limitations on this.

[0134] The voltage-to-current conversion unit can convert the input signal VBP into a current signal IEP, and the input signal VBN into a current signal IEN. The function of the voltage-to-current conversion unit can be implemented using existing transconductance amplifiers, which will not be elaborated upon here.

[0135] The current signal IEP can be input to a first end of the second chopper unit, and the current signal IEN can be input to a second end of the second chopper unit. The second chopper unit can have the same structure and function as the first chopper unit, and thus details are not repeated here. A third end of the second chopper unit outputs a signal IFP obtained by chopping the signal IEP, and a fourth end of the second chopper unit outputs a signal IFN obtained by chopping the signal IEN.

[0136] As shown in Figure 9b , the integration unit can include a first integrator and a second integrator. The signal IFP can be input to one end of the first integrator (a first end of the integration unit), and the first integrator integrates the signal IFP and outputs a signal IGP through the other end (a third end of the integration unit). The signal IFN can be input to one end of the second integrator (a second end of the integration unit), and the second integrator integrates the signal IFN and outputs a signal IGN through the other end (a fourth end of the integration unit). The first integrator and the second integrator can be implemented based on prior art, and thus details of the structure of the first integrator and the second integrator are not repeated here.

[0137] The signal IGP can be input to a first end of the quantization unit, and the signal IGN can be input to a second end of the quantization unit. The quantization unit can quantize the signal IGP into a value A and quantize the signal IGN into a value B, and the value A can be output through a third end of the quantization unit and the value B can be output through a fourth end of the quantization unit. The quantization unit can be implemented based on prior art, and thus details of the structure of the quantization unit are not repeated here.

[0138] The value A can be input to a first end of the output unit, and the value B can be input to a second end of the output unit. As shown in Figure 9b , the output unit can perform a subtraction operation on the value A and the value B, and output the operation result as a digital output signal DOUT. The digital output signal DOUT can be output by a third end of the output unit. The output unit can be implemented based on prior art, and thus details of the specific structure of the output unit are not repeated here.

[0139] As shown in Figure 9a , the value A and the value B are also input to the feedback module. The feedback module can output a first feedback signal VFP and a second feedback signal VFN according to the value A and the value B. Details of the structure of the feedback module and examples of the feedback module implementing the above function can be found in Figure 10 .

[0140] In a possible implementation, the quantization unit is a time-domain quantization unit, the integration unit is a time-domain integration unit, and the quantization unit and the integration unit are implemented by using digital circuits.

[0141] For example, since the time-domain integration unit and the time-domain quantization unit have the characteristic of processing signals in the time domain rather than in the analog domain, the time-domain integration unit and the time-domain quantization unit can be implemented by digital circuits. Digital circuits can work at low voltages (especially digital circuits in advanced processes, the more advanced the process, the lower the voltage at which it can work), so the time-domain integration unit and the time-domain quantization unit can maintain high performance at a power supply voltage lower than the first threshold. This further increases the proportion of digital circuits in the analog-to-digital converter circuit, further reducing the power consumption of the analog-to-digital conversion circuit.

[0142] In a possible implementation, the clock signal is used to drive the first chopping unit, the dead-time control unit, and the second chopping unit.

[0143] The clock signal output by the clock signal bootstrap module mentioned above can be used to drive at least one unit in the conversion module. In one example, the first chopping unit, the dead-time control unit, and the second chopping unit can be driven.

[0144] In a possible implementation, the clock signal used to drive the dead-time control unit has an amplitude greater than or equal to the second threshold, and the clock signal used to drive the first chopping unit and the second chopping unit has an amplitude greater than or equal to the third threshold, and the second threshold is greater than the third threshold.

[0145] For example, the higher the amplitude of the clock signal, the better the effect of driving the first chopping unit, the dead-time control unit, and the second chopping unit, but the power consumption is also higher. Therefore, the clock signal used to drive the first chopping unit, the dead-time control unit, and the second chopping unit can be determined according to the requirements of the first chopping unit, the dead-time control unit, and the second chopping unit for the amplitude of the clock signal.

[0146] In this case, the first pair of clock signals output by the clock signal bootstrap module can be used to drive the first chopping unit and the second chopping unit, and the third pair of clock signals can be used to drive the dead-time control unit.

[0147] If the amplitude of the pair of clock signals with the lowest amplitude output by the clock signal bootstrap module has already exceeded the second threshold, the pair of clock signals with the lowest amplitude can be used to drive the first chopping unit, the dead-time control unit, and the second chopping unit.

[0148] That is, the swing of the clock signal used by the drive dead zone control unit is greater than or equal to a second threshold value, the swing of the clock signal used by the first and second chopping units is greater than or equal to a third threshold value, and the second threshold value is greater than the third threshold value.

[0149] In this way, the quality of analog-to-digital conversion can be ensured while reducing the power consumption of the analog-to-digital conversion circuit.

[0150] Figure 10 A schematic diagram showing the structure of the feedback module according to an embodiment of the present disclosure is shown.

[0151] As shown in Figure 10 In one possible implementation, the feedback module includes a logic control unit, a third chopping unit, a capacitive digital-to-analog conversion unit,

[0152] The first end of the logic control unit is the first end of the feedback module, the second end of the logic control unit is the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopping unit, and the fourth end of the logic control unit is connected to the second end of the third chopping unit.

[0153] The third end of the third chopping unit is connected to the first end of the capacitive digital-to-analog conversion unit, and the fourth end of the third chopping unit is connected to the second end of the capacitive digital-to-analog conversion unit.

[0154] The third end of the capacitive digital-to-analog conversion unit is the third end of the feedback module, and the fourth end of the capacitive digital-to-analog conversion unit is the fourth end of the feedback module.

[0155] For example, the feedback module as a whole can be implemented using a digital circuit and can include a logic control unit 11, a third chopping unit 21, and a capacitive digital-to-analog conversion unit 31.

[0156] The first end n1 of the logic control unit receives a value A as the first end of the feedback module, and the second end n2 of the logic control unit receives a value B as the second end of the feedback module. According to the value A and the value B, the logic control unit can obtain a digital control signal, which can be a differential signal including a signal ctrl1 and a signal ctrl2. The digital control signal is used to control the degree of adjustment of the feedback module to the analog input signal. The logic control unit can be implemented based on existing technology, and therefore the specific implementation of the logic control unit will not be described here.

[0157] The third end p3 of the logic control unit can be connected to the first end q1 of the third chopper unit, and the fourth end p4 of the logic control unit can be connected to the second end q2 of the third chopper unit, so that the signal ctrl1 and the signal ctrl2 are input to the third chopper unit for chopping. The signal ctrl1 is chopped to obtain the signal ctrl11, and the signal ctrl2 is chopped to obtain the signal ctrl22. The third chopper unit can be implemented based on the prior art, and details of the implementation of the third chopper unit are not described herein.

[0158] The third end q3 of the third chopper unit can input the signal ctrl11 to the first end p1 of the capacitive digital-to-analog conversion unit, and the fourth end q4 of the third chopper unit can input the signal ctrl22 to the second end p2 of the capacitive digital-to-analog conversion unit. The capacitive digital-to-analog conversion unit can perform digital-to-analog conversion on the signal ctrl11 to obtain the signal VFN, and perform digital-to-analog conversion on the signal ctrl22 to obtain the signal VFP. The signals VFP and VFN can be analog signals. In this case, the signal VFP can be operated with the signal VAP, and the signal VFN can be operated with the signal VAN. The third end n3 of the capacitive digital-to-analog conversion unit can output the signal VFN, and the fourth end n4 can output the signal VFP. The capacitive digital-to-analog conversion unit can be implemented based on the prior art, and details of the implementation of the capacitive digital-to-analog conversion unit are not described herein.

[0159] The chip provided in the embodiments of the present disclosure includes the analog-to-digital conversion circuit described above. Figure 4 .

[0160] The chip provided in the embodiments of the present disclosure includes the analog-to-digital conversion circuit described above.

[0161] The flowcharts and block diagrams in the drawings show the possible implementation architecture, functions and operations of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment or a part of instructions, which includes one or more executable instructions for implementing the specified logic function. In some alternative implementations, the functions noted in the blocks can occur in different order from that shown in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and sometimes in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0162] Having described above several embodiments of the disclosure, any modifications and variations that fall within the scope of the described embodiments are also contemplated. It is also contemplated that the application covered by the claims extends to any alternative combination of claim elements not specifically disclosed. The use of the terms "preferably," "preferably," "preferred," and "has been preferred" in the description above indicates that the described feature is but one replacement for the term "the technology."

Claims

1. An analog-to-digital converter circuit based on a clock signal bootstrap module, characterized in that, The circuit includes a clock signal bootstrap module, a conversion module, and a feedback module. The power supply voltages of the clock signal bootstrap module, the conversion module, and the feedback module are equal and less than or equal to a first threshold. The clock signal bootstrap module is used to generate at least one pair of clock signals with an amplitude greater than the first threshold, and output the clock signals to the conversion module to drive at least one unit in the conversion module; The conversion module is used to obtain a digital output signal based on the analog input signal and the feedback signal; The feedback module is used to generate the feedback signal based on the latest digital output signal and output it to the conversion module; The conversion module includes a first chopper unit, a capacitor filter unit, a dead-time control unit, a voltage-to-current conversion unit, a second chopper unit, an integration unit, a quantization unit, and an output unit. The analog input signal includes a differential first input signal and a differential second input signal, and the feedback signal includes a differential first feedback signal and a differential second feedback signal. The first terminal of the first chopper unit receives the first input signal, the second terminal of the first chopper unit receives the second input signal, the third terminal of the first chopper unit is connected to the first terminal of the capacitor filter unit, and the fourth terminal of the first chopper unit is connected to the second terminal of the capacitor filter unit. The third terminal of the capacitor filter unit is connected to the first terminal of the dead zone control unit and the fourth terminal of the feedback module. The fourth terminal of the capacitor filter unit is connected to the second terminal of the dead zone control unit and the third terminal of the feedback module. The fourth terminal of the feedback module outputs the first feedback signal, and the third terminal of the feedback module outputs the second feedback signal. The third terminal of the dead zone control unit is connected to the first terminal of the voltage-to-current conversion unit, and the fourth terminal of the dead zone control unit is connected to the second terminal of the voltage-to-current conversion unit. The third terminal of the voltage-to-current conversion unit is connected to the first terminal of the second chopper unit, and the fourth terminal of the voltage-to-current conversion unit is connected to the second terminal of the second chopper unit. The third end of the second chopper unit is connected to the first end of the integrator unit, and the fourth end of the second chopper unit is connected to the second end of the integrator unit. The third end of the integration unit is connected to the first end of the quantization unit, the fourth end of the integration unit is connected to the second end of the quantization unit, the third end of the quantization unit is connected to the first end of the output unit and the first end of the feedback module, and the fourth end of the quantization unit is connected to the second end of the output unit and the second end of the feedback module. The digital output signal is output from the third terminal of the output unit; The clock signal is used to drive the first chopper unit, the dead-time control unit, and the second chopper unit.

2. The circuit according to claim 1, characterized in that, The quantization unit is a time-domain quantization unit, and the integration unit is a time-domain integration unit. Both the quantization unit and the integration unit are implemented using digital circuits.

3. The circuit according to claim 1, characterized in that, The clock signal bootstrap module includes at least one cascaded clock signal bootstrap unit. Each clock signal bootstrap unit outputs a pair of clock signals. The clock signal output by the preceding clock signal bootstrap unit serves as the clock signal input to the following clock signal bootstrap unit. The swing of the clock signal output by the following clock signal bootstrap unit is higher than the swing of the clock signal output by the preceding clock signal bootstrap unit.

4. The circuit according to claim 3, characterized in that, The swing of the clock signal used to drive the dead zone control unit is greater than or equal to the second threshold, and the swing of the clock signal used to drive the first chopper unit and the second chopper unit is greater than or equal to the third threshold, wherein the second threshold is greater than the third threshold.

5. The circuit according to claim 3, characterized in that, The feedback module includes a logic control unit, a third chopper unit, and a capacitive digital-to-analog converter unit. The first end of the logic control unit serves as the first end of the feedback module, the second end of the logic control unit serves as the second end of the feedback module, the third end of the logic control unit is connected to the first end of the third chopper unit, and the fourth end of the logic control unit is connected to the second end of the third chopper unit. The third terminal of the third chopper unit is connected to the first terminal of the capacitive digital-to-analog converter unit, and the fourth terminal of the third chopper unit is connected to the second terminal of the capacitive digital-to-analog converter unit. The third terminal of the capacitive digital-to-analog converter unit serves as the third terminal of the feedback module, and the fourth terminal of the capacitive digital-to-analog converter unit serves as the fourth terminal of the feedback module.

6. The circuit according to claim 3, characterized in that, The clock signal bootstrap unit includes a first bootstrap subunit and a second bootstrap subunit. The first bootstrap subunit includes a first transistor, a second transistor, a third transistor, and a first capacitor. The second bootstrap subunit includes a fourth transistor, a fifth transistor, a sixth transistor, and a second capacitor. The first terminal of the first transistor is connected to the first terminal of the second transistor and serves as the first input terminal of the first bootstrap unit. The second terminal of the first transistor is connected to the first terminal of the first capacitor and serves as the second input terminal of the first bootstrap unit. The third terminal of the first transistor is connected to the third terminal of the second transistor and the first terminal of the third transistor and serves as the output terminal of the first bootstrap unit. The second terminal of the second transistor is connected to the second terminal of the third transistor and the second terminal of the first capacitor. The third terminal of the third transistor is connected to the power supply voltage. The first terminal of the fourth transistor is connected to the first terminal of the fifth transistor and serves as the first input terminal of the second bootstrap unit. The second terminal of the fourth transistor is connected to the first terminal of the second capacitor and serves as the second input terminal of the second bootstrap unit. The third terminal of the fourth transistor is connected to the third terminal of the fifth transistor and the first terminal of the sixth transistor and serves as the output terminal of the second bootstrap unit. The second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the second terminal of the second capacitor. The third terminal of the sixth transistor is connected to the power supply voltage. The first input terminal of the second bootstrap subunit is connected to the second input terminal of the first bootstrap subunit to receive a first clock signal. The second input terminal of the second bootstrap subunit is connected to the first input terminal of the first bootstrap subunit to receive a second clock signal. The output terminal of the first bootstrap subunit outputs a third clock signal. The output terminal of the second bootstrap subunit outputs a fourth clock signal. The first clock signal and the second clock signal are a pair of differential signals and serve as the clock signals input to the clock signal bootstrap unit. The third clock signal and the fourth clock signal are a pair of differential signals and serve as the clock signals output by the clock signal bootstrap unit.

7. A chip, characterized in that, The analog-to-digital converter circuit includes any one of claims 1-6.

8. An electronic device, characterized in that, Includes the chip described in claim 7.

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