Offset mismatch calibration method and storage medium for dual-comparator SAR ADC

Abstract

This invention discloses an offset mismatch calibration method and storage medium for a dual-comparator SAR ADC, comprising: step S1: starting ADC calibration; step S2: statistically analyzing the last comparison result n times; step S3: calculating the expected values ​​P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively; step S4: calculating whether the interpolation is within a set range; if yes, the calibration is complete; if no, calculating the error function; adjusting the comparator offset according to the set step size, and returning to step S2. The storage medium is used to store a computer program for executing the above method. This invention has the advantages of simple principle, easy operation, wide applicability, good calibration effect, and high accuracy.

Description

Technical Field

[0001] This invention relates primarily to the field of analog-to-digital converter (ADC) technology, specifically to an offset mismatch calibration method and storage medium for a dual-comparator structure SARADC. Background Technology

[0002] Analog-to-digital converters (ADCs), as key interface modules in mixed-signal systems, are used to quantize analog signals and convert them into digital signals for storage and computation. In high-speed serial interfaces (Serializer / Deserializer, SerDes) based on digital signal processing, high-speed ADCs play a crucial role.

[0003] High-speed ADCs in PAM4 SerDes typically employ a time-interleaved (TI) architecture. Among current mainstream ADC architectures, successive approximation (SAR) ADCs, characterized by multi-digital architecture, no operational amplifiers, low power consumption, and small area, are increasingly favored, especially as manufacturing processes move towards deeper submicron levels, further highlighting the advantages of SAR ADCs. Therefore, sub-ADCs within TI-type ADCs primarily utilize SAR structures, offering advantages such as small area and low power consumption.

[0004] As is well known, increasing the speed of the sub-channel ADC can effectively improve the overall speed of the time-interleaved ADC while reducing the number of channels, which in turn helps to reduce mismatch effects. Furthermore, this also helps to reduce the complexity, power consumption, and area of ​​the calibration circuit. Since PAM4 SerDes does not require high ADC resolution, typically only 7-8 bits, the settling time of the capacitor array does not limit the speed of the SAR ADC; rather, the comparator's comparison and reset times become the main factors limiting the speed of the SAR ADC.

[0005] A dual-comparator SAR ADC can effectively reduce the impact of reset time on speed. See also Figure 1 Dual-comparator SAR ADCs use two comparators that operate alternately; while one comparator is performing a comparison, the other is reset. This avoids the reset time of the comparators affecting the ADC speed, thus improving the conversion rate of the SAR ADC. TI-ADCs typically employ a dual-comparator structure for their sub-channel SAR ADCs. Furthermore, TI-ADCs have dedicated offset calibration circuitry to calibrate the absolute offset of each sub-channel SAR ADC, so the absolute offset of the SAR ADC has little impact on the TI-ADC. However, the problem with dual-comparator SAR ADCs is that they are susceptible to the effects of mismatch between the two comparators, which can severely degrade the ADC's performance.

[0006] Currently, the calibration methods for dual-comparator SAR ADCs mainly include the following:

[0007] 1) Reference comparator-based calibration method: Add an extra reference comparator to the circuit. During the conversion, the reference comparator is simultaneously triggered and compared with another comparator. The results of the comparisons of the other comparators are compared with the results of the reference comparator to obtain the calibration direction of the mismatch. Finally, the mismatch of each comparator is made consistent with the mismatch of the reference comparator, thus eliminating the mismatch between comparators.

[0008] 2) Low-power comparator calibration method based on charge sharing: After the normal conversion of the SAR ADC is completed, an additional comparison clock cycle is added. Before the comparison starts, the input of the comparator is shorted. Then the comparison is performed, the offset of the comparator is measured, and the magnitude of the calibration voltage is adjusted according to the comparison result.

[0009] However, the above two methods still have the following drawbacks:

[0010] 1. The calibration method based on the reference comparator requires an additional comparator, which has a large hardware overhead and requires a more complex clock.

[0011] 2. The low-power comparator calibration method based on charge sharing requires an additional comparator clock phase for calibration. This additional clock phase will increase the conversion time and slow down the ADC's operating speed.

[0012] In SAR ADCs, there is an imbalance or mismatch between the two comparators, which can severely degrade the ADC's performance, such as... Figure 2 As shown. Summary of the Invention

[0013] The technical problem to be solved by this invention is: in view of the technical problems existing in the prior art, this invention provides a method and storage medium for offset mismatch calibration of dual comparator structure SAR ADC that is simple in principle, easy to operate, widely applicable, has good calibration effect and high accuracy.

[0014] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0015] An offset mismatch calibration method for a dual-comparator SAR ADC, comprising:

[0016] Step S1: ADC calibration begins;

[0017] Step S2: Calculate the results of the last comparison in n iterations;

[0018] Step S3: Calculate the expected values ​​P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively;

[0019] Step S4: Calculate whether the interpolation is within the set range; if yes, the calibration is complete; if no, calculate the error function; adjust the comparator offset according to the set step size, and return to step S2.

[0020] As a further improvement of the present invention: the starting order of comparator 1 and comparator 2 is controlled by using a random signal, so that the starting probability of comparator 1 and comparator 2 is the same in one conversion. Then, after a period of time, the expected value of the comparison result of comparator 1 and the expected value of the comparison result of comparator 2 are statistically analyzed, and the error function is calculated. :

[0021]

[0022] As a further improvement of the present invention: when comparator 1 starts the comparison first, and the input signal follows a uniform distribution, the probability that the result of the Nth comparison is 1. for:

[0023]

[0024] In the above formula, when N is even, The value is "0"; when N is odd, It is "1".

[0025] As a further improvement of the present invention: when comparator 2 starts the comparison first, the probability that the result of the Nth comparison is 1 for:

[0026]

[0027] In the above formula, when N is even, The value is "0"; when N is odd, It is "1".

[0028] As a further improvement to the present invention: the LMS iterative algorithm is used to make the mismatch between the two comparators approach 0.

[0029]

[0030] In the above formula, Vos1(n) represents the misalignment of comparator 1 during the nth statistical iteration, and μ is the iteration step size. Let be the error function for the nth statistical iteration.

[0031] As a further improvement of the present invention, calibration is achieved by utilizing the mathematical expectation of the last comparison result.

[0032] The present invention further provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for performing any of the above methods.

[0033] Compared with the prior art, the advantages of the present invention are as follows:

[0034] 1. This invention relates to an offset mismatch calibration method and storage medium for dual-comparator SAR ADCs. The method is simple in principle, easy to operate, widely applicable, and offers good calibration results and high accuracy. This invention provides a background calibration algorithm for offset mismatch in successive approximation (SAR) analog-to-digital converters (ADCs) with a dual-comparator structure. This invention primarily addresses the offset mismatch problem between comparators. By statistically analyzing the last comparison result under normal operating conditions of the SAR ADC, the least mean square (LMS) algorithm is used to minimize the offset mismatch error between comparators, thereby improving the performance of the SAR ADC. This design does not require additional clock phase or an additional reference comparator.

[0035] 2. The offset mismatch calibration method and storage medium for dual-comparator SAR ADCs of the present invention is a background calibration algorithm for comparator offset mismatch. It does not occupy an additional comparison clock phase, thus slowing down the SAR ADC, nor does it require a reference comparator, resulting in low hardware overhead. Under normal SAR ADC operation, the last comparison result of the comparator is detected, and the adjustment direction of the comparator offset can be obtained based on the statistical distribution of the comparison result.

[0036] 3. The offset mismatch calibration method and storage medium for dual-comparator SAR ADCs of this invention can avoid performance degradation caused by offset mismatch between the two comparators. The method of this invention detects the last comparison result during normal operation of the SAR ADC and derives the comparator offset adjustment direction based on the statistical distribution of the comparison result. The LMS algorithm is used to minimize offset mismatch. This algorithm does not introduce additional calibration cycles into the circuitry, therefore it does not affect the speed of the SAR ADC and is very suitable for high-speed applications. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a dual-comparator SAR ADC structure.

[0038] Figure 2 This is a schematic diagram illustrating the impact of mismatch and mispairing on the significant number of bits.

[0039] Figure 3 This is a schematic diagram of a SAR ADC with a 4-bit dual comparator structure in a specific application example of the present invention.

[0040] Figure 4 is a schematic diagram of the voltage change of the DAC base plate after the first comparison of comparator 1 in a specific embodiment of the present invention; where (a) is when the comparison result is 0 and the voltage of the DAC base plate flips; and (b) is when the result is 1 and the voltage of the DAC base plate flips.

[0041] Figure 5 is a schematic diagram of the voltage change of the DAC base plate after the first comparison of the comparator 2 in a specific embodiment of the present invention; where (a) is when the comparison result is 0 and the voltage of the DAC base plate flips; and (b) is when the result is 1 and the voltage of the DAC base plate flips.

[0042] Figure 6 is a schematic diagram of the voltage change of the DAC base plate when the differential voltage of the DAC top plate is different after the first comparison in a specific embodiment of the present invention; where (a) is when the comparison result is 0 and the DAC base plate voltage flips; and (b) is when the result is 1 and the DAC base plate voltage flips.

[0043] Figure 7 This is a flowchart illustrating the present invention in a specific embodiment.

[0044] Figure 8 This is a schematic diagram illustrating the offset voltage convergence under sinusoidal signal input in a specific embodiment of the present invention.

[0045] Figure 9 This is a schematic diagram illustrating the convergence of the effective number of bits when a sinusoidal signal is input in a specific embodiment of the present invention.

[0046] Figure 10 This is a schematic diagram illustrating the convergence speed and accuracy of the present invention under different inputs in a specific embodiment. Detailed Implementation

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] This invention provides an offset mismatch calibration method for a dual-comparator SAR ADC. Its core principle and idea is to obtain the offset information by using the comparison result of the last comparator, and then use the LMS algorithm to make the offset mismatch between the two comparators approach 0.

[0049] like Figure 7 As shown, the present invention provides an offset mismatch calibration method for a dual-comparator structure SAR ADC, comprising:

[0050] Step S1: ADC calibration begins;

[0051] Step S2: Calculate the results of the last comparison in n iterations;

[0052] Step S3: Calculate the expected values ​​P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2 respectively;

[0053] Step S4: Calculate whether the interpolation is within the set range; if so, the calibration is completed; if not, calculate the error function; adjust the comparator offset according to the set step size, and return to step S2.

[0054] In this example, taking a 4-bit dual-comparator SAR ADC as an example, as Figure 3 shown, the quantization range is from -Vref to Vref; the two comparators (Comparator 1 and Comparator 2) work alternately. Assume that the offset of Comparator 1 is Vos1, the offset of Comparator 2 is Vos2, and LSB = 2*Vref / 2^4. The input differential voltage Vinp - Vinn = u, that is, the differential voltage of the top plate of the capacitor array (DAC) after sampling is u.

[0055] When Comparator 1 starts to compare first, due to the offset voltage of Comparator 1 being Vos1, when u < Vos1, the comparison result is 0, and the voltage of the bottom plate of the DAC flips as shown in Figure 4(a); otherwise the result is 1, and the voltage of the bottom plate of the DAC flips as shown in Figure 4(b).

[0056] The differential voltages of the top plate of the DAC in these two cases are respectively:

[0057]

[0058] If the differential voltage of the top plate of the DAC after the first comparison is u , the second time it is Comparator 2 that makes the comparison, and the offset voltage of Comparator 1 is Vos2. When u , the result of the second comparison is 0, and the voltage of the bottom plate of the DAC flips as shown in Figure 5(a); otherwise the result is 1, and the voltage of the bottom plate of the DAC flips as shown in Figure 5(b).

[0059] Similarly, if the differential voltage of the top plate of the DAC after the first comparison is u , there will also be two cases where the result is 0 and the result is 1, and the voltage flips of the bottom plate of the DAC are shown in Figure 6(a) and Figure 6(b) respectively.

[0060] In the above four cases, the differential voltages of the top plate of the DAC are respectively:

[0061] <0000​​​​​​

[0064]

[0065] As can be seen from the above formula, after the third comparison, there are eight different differential voltages on the top plate of the DAC.

[0066] The fourth comparison is performed by comparator 2. If the input signal follows a uniform distribution between -Vref and Vref, the probability of the fourth comparison being 1 is... for;

[0067]

[0068] By analogy, for an N-bit (N≥2) SAR ADC, when comparator 1 starts comparing first and the input signal follows a uniform distribution, the probability that the result of the Nth comparison is 1 is... for:

[0069]

[0070] In the above formula, when N is even, The value is "0"; when N is odd, It is "1".

[0071] Similarly, when comparator 2 starts comparing first, the probability that the result of the Nth comparison is 1 is... for:

[0072]

[0073] It can be seen that when N is the same, but Vos1 and Vos2 are different, the probability that the last comparison result is 1 when comparator 1 starts comparing first is different from the probability when comparator 1 starts comparing first. Therefore, the misalignment calibration direction can be obtained based on the mathematical expectation of its statistical distribution.

[0074] As can be seen from the above, the specific implementation method of this invention is as follows: The starting order of comparator 1 and comparator 2 is controlled by using a random signal, ensuring that the starting probabilities of comparator 1 and comparator 2 are the same in a single conversion. Then, after a period of time, the expected values ​​of the last comparison results of comparator 1 and comparator 2 are statistically analyzed, and the error function is calculated. :

[0075]

[0076] The following LMS iterative algorithm can be used to reduce the mismatch between two comparators to near zero:

[0077]

[0078] In the above formula, Vos1(n) represents the misalignment of comparator 1 during the nth statistical iteration, and μ is the iteration step size. Let be the error function for the nth statistical iteration. Here, we use a method of simultaneously calibrating the offset of two comparators, which can accelerate the convergence speed. In practical circuits, this can be achieved in various ways, such as changing the load capacitance or using a switched capacitor circuit to adjust the offset voltage.

[0079] It is worth noting that although the input signal is a uniformly distributed random signal when deriving the probability formula, even a sinusoidal input signal will exhibit a similar distribution, and calibration can be achieved using the mathematical expectation of the last comparison result. This algorithm does not add a dedicated calibration cycle, does not reduce the speed of the ADC, and does not require an additional reference comparator, resulting in low hardware overhead. The calibration direction of the comparator misalignment can be obtained by statistically analyzing the result of the last comparator comparison.

[0080] In a specific application example, this invention constructs an 8-bit SAR ADC behavioral model to verify the calibration process, sets Vref=1V, and simulates the behavior of the calibration algorithm under different conditions.

[0081] Convergence speed: Set Vos1 = -5 mV, Vos2 = 3 mV, and input a sinusoidal signal with a fully differential peak-to-peak value of 0.8V;

[0082] Sample 256 sets of data, calculate the expected value of the last comparison result between comparator 1 and comparator 2; then calculate the difference and adjust according to the calculated result; next, resample 256 sets of data, calculate the difference of the new expected value, and adjust again according to the calculated result; repeat this process.

[0083] As a preferred embodiment, the calibration step size can be set to 0.2mV. This is because if the amount of data sampled each time is too large, the convergence speed will be slow; if it is too small, the randomness will be too strong, affecting the calibration accuracy. In addition, the size of the calibration step size will also affect the calibration accuracy and speed.

[0084] During the calibration process, the changes in the misalignment of the two comparators are as follows: Figure 8 As shown, convergence was achieved after 20 iterations and sampling 5000 data points. The change in the effective number of bits (ENOB) of the SAR ADC is as follows. Figure 9 As shown, after calibration, ENOB increased from 7.01 bits to 7.93 bits.

[0085] Influence of input signal: The calibration accuracy of the background calibration algorithm usually depends on the amplitude distribution of the input signal. The larger the amplitude of the input signal, the higher the calibration accuracy. If the amplitude of the input signal changes very little, the calibration accuracy will be affected.

[0086] like Figure 10 As shown, the effect of different input signals on calibration accuracy is illustrated, including DC signals, uniformly distributed random signals, and sinusoidal signals with frequencies of 0.1, 0.5, and 0.9 times the sampling frequency, respectively.

[0087] It can be seen that the calibration effect is worse when the input signal is a DC signal. However, when the input is a sinusoidal signal of different frequencies and a uniformly distributed random signal, the convergence speed and the final calibration effect are both better.

[0088] The present invention further provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for performing the above-described method.

[0089] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A method for offset mismatch calibration for a dual-comparator structure SAR ADC, characterized in that, Comprising: Step S1: ADC starts calibration; Step S2: statistics n last comparison results; Step S3: respectively calculate the mathematical expectation P1(1) and P2(1) of the comparison results of comparator 1 and comparator 2; Step S4: calculate whether the interpolation is within the set range; if yes, the calibration is completed; if no, calculate the error function; adjust the comparator offset according to the set step, return to step S2; By using a random signal to control the first start order of the comparator 1 and the comparator 2, the first start probability of the comparator 1 and the comparator 2 in one conversion is made the same, and then the mathematical expectation of the last comparator 1 comparison result and the mathematical expectation of the comparator 2 comparison result are counted with a time interval, to calculate the error function : ； The probability that the Nth comparison result is 1 when the comparator 1 first starts comparing and the input signal is subject to a uniform distribution is: where Vos1 is the offset voltage of comparator 1 and Vos2 is the offset voltage of comparator 2; in the above equation, when N is even, is "0"; when N is odd, is "1". The probability that the Nth comparison result is 1 when the comparator 2 starts comparing first is: In the above formula, when N is even, is "0"; when N is odd, is "1"; Adopt LMS iterative algorithm to make the offset mismatch between the two comparators approach to 0: In the above equation, Vos1(n) is the offset of comparator 1 at the n-th iteration, μ is the iteration step size, is the error function at the n-th iteration.

2. The method for calibration of mismatch of offset for dual comparator structure SAR ADC according to claim 1, wherein, Use the mathematical expectation of the last comparison result to realize calibration.

3. A storage medium, which can be read by a computer or a processor, characterized in that, The storage medium has a computer program stored therein for executing the method of any one of claims 1-2.

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