Calibration method for ti- adc sampling time offset mismatch of serdes and storage medium

Abstract

This invention discloses a calibration method and storage medium for TI-ADC sampling time offset mismatch in SerDes. The method includes: performing calculations on the current output value obtained by quantization of each sub-ADC and the previous time data recovered by SerDes decision; using a certain sub-ADC channel as a reference, obtaining the error function of the sampling time offset of the remaining sub-ADCs relative to the reference time; and adjusting the sampling time of the sub-ADCs using the LMS algorithm to minimize the error function, thereby completing the calibration of the sampling time offset mismatch. The storage medium stores a computer program used to execute the above method. This invention has the advantages of simple principle, easy operation, wide applicability, good calibration effect, and high accuracy.

Description

Technical Field

[0001] This invention mainly relates to the field of SerDes receiver design, specifically a calibration method and storage medium for TI-ADC sampling time offset mismatch in SerDes. Background Technology

[0002] Time-interleaved analog-to-digital converters (TI-ADCs) are widely used in ultra-high-speed SerDes. TI-ADCs employ multiple sub-ADCs operating alternately to improve the sampling rate. However, the sampling time mismatch between these sub-ADCs is a key factor limiting the performance of TI-ADCs.

[0003] like Figure 1 The diagram shown is a schematic of a high-speed SerDes receiver based on an ADC structure. PAM4 or NRZ signals are quantized by the ADC after passing through the channel and the front-end analog circuitry in the SerDes, completing the analog-to-digital signal conversion. The performance of the ADC is one of the main factors affecting the bit error rate of the SerDes.

[0004] High-speed ADCs used in SerDes typically employ a time-interleaved structure, such as... Figure 2 As shown in (a), mismatched input buffers, unequal input signal traces, mismatched sampling switches, and suboptimal clock generator circuitry in TI-ADC can all cause sampling time offsets in the sub-ADC, resulting in mismatch. Figure 2 (b) illustrates the impact of sampling time mismatch on output value error. Ideally, the sampling interval between adjacent sampling channels should be one sampling period Ts of the TI-ADC. Due to the sampling time mismatch, the adjacent sampling interval is not Ts, and this time deviation is converted into an amplitude deviation, which severely degrades the performance of the TI-ADC.

[0005] One industry practitioner has proposed a technical solution: the cross-correlation calibration algorithm (Time skew extraction of interleaved analog-to-digital converters. US 8830094 B1.). Figure 3 (a) illustrates the case where ADC2 in a two-channel TI-ADC exhibits a time offset error. If the time offset is positive, then y2(n-1) is more biased towards y1(n), and the cross-correlation coefficient between the two is greater than the cross-correlation coefficient where y2(n-1) is more biased towards y1(n-1). Therefore, the difference between the two cross-correlation coefficients can be used as the error function. When the error function approaches 0, it indicates that the sampling time offset of ADC2 has been calibrated to the ideal value. The specific implementation method is as follows... Figure 3 As shown in (b).

[0006] Therefore, existing multi-channel TI-ADCs using cross-correlation calibration algorithms require step-by-step calibration: first, the middle channel is calibrated using a reference channel, and then the remaining channels are calibrated using both the calibrated and reference channels. However, as the number of channels increases, the convergence speed decreases significantly, leading to a reduction in convergence accuracy. The calibration accuracy primarily depends on the accuracy of the first calibration step. In this first step, the middle channel is calibrated using the reference channel. Since the middle channel has the longest sampling time interval with the reference channel and exhibits the lowest correlation, the calibration effect deteriorates. Summary of the Invention

[0007] The technical problem to be solved by the present invention is: in view of the technical problems existing in the prior art, the present invention provides a calibration method and storage medium for TI-ADC sampling time offset mismatch of SerDes that is simple in principle, easy to operate, widely applicable, has good calibration effect and high accuracy.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] A calibration method for sampling time offset mismatch of TI-ADC for SerDes, comprising:

[0010] The current output value obtained by quantizing each sub-ADC is calculated with the previous frame data recovered by the SerDes decision;

[0011] Using a certain sub-ADC channel as a reference, the error function of the sampling time offset of the other sub-ADCs relative to the reference time is obtained;

[0012] The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0013] As a further improvement of the present invention: the sampling clock of the first channel sub-ADC is kMT S Where k represents the k-th sample, T S This indicates the sampling period of the TI-ADC; the sampling clock of the second channel sub-ADC is kMT. S +T S Similarly, the sampling clock for the m-th channel is kMT. S +(m-1)T S Considering the sampling time offset error, the output signal of the first channel of the TI-ADC is expressed by the following formula:

[0014]

[0015] in, This represents the k-th sample value of the first channel of the TI-ADC. Indicates the input code element. This indicates the sampling clock offset of the first channel.

[0016] As a further improvement of the present invention: when only considering the data of the current frame and the previous frame, where the current frame is the k-th sample value and the previous frame is the (k-1)-th sample value, then:

[0017]

[0018]

[0019] In the above formula, the last term on the right side represents the inter-symbol interference (ISI) caused by the remaining data at the current sampling time.

[0020] As a further improvement to the present invention: [The following is a description of the invention] Finding the mean, we get:

[0021]

[0022] As the m-th channel, Represented as:

[0023]

[0024] Since is a constant, we get:

[0025]

[0026]

[0027] in, express hour The slope;

[0028] The above equation is fed as an error function to the LMS module, making... The value approaches 0, thus calibrating the sampling clock offset.

[0029] As a further improvement of the present invention: the TI-ADC includes an input data prediction module, an LMS module, and a delay adjustment module.

[0030] As a further improvement of the present invention: the input symbols are provided by the input data prediction module.

[0031] As a further improvement of the present invention: the calibration reference value is determined by the output value of the first channel. Compared with the previous prediction data The product is represented as; where Depend on Similarly, the product of the output of each calibration channel and the predicted data of the previous step is obtained. Then, the sampling clock offset error value of each channel is obtained by subtracting the product value to be calibrated from the reference product value.

[0032] As a further improvement of the present invention: the error value is sent to the LMS module, and the output of the LMS will generate corresponding control codes to adjust the delay of each channel so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

[0033] The present invention further provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for performing any of the above methods.

[0034] Compared with the prior art, the advantages of the present invention are as follows:

[0035] 1. The present invention relates to a calibration method and storage medium for TI-ADC sampling time offset mismatch in SerDes. This method is simple in principle, easy to operate, widely applicable, and provides good calibration results and high accuracy. The calibration method performs correlation calculations between the current output value obtained by quantization of each sub-ADC and the previous frame data recovered by SerDes decision. This correlation value contains the sampling time offset information of each sub-ADC. Using a certain sub-ADC channel as a reference, the error function of the sampling time offset of the other sub-ADCs relative to the reference time can be obtained. Finally, the LMS algorithm is used to adjust the sampling time of the sub-ADCs to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0036] 2. The calibration method and storage medium for sampling time offset mismatch of TI-ADC for SerDes of the present invention utilize the cross-correlation coefficient between the output data of the calibration channel and the input symbol of the previous cycle. Since these two data are only separated by one sampling cycle, their correlation is very high, thereby achieving better calibration results. On the other hand, this calibration algorithm is independent of the number of channels and does not require calibrating one channel first and then calibrating the remaining channels. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a SerDes receiver based on an ADC structure.

[0038] Figure 2 (a) is a schematic diagram of the M-channel TI-ADC structure; Figure 2 (b) is a schematic diagram showing the error in the sampling output caused by the sampling time offset mismatch of TI-ADC.

[0039] Figure 3 (a) is the time offset information obtained by using the cross-correlation algorithm of the two-channel TI-ADC; Figure 3(b) Sampling time diagram of two-channel TI-ADC.

[0040] Figure 4 This is a schematic diagram of the M-channel TI-ADC and its input front-end circuit in a specific implementation of the present invention.

[0041] Figure 5 This is a schematic diagram illustrating the impact of the previous symbol on the current sampled data in a specific implementation of the present invention.

[0042] Figure 6 This is a schematic diagram illustrating the implementation principle of the method in a specific application example of the present invention.

[0043] Figure 7 This is a schematic diagram of a 4-channel TI-ADC used in a specific application example of the present invention.

[0044] Figure 8 This is a schematic diagram of the sampling clock offset calibration circuit implemented in a specific application example of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] like Figure 6 As shown, this invention provides a calibration method for sampling time offset mismatch of a TI-ADC using SerDes. It is a sampling time offset mismatch calibration method based on the SerDes decision output, and includes:

[0047] The current output value obtained by quantizing each sub-ADC is correlated with the previous frame data recovered by the SerDes decision;

[0048] Using a certain sub-ADC channel as a reference, the error function of the sampling time offset of the other sub-ADCs relative to the reference time is obtained;

[0049] The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch.

[0050] like Figure 5 As shown, by adopting the above scheme, this invention utilizes the cross-correlation coefficient between the output data of the calibration channel and the input symbol of the previous cycle. Since these two data are only separated by one sampling period, their correlation is very high, thus achieving better calibration results. On the other hand, this calibration algorithm is independent of the number of channels and does not require calibrating one channel first and then calibrating the remaining channels.

[0051] like Figure 4The diagram shows the input front-end circuit of an M-channel TI-ADC. An ideal PAM4 or NRZ signal is fed to the M-channel TI-ADC after passing through a cascaded system consisting of a channel and a CTLE. The sampling clock of the first channel sub-ADC is kMT. S (where k represents the k-th sampling, T) S (This indicates the sampling period of the TI-ADC), and the sampling clock of the second channel sub-ADC is kMT. S +T S Similarly, the sampling clock for the m-th channel is kMT. S +(m-1)T S If sampling time offset error is taken into account, the output signal of the first channel of the TI-ADC can be expressed by the following formula:

[0052] (1)

[0053] in, This represents the k-th sample value of the first channel of the TI-ADC. Indicates the input code element. This represents the sampling clock offset of the first channel. If we only consider the data from the current frame (the k-th sample value) and the previous frame (the (k-1)-th sample value), the above formula can be further rewritten as:

[0054]

[0055] (2)

[0056] In the above equation, the last term on the right-hand side represents the inter-symbol interference (ISI) caused by the remaining data at the current sampling time. If we calculate... and From the cross-correlation, we can obtain:

[0057]

[0058] (3)

[0059] Since the input PAM4 or NRZ signal is encoded into a PRBS signal using a corresponding encoding method, this means that the symbols are independent of each other, resulting in the following formula:

[0060] (4)

[0061] (5)

[0062] The above formula shows that two different code symbols are independent of each other, and their correlation is 0. Based on the above conclusion, we can then... To find the mean, we can obtain:

[0063] (6)

[0064] It can be seen from the above formula that, Only depends on .and This indicates the impact of the previous symbol on the current sampled data. The size depends on the input symbol pulse width, channel attenuation, CTLE equalization size, and the clock offset of the current sample. Therefore This includes sampling clock offset information. For each sub-channel of the TI-ADC, the input symbol pulse width, channel attenuation, and CTLE equalization magnitude are the same; the only difference is the current sampling clock offset. Therefore, it is possible to... As a reference, calibrate the sampling clock offset of other channels.

[0065] Taking the m-th channel as an example, according to formula (6). It can be represented as:

[0066] (7)

[0067] because Since it is a constant, subtracting (6) from formula (7) yields:

[0068]

[0069] (8)

[0070] in, express hour The slope. Submitting the above equation as an error function to the LMS module will ultimately enable... Approaching 0, which means Therefore, it is possible to calibrate the sampling clock offset.

[0071] As can be seen from the above, the method of the present invention adds an input data prediction module, an LMS module, and a delay adjustment module to the original TI-ADC.

[0072] The input symbols in formula (8) are provided by the input data prediction module.

[0073] The reference value calibrated in this figure is the output value of the first channel. Compared with the previous prediction data The product is represented as . Where . Depend on Similarly, the product of the output of each calibration channel and the predicted data of the previous step can be obtained. Then, the sampling clock offset error value of each channel is obtained by subtracting the product value to be calibrated from the reference product value.

[0074] Finally, the error value is sent to the LMS module. The LMS output will generate corresponding control codes to adjust the delay of each channel, so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

[0075] In the design of the SerDes receiver circuit, the input front-end circuit of the TI-ADC consists of CTLE and VGA. The CTLE circuit performs equalization on the input signal, and the VGA amplifies the swing of the input signal to within the effective input range of the TI-ADC. The subsequent circuits of the TI-ADC are FFE and DFE. The DFE performs data equalization and also functions to recover the input symbols. That is, the DFE can be used as an input data prediction module. The FFE performs equalization on the output of the TI-ADC. The equalization of the data by the FFE can improve the accuracy of the DFE's prediction of the input data. Because the method of this invention uses the output of the DFE, the method of this invention is called a clock offset calibration algorithm based on decision output. The above analysis shows that the clock offset calibration algorithm based on decision output can effectively reuse the existing circuit modules in the SerDes circuit and achieve sampling clock offset calibration without adding extra circuit overhead.

[0076] In specific applications, such as Figure 7 As shown, the working process of TI-ADC will be explained in detail using a SerDes receiver based on a 4-channel TI-ADC as an example.

[0077] The output of the 4-channel TI-ADC is first calibrated for offset and gain error, and then sent to the FFE and DFE modules. After equalization decision, the input symbols are recovered.

[0078] Then, the recovered input symbols and the output of the TI-ADC are sent to the clock data recovery module and the sampling clock calibration module, respectively. The clock data recovery module can recover the sampling clock from the input data and ensure that the sampling point of the sampling clock is near the middle of the input symbol eye diagram. However, because the sampling clock of each sub-channel of the TI-ADC has a clock offset, the sampling clock of each channel is offset from the ideal sampling point, which reduces the bit error rate of the SerDes receiver. The sampling clock calibration module is used to solve this problem.

[0079] The clock Fs recovered by the clock data recovery module is sent to the sampling clock calibration circuit. The specific implementation method of the sampling clock offset calibration circuit is as follows: Figure 8As shown, Fs outputs a 4-phase sampling clock after passing through the sampling clock generation circuit, which is then sent to four digital to time converters (DTCs). The DTCs can adjust the input clock delay based on the input control code value, and can be considered as numerically controlled delay devices. The core of the clock offset calibration algorithm is to obtain the DTC control code value through an adaptive algorithm, ensuring that its output sampling clock meets the delay requirements. Its core principle is to calculate the correlation between the output of each sub-channel of the TI-ADC and the predicted input symbol of the previous cycle; and to use the correlation of the first channel as a reference value, causing the correlation values ​​of other channels to converge to this reference value. Because the output value of the TI-ADC will experience data delay after passing through the FFE and DFE, to compensate for this data delay, the output of the TI-ADC will be delayed by a corresponding period after entering the clock offset calibration module, aligning it with the output of the DFE.

[0080] According to formula (8), the clock offset error function can be obtained, and the control code value of DTC can be obtained by using the following LMS iterative algorithm:

[0081]

[0082] (9)

[0083] In the above formula The control code value for the m-th channel DTC. The iteration step size, Let be the error function of the m-th channel.

[0084] The present invention further provides a storage medium that can be read by a computer or processor, wherein the storage medium stores a computer program for performing the above-described method.

[0085] Those skilled in the art will understand that the above embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0086] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A calibration method for sampling time offset mismatch of TI-ADC for SerDes, characterized in that, include: The current output value obtained by quantizing each sub-ADC is calculated with the previous frame data recovered by the SerDes decision; Using a certain sub-ADC channel as a reference, the error function of the sampling time offset of the other sub-ADCs relative to the reference time is obtained; The LMS algorithm is used to adjust the sampling time of the sub-ADC to minimize the error function, thereby completing the calibration of the sampling time offset mismatch; The sampling clock of the first channel sub-ADC is kMT. S Where k represents the k-th sample, T S This indicates the sampling period of the TI-ADC; the sampling clock of the second channel sub-ADC is kMT. S +T S Similarly, the sampling clock for the m-th channel is kMT. S +(m-1)T S Considering the sampling time offset error, the output signal of the first channel of the TI-ADC is expressed by the following formula: in, This represents the k-th sample value of the first channel of the TI-ADC. Indicates the input code element. This indicates the sampling clock offset of the first channel; If we only consider the data from the current frame and the previous frame, where the current frame is the k-th sample value and the previous frame is the (k-1)-th sample value, then: In the above formula, the last term on the right side represents the inter-symbol interference (ISI) caused by the remaining data at the current sampling time; right Finding the mean, we get: As the m-th channel, Represented as: Since is a constant, we get: in, express hour The slope; the above equation As an error function, it is fed to the LMS module, so that The value approaches 0, thus calibrating the sampling clock offset.

2. The calibration method for sampling time offset mismatch of TI-ADC for SerDes according to claim 1, characterized in that, The TI-ADC includes an input data prediction module, an LMS module, and a delay adjustment module.

3. The calibration method for sampling time offset mismatch of TI-ADC for SerDes according to claim 1, characterized in that, The input symbols are provided by the input data prediction module.

4. The calibration method for sampling time offset mismatch of TI-ADC for SerDes according to claim 1, characterized in that, The error value is sent to the LMS module, and the LMS output will generate corresponding control codes to adjust the delay of each channel so that the sampling clock offset of each channel is aligned with the clock offset of the reference channel.

5. A storage medium capable of being read by a computer or processor, characterized in that, The storage medium stores a computer program for performing any one of the methods of claims 1-4.

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