Sampling circuit for clock regulation, sampling control method and electronic equipment

Abstract

The invention discloses a clock regulation sampling circuit, a sampling control method and electronic equipment. The sampling circuit comprises a first differential branch, a second differential branch, a phase detection circuit, a correction circuit and an adjusting circuit. The first differential branch is connected between the first port and the first input end of the phase detection circuit; the second differential branch is connected between the second port and the second input end of the phase detection circuit; the correction circuit is connected between the output end of the phase detection circuit and the adjusting circuit, and is configured to output a control signal to the adjusting circuit based on a detection result of the phase detection circuit; the adjusting circuit is coupled to the first differential branch circuit and the second differential branch circuit, is coupled to the first clock signal source, and is configured to adjust the sampling clock of one or more of the first differential branch circuit or the second differential branch circuit based on the control signal. The invention has the technical effects of reducing the differential input signal mismatch, reducing the even harmonic energy and improving the operation stability of the equipment.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of circuit technology, and in particular to a sampling circuit for clock adjustment, a sampling control method, and an electronic device. Background Art

[0002] The development of wireless communication technology has continuously increased the signal frequency requirements of high-speed and high-precision analog-to-digital converters. In high-sampling-rate analog-to-digital converters, time-domain interleaved sampling is usually used to increase the sampling rate. The spectrum finally output by the analog-to-digital converter contains the higher-order harmonics of each sub-channel analog-to-digital converter itself, as well as the multi-channel spurious generated by the mismatch of amplitude and phase between multiple channels. In addition, due to non-ideal factors such as asymmetric routing and device mismatch, the even-order linearity of the differential signal becomes worse with frequency. Therefore, the harmonic problem of the differential signal input to the analog-to-digital converter deserves attention. Summary of the invention

[0003] In view of this, the embodiments of the present disclosure provide a sampling circuit, a sampling control method, and an electronic device with clock adjustment, in order to reduce the harmonic influence in the differential signal of the input analog-to-digital converter. A sampling circuit includes: a first differential branch, a second differential branch, a phase detection circuit, a correction circuit, and an adjustment circuit; the first differential branch is connected between a first port and a first input end of the phase detection circuit; the second differential branch is connected between a second port and a second input end of the phase detection circuit; the correction circuit is connected between an output end of the phase detection circuit and the adjustment circuit, and is configured to output a control signal to the adjustment circuit based on the detection result of the phase detection circuit; the adjustment circuit is coupled to the first differential branch and the second differential branch, and is coupled to a first clock signal source, and is configured to adjust the sampling clock of one or more differential branches of the first differential branch through the first adjustment branch or through the second adjustment branch based on the control signal.

[0004] The above clock-adjusted sampling circuit determines the phase error through the detection result of the phase detection circuit, and then the correction circuit generates a control signal according to the detection result to change the sampling clock in the differential branch through the adjustment circuit, thereby realizing effective adjustment of the phase error, reducing the mismatch of the differential input signal, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip, reducing interference to sensitive equipment, and improving the operating stability and reliability of the equipment.

[0005] Optionally, the first differential branch includes: a first sampling switch and a first sampling capacitor, the first sampling switch is connected between the first port and the first end of the first sampling capacitor; the second differential branch includes: a second sampling switch and a second sampling capacitor, the second sampling switch is connected between the second port and the first end of the second sampling capacitor.

[0006] Optionally, a first end of the first sampling capacitor is coupled to the first input end, and a second end of the first sampling capacitor is grounded; a first end of the second sampling capacitor is coupled to the second input end, and a second end of the second sampling capacitor is grounded.

[0007] Optionally, the regulating circuit includes a first regulating branch and a second regulating branch; the first regulating branch is connected between the correction circuit and the first sampling switch; and the second regulating branch is connected between the correction circuit and the second sampling switch.

[0008] Optionally, it also includes: a third sampling switch and a fourth sampling switch; the second end of the first sampling capacitor is coupled to the first input end; the second end of the second sampling capacitor is coupled to the second input end; the third sampling switch is connected between the first input end and the common-mode voltage source; the fourth sampling switch is connected between the second input end and the common-mode voltage source; and the regulating circuit is coupled to the third sampling switch and the fourth sampling switch respectively.

[0009] Optionally, the first sampling switch and the second sampling switch are respectively coupled to a second clock signal source.

[0010] Optionally, the phase detection circuit includes: a first switch tube, a second switch tube, a third switch tube and an operational amplifier; the drain of the first switch tube and the drain of the second switch tube are coupled to the first power supply, the source of the first switch tube and the source of the second switch tube are coupled to the drain of the third switch tube; the gate of the first switch tube is coupled to the output end of the operational amplifier, the gate of the second switch tube is coupled to the reference voltage source, and the gate of the third switch tube is coupled to the bias voltage source; the drain of the third switch tube serves as the output end of the phase detection circuit, and the source of the third switch tube is grounded.

[0011] Optionally, the phase detection circuit also includes: a first capacitor, a second capacitor and a third capacitor; the first capacitor is connected between the input terminal and the first input terminal of the operational amplifier, and the second capacitor is connected between the input terminal and the second input terminal of the operational amplifier; one end of the third capacitor is coupled to the output terminal of the phase detection circuit, and the other end is grounded.

[0012] In a second aspect, a sampling control method is provided, which is used to control the sampling circuit provided in the first aspect, including: configuring a first regulating branch and a second regulating branch in the regulating circuit to be a first preset gear; obtaining a first output result of the phase detection circuit; adjusting the first regulating branch to a second preset gear based on the first output result, and adjusting the second regulating branch to a third preset gear, wherein the phase adjustment value of the second preset gear is greater than the first preset gear, and the phase adjustment value of the third preset gear is less than the first preset gear; obtaining a second output result of the phase detection circuit; when the second output result is greater than the first output result, adjusting the first regulating branch to a fourth preset gear, and adjusting the second regulating branch to a fifth preset gear, wherein the phase adjustment value of the fourth preset gear is less than the first preset gear, and the phase adjustment value of the fifth preset gear is greater than the first preset gear; when the second output result is less than the first output result, adjusting the first regulating branch to a sixth preset gear, and adjusting the second regulating branch to a seventh preset gear, until the second output result meets the preset output threshold, wherein the phase adjustment value of the sixth preset gear is greater than the second preset gear, and the phase adjustment value of the seventh preset gear is less than the third preset gear.

[0013] According to a third aspect, an electronic device is provided, comprising the sampling circuit provided in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following is a brief introduction to the drawings used in describing the embodiments of the present disclosure: Figure 1 A schematic diagram of a conventional test scenario provided in some embodiments of the present application is shown; Figure 2 A schematic diagram of the circuit structure of a clock-regulated sampling circuit provided in some embodiments of the present application is shown; Figure 3 A schematic diagram of the circuit structure of another clock-regulated sampling circuit provided in some embodiments of the present application is shown; Figure 4 A timing diagram of a clock-regulated sampling circuit provided in some embodiments of the present application is shown; Figure 5 A circuit structure diagram of another clock-regulated sampling circuit provided in some embodiments of the present application is shown; Figure 6 A timing diagram of another clock-regulated sampling circuit provided in some embodiments of the present application is shown; Figure 7 A circuit structure schematic diagram of a phase detection circuit provided in some embodiments of the present application is shown; Figure 8 A schematic flow chart of a sampling control method provided in some embodiments of the present application is shown; Fig. 9 A schematic structural diagram of a sampling control device provided in some embodiments of the present application is shown. DETAILED DESCRIPTION

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will illustrate examples of implementation of the present disclosure with reference to the accompanying drawings. The accompanying drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other accompanying drawings and other implementations can be obtained based on these drawings without creative work. Adjustments and improvements made without departing from the concept of the present disclosure are all within the protection scope of the present disclosure.

[0016] In order to simplify the drawings, each figure only schematically shows the parts related to the embodiments, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only a part of the components with the same structure or function is schematically drawn, and there may be more or less components with the same structure or function in reality.

[0017] In the present disclosure, unless otherwise clearly specified and limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish and describe associated objects, and cannot be understood as indicating or implying the relative importance or order between associated objects; in addition, they do not represent the number of associated objects. "Multiple" includes two or more, and other quantifiers are similar. " / " is used to describe the relationship between associated objects, which indicates the "or" relationship between associated objects. "And / or" is used to describe the relationship between associated objects, which includes any combination relationship between associated objects, such as "a and / or b" includes: "alone a", "alone b", or "a and b". "One or more" or "at least one" in multiple objects refers to any object or any combination of multiple objects, such as "one or more of a1, a2, a3" or "at least one of a1, a2, a3" includes: "alone a1", "alone a2", "alone a3", "a1 and a2", "a1 and a3", "a2 and a3", or "a1, a2 and a3".

[0018] The development of wireless communication technology has continuously increased the signal frequency requirements of high-speed and high-precision analog-to-digital converters. In high-sampling-rate analog-to-digital converters, time-domain interleaved sampling is usually used to increase the sampling rate. The spectrum finally output by the analog-to-digital converter contains the higher-order harmonics of each sub-channel analog-to-digital converter itself, as well as the multi-channel spurious generated by the mismatch of amplitude and phase between multiple channels. In addition, due to non-ideal factors such as asymmetric routing and device mismatch, the even-order linearity of the differential signal is more severe with frequency. In the actual chip testing process, the even-order harmonic energy is often much higher than the other harmonic energies. This problem is difficult to accept in some special scenarios such as radar detection and other applications. Figure 1 A schematic diagram of a conventional test scenario provided in some embodiments of the present application is shown. A high-frequency signal is provided by a signal source 10, converted into a differential signal by an external balun 20, and the differential signal is connected to the PCB board through two equal-length transmission lines, and then sent to the chip to be tested 30 through a series of RC matching network devices. However, the differential signal generated by the balun 20 cannot completely achieve a phase difference of 180 degrees, and the two transmission lines of the differential signal are also difficult to be completely symmetrical, so the differential signal sent to the chip to be tested 30 will produce a phase or amplitude difference. Inside the chip to be tested 30, the differential input is sent to the input port of the analog front-end circuit through a symmetrical routing, and then provided to each sub-analog-to-digital converter through a tree-like routing. In the actual layout, due to physical routing limitations, there is also a mismatch between the differential input routing and the tree-like routing, and there may also be a device mismatch in the analog front-end circuit, so the signal actually sent to the sampling input end of the sub-analog-to-digital converter must have a phase and amplitude mismatch, affecting the final test results or causing unexpected failures. Therefore, a sampling circuit provided in the present application detects the phase difference of the differential input signal and adjusts the clock of the sampling switch according to the detection result to achieve the minimum phase difference, so as to reduce the mismatch of the differential input signal and thus reduce the even harmonic energy of the entire analog-to-digital conversion chip.

[0019] Figure 2 The circuit structure diagram of a clock-regulated sampling circuit provided in some embodiments of the present application is shown. The clock-regulated sampling circuit 200 includes: a first differential branch 210, a second differential branch 220, a phase detection circuit 230, a correction circuit 240 and an adjustment circuit 250; the first differential branch 210 is connected between the first port IN1 and the first input end of the phase detection circuit 230; the second differential branch 220 is connected between the second port IN2 and the second input end of the phase detection circuit 230; the correction circuit 240 is connected between the output end of the phase detection circuit 230 and the adjustment circuit 250, and is configured to output a control signal to the adjustment circuit 250 based on the detection result of the phase detection circuit 230; the adjustment circuit 250 is coupled to the first differential branch 210 and the second differential branch 220, and is coupled to a clock signal source, and is configured to adjust the sampling clock of one or more differential branches of the first differential branch 210 through the first adjustment branch or the second differential branch 220 through the second adjustment branch based on the control signal.

[0020] In the above sampling circuit, the first differential branch 210 and the second differential branch 220 obtain input signals from the connected signal source through the first port IN1 and the second port IN2 respectively. For example, the first differential branch 210 can control the on and off of the sampling switch according to the preset sampling period. When the sampling switch is on, the input signal is sampled through the sampling capacitor. When the sampling switch is off, the input signal is suspended and the charge stored in the sampling capacitor is transferred to the subsequent circuit to complete the sampling. After the sampling is completed, the differential signal provided by the first differential branch 210 and the second differential branch 220 can enter the phase detection circuit 230 from the first input end and the second input end respectively, detect the phase error between the two signals and provide the detection result to the correction circuit 240. For example, when the phase error at both ends of the difference is the smallest, the output value of the phase detection circuit 230 is the lowest, and when the phase error increases, the output value of the phase detection circuit 230 increases accordingly. During the detection process, the output result can be further sent to the correction circuit 240, and the control signal of the control adjustment circuit 250 is generated according to the specific parameters of the output result. For example, when the phase error is large, the sampling period of one or all branches in the first differential branch 210 or the second differential branch 220 is adjusted. Accordingly, the change of the sampling period can change the on and off time of the sampling switch, thereby accumulating different amounts of charge in the sampling capacitor, and reflecting different phase error results in the phase detection circuit 230. When the adjustment circuit 250 is performing phase adjustment, for example, it can include a series of control gears. During the initial adjustment, the adjustment circuit 250 can be set to be in the middle gear. When the output value of the phase detection circuit 230 is small, the differential control signals generated by the correction circuit 240 are relatively close on both sides of the middle gear. When the output value of the phase detection circuit 230 is large, the difference between the differential control signals on both sides of the middle gear is large, thereby achieving effective adjustment of the phase error. The above sampling circuit reduces the mismatch of the differential input signal by adjusting the sampling time, thereby reducing the even harmonic energy of the entire analog-to-digital conversion chip, reducing interference to sensitive equipment, and improving the operating stability and reliability of the equipment.

[0021] Figure 3A circuit structure diagram of another clock-regulated sampling circuit provided in some embodiments of the present application is shown. In the clock-regulated sampling circuit 300, the first differential branch includes: a first sampling switch Sc1 and a first sampling capacitor Cc1, and the first sampling switch Sc1 is connected between the first port IN1 and the first end of the first sampling capacitor Cc1; the second differential branch includes: a second sampling switch and a second sampling capacitor Cc2, and the second sampling switch is connected between the second port IN2 and the first end of the second sampling capacitor Cc2. The first sampling switch Sc1 and the second sampling switch can be turned on and off according to the sampling clock cycle provided by the first clock signal source CKS1. When the first sampling switch Sc1 and the second sampling switch are turned on, the input signal enters from the first port IN1 and the second port IN2, and is sampled by the first sampling capacitor Cc1 and the second sampling capacitor Cc2. When the sampling clock cycle indicates that the first sampling switch Sc1 and the second sampling switch are turned off, the charge stored in the first sampling capacitor Cc1 and the second sampling capacitor Cc2 can be transferred to the phase detection circuit 330, thereby completing the sampling within the cycle, and detecting the phase difference between the input differential signals via the phase detection circuit 330.

[0022] Continue to refer Figure 3 , the first end of the first sampling capacitor Cc1 is coupled to the first input end, and the second end of the first sampling capacitor Cc1 is grounded; the first end of the second sampling capacitor Cc2 is coupled to the second input end, and the second end of the second sampling capacitor Cc2 is grounded. The above sampling circuit structure forms a top plate sampling, which can be applied to the scene with high requirements on sampling speed but relatively low requirements on accuracy. Figure 3 In the sampling circuit, when the clock signal provided by the first clock signal source CKS1 is at a high level, the first sampling switch Sc1 and the second sampling switch can be controlled to be turned on, and the input signal charges the first sampling capacitor Cc1 and the second sampling capacitor Cc2. The input signal corresponding to the falling edge of the clock signal provided by the first clock signal source CKS1 is the signal level finally maintained in the first sampling capacitor Cc1 and the second sampling capacitor Cc2. When the clock signal provided by the first clock signal source CKS1 is at a low level, the phase detection circuit 330 compares the phase difference between VSP and VSN of the signal holding node to determine the detection result. Figure 4A timing diagram of a clock-regulated sampling circuit provided in some embodiments of the present application is shown. The input signals VINp and VINn enter from the first port IN1 and the second port IN2 respectively, and the first clock signal source CKS1 provides a clock signal waveform. Φp or Φn represents the on-off timing of the first sampling switch Sc1 or the second sampling switch, and the shaded part represents the possible off-time of the first sampling switch Sc1 or the second sampling switch. When the phase error at both ends of the difference is the smallest, the output value of the phase detection circuit 330 is the lowest. Conversely, when the phase difference increases, the output value of the phase detection circuit 330 will increase accordingly. The detection result is further sent to the correction circuit 340, and a control signal for controlling the adjustment circuit is generated based on the detection result, thereby adjusting the sampling period of the clock signal provided to the first sampling switch Sc1 and the second sampling switch to reduce the entire even harmonic energy.

[0023] Continue to refer Figure 3 The regulating circuit may include a first regulating branch 351 and a second regulating branch 352; the first regulating branch 351 is connected between the correction circuit 340 and the first sampling switch Sc1; the second regulating branch 352 is connected between the correction circuit 340 and the second sampling switch. The first regulating branch 351 and the second regulating branch 352 in the regulating circuit may be realized by adjusting the inverter of the tail current source, the inverter load plus the DAC capacitor, etc., and the regulating accuracy may be the minimum value of the phase error correction.

[0024] Figure 5 A circuit structure diagram of another clock-regulated sampling circuit provided in some embodiments of the present application is shown. The sampling circuit 500 also includes: a third sampling switch Sc3 and a fourth sampling switch Sc4; the second end of the first sampling capacitor Cc1 is coupled to the first input end; the second end of the second sampling capacitor Cc2 is coupled to the second input end; the third sampling switch Sc3 is connected between the first input end and the common-mode voltage source; the fourth sampling switch Sc4 is connected between the second input end and the common-mode voltage source; and the regulating circuit is coupled to the third sampling switch Sc3 and the fourth sampling switch Sc4, respectively.

[0025] In some embodiments, the first sampling switch and the second sampling switch are respectively coupled to a second clock signal source.

[0026] The sampling method of the above sampling circuit is bottom plate sampling. The bottom plate charge of the sampling capacitor is not easily affected by switch control and input current, and has low requirements for switches, which can improve the stability of the circuit and is suitable for scenarios with high requirements for sampling accuracy and more complex circuit designs. Different from top plate sampling, the adjustment circuit can adjust the control timing of the third sampling switch Sc3 and the fourth sampling switch Sc4 of the bottom plate of the sampling capacitor. Figure 6FIG. 2 shows a timing diagram of another clock-adjusted sampling circuit provided in some embodiments of the present application. Figure 6 In the bottom plate sampling, the falling edge of the sampling clock provided by the first clock signal source CKS1 is earlier than the sampling clock provided by the second clock signal source CKS2. Therefore, in this sampling circuit, when the sampling clock delay is adjusted to the maximum gear, the third sampling switch Sc3 and the fourth sampling switch Sc4 can be turned on and off in the timing sequence. and The falling edge of is earlier than the falling edge of the second clock signal source CKS2.

[0027] Figure 7 A circuit structure diagram of a phase detection circuit provided in some embodiments of the present application is shown. The phase detection circuit includes: a first switch tube M1, a second switch tube M2, a third switch tube M3 and an operational amplifier A1; the drain of the first switch tube M1 and the drain of the second switch tube M2 are coupled to the first power supply VDD, the source of the first switch tube M1 and the source of the second switch tube M2 are coupled to the drain of the third switch tube M3; the gate of the first switch tube M1 is coupled to the output end of the operational amplifier A1, the gate of the second switch tube M2 is coupled to the reference voltage source VREF, and the gate of the third switch tube M3 is coupled to the bias voltage source VBIAS; the drain of the third switch tube M3 serves as the output end of the phase detection circuit, and the source of the third switch tube M3 is grounded.

[0028] The phase detection circuit also includes: a first capacitor C1, a second capacitor C2 and a third capacitor C3; the first capacitor C1 is connected between the input terminal and the first input terminal of the operational amplifier A1, and the second capacitor C2 is connected between the input terminal and the second input terminal of the operational amplifier A1; one end of the third capacitor C3 is coupled to the output terminal of the phase detection circuit, and the other end is grounded.

[0029] The above sampling circuit receives the signal from the sampling and holding nodes VSP and VSN, and connects the first capacitor C1 and the second capacitor C2 of the same size in series to perform AC coupling, remove the DC component in the input signal, and transmit the AC part to prevent the DC bias from affecting the operation of the subsequent circuit, and avoid the DC level in the input signal being too high or too low. After the intermediate node is formed in series, the signal amplitude is increased by the operational amplifier A1, and the operational amplifier A1 outputs it and connects it to the drain of the first switch tube M1 and the second switch tube M2 respectively with the reference voltage source VREF. After the source of the first switch tube M1 and the source of the second switch tube M2 are short-circuited, the output voltage size represents the phase size of the input differential signal. When the phase difference between the two ends of the differential input is 0, its output is a common mode level.

[0030] Figure 8A flow chart of a sampling control method provided in some embodiments of the present application is shown. The sampling control method is used to control the sampling circuit provided in the above embodiments, and at least includes the following steps: S810: configuring a first regulating branch and a second regulating branch in the regulating circuit to a first preset gear position; S820: Obtain a first output result of the phase detection circuit; S830: adjusting the first regulating branch to a second preset gear position based on the first output result, and adjusting the second regulating branch to a third preset gear position, wherein the phase adjustment value of the second preset gear position is greater than the first preset gear position, and the phase adjustment value of the third preset gear position is less than the first preset gear position; S840: Obtain a second output result of the phase detection circuit; S850: When the second output result is greater than the first output result, adjusting the first regulating branch to a fourth preset gear position, and adjusting the second regulating branch to a fifth preset gear position, wherein the phase adjustment value of the fourth preset gear position is less than the first preset gear position, and the phase adjustment value of the fifth preset gear position is greater than the first preset gear position; S860: When the second output result is less than the first output result, adjust the first adjustment branch to the sixth preset gear, and adjust the second adjustment branch to the seventh preset gear, until the second output result meets the preset output threshold, wherein the phase adjustment value of the sixth preset gear is greater than the second preset gear, and the phase adjustment value of the seventh preset gear is less than the third preset gear.

[0031] In the above sampling control method, when obtaining the first output result, it is determined that the output of the phase detection circuit increases, and the phase adjustment control gear of the adjustment circuit corresponding to the first differential branch or the second differential branch in the sampling circuit can be increased, such as increasing the control gear of the first adjustment branch and reducing the control gear of the second adjustment branch, and then the sampling results after a certain number of adjustments are accumulated and detected again by the phase detection circuit. If the output value of the phase detection circuit increases compared with the last time, the adjustment direction is reversed, for example, the control gear of the first adjustment branch is reduced from the middle gear, and the phase adjustment control of the control gear of the second adjustment branch is increased from the middle gear. If the output value of the phase detection circuit decreases compared with the last time, the adjustment amplitude is further increased, for example, the control gear of the first adjustment branch is further increased, and the control gear of the second adjustment branch is reduced. When the output of the phase detection circuit falls within the range of the preset output threshold, the correction is completed, and the control gear no longer changes.

[0032] Based on the same technical concept, an electronic device is provided, comprising the sampling circuit provided in the above embodiment.

[0033] Based on the same technical concept, Fig. 9A schematic diagram of the structure of a sampling control device provided in some embodiments of the present application is shown. The sampling control device 900 includes: a configuration unit 910, configured to configure the first adjustment branch and the second adjustment branch in the adjustment circuit to a first preset gear; an acquisition unit 920, configured to acquire a first output result of the phase detection circuit; an adjustment unit 930, configured to adjust the first adjustment branch to a second preset gear based on the first output result, and to adjust the second adjustment branch to a third preset gear, wherein the phase adjustment value of the second preset gear is greater than the first preset gear, and the phase adjustment value of the third preset gear is less than the first preset gear; the acquisition unit 920 is also configured to acquire the second output result of the phase detection circuit; The adjustment unit 930 is also used to adjust the first adjustment branch to the fourth preset gear position and the second adjustment branch to the fifth preset gear position when the second output result is greater than the first output result, wherein the phase adjustment value of the fourth preset gear position is less than the first preset gear position, and the phase adjustment value of the fifth preset gear position is greater than the first preset gear position; and to adjust the first adjustment branch to the sixth preset gear position and the second adjustment branch to the seventh preset gear position when the second output result is less than the first output result, until the second output result meets the preset output threshold, wherein the phase adjustment value of the sixth preset gear position is greater than the second preset gear position, and the phase adjustment value of the seventh preset gear position is less than the third preset gear position.

[0034] The division of the above units is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. In addition, the above units can be implemented in the form of a processor calling software; for example, a photovoltaic component roller brush cleaning control device includes a processor, the processor is connected to a memory, and instructions are stored in the memory. The processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of each unit, wherein the processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory is a memory in the device or a memory outside the device. Alternatively, the above units can be implemented in the form of hardware circuits, and the functions of some or all of the units can be realized by designing the hardware circuits. The hardware circuit can be understood as one or more processors; for example, in some embodiments, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of some or all of the above units are realized by designing the logical relationship of the components in the circuit; for example, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD), which can include a large number of logic gate circuits, and the logical relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of some or all of the above units. All units of the above device may be implemented entirely in the form of a processor calling a program, or entirely in the form of a hardware circuit, or partially in the form of a processor calling a program and the rest in the form of a hardware circuit.

[0035] In some embodiments of the present disclosure, the processor is a circuit with signal processing capability. In some embodiments, the processor may be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a graphics processing unit (GPU) or a digital signal processor (DSP), etc. In another implementation, the processor may implement certain functions through the logical relationship of a hardware circuit, and the logical relationship of the hardware circuit is fixed or reconfigurable, such as a hardware circuit implemented by an ASIC or PLD, such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the process of the processor loading a configuration document and implementing the hardware circuit configuration can be understood as the process of the processor loading instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc. It can be seen that each unit in the above device can be one or more processors (or processing circuits) configured to implement the above method, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms. In addition, each unit in the above device can be integrated together in whole or in part, or can be implemented independently. In some embodiments, these units are integrated together and implemented in the form of a system on chip (SOC). The SOC may include at least one processor for implementing any of the above methods or implementing the functions of each unit of the above device.

[0036] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments. In addition, the above embodiments can be freely combined as needed.

Claims

1. A clock-regulated sampling circuit, characterized in that: include: A first differential branch, a second differential branch, a phase detection circuit, a correction circuit and an adjustment circuit; The first differential branch is connected between the first port and the first input terminal of the phase detection circuit; The second differential branch is connected between the second port and the second input terminal of the phase detection circuit; The correction circuit is connected between the output terminal of the phase detection circuit and the adjustment circuit, and is configured to output a control signal to the adjustment circuit based on the detection result of the phase detection circuit; The adjustment circuit is coupled to the first differential branch and the second differential branch, and to a first clock signal source, and is configured to adjust the sampling clock of the first differential branch through the first adjustment branch or adjust the sampling clock of one or more differential branches in the second differential branch through the second adjustment branch based on the control signal.

2. The sampling circuit according to claim 1, characterized in that: The first differential branch includes: a first sampling switch and a first sampling capacitor, wherein the first sampling switch is connected between the first port and a first end of the first sampling capacitor; The second differential branch includes: a second sampling switch and a second sampling capacitor, wherein the second sampling switch is connected between the second port and a first end of the second sampling capacitor.

3. The sampling circuit according to claim 2, characterized in that: A first terminal of the first sampling capacitor is coupled to the first input terminal, and a second terminal of the first sampling capacitor is grounded; A first terminal of the second sampling capacitor is coupled to the second input terminal, and a second terminal of the second sampling capacitor is grounded.

4. The sampling circuit according to claim 3, characterized in that: The first regulating branch is connected between the correction circuit and the first sampling switch; The second regulating branch is connected between the correction circuit and the second sampling switch.

5. The sampling circuit according to claim 2, characterized in that: Also includes: a third sampling switch and a fourth sampling switch; The second terminal of the first sampling capacitor is coupled to the first input terminal; The second terminal of the second sampling capacitor is coupled to the second input terminal; The third sampling switch is connected between the first input terminal and the common mode voltage source; The fourth sampling switch is connected between the second input terminal and the common mode voltage source; The regulating circuit is coupled to the third sampling switch and the fourth sampling switch respectively.

6. The sampling circuit according to claim 5, characterized in that: The first sampling switch and the second sampling switch are respectively coupled to a second clock signal source.

7. The sampling circuit according to any one of claims 1 to 6, characterized in that: The phase detection circuit comprises: a first switch tube, a second switch tube, a third switch tube and an operational amplifier; The drain of the first switch tube and the drain of the second switch tube are coupled to a first power source, and the source of the first switch tube and the source of the second switch tube are coupled to the drain of the third switch tube; The gate of the first switch tube is coupled to the output terminal of the operational amplifier, the gate of the second switch tube is coupled to a reference voltage source, and the gate of the third switch tube is coupled to a bias voltage source; The drain of the third switch tube serves as the output end of the phase detection circuit, and the source of the third switch tube is grounded.

8. The sampling circuit according to claim 7, characterized in that: The phase detection circuit further includes: a first capacitor, a second capacitor and a third capacitor; The first capacitor is connected between the input terminal of the operational amplifier and the first input terminal, and the second capacitor is connected between the input terminal of the operational amplifier and the second input terminal; One end of the third capacitor is coupled to the output end of the phase detection circuit, and the other end of the third capacitor is grounded.

9. A sampling control method, characterized in that: A method for controlling a sampling circuit according to any one of claims 1 to 8, comprising: configuring a first regulating branch and a second regulating branch in the regulating circuit to a first preset gear position; Acquire a first output result of the phase detection circuit; Based on the first output result, the first regulating branch is adjusted to a second preset gear position, and the second regulating branch is adjusted to a third preset gear position, wherein a phase adjustment value of the second preset gear position is greater than that of the first preset gear position, and a phase adjustment value of the third preset gear position is less than that of the first preset gear position; Obtaining a second output result of the phase detection circuit; When the second output result is greater than the first output result, adjusting the first regulating branch to a fourth preset gear position, and adjusting the second regulating branch to a fifth preset gear position, wherein the phase adjustment value of the fourth preset gear position is less than the first preset gear position, and the phase adjustment value of the fifth preset gear position is greater than the first preset gear position; When the second output result is less than the first output result, the first adjustment branch is adjusted to a sixth preset gear position, and the second adjustment branch is adjusted to a seventh preset gear position, until the second output result meets a preset output threshold, wherein the phase adjustment value of the sixth preset gear position is greater than the second preset gear position, and the phase adjustment value of the seventh preset gear position is less than the third preset gear position.

10. An electronic device, characterized in that: The sampling circuit comprises the sampling circuit described in any one of claims 1 to 8.

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