Fully differential input dynamic latch comparator applied to flash ADC

Abstract

The invention relates to a fully differential input dynamic latch comparator applied to a flash ADC (Analog to Digital Converter). The fully differential input dynamic latch comparator comprises a non-overlapping clock, a preamplifier, a dynamic latch comparator, an RS trigger and a switched capacitor module. The two-phase non-overlapping clock module is used for generating clocks clk1 and clk2 and respective early turn-off clocks clk1a and clk2a. And the pre-amplifier module is used for summing and amplifying the input differential signal and the reference voltage of the comparator. And the dynamic latch comparator module is used for comparing the output of the pre-amplifier to obtain a final result. The RS trigger is used for latching a comparison result for a half period, and the input end of the amplifier and the input end of the comparator are connected to the capacitor formed by the MOS tube to reduce kickback noise.

Description

Technical Field

[0001] The invention belongs to the field of analog integrated circuits, and in particular relates to a fully differential input dynamic latch comparator in a flash ADC used as a multi-bit quantizer in a sigma-delta ADC. Background Art

[0002] In the field of analog signal to digital signal conversion, the comparator is a very important module circuit, which often determines the performance of ADC. As the core module of analog-to-digital converter, the comparator's offset voltage, power consumption, return noise, comparison speed and other characteristics will have an extremely important impact on the formation of analog-to-digital converter. The large offset voltage of the comparator will cause the analog-to-digital converter to lose code and cause conversion errors; if the comparator speed is not enough, it will not be able to complete the correct comparison output within the required time, and metastable output will appear. Therefore, to realize a high-speed and high-precision analog-to-digital converter, the accuracy and speed of the comparator used are the key.

[0003] Common comparators can be divided into static and dynamic comparators. Static comparators have static current in the reset and regeneration stages, resulting in high power consumption and slow speed. Dynamic comparators use a pair of back-to-back cross-coupled inverters to form positive feedback, which has the advantages of fast response speed and extremely low static power consumption.

[0004] Figure 1 It is a simplified structure of the traditional comparator and the previous circuit. In the reset phase, the input voltage determines the current in the differential pair transistor, and the MOS switch will introduce a small output voltage due to the non-zero resistance, making the circuit an amplifier. The large voltage change on the regeneration node will inevitably couple to the input end through the parasitic capacitance, causing the input pair tube drain voltage to change, interfering with the input signal, which is called kickback noise.

[0005] The latch comparator is the most commonly used circuit in high-speed comparators and can quickly compare the size of signals. Figure 2 The figure shows a circuit diagram of a latch comparator in the prior art. The latch comparator includes a preamplifier and a latch. The preamplifier is used to amplify the differential mode of the input signal and then input it into the latch. The latch compares the amplified differential mode signal output by the preamplifier using positive feedback and then outputs it.

[0006] In order to realize the full differential input of the reference voltage and the input signal, the existing dynamic latch comparator generally uses two pre-operational amplifiers, and the circuit module thereof is complex, and needs to consume greater static power consumption, and the offset voltage of the pre-operational amplifier is also large.

[0007] After searching, the application publication number CN102957405A discloses a dynamic latch comparator, including a first switch circuit and a second switch circuit controlled by a positive latch signal, and a third switch circuit and a fourth switch circuit controlled by an inverse latch signal, wherein: the first switch circuit is connected between the first positive feedback node regeneration node and the output end of the first input tube; the second switch circuit is connected between the second positive feedback node regeneration node and the output end of the second input tube; the third switch circuit is connected between the output end of the first input tube and the ground / power supply; the fourth switch circuit is connected between the output end of the second input tube and the ground / power supply. Four switch circuits are added on the basis of the existing dynamic latch, and the output potential of the input pair tube can be kept stable during the reset cycle and the regeneration cycle, thereby effectively reducing the kick-back noise on the basis of low power consumption.

[0008] Differences and shortcomings: This patent only uses a dynamic latch comparator structure without adding a pre-operational amplifier. When the difference in the input differential voltage is small, the dynamic latch comparator has a slow latch speed and a large delay, and the input offset voltage will also affect the comparator result.

[0009] Ways to overcome: Use a preamplifier plus a dynamic latch comparator structure, and introduce a positive feedback to the dynamic latch comparator on the traditional structure, which can effectively increase the speed of the comparator and reduce the delay time. The input end of the op amp uses a switched capacitor with a two-phase clock circuit to achieve full differential signal input, and the added capacitor can reduce the impact of the input offset voltage of the operational amplifier. Summary of the invention

[0010] The present invention aims to solve the above problems of the prior art. A fully differential input dynamic latch comparator applied to flash ADC is proposed. The technical solution of the present invention is as follows:

[0011] A fully differential input dynamic latch comparator applied to flash ADC includes: a two-phase non-overlapping clock, a preamplifier, a dynamic latch circuit, an RS trigger and a switch capacitor module, wherein the non-overlapping clock circuit is used to generate two-phase clock signals clk1 and clk2 and respective early shutdown clock signals clk1a and clk2a; the preamplifier circuit is used to amplify the input differential signal and the reference voltage; the dynamic latch circuit is used to compare and latch the result according to the output of the preamplifier; the RS trigger circuit is used to further latch the latch result for half a cycle; the switch capacitor module includes switches S1, S2, S3, S4 and capacitors C1 and C2, which are used to realize the fully differential input of the reference voltage and the input signal. The whole circuit connection mode is: clk1 is connected to the S1 and S3 switches at the input end of the preamplifier, clk2 is connected to the S2 and S4 switches, and the capacitors C1 and C2 are controlled to sample the input signal. The Clk2 signal is inverted to become the clk2b signal, which is used to connect the M18, M19, M22, M23, and M11 tubes of the dynamic latch comparator to control the reset and regeneration stages of the comparator. The two input ends of the preamplifier are connected to the capacitors C1 and C2 respectively, and the output end is connected to the input tubes M12 and M15 of the latch through the MOS tubes M7 and M8. The latch result of the latch is output from the P and N terminals and connected to the P and N input terminals of the RS trigger for latching for half a cycle. Finally, the result of the comparator is output from the OUTP and OUTN terminals of the RS trigger.

[0012] Furthermore, the two-phase non-overlapping clock includes two AND gates AND1 and AND2, two NAND gates NAND1 and NAND2, and 17 inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, INV10, INV11, INV12, INV13, INV14, INV15, INV16, and INV17. The external input clock signal CLK is directly input to the NAND gate AND1, and the inverter INV1 inverts the external input clock signal CLK and then inputs it to the NAND gate AND2; the inverters INV2, INV3, and INV 4. INV5, INV6, and INV7 play a delay role within the loop of the two-phase non-overlapping clock signal generating circuit, among which inverters INV6 and INV7 are used to control the non-overlapping time of the two-phase clocks; inverters INV8, INV9, INV10, INV11, INV12, INV13, INV14, and INV15 play a role in increasing the driving capability of the two-phase non-overlapping clocks CLK1, CLK2 and the early-turnoff switch CLK1a, CLK2a clock signals outside the loop of the two-phase non-overlapping clock signal generating circuit, and INV16 and INV17 obtain the inverse signals clk1b and clk2b of the clocks clk1 and clk2.

[0013] Furthermore, the preamplifier mainly includes NMOS tubes M0, M1, M2, M24, M25, M26, M27, and PMOS tubes M3, M4, M5, M6. The connection relationship is as follows: M0 is an enable switch, whose gate is connected to the enable signal EN, and whose drain is connected to the source of the input tubes M1 and M2. The drains of the tubes M1 and M2 are connected to the drains of the tubes M3, M4, M5, and M6; at the same time, the gates of the tubes M3 and M6 are connected to their drains to form a diode; the gate of the tube M4 is connected to the drain of the tube M5, and the gate of the tube M5 is connected to the drain of the tube M4; the sources of the tubes M3, M4, M5, and M6 are connected to the power supply VDD. The drain of the tube M24 is connected to the gate of the tube M1, and the source of the tube M24 is connected to the drain of the tube M1; similarly, the drain of the tube M25 is connected to the gate of the tube M2, and the source is connected to the drain of the tube M2. The source, drain and substrate of the M26 tube are short-circuited together and connected to the drain of the M2 tube, and its gate is connected to the gate of the M1 tube; similarly, the source, drain and substrate of the M27 tube are short-circuited together and connected to the drain of the M1 tube, and its gate is connected to the gate of the M1 tube.

[0014] Furthermore, the dynamic comparator includes four reset switches M18, M19, M22, and M23, which are PMOS. The gate of M18 is connected to the control signal clk2b. The drains of M18 and M23 are respectively connected to the A point and B point of the latch, and the voltages of the A point and the B point are reset to VDD under the control signal; the drains of M19 and M22 are respectively connected to the P point and the N point of the latch comparator, and the voltages of the points are reset under the control signal. The sources of M18, M19, M22, and M23 are all connected to the power supply voltage VDD.

[0015] Furthermore, the switch capacitor module uses switches S1, S2, S3, and S4, and capacitors C1 and C2 cooperate with clocks clk1 and clk2 to complete signal input; in the Clk1 phase, capacitors C1 and C2 sample the reference voltages vrn and vrp respectively, and in the clk2 phase, capacitors C1 and C2 sample the input signals vin and vip. Finally, according to the principle of charge conservation on the capacitor, the positive input voltage of the preamplifier is (vip-vrp) and the negative input voltage is (vin-vrn), so the final differential voltage at the pre-amplifier input is (vip-vin)-(vrp-vrn).

[0016] Furthermore, the preamplifier circuit uses MOS tube M0 as a tail current source, MOS tube M1 and MOS tube M2 as input differential pair tubes, MOS tube M24 and MOS tube M25 are used for circuit unit gain connection, MOS tube M26 and MOS tube M27 are used to reduce the return noise at the input end, and MOS tube M4 and MOS tube M5 form a positive feedback connection to quickly establish a voltage difference between the two ends.

[0017] Furthermore, the dynamic latch circuit includes reset switches M18, M19, M22, M23, a control switch M11, and input switches M12 and M15, which are used to perform reset and comparison operations under clock control to reduce return noise and increase comparison speed.

[0018] Furthermore, the dynamic latch circuit also includes NMOS tubes M13 and M14, which are used to connect the A and B nodes during the comparison process to speed up the comparison; and NMOS tube M9 and PMOS tube M10, which are used to reset the input end of the comparator under the control of clk1 and clk1b clocks to prevent the charge stored in the parasitic capacitor from affecting the next comparison result.

[0019] Furthermore, the RS trigger circuit includes PMOS tubes M20 and M21 and NMOS tubes M16 and M17, which are used to maintain the result of the comparator under the control of the clock, reduce delay and improve stability.

[0020] The advantages and beneficial effects of the present invention are as follows:

[0021] The present invention introduces a switched capacitor to sample a reference voltage and an input signal on the basis of a traditional preamplifier, and can realize an input of a fully differential signal. The structure is simple and the power consumption is low. The introduced capacitor can also effectively reduce the input offset voltage of the preamplifier.

[0022] The present invention adds a pair of positive feedback circuits on the basis of the traditional dynamic latch comparator, which can more effectively speed up the latching speed of the comparator.

[0023] The present invention adds a clock-controlled CMOS switch to the input end of a traditional dynamic latch comparator. In the comparator reset phase, the charge at the comparator input end is reset to prevent the charge stored in the parasitic capacitor at the comparator input end from affecting the next comparison result. In addition, the use of the CMOS switch can effectively reduce the influence of MOS channel charge injection.

[0024] The innovative points of the present invention are:

[0025] 1. Fully differential input structure: The present invention uses switched capacitor sampling technology to achieve fully differential input of input signals and reference voltages, which can be processed by only one preamplifier. Compared with the traditional dual-preamplifier solution, the circuit structure is simpler, reducing power consumption and circuit complexity.

[0026] 2. Positive feedback enhancement: Based on the dynamic latch comparator, an additional positive feedback circuit is introduced, which is composed of PMOS tubes M20, M21 and NMOS tubes M16, M17. This significantly improves the latching speed of the comparator and reduces the delay time, thereby improving the overall performance of the comparator.

[0027] 3. Non-overlapping clock circuit optimization: A non-overlapping clock generation circuit including AND gates, NAND gates and multiple inverters is designed, which can accurately control the non-overlapping time of clk1 and clk2 to ensure the stability and accuracy of the circuit during the sampling and comparison stages, and at the same time reduce the impact of channel charge injection by shutting down clocks clk1a and clk2a in advance.

[0028] 4. Return noise suppression: The special connection method of M26 and M27 MOS tubes in the preamplifier circuit effectively suppresses return noise, improves signal transmission quality, and further improves the accuracy and stability of the comparator.

[0029] Beneficial Effects

[0030] - Reduced power consumption: The combination of a single preamplifier design and switched capacitor sampling technology significantly reduces the static power consumption of the entire comparator, which is especially important for flash ADCs that require high-speed, low-power operation. - Improved comparison speed: Additional positive feedback circuits and optimized clock control mechanisms make the dynamic latch comparator latch faster and reduce delay time, enabling faster response to changes in input signals and improving speed performance.

[0031] - Improved accuracy: The suppression of return noise and the elimination of input offset voltage improve the accuracy of the comparator and reduce conversion errors, which is essential for achieving high-precision analog-to-digital conversion.

[0032] Why is it not easy to think of?

[0033] - Complexity of circuit design: It is very difficult to achieve a balance between low power consumption, high precision and high speed in analog circuit design. Generally, improving precision and speed will increase power consumption, but the present invention improves speed and precision while maintaining low power consumption, which requires in-depth innovation in circuit structure and control mechanism.

[0034] - Clever introduction of positive feedback: In the dynamic latch comparator, the optimal design of positive feedback requires precise circuit parameter adjustment and in-depth theoretical analysis to ensure the stability of the circuit while improving the speed. This design requires a deep understanding of feedback theory and accurate prediction of the dynamic characteristics of the circuit.

[0035] - Collaborative solution of non-overlapping clock and return noise: Non-overlapping clock and return noise are two key factors affecting the performance of the comparator. The present invention solves these two problems at the same time through a unique circuit design, which is rare in existing technical literature and requires designers to have innovative ideas and a deep understanding of ADC design principles.

[0036] In summary, the present invention solves the key problems in the traditional comparator design through a series of innovative designs. Its innovations and beneficial effects are not easy to think of in the prior art, mainly due to the in-depth understanding of analog circuit design theory and the accurate grasp of ADC performance requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 The present invention provides a simplified structure of a conventional comparator and the preceding circuit in a preferred embodiment;

[0038] Figure 2 Traditional latch comparator circuit structure;

[0039] Figure 3 A preferred example comparator circuit diagram provided by the present invention;

[0040] Figure 4 Two-phase non-overlapping clock circuit diagram;

[0041] Figure 5 Non-overlapping clock simulation diagram;

[0042] Figure 6 Comparator function verification diagram;

[0043] Figure 7 Comparator delay simulation result diagram;

[0044] Figure 8 RS flip-flop structure diagram; DETAILED DESCRIPTION

[0045] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0046] The technical solution of the present invention to solve the above technical problems is:

[0047] like Figure 3 , Figure 4 A fully differential input dynamic latch comparator circuit applied to a flash ADC mainly comprises a pre-operational amplifier circuit, a two-phase non-overlapping clock circuit, a dynamic latch comparator circuit and a switch capacitor circuit.

[0048] The switch capacitor circuit uses switches S1, S2, S3, S4, capacitors C1, C2 with clocks clk1 and clk2 to complete the signal input. In the clk1 phase, switch S1 is closed, NMOS tube M24 is turned on, the operational amplifier is connected in unit gain at this time, capacitor C1 samples the reference voltage vrn, considering the input offset voltage vos of the operational amplifier, the charge Q1 stored on capacitor C1 = (Vrn-Vos)*C, when the comparator is in the clk2 phase, capacitor C1 samples the input signal Vin, at this time the charge Q2 stored on capacitor C1 = (Vin-Vr)*C, Vr represents the right plate voltage of capacitor C1, by The charge is conserved during the two phases of clk1 and clk2, so the voltage at the negative input of the pre-amplifier is V-=(Vin-Vrn+Vos-Vos)=(Vin-Vrn). Similarly, the voltage at the positive input is V+=(Vip-Vrp). The differential input voltage of the pre-amplifier is Vdiff=(Vip-Vin)-(Vrp-Vrn). From the above formula, it can be seen that the capacitor C has an offset storage function, which eliminates the offset voltage at the input of the pre-amplifier.

[0049] The preamplifier module is composed of an NMOS tube M0 tail current source tube, M1 and M2 input differential pair tubes, and M24 and M25 tubes are used to connect the circuit unit gain under the control of clock clk1, and the input reference voltage is sampled in cooperation with the capacitor. The capacitor connection method of M26 and M27 MOS tubes is used to reduce the impact of the kickback noise at the input end. PMOS tubes M4 and M5 are connected in positive feedback, the gate of M5 tube is connected to the drain of M4 tube, and the gate of M4 tube is connected to the drain of M5 tube, which can quickly establish the voltage difference between the two ends. PMOS tubes M3 and M6 are connected by diodes to ensure that there is current in the conduction circuit when the operational amplifier is working normally. The preamplifier amplifies the differential voltage Vdiff at the input end by a certain multiple and is passed to the input end of the dynamic latch comparator through the conduction of M7 and M8 tubes under the control of clock clk2.

[0050] The two-phase non-overlapping clock circuit comprises two AND gates AND1 and AND2, two NAND gates NAND1 and NAND2, and 17 inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, INV10, INV11, INV12, INV13, INV14, INV15, INV16, and INV17. The external input clock signal CLK is directly input to the NAND gate AND1, and the inverter INV1 inverts the external input clock signal CLK and inputs it to the NAND gate AND2. The inverters INV2, INV3, INV4, INV5, INV6, and INV7 play a delay role in the loop of the two-phase non-overlapping clock signal generating circuit, wherein the inverters INV6 and INV7 are used to control the non-overlapping time of the two-phase clock. Inverters INV8, INV9, INV10, INV11, INV12, INV13, INV14, and INV15 serve to increase the driving capability of the two-phase non-overlapping clocks CLK1 and CLK2 and the early-turnoff switch CLK1a and CLK2a clock signals outside the loop of the two-phase non-overlapping clock signal generating circuit. INV16 and INV17 obtain the inverse signals clk1b and clk2b of the clocks clk1 and clk2.

[0051] The dynamic comparator includes four reset switches M18, M19, M22, and M23, which are PMOS switches. Under the control of clock clk2ab, the A, B, P, and N nodes in the circuit are reset. NMOS tube M11 controls the entire comparator circuit to start the comparison operation under the control of clock clkab, and is turned off in the reset stage to reduce circuit power consumption. NMOS tubes M12 and M15 are the input ends of the comparator, and their input signals come from the output of the preamplifier. The preamplifier and the comparator are connected through NMOS tubes M7 and M8 for signal transmission. NMOS tube M9 and PMOS tube M10 are turned on to reset the comparator input end under the control of clk1 and clk1b clocks to prevent the charge stored in the input end parasitic capacitor from affecting the next comparison result of the comparator. The gate of NMOS tube M13 is connected to point B, the drain is connected to point A, and the gate of M14 is connected to point A and the drain is connected to point B, which speeds up the comparison speed of the comparator. The PMOS tubes M20 and M21 and the NMOS tubes M16 and M17 are cross-coupled in positive feedback connection to accelerate the latching of the voltages at the P point and the N point, so as to achieve the purpose of reducing the delay of the comparator.

[0052] Simulation Results

[0053] Figure 5A simulation result of non-overlapping clocks is shown, where the non-overlapping time of clk1 and clk2 is 5ns; clk1a and clk2a are the early shutdown clocks of clk1 and clk2, and the early shutdown time is 3ns; the non-overlapping clock is mainly used in the reset and regeneration stages of the comparator, and the early shutdown clock is mainly used to reduce the impact of channel charge injection in the capacitor sampling stage.

[0054] Figure 6 The simulation result diagram of the comparator function verification obtained by inputting a sine wave input signal and a common-mode reference voltage. From the result diagram, we can see that the comparator function is normal. Figure 7 To simulate the delay time of the comparator, the comparator starts to compare at the rising edge of the clock clk2ab, and the delay is about 32ps.

[0055] From the above results, it can be seen that the circuit of the dynamic latch comparator for full differential input applied to the flash ADC proposed by the present invention can realize the input of full differential signals, can reduce the input offset voltage of the pre-amplifier, and the comparator has a small delay, which is suitable for the comparator module in the quantizer of the sigma-delta ADC.

[0056] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions.

[0057] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0058] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A fully differential input dynamic latch comparator for flash ADC, characterized in that: include: Two-phase non-overlapping clock, preamplifier, dynamic latch circuit, RS trigger and switch capacitor module, non-overlapping clock circuit, used to generate two-phase clock signals clk1 and clk2 and respective early shutdown clock signals clk1a and clk2a; preamplifier circuit, used to amplify the input differential signal and reference voltage; dynamic latch circuit, used to compare and latch the result according to the output of the preamplifier; The RS trigger circuit is used to further latch the latch result for half a cycle; the switch capacitor module includes switches S1, S2, S3, S4 and capacitors C1 and C2, which are used to realize the full differential input of the reference voltage and the input signal; wherein clk1 is connected to the S1 and S3 switches at the input end of the preamplifier, and clk2 is connected to the S2 and S4 switches to control the capacitors C1 and C2 to sample the input signal. The Clk2 signal is inverted to become the clk2b signal to connect the M18, M19, M22, M23, and M11 tubes of the dynamic latch comparator to control the reset and regeneration phase of the comparator; the two input ends of the preamplifier are connected to the capacitors C1 and C2 respectively, and the output end is connected to the input tubes M12 and M15 of the latch through the MOS tubes M7 and M8. The latch result of the latch is output from the P and N ends, connected to the P and N input ends of the RS trigger, and latched for half a cycle. Finally, the result of the comparator is output from the OUTP and OUTN ends of the RS trigger.

2. A fully differential input dynamic latch comparator applied to a flash ADC according to claim 1, characterized in that: The two-phase non-overlapping clock includes two AND gates AND1 and AND2, two NAND gates NAND1 and NAND2, and 17 inverters INV1, INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, INV10, INV11, INV12, INV13, INV14, INV15, INV16, and INV17. The external input clock signal CLK is directly input to the NAND gate AND1, and the inverter INV1 inverts the external input clock signal CLK and then inputs it to the NAND gate AND2; the inverters INV2, INV3, INV4, INV5, INV6, INV7, INV8, INV9, INV10, INV11, INV12, INV13, INV14, INV15, INV16, and INV17. NV5, INV6, and INV7 play a delay role within the loop of the two-phase non-overlapping clock signal generating circuit, among which inverters INV6 and INV7 are used to control the non-overlapping time of the two-phase clocks; inverters INV8, INV9, INV10, INV11, INV12, INV13, INV14, and INV15 play a role outside the loop of the two-phase non-overlapping clock signal generating circuit to increase the driving capability of the two-phase non-overlapping clocks CLK1, CLK2 and the early shutdown switch CLK1a, CLK2a clock signals, and INV16 and INV17 obtain the inverse signals clk1b and clk2b of the clocks clk1 and clk2.

3. The fully differential input dynamic latch comparator applied to flash ADC according to claim 1, characterized in that: The invention mainly includes NMOS tubes M0, M1, M2, M24, M25, M26, M27, and PMOS tubes M3, M4, M5, M6, and the connection relationship thereof is as follows: M0 is an enable switch, whose gate is connected to the enable signal EN, and whose drain is connected to the source of input tubes M1 and M2; the drains of tubes M1 and M2 are connected to the drains of tubes M3, M4, M5, M6; at the same time, the gates of tubes M3 and M6 are connected to their drains to form a diode; the gate of tube M4 is connected to the source of tube M1 and M2; The drain of M5 tube and the gate of M5 tube are connected to the drain of M4 tube; the source of M3, M4, M5 and M6 tubes are connected to the power supply VDD; the drain of M24 tube is connected to the gate of M1 tube, and the source of M24 tube is connected to the drain of M1 tube; similarly, the drain of M25 tube is connected to the gate of M2 tube, and the source is connected to the drain of M2 tube; the source, drain and substrate of M26 tube are short-circuited together and connected to the drain of M2 tube, and its gate is connected to the gate of M1 tube; similarly, the source, drain and substrate of M27 tube are short-circuited together and connected to the drain of M1 tube, and its gate is connected to the gate of M1 tube.

4. The fully differential input dynamic latch comparator applied to flash ADC according to claim 1, characterized in that: The dynamic comparator includes four reset switches M18, M19, M22, and M23, which are PMOS transistors. The gate of M18 is connected to the control signal clk2b. The drains of M18 and M23 are respectively connected to the A point and the B point of the latch. Under the action of the control signal, the voltages of the A point and the B point are reset to VDD. The drains of M19 and M22 are respectively connected to the P point and the N point of the latch comparator. Under the action of the control signal, the voltages of these points are reset. The sources of M18, M19, M22, and M23 are all connected to the power supply voltage VDD.

5. The fully differential input dynamic latch comparator applied to flash ADC according to claim 1, characterized in that: The switch capacitor module uses switches S1, S2, S3, and S4, and capacitors C1 and C2 cooperate with clocks clk1 and clk2 to complete signal input; in the Clk1 phase, capacitors C1 and C2 sample reference voltages vrn and vrp respectively, and in the clk2 phase, capacitors C1 and C2 sample input signals vin and vip. Finally, according to the charge conservation principle on the capacitor, the positive input voltage of the preamplifier is (vip-vrp) and the negative input voltage is (vin-vrn), so the final differential voltage of the preamplifier input is (vip-vin)-(vrp-vrn).

6. The fully differential input dynamic latch comparator applied to flash ADC according to claim 3, characterized in that: The preamplifier circuit uses MOS tube M0 as a tail current source, MOS tube M1 and MOS tube M2 as input differential pair tubes, MOS tube M24 and MOS tube M25 are used for circuit unit gain connection, MOS tube M26 and MOS tube M27 are used to reduce the return noise at the input end, and MOS tube M4 and MOS tube M5 form a positive feedback connection to quickly establish a voltage difference between the two ends.

7. The fully differential input dynamic latch comparator applied to flash ADC according to claim 1, characterized in that: The dynamic latch circuit includes reset switches M18, M19, M22, M23, a control switch M11, and input switches M12 and M15, which are used to perform reset and comparison operations under clock control to reduce return noise and increase comparison speed.

8. The fully differential input dynamic latch comparator applied to flash ADC according to claim 7, characterized in that: The dynamic latch circuit also includes NMOS tubes M13 and M14, which are used to connect the A and B nodes during the comparison process to speed up the comparison; and NMOS tube M9 and PMOS tube M10, which are used to reset the input end of the comparator under the control of clk1 and clk1b clocks to prevent the charge stored in the parasitic capacitor from affecting the next comparison result.

9. The fully differential input dynamic latch comparator applied to flash ADC according to claim 1, characterized in that: The RS trigger circuit includes PMOS tubes M20 and M21 and NMOS tubes M16 and M17, which are used to maintain the result of the comparator under the control of the clock, reduce delay and improve stability.

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