Reference voltage generating circuit for generating high-speed random jitter

Abstract

The invention discloses a reference voltage generating circuit capable of generating high-speed random jitter, which is characterized in that random jitter is introduced on a threshold value of a comparator, and the threshold value of the comparator is adjusted within a certain range to reduce the influence of a gain error on an ADC (Analog to Digital Converter). The reference voltage generating circuit comprises a comparator A1, a comparator A2, PMOS (P-channel Metal Oxide Semiconductor) tubes P1-P3, NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N3, switches K1-K8, resistors R11-R14, resistors R21-R27 and resistors R31-R37; besides, DP / DN / DPB / DNB are control signals of corresponding switches respectively, DPB / DNB are reverse signals of DP / DN respectively, when the control signal is 1, the switches are switched on, and when the control signal is 0, the switches are switched off. According to the structure, the threshold voltage can be changed by controlling DP / DN, meanwhile, the structure can change the voltage only by controlling the switch of the current mirror, and the establishment speed of the output voltage does not depend on the switch on resistance, so that the structure can be applied to a high-speed ADC (Analog to Digital Converter).

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a reference voltage generating circuit for generating high-speed random jitter. Background Art

[0002] The traditional pipeline ADC (pipeline analog-to-digital converter) structure is as follows Figure 1 As shown, it is composed of a multi-stage MDAC (multiplication digital-to-analog converter), and the digital code output by each stage of MDAC is transmitted to the digital calibration circuit to obtain the final ADC output code.

[0003] The transfer function of the traditional 2.5-bit MDAC is as follows: Figure 2 As shown in the figure, the input range is -Vref~+Vref, and the output range is also -Vref~+Vref. There are 6 comparators, and the threshold voltages are -5Vref / 8, -3Vref / 8, -Vref / 8, +Vref / 8, +3Vref / 8, and +5Vref / 8. The slope of the transfer function in each region is 4, and the slope is the ratio of the capacitors in the MDAC. However, due to the mismatch of the capacitors used in the MDAC, there will be some regions with a slope greater than 4 and some regions with a slope less than 4, which will produce a gain error, and the transfer curve will become as follows Figure 3 As shown by the solid line in , the final pipeline ADC output will produce nonlinearity, thereby generating spurious high-order harmonics in the spectrum, which will deteriorate the spurious-free dynamic range (SFDR) and also deteriorate the integral nonlinearity (INL) and differential nonlinearity (DNL) of the ADC, which is very important in the communication field of certain small signal applications.

[0004] The traditional comparator reference voltage generation circuit structure is as follows Figure 4 As shown, a reference voltage buffer plus a voltage-dividing resistor string generates the required reference voltage and sends it to the comparator input to provide the required reference voltage. If this structure is used directly to generate more voltage-dividing nodes to obtain the required reference voltage jitter, additional switch impedance needs to be introduced, and the resistor string also needs to be divided into finer and smaller units. This will affect the speed of the comparator reference voltage and increase the area required for the resistor string, which is not suitable for use in high-speed and high-precision ADCs. Summary of the invention

[0005] The object of the present invention is to provide a reference voltage generating circuit for generating high-speed random jitter to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a reference voltage generating circuit for generating high-speed random jitter, including comparators A1 and A2, PMOS tubes P1-P3, NMOS tubes N1-N3, switches K1-K8, resistors R11-R14, resistors R21-R27, and resistors R31-R37; The sources of the PMOS transistors P1, PMOS transistors P2 and PMOS transistors P3 are all connected to the power supply voltage VDD, and the gates of the three are all connected to the output end of the comparator A1. The positive input end of the comparator A1 is connected to the reference voltage VREFH, and the negative input end is connected to the drain of the PMOS transistor P3; the drain of the PMOS transistor P1 is simultaneously connected to the first end of the resistor R11 and the first end of the resistor R12, the drain of the PMOS transistor P2 is simultaneously connected to the first end of the switch K1 and the first end of the switch K2, and the drain of the PMOS transistor P3 is simultaneously connected to the first end of the switch K3 and the first end of the switch K4; the second end of the switch K1 and the second end of the switch K3 are commonly connected to the second end of the resistor R11, and the second end of the switch K2 and the second end of the switch K4 are commonly connected to the second end of the resistor R12; The sources of the NMOS transistors M1, M2 and M3 are all grounded, and the gates of the three are all connected to the output end of the comparator A2. The positive input end of the comparator A2 is connected to the reference voltage VREFL, and the negative input end is connected to the drain of the NMOS transistor M3; the drain of the NMOS transistor M3 is simultaneously connected to the first end of the resistor R13 and the first end of the resistor R14, the drain of the NMOS transistor M1 is simultaneously connected to the first end of the switch K7 and the first end of the switch K8, and the drain of the NMOS transistor M2 is simultaneously connected to the first end of the switch K5 and the first end of the switch K6; the second end of the switch K8 and the second end of the switch K6 are commonly connected to the second end of the resistor R13, and the second end of the switch K7 and the second end of the switch K5 are commonly connected to the second end of the resistor R14; The resistors R21 - R27 are sequentially connected in series between the second end of the resistor R11 and the second end of the resistor R14 ; the resistors R31 - R37 are sequentially connected in series between the second end of the resistor R12 and the second end of the resistor R13 .

[0007] In one embodiment, the reference voltage generating circuit adjusts the threshold voltage range by expanding the current mirror, splitting the current mirror composed of PMOS tubes P1 and P2 and the current mirror composed of NMOS tubes M1 and M2 into a set of small current mirrors with multi-bit binary weights, and controlling their current switches with control signals of different weights to control the current ratio, so that the threshold voltage can be finely changed within the range of -Vref / 8~+Vref / 8, and the required current control signal is obtained through a pseudo-random code generator.

[0008] In one embodiment, the control signals of the switches K1, K2, K3, and K4 are DPB, DP, DNB, and DN, respectively; the control signals of the switches K5, K6, K7, and K8 are DP, DPB, DN, and DNB, respectively; the control signals DPB and DNB are respectively the reverse signals of DP and DN. When the control signal is 1, the switch is turned on, and when the control signal is 0, the switch is turned off.

[0009] The present invention provides a reference voltage generating circuit for generating high-speed random jitter, which can be used in a high-speed pipeline ADC. By introducing threshold voltage jitter, the nonlinearity caused by gain error can be significantly reduced, the linearity of the entire pipeline ADC can be improved, and the spurious-free dynamic range of the ADC can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the structure of a traditional pipeline analog-to-digital converter.

[0011] Figure 2 It is a schematic diagram of the MDAC transfer function of the traditional 2.5-bit structure.

[0012] Figure 3 It is a schematic diagram of the transmission curve that produces gain error.

[0013] Figure 4 It is a schematic diagram of the structure of a traditional comparator reference voltage generating circuit.

[0014] Figure 5 It is a schematic diagram showing that the maximum adjustable range of each comparator threshold is + / -Vref / 8.

[0015] Figure 6 The invention discloses a reference voltage generating circuit for generating high-speed random jitter.

[0016] Figure 7 It is a schematic diagram of adjusting the threshold voltage range by expanding the current mirror. DETAILED DESCRIPTION

[0017] The following is a further detailed description of a reference voltage generating circuit for generating high-speed random jitter proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] The present invention introduces a random jitter on the comparator threshold and adjusts the comparator threshold within a certain range to reduce the influence of gain error on ADC. Figure 5As shown in the figure, the maximum adjustable range of each comparator threshold is + / -Vref / 8. If it exceeds this range, the output of the MDAC at this level will exceed the input quantization range of the MDAC at the next level, resulting in missing codes in the entire ADC output. At the same time, each comparator will naturally have some threshold voltage offset due to process deviation, so it is necessary to leave some margin when designing the threshold jitter to prevent the MDAC output from exceeding the range. If the comparator threshold voltage is randomly jittered within the range of + / -Vref / 8, the MDAC output will not exceed the range, and the nonlinear effect caused by the gain error can be reduced.

[0019] The present invention provides a new reference voltage generating circuit which can generate random jitter. Figure 6 As shown, it includes comparators A1 and A2, PMOS tubes P1~P3, NMOS tubes N1~N3, switches K1~K8, resistors R11~R14, resistors R21~R27, and resistors R31~R37; in addition, DP / DN / DPB / DNB are control signals of the corresponding switches, DPB / DNB are reverse signals of DP / DN, and when the control signal is 1, the switch is turned on, and when it is 0, the switch is turned off.

[0020] The sources of the PMOS transistors P1, PMOS transistors P2 and PMOS transistors P3 are all connected to the power supply voltage VDD, and the gates of the three are all connected to the output terminal of the comparator A1. The positive input terminal of the comparator A1 is connected to the reference voltage VREFH, and the negative input terminal is connected to the drain of the PMOS transistor P3; the drain of the PMOS transistor P1 is simultaneously connected to the first end of the resistor R11 and the first end of the resistor R12, the drain of the PMOS transistor P2 is simultaneously connected to the first end of the switch K1 and the first end of the switch K2, and the drain of the PMOS transistor P3 is simultaneously connected to the first end of the switch K3 and the first end of the switch K4; the second end of the switch K1 and the second end of the switch K3 are commonly connected to the second end of the resistor R11, and the second end of the switch K2 and the second end of the switch K4 are commonly connected to the second end of the resistor R12; the control signals of the switches K1, K2, K3 and K4 are DPB, DP, DNB and DN respectively; The sources of the NMOS transistors M1, M2 and M3 are all grounded, and the gates of the three are all connected to the output end of the comparator A2. The positive input end of the comparator A2 is connected to the reference voltage VREFL, and the negative input end is connected to the drain of the NMOS transistor M3; the drain of the NMOS transistor M3 is simultaneously connected to the first end of the resistor R13 and the first end of the resistor R14, the drain of the NMOS transistor M1 is simultaneously connected to the first end of the switch K7 and the first end of the switch K8, and the drain of the NMOS transistor M2 is simultaneously connected to the first end of the switch K5 and the first end of the switch K6; the second end of the switch K8 and the second end of the switch K6 are commonly connected to the second end of the resistor R13, and the second end of the switch K7 and the second end of the switch K5 are commonly connected to the second end of the resistor R14; the control signals of the switches K5, K6, K7 and K8 are DP, DPB, DN and DNB respectively; Resistors R21~R27 are connected in series between the second end of resistor R11 and the second end of resistor R14, and the voltage between every two resistors is VRP6, VRP5, VRP4, VRP3, VRP2, and VRP1 respectively; resistors R31~R37 are connected in series between the second end of resistor R12 and the second end of resistor R13, and the voltage between every two resistors is VRM1, VRM2, VRM3, VRM4, VRM5, and VRM6 respectively.

[0021] When the dither function is not turned on, DP=0, DN=1, and the voltage and current equations can be easily derived: VRP6-VRM6=5Vref / 8, VRP5-VRM5=3Vref / 8, VRP4-VRM4=Vref / 8, VRP3-VRM3=-Vref / 8, VRP2-VRM2=-3Vref / 8, VRP1-VRM1=-5Vref / 8.

[0022] It can be seen that the result is Figure 4 The threshold voltage of the traditional structure remains the same and has not changed.

[0023] When DP=1, DN=0, it is easy to derive the voltage and current equations: VRP6-VRM6=4Vref / 8, VRP5-VRM5=2Vref / 8, VRP4-VRM4=0, VRP3-VRM3=-2Vref / 8, VRP2-VRM2=-4Vref / 8, VRP1-VRM1=-6Vref / 8.

[0024] It can be seen that the above threshold voltages are uniformly shifted by -Vref / 8.

[0025] When DP=0, DN=1, it is easy to derive the voltage and current equations: VRP6-VRM6=6Vref / 8, VRP5-VRM5=4Vref / 8, VRP4-VRM4=2Vref / 8, VRP3-VRM3=0, VRP2-VRM2=-2Vref / 8, VRP1-VRM1=-4Vref / 8.

[0026] It can be seen that the above threshold voltages are uniformly shifted by +Vref / 8.

[0027] It can be seen that the structure of the present invention can achieve the change of threshold voltage by controlling DP / DN. At the same time, the structure can achieve voltage change only by controlling the switch of the current mirror. The output voltage establishment speed does not depend on the switch on-resistance, so it can be used for high-speed ADC applications.

[0028] The reference voltage generating circuit provided by the present invention can adjust the threshold voltage range by expanding the current mirror, such as Figure 7 As shown, that is, Figure 6 The current mirror with M=1 on the right side is split into a set of small current mirrors with multi-bit binary weights, and their current switches are controlled by control signals of different weights, which is equivalent to becoming a current mirror digital-to-analog converter (IDAC). From left to right, DPn / DPn-1 / …DP1 / DP0 are binary control codes from high to low, corresponding to different current weights, and M=(2^n+2^(n-1)+...2+1)*2 must be ensured.

[0029] From this, we can see that the current mirror is split into proportional currents of different weights. The current ratio is controlled by switches of different weights, so that the threshold voltage can be finely changed within the range of -Vref / 8~+Vref / 8. At the same time, the pseudo-random code generator obtains the required current control signal. If the IDAC on the right is fully turned on, the maximum range of the adjustable threshold voltage is reached. If the threshold voltage jitter range is to be reduced, the corresponding weighted DPi / DNi is set to DPi=0, DNi=1 (i=0, 1,..., n), which corresponds to the equilibrium state of the bit current mirror and will not affect the threshold voltage. The state of each bit can be controlled by a digital circuit, and the range and precision of the threshold voltage that needs to be adjusted can be obtained very conveniently.

[0030] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A reference voltage generating circuit for generating high-speed random jitter, characterized in that: It includes comparators A1 and A2, PMOS tubes P1-P3, NMOS tubes N1-N3, switches K1-K8, resistors R11-R14, resistors R21-R27, and resistors R31-R37; The sources of the PMOS transistors P1, PMOS transistors P2 and PMOS transistors P3 are all connected to the power supply voltage VDD, and the gates of the three are all connected to the output end of the comparator A1. The positive input end of the comparator A1 is connected to the reference voltage VREFH, and the negative input end is connected to the drain of the PMOS transistor P3; the drain of the PMOS transistor P1 is simultaneously connected to the first end of the resistor R11 and the first end of the resistor R12, the drain of the PMOS transistor P2 is simultaneously connected to the first end of the switch K1 and the first end of the switch K2, and the drain of the PMOS transistor P3 is simultaneously connected to the first end of the switch K3 and the first end of the switch K4; the second end of the switch K1 and the second end of the switch K3 are commonly connected to the second end of the resistor R11, and the second end of the switch K2 and the second end of the switch K4 are commonly connected to the second end of the resistor R12; The sources of the NMOS transistors M1, M2 and M3 are all grounded, and the gates of the three are all connected to the output end of the comparator A2. The positive input end of the comparator A2 is connected to the reference voltage VREFL, and the negative input end is connected to the drain of the NMOS transistor M3; the drain of the NMOS transistor M3 is simultaneously connected to the first end of the resistor R13 and the first end of the resistor R14, the drain of the NMOS transistor M1 is simultaneously connected to the first end of the switch K7 and the first end of the switch K8, and the drain of the NMOS transistor M2 is simultaneously connected to the first end of the switch K5 and the first end of the switch K6; the second end of the switch K8 and the second end of the switch K6 are commonly connected to the second end of the resistor R13, and the second end of the switch K7 and the second end of the switch K5 are commonly connected to the second end of the resistor R14; The resistors R21 - R27 are sequentially connected in series between the second end of the resistor R11 and the second end of the resistor R14 ; the resistors R31 - R37 are sequentially connected in series between the second end of the resistor R12 and the second end of the resistor R13 .

2. The reference voltage generating circuit for generating high-speed random jitter according to claim 1, characterized in that: The reference voltage generating circuit adjusts the threshold voltage range by expanding the current mirror, splitting the current mirror composed of PMOS tubes P1 and P2 and the current mirror composed of NMOS tubes M1 and M2 into a set of small current mirrors with multi-bit binary weights, and controlling their current switches with control signals of different weights to control the current ratio, so that the threshold voltage can be finely changed within the range of -Vref / 8~+Vref / 8, and the required current control signal is obtained through the pseudo-random code generator.

3. The reference voltage generating circuit for generating high-speed random jitter according to claim 1, characterized in that: The control signals of the switches K1, K2, K3, and K4 are DPB, DP, DNB, and DN, respectively; the control signals of the switches K5, K6, K7, and K8 are DP, DPB, DN, and DNB, respectively; the control signals DPB and DNB are the reverse signals of DP and DN, respectively. When the control signal is 1, the switch is turned on, and when it is 0, the switch is turned off.

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