Current steering DAC circuit and electronic equipment

Abstract

The invention provides a current steering DAC circuit and electronic equipment, a current source array of the circuit sends differential current signals to a normal phase input end and an inverted phase input end of a fully differential transimpedance amplification module based on digital code control signals, and a common mode voltage adjusting end of the fully differential transimpedance amplification module receives set voltage. A normal phase input end and an inverted phase input end of the current translation module are respectively coupled to a normal phase output end and an inverted phase output end through a first resistor and a second resistor, and a first end and a second end of the current translation module are respectively coupled to the normal phase input end and the inverted phase input end. According to the invention, the first current and the second current received by the normal-phase input end and the inverted-phase input end are controlled to take 0 as the center, so that the minimum value of the voltage of the differential voltage signal output by the current-steering DAC is reduced; a differential voltage signal is output based on the voltage generated when the current of the differential current signal flows through the first resistor and the second resistor, and the maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a current steering DAC circuit and electronic equipment. Background Art

[0002] A digital to analog converter (DAC) is a signal converter that can convert digital signals into analog signals. A current steering digital to analog converter (CSDAC) is a commonly used digital to analog converter. Current steering DAC has the advantages of high matching accuracy, fast response speed and high energy utilization. Therefore, current steering DAC is widely used in the fields of computers, communications, audio and video processing, and measurement and control systems.

[0003] The maximum voltage of the differential voltage signal output by the traditional current steering DAC is V out_max =I max ×R L , where V out_max is the maximum value of the differential voltage signal, I max is the full bias current of the current source array, R L is the resistance value of the load.

[0004] It can be seen that the maximum value of the differential voltage signal output by the conventional current-steering DAC is limited by the full-bias current, while the minimum value of the differential voltage signal output by the conventional current-steering DAC is zero, which limits the voltage swing of the differential voltage signal output by the current-steering DAC.

[0005] Therefore, how to solve the technical problem that the voltage swing of the differential voltage signal output by the traditional current steering DAC is limited has become a technical problem that urgently needs to be solved in the industry. Summary of the invention

[0006] The present invention provides a current steering DAC circuit and electronic equipment thereof, aiming to solve the technical problem that the voltage swing of a differential voltage signal output by a current steering DAC is limited.

[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a current steering DAC circuit, comprising: a current source array, which is formed by N working units connected in parallel, N is an integer and N≥2, and each working unit comprises: a current source, a first differential switch and a second differential switch; wherein:

[0008] The first end of the current source receives a first voltage, the second end of the current source is coupled to the non-inverting input end and the inverting input end of the fully differential transimpedance amplifier module through the first differential switch and the second differential switch respectively, the control end of the first differential switch and the control end of the second differential switch both receive corresponding digital code control signals, the working unit controls the corresponding current source to connect to the non-inverting input end or the inverting input end based on the digital code control signal, the current source array sends differential current signals to the non-inverting input end and the inverting input end, and the differential current signals include a first differential current signal and a second differential current signal;

[0009] The fully differential transimpedance amplifier module, wherein a first resistor is connected between the non-phase input terminal and the non-phase output terminal thereof, a second resistor is connected between the inverting input terminal and the inverting output terminal thereof, and a common-mode voltage adjustment terminal thereof receives a set voltage. The fully differential transimpedance amplifier module is configured to output a differential voltage signal based on the voltage generated by the currents of the first differential current signal and the second differential current signal flowing through the first resistor and the second resistor, respectively, with the set voltage as the common-mode voltage. The differential voltage signal includes a first differential voltage signal and a second differential voltage signal;

[0010] A current shift module, wherein a first terminal and a second terminal are respectively coupled to the non-inverting input terminal and the inverting input terminal, and a third terminal is grounded;

[0011] The current shift module is used to control a first current of a first differential current signal received by the non-phase input terminal and a second current of a second differential current signal received by the inverting input terminal to be centered around 0.

[0012] Optionally, the current shift module includes: a first current source and a second current source;

[0013] The first end of the first current source is coupled to the non-inverting input end, the first end of the second current source is coupled to the inverting input end, and the second end of the first current source and the second end of the second current source are both grounded;

[0014] The currents provided by the first current source and the second current source are both 1 / 2 of the full bias current of the current source array.

[0015] Optionally, the first current source includes a first NMOS transistor and a second NMOS transistor; the second current source includes a third NMOS transistor and a fourth NMOS transistor;

[0016] The drain of the first NMOS tube is coupled to the non-inverting input terminal, the gate of the first NMOS tube receives a first bias voltage, the source of the first NMOS tube is coupled to the drain of the second NMOS tube, the gate of the second NMOS tube receives a second bias voltage, and the drain of the second NMOS tube is grounded;

[0017] The drain of the third NMOS tube is coupled to the inverting input terminal, the gate of the third NMOS tube receives the first bias voltage, the source of the third NMOS tube is coupled to the drain of the fourth NMOS tube, the gate of the third NMOS tube receives the second bias voltage, and the drain of the fourth NMOS tube is grounded;

[0018] The first current source is used to control the first current of the first differential current signal received by the non-phase input terminal to be centered at 0;

[0019] The second current source is used to control the second current of the second differential current signal received by the inverting input terminal to be centered around 0.

[0020] Optionally, the current source includes: a first PMOS tube and a second PMOS tube;

[0021] The source of the first PMOS tube receives a first voltage, the gate of the first PMOS tube receives a third bias voltage, the drain of the first PMOS tube is coupled to the source of the second PMOS tube, the gate of the second PMOS tube receives a fourth bias voltage, and the drain of the second PMOS tube is respectively coupled to the non-inverting input terminal and the inverting input terminal through the corresponding first differential switch and second differential switch.

[0022] Optionally, the magnitude of the current provided by each working unit of the current source array increases in sequence by a power of 2 from a low position to a high position.

[0023] Optionally, the current steering DAC circuit further includes a second decoding module;

[0024] The input end of the second decoding module receives a digital code signal, and the second decoding module is used to generate a digital code control signal required by each working unit based on the digital code signal.

[0025] Optionally, the current source array includes a high-order current source array and a low-order current source array, wherein 2 of the N working units are n - 1 of the working units as the high-level current source array, 2 m The working units are used as the low-order current source array, and n and m are both integers greater than or equal to 1;

[0026] The current provided by each working unit in the high-level current source array is the same in magnitude;

[0027] The current provided by each working unit in the low-order current source array increases in power of 2 from low to high, and the current provided by the highest-order working unit is 1 / 2 of the current provided by the current source in the high-order current source array.

[0028] Optionally, the digital code control signal includes a high-bit digital code control signal and a low-bit digital code control signal; the current steering DAC circuit also includes a first decoding module, the input end of the first decoding module receives the digital coding signal, and the first decoding module includes a high-bit decoding unit and a low-bit decoding unit;

[0029] The high-order decoding unit is used to generate a high-order digital code control signal required by each working unit in the high-order current source array based on the digital coding signal;

[0030] The low-bit decoding unit is used to generate a low-bit digital code control signal required by each working unit in the low-bit current source array based on the digital coding signal.

[0031] Optionally, the fully differential transimpedance amplifier module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first voltage-stabilizing resistor, and a second voltage-stabilizing resistor;

[0032] The sources of the first transistor, the second transistor, the third transistor and the fourth transistor all receive a power supply voltage, the gates of the first transistor, the second transistor, the third transistor and the fourth transistor all receive a bias voltage, the drain of the first transistor is coupled to the drain of the fifth transistor, the drain of the second transistor is coupled to the source of the sixth transistor and the source of the seventh transistor, the drain of the third transistor is coupled to the drain of the eighth transistor, the drain of the fourth transistor is coupled to the source of the ninth transistor and the source of the tenth transistor, the drain and gate of the fifth transistor are coupled to the drain of the sixth transistor and the drain of the eleventh transistor, the gate of the sixth transistor is the non-inverting input terminal, and is coupled to the non-inverting output terminal through the first resistor, and the gate of the seventh transistor is the inverting input terminal. The input terminal is coupled to the inverting output terminal through the second resistor, the drain of the seventh transistor and the drain of the twelfth transistor are both coupled to the gate of the eighth transistor, the gate of the ninth transistor is respectively coupled to the inverting output terminal and the positive output terminal through the first end of the first voltage-stabilizing resistor and the first end of the second voltage-stabilizing resistor, the second end of the first voltage-stabilizing resistor and the second end of the second voltage-stabilizing resistor, the drain of the ninth transistor is coupled to the drain and gate of the thirteenth transistor, the drain of the tenth transistor is coupled to the drain and gate of the fourteenth transistor, the gate of the tenth transistor is a common-mode adjustment terminal, the common-mode adjustment terminal receives the set voltage, and the sources of the fifth transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are all grounded.

[0033] According to a second aspect of the present invention, there is provided an electronic device, comprising the current-steering DAC circuit as described in any one of the first aspects.

[0034] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0035] In a current steering DAC circuit and electronic device provided by the present invention, the current source array in the circuit is formed by N working units connected in parallel, each working unit sends a first differential current signal and a second differential current signal to the positive input terminal and the negative input terminal of the full differential transimpedance amplifier module respectively, the common mode voltage adjustment terminal of the full differential transimpedance amplifier module receives a set voltage, and its positive input terminal and the negative input terminal are coupled to the positive output terminal and the negative output terminal through a first resistor and a second resistor respectively, and the first end and the second end of the current translation module are coupled to the positive input terminal and the negative input terminal respectively. The present invention reduces the minimum value of the voltage of the differential voltage signal output by the current steering DAC by controlling the first current and the second current received by the positive input terminal and the negative input terminal to be centered on 0 respectively. By taking the set voltage as the common mode voltage, the differential voltage signal is output based on the voltage generated by the current of the differential current signal flowing through the first resistor and the second resistor. The maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased. Therefore, the voltage swing of the differential voltage signal output by the current steering DAC is not limited by the full bias current of the current source array.

[0036] Furthermore, since the fully differential impedance amplifier module stabilizes the voltages of the non-phase input terminal and the inverting input terminal at a set voltage, when the working units in the current source array of the present invention receive different digital code control signals, the drain voltages of the PMOS tubes of the current sources are the same, thereby improving the stability of the current sources in the current source array and avoiding current errors in the differential current signals output by the current sources in the current source array. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 It is a schematic diagram of the structure of a traditional current steering DAC circuit;

[0039] Figure 2 It is a structural schematic diagram of a current steering DAC circuit in a first embodiment of the present invention;

[0040] Figure 3 It is a structural schematic diagram of a first decoding module in a first embodiment of the present invention;

[0041] Figure 4 Schematic diagram of the structure of the current steering DAC circuit in the second embodiment of the present invention;

[0042] Figure 5A schematic diagram of a second decoding structure in a second embodiment of the present invention;

[0043] Figure 6 is a schematic diagram of the structure of the current source in the current source array of the present invention;

[0044] Figure 7 It is a structural schematic diagram of a fully differential transimpedance amplifier module of the present invention;

[0045] Figure 8 This is a structural schematic diagram of a current shift module of the present invention;

[0046] Fig. 9 It is a structural schematic diagram of another current shift module of the present invention. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0050] As described in the background art, the present invention aims to solve the technical problem that the swing of the differential voltage output by the traditional current-steering DAC is limited, which will be described below with reference to the accompanying drawings.

[0051] For a conventional current-steering DAC, the maximum value of the differential voltage signal output by the conventional current-steering DAC is limited by the full-bias current, and the minimum value of the differential voltage output by the conventional current-steering DAC is zero, which limits the swing of the differential voltage output by the current-steering DAC.

[0052] Specifically, please refer to Figure 1 , Figure 1 A current steering DAC in the prior art is shown. In this embodiment, a method for increasing the maximum voltage of the differential voltage signal output by the conventional current steering DAC is to control the current of the differential current signal output by the current source array 100 to be greater than the full-bias current.

[0053] However, this method will cause the first PMOS transistor MP1 and the second PMOS transistor MP2 of the current source in the current source array 100 to enter the linear region, resulting in an error in the output current of the current source 1011, and further resulting in inaccurate output of the current steering DAC.

[0054] Moreover, this method can only increase the maximum value of the output voltage of the first differential voltage signal Vout_n and the second differential voltage signal Vout_p, but cannot reduce the minimum value of the output voltage of the first differential voltage signal Vout_n and the second differential voltage signal Vout_p.

[0055] It should be understood that Figure 1 R L1 is the first load, R L2 For the second load.

[0056] It can be seen that how to solve the technical problem that the swing of the differential voltage output by the traditional current-steering DAC is limited while taking into account the accurate output of the current-steering DAC has become a technical problem that urgently needs to be solved in the industry.

[0057] In view of this, the present invention proposes a current steering DAC circuit, comprising: a current source array sends a differential current signal to the positive input terminal and the negative input terminal of a fully differential transimpedance amplifier module based on a digital code control signal, the common mode voltage adjustment terminal of the fully differential transimpedance amplifier module receives a set voltage, the positive input terminal and the negative input terminal are respectively coupled to the positive output terminal and the negative output terminal through a first resistor and a second resistor, and the first terminal and the second terminal of the current shift module are respectively coupled to the positive input terminal and the negative input terminal. The present invention reduces the minimum value of the voltage of the differential voltage signal output by the current steering DAC by controlling the first current and the second current respectively received by the positive input terminal and the negative input terminal to be centered on 0. By taking the set voltage as the common mode voltage, the differential voltage signal is output based on the voltage generated by the current of the differential current signal flowing through the first resistor and the second resistor. The maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased. Thereby, the voltage swing of the differential voltage signal output by the current steering DAC is not limited by the full bias current of the current source array, and the output accuracy of the current steering DAC is taken into account.

[0058] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0059] According to an embodiment of the present invention, please refer to 2, the present invention provides a current steering DAC circuit, including:

[0060] The current source array 100 is formed by N working units 101 connected in parallel, where N is an integer and N≥2. Each working unit 110 includes: a current source 1011, a first differential switch S1 and a second differential switch S2; wherein:

[0061] The first end of the current source 1011 receives the first voltage V1, and the second end of the current source 1011 is coupled to the positive input end and the negative input end of the fully differential transimpedance amplifier module 200 through the first differential switch S1 and the second differential switch S2 respectively. The control end of the first differential switch S1 and the control end of the second differential switch S2 both receive the corresponding digital code control signal DSC. The working unit 101 controls the corresponding current source 1011 to connect to the positive input end or the negative input end based on the digital code control signal DSC. The current source array 100 sends a differential current signal to the positive input end and the negative input end, and the differential current signal includes a first differential current signal Iip and a second differential current signal Iin.

[0062] The fully differential transimpedance amplifier module 200, a first resistor R1 is connected between the non-phase input terminal and the non-phase output terminal thereof, a second resistor R2 is connected between the inverting input terminal and the inverting output terminal thereof, and a common-mode voltage adjustment terminal thereof receives a set voltage Vcm. The fully differential transimpedance amplifier module 200 is configured to output a differential voltage signal based on the voltage generated by the first differential current signal Iip and the second differential current signal Iin flowing through the first resistor R1 and the second resistor R2, respectively, with the set voltage Vcm as the common-mode voltage, and the differential voltage signal includes a first differential voltage signal Vout_n and a second differential voltage signal Vout_p;

[0063] A current shift module 300, wherein a first terminal and a second terminal are respectively coupled to the non-inverting input terminal and the inverting input terminal, and a third terminal is grounded GND;

[0064] The current shift module 300 is used to control a first current of the first differential current signal Iip received at the non-phase input terminal and a second current of the second differential current signal Iin received at the inverting input terminal to be centered around 0.

[0065] for Figure 2 The control end of the first differential switch S1 and the control end of the second differential switch S2 receive the digital code control signal DSC, Figure 2 Only the circuit structure of one working unit 101 in which the control end of the first differential switch S1 and the control end of the second differential switch S2 receive the digital code control signal DSC is shown. It should be understood that the structure of the other control ends of the first differential switch S1 and the control ends of the second differential switch S2 receiving the digital code control signal DSC is the same as that of the above-mentioned working unit 101.

[0066] In actual implementation, the first voltage V1 is used to provide a stable voltage to the first end of the current source 1011 in the current source array 100 , and those skilled in the art can select a suitable voltage as needed.

[0067] As an example, the set voltage Vcm is usually set to 1 / 2 of the first voltage. Of course, the present invention is not limited to this.

[0068] Now Figure 2 Based on this, the working principle of the present invention is further explained.

[0069] Since the current shift module 300 reduces the current of the first differential current signal Iip to 1 / 2 of the full bias current Imax of the current source array 100, the first current of the first differential current signal Iip is centered on 0, so that the voltage swing of the first differential voltage signal Vout_n outputted from the positive phase output terminal of the current steering DAC is shifted from 0 to Imax×R1.

[0070] At the same time, since the current shift module 300 reduces the current of the second differential current signal Iin by 1 / 2 of the full bias current Imax of the current source array 100, the second current of the second differential current signal Iin is centered around 0, so that the voltage swing of the first differential voltage signal Vout_p outputted from the inverting output terminal of the current steering DAC is shifted from 0 to Imax×R2.

[0071] It can be seen that the present invention reduces the minimum value of the voltage of the differential voltage signal output by the current steering DAC.

[0072] The full bias current is the maximum current that the current source array 100 can provide when all current sources 1011 in the current source array 100 ensure output accuracy and all output current to the non-inverting input terminal or all output current to the inverting input terminal.

[0073] Since the common mode voltage of the fully differential transresistance amplifier module 200 is the set voltage Vcm, based on the voltage generated by the first differential current signal Iip flowing through the first resistor R1, the voltage swing of the output first differential voltage signal Vout_n is

[0074]

[0075] At the same time, based on the voltage generated by the second differential current signal Iin flowing through the second resistor R2, the voltage swing of the output second differential voltage signal Vout_p is

[0076]

[0077] It can be seen that the maximum value of the voltage of the output differential voltage signal of the present invention only needs to increase the set voltage. Therefore, the present invention can also meet the application scenario where the voltage of the output differential voltage signal is large when the full bias current output by the current source array 100 is small.

[0078] In summary, the present invention reduces the minimum value of the voltage value of the differential voltage signal output by the current steering DAC by controlling the first current and the second current of the differential current signal received by the positive input terminal and the negative input terminal to be centered at 0. By setting the voltage as the common mode voltage, the differential voltage signal is output based on the voltage generated by the current of the differential current signal flowing through the first resistor and the second resistor. The maximum value of the voltage value of the differential voltage signal output by the current steering DAC is increased. As a result, the voltage swing of the differential voltage signal output by the current steering DAC is not limited by the full bias current of the current source array, and the accuracy of the current steering DAC output is taken into account.

[0079] It should be understood that the present invention does not limit the specific composition of the current source array 100 .

[0080] For a specific implementation, please continue to refer to Figure 2 The current magnitude provided by each working unit 101 of the current source array 100 increases in sequence by a power of 2 from a low position to a high position.

[0081] To control the current provided by each working unit 101, as a specific implementation method, please refer to Figure 3 , the current steering DAC circuit also includes a first decoding module 400;

[0082] The input end of the first decoding module 400 receives a digital code signal DS, and the first decoding module 400 is used to generate a digital code control signal DSC required by each working unit 101 based on the digital code signal DS.

[0083] Each working unit 101 is controlled by a corresponding digital code control signal DSC. The working unit 101 is configured to control a corresponding current source to be coupled to a non-inverting input terminal or an inverting input terminal based on the digital code control signal DSC.

[0084] Figure 3 The control end of the first differential switch S1 and the control end of the second differential switch S2 both receive the digital code control signal DSC sent by the first decoding module 400. Figure 3 Only the circuit structure of the control end of the first differential switch S1 and the control end of the second differential switch S2 in one working unit 101 receiving the digital code control signal DSC sent by the first decoding module 400 is shown. It should be understood that the structure of the control end of the other first differential switch S1 and the control end of the second differential switch S2 receiving the digital code control signal DSC sent by the first decoding module 400 is the same as that of the above-mentioned working unit 101.

[0085] As another specific implementation, please refer to Figure 4The current source array 100 includes a high-order current source array 110 and a low-order current source array 120, wherein there are 2 n - one of the working units 101 as the high-level current source array 110, 2 m The working units 101 are used as the low-order current source array 120, and n and m are both integers greater than or equal to 1;

[0086] The currents provided by the working units 101 in the high-order current source array 110 are of the same magnitude; the currents provided by the working units 101 in the low-order current source array 110 increase in order from low to high by powers of 2, and the current provided by the highest-order working unit 101 is 1 / 2 of the current provided by the current source 1011 in the high-order current source array 110.

[0087] in, Figure 4 The current source array 100 is Figure 2 Another implementation of the current source array 100. Of course, the present invention is not limited to this. The current source array 100 can also be a current source array 100 in which the currents output by the current sources 1011 in each working unit 101 are the same. Technicians in this field can select the appropriate type of current source array 100 as needed.

[0088] To control the current provided by each working unit 101, as a specific implementation method, please refer to Figure 5 The digital code control signal DSC includes a high-order digital code control signal DSC H And the low-order digital code control signal DSC H The current steering DAC circuit further includes a second decoding module 500, the input end of the second decoding module 500 receives the digital coding signal DS, and the second decoding module 500 includes a high-order decoding unit 501 and a low-order decoding unit 502;

[0089] The high-order decoding unit 501 is used to generate a high-order digital code control signal DSC required by each working unit 101 in the high-order current source array 110 based on the digital code signal DS. H ;

[0090] The low-bit decoding unit 502 is used to generate a low-bit digital code control signal DSC required by each working unit 101 in the low-bit current source array 120 based on the digital code signal DS. L .

[0091] Each working unit 101 in the high-order current source array 110 is controlled by a corresponding high-order digital code control signal DSC. HEach working unit 101 in the low-order current source array 120 is controlled by a corresponding low-order digital code control signal DSC L The working unit 101 is configured to: based on the high-bit digital code control signal DSC H Or the low-order digital code control signal DSC L , controlling the corresponding current source 1011 to be coupled to the non-inverting input terminal or the inverting input terminal.

[0092] Figure 5 The control end of the first differential switch S1 and the control end of the second differential switch S2 in the high-order current source array 110 both receive the high-order digital code control signal DSC sent by the high-order decoding unit 501. H The control end of the first differential switch S1 and the control end of the second differential switch S2 in the low-bit current source array 120 both receive the low-bit digital code control signal DSC sent by the low-bit decoding unit 502. L , Figure 5 Only the control end of the first differential switch S1 and the control end of the second differential switch S2 in one working unit 101 in the high-order current source array 110 receive the high-order digital code control signal DSC of the high-order decoding unit 501. H The circuit structure of the present invention is as follows: the control end of the first differential switch S1 and the control end of the second differential switch S2 in a working unit 101 in the low-order current source array 120 receive the low-order digital code control signal DSC of the low-order decoding unit 502. L It should be understood that in the high-order current source array 110, the control end of the other first differential switches S1 and the control end of one second differential switch S2 both receive the high-order digital code control signal DSC sent by the high-order decoding unit 501. H The control end of the other first differential switch S1 and the control end of the second differential switch S2 all receive the low-bit digital code control signal DSC sent by the low-bit decoding unit 502. L .

[0093] As a specific implementation method, please refer to Figure 6 , the current source 1011 includes: a first PMOS tube MP1 and a second PMOS tube MP2;

[0094] The source of the first PMOS tube MP1 receives the first voltage V1, the gate of the first PMOS tube MP1 receives the third bias voltage VBP, the drain of the first PMOS tube MP1 is coupled to the source of the second PMOS tube MP2, the gate of the second PMOS tube MP2 receives the fourth bias voltage VBP_CAS, and the drain of the second PMOS tube MP2 is respectively coupled to the non-inverting input terminal and the inverting input terminal through the corresponding first differential switch S1 and second differential switch S2.

[0095] The third bias voltage VBP and the fourth bias voltage VBP_CAS are in the range of 1V to 3V. It should be understood that the present invention is not limited thereto. The third bias voltage VBP and the fourth bias voltage VBP_CAS can turn on the first PMOS tube MP1 and the second PMOS tube MP2.

[0096] Because the current magnitudes of the first differential current signal Iip and the second differential current signal Iin sent by the current source array 100 to the positive input terminal and to the negative output terminal are different, the voltage magnitudes of the positive input terminal and the negative input terminal are different. Also, because when the digital coding signals DS of the digital code control signal DSC received by each working unit 101 are different, the input ports of the fully differential transimpedance amplifier module 200 that are turned on with the current source 1011 are different, and the input ports are the positive input terminal and the negative input terminal. Therefore, when the digital coding signals DS of the digital code control signal DSC received are different, the drain terminal voltages of the first PMOS tube MP1 and the second PMOS tube MP2 in each current source will change, causing an error in the current source 1011.

[0097] Therefore, as a preferred implementation, please refer to Figure 7 , the fully differential transimpedance amplifier module 200 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a first voltage-stabilizing resistor R3, and a second voltage-stabilizing resistor R4;

[0098] Sources of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 all receive a power supply voltage VDD, gates of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 all receive a bias voltage VB, a drain of the first transistor M1 is coupled to a drain of the fifth transistor M5, a drain of the second transistor M2 is coupled to a source of the sixth transistor M6 and a source of the seventh transistor M7, a drain of the third transistor M3 is coupled to a drain of the eighth transistor M8, a drain of the fourth transistor M4 is coupled to a source of the ninth transistor M9 and a source of the tenth transistor M10, a drain and a gate of the fifth transistor M5 are coupled to a drain of the sixth transistor M6 and a drain of the eleventh transistor M11, a gate of the sixth transistor M6 is the non-inverting input terminal, and is coupled to the non-inverting output terminal through the first resistor R1, and a gate of the seventh transistor M7 is a negative input terminal. The second resistor R2 is coupled to the inverting output terminal out2, the drain of the seventh transistor M7 and the drain of the twelfth transistor M12 are both coupled to the gate of the eighth transistor M8, the gate of the ninth transistor M9 is respectively coupled to the inverting output terminal out2 and the non-inverting output terminal through the first end of the first voltage-stabilizing resistor R3 and the first end of the second voltage-stabilizing resistor R4, the second end of the first voltage-stabilizing resistor R3 and the second end of the second voltage-stabilizing resistor R4, the drain of the ninth transistor M9 is coupled to the drain and gate of the thirteenth transistor M13, the drain of the tenth transistor M10 is coupled to the drain and gate of the fourteenth transistor M14, the gate of the tenth transistor M10 is a common-mode adjustment terminal, and the common-mode adjustment terminal receives the set voltage Vcm, and the sources of the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are all grounded GND.

[0099] As an example, the bias voltage VB and the power voltage VDD can turn on the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4. The present invention does not limit the power voltage VDD and the bias voltage VB.

[0100] The fully differential transimpedance amplifier module 200 controls the voltages of the non-inverting input terminal and the inverting input terminal to the set voltage Vcm, so that when the digital codes of the received digital code control signal DSC are different, the drain voltages of the first PMOS tube MP1 and the second PMOS tube MP2 in each current source 1011 are constant voltages. Thus, the size of the current source 1011 will not cause errors due to the difference in the digital code control signal DSC, thereby improving the dynamic performance of the current steering DAC.

[0101] It should be understood that Fig. 9 The structure of the fully differential transimpedance amplifier module 200 is only an example, and the present invention does not limit the specific structure of the fully differential transimpedance amplifier module 200.

[0102] The internal structure of the current shift module 300 is now further described.

[0103] Please refer to Figure 8 As an embodiment, the current shift module 300 includes: a first current source I1 and a second current source I2;

[0104] A first terminal of the first current source I1 is coupled to the non-inverting input terminal, a first terminal of the second current source I2 is coupled to the inverting input terminal, and a second terminal of the first current source I1 and a second terminal of the second current source I2 are both grounded GND;

[0105] The currents provided by the first current source I1 and the second current source I2 are both 1 / 2 of the full bias current of the current source array 100 .

[0106] As a specific example, please refer to Fig. 9 , the first current source I1 includes a first NMOS transistor MN1 and a second NMOS transistor MN2; the second current source I2 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4;

[0107] The drain of the first NMOS transistor MN1 is coupled to the non-inverting input terminal, the gate of the first NMOS transistor MN1 receives the first bias voltage VBN_CS, the source of the first NMOS transistor MN1 is coupled to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 receives the second bias voltage VBN, and the drain of the second NMOS transistor MN2 is grounded;

[0108] The drain of the third NMOS transistor MN3 is coupled to the inverting input terminal, the gate of the third NMOS transistor MN3 receives the first bias voltage VBN_CS, the source of the third NMOS transistor MN3 is coupled to the drain of the fourth NMOS transistor MN4, the gate of the third NMOS transistor MN3 receives the second bias voltage VBN, and the drain of the fourth NMOS transistor MN4 is grounded GND;

[0109] The first current source I1 is used to control the first current of the first differential current signal Iip received by the non-phase input terminal to be centered at 0;

[0110] The second current source I2 is used to control the second current of the second differential current signal Iin received by the inverting input terminal to be centered around 0.

[0111] As an example, the first bias voltage VBN_CS and the second bias voltage VBN may be sufficient to turn on the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.

[0112] In summary, the current steering DAC circuit provided by the present invention comprises: a current source array is formed by N working units connected in parallel, each working unit sends a first differential current signal and a second differential current signal to the positive input terminal and the negative input terminal of the full differential transimpedance amplifier module respectively, the common mode voltage adjustment terminal of the full differential transimpedance amplifier module receives a set voltage, and its positive input terminal and the negative input terminal are respectively coupled to the positive output terminal and the negative output terminal through the first resistor and the second resistor, and the first end and the second end of the current shift module are respectively coupled to the positive input terminal and the negative input terminal. The present invention reduces the minimum value of the voltage of the differential voltage signal output by the current steering DAC by controlling the first current and the second current of the differential current signal received by the positive input terminal and the negative input terminal to be centered at 0. By taking the set voltage as the common mode voltage, the differential voltage signal is output based on the voltage generated by the differential current signal flowing through the first resistor and the second resistor. The maximum value of the voltage of the differential voltage signal output by the current steering DAC is increased. Thus, the voltage swing of the differential voltage signal output by the current steering DAC is not limited by the full bias current of the current source array and the output accuracy of the current steering DAC is taken into account. The present invention also controls the voltage of the non-phase input terminal and the inverting input terminal to a set voltage, so that the size of the current source will not cause errors due to different digital code control signals, thereby improving the dynamic performance of the current steering DAC.

[0113] In addition, the present invention also provides an electronic device, comprising any of the current steering DAC circuits described above. As an example, the electronic device includes but is not limited to a camera, a mobile phone, an unmanned aerial vehicle, and the like.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A current steering DAC circuit, characterized in that: include: A current source array is formed by connecting N working units in parallel, where N is an integer and N≥2, and each working unit includes: a current source, a first differential switch, and a second differential switch; wherein: The first end of the current source receives a first voltage, the second end of the current source is coupled to the non-inverting input end and the inverting input end of the fully differential transimpedance amplifier module through the first differential switch and the second differential switch respectively, the control end of the first differential switch and the control end of the second differential switch both receive corresponding digital code control signals, the working unit controls the corresponding current source to connect to the non-inverting input end or the inverting input end based on the digital code control signal, the current source array sends differential current signals to the non-inverting input end and the inverting input end, and the differential current signals include a first differential current signal and a second differential current signal; The fully differential transimpedance amplifier module, wherein a first resistor is connected between the non-phase input terminal and the non-phase output terminal thereof, a second resistor is connected between the inverting input terminal and the inverting output terminal thereof, and a common-mode voltage adjustment terminal thereof receives a set voltage. The fully differential transimpedance amplifier module is configured to output a differential voltage signal based on the voltage generated by the currents of the first differential current signal and the second differential current signal flowing through the first resistor and the second resistor, respectively, with the set voltage as the common-mode voltage. The differential voltage signal includes a first differential voltage signal and a second differential voltage signal; A current shift module, wherein a first terminal and a second terminal are respectively coupled to the non-inverting input terminal and the inverting input terminal, and a third terminal is grounded; The current shift module is used to control a first current of a first differential current signal received by the non-phase input terminal and a second current of a second differential current signal received by the inverting input terminal to be centered around 0.

2. The current steering DAC circuit according to claim 1, characterized in that: The current shift module includes: a first current source and a second current source; The first terminal of the first current source is coupled to the non-inverting input terminal, the first terminal of the second current source is coupled to the inverting input terminal, and the second terminal of the first current source and the second terminal of the second current source are both grounded; The currents provided by the first current source and the second current source are both 1 / 2 of the full bias current of the current source array.

3. The current steering DAC circuit according to claim 2, characterized in that: The first current source includes a first NMOS tube and a second NMOS tube; the second current source includes a third NMOS tube and a fourth NMOS tube; The drain of the first NMOS tube is coupled to the non-inverting input terminal, the gate of the first NMOS tube receives a first bias voltage, the source of the first NMOS tube is coupled to the drain of the second NMOS tube, the gate of the second NMOS tube receives a second bias voltage, and the drain of the second NMOS tube is grounded; The drain of the third NMOS tube is coupled to the inverting input terminal, the gate of the third NMOS tube receives the first bias voltage, the source of the third NMOS tube is coupled to the drain of the fourth NMOS tube, the gate of the third NMOS tube receives the second bias voltage, and the drain of the fourth NMOS tube is grounded; The first current source is used to control the first current of the first differential current signal received by the non-phase input terminal to be centered at 0; The second current source is used to control the second current of the second differential current signal received by the inverting input terminal to be centered around 0.

4. The current steering DAC circuit according to claim 1, characterized in that: The current source includes: a first PMOS tube and a second PMOS tube; The source of the first PMOS tube receives a first voltage, the gate of the first PMOS tube receives a third bias voltage, the drain of the first PMOS tube is coupled to the source of the second PMOS tube, the gate of the second PMOS tube receives a fourth bias voltage, and the drain of the second PMOS tube is respectively coupled to the non-inverting input terminal and the inverting input terminal through the corresponding first differential switch and second differential switch.

5. The current steering DAC circuit according to claim 4, characterized in that: The magnitude of the current provided by each working unit of the current source array increases in power of 2 from low to high.

6. The current steering DAC circuit as claimed in claim 5, characterized in that: The current steering DAC circuit also includes a second decoding module; The input end of the second decoding module receives a digital code signal, and the second decoding module is used to generate a digital code control signal required by each working unit based on the digital code signal.

7. The current steering DAC circuit according to claim 4, characterized in that: The current source array includes a high-order current source array and a low-order current source array, wherein 2 of the N working units n - 1 of the working units as the high-level current source array, 2 m The working units are used as the low-order current source array, and n and m are both integers greater than or equal to 1; The current provided by each working unit in the high-level current source array is the same in magnitude; The current provided by each working unit in the low-order current source array increases in power of 2 from low to high, and the current provided by the highest-order working unit is 1 / 2 of the current provided by the current source in the high-order current source array.

8. The current steering DAC circuit as claimed in claim 7, characterized in that: The digital code control signal includes a high-bit digital code control signal and a low-bit digital code control signal; the current steering DAC circuit also includes a first decoding module, the input end of the first decoding module receives the digital coding signal, and the first decoding module includes a high-bit decoding unit and a low-bit decoding unit; The high-order decoding unit is used to generate a high-order digital code control signal required by each working unit in the high-order current source array based on the digital code signal; The low-bit decoding unit is used to generate a low-bit digital code control signal required by each working unit in the low-bit current source array based on the digital coding signal.

9. The current steering DAC circuit according to claim 1, characterized in that: The fully differential transimpedance amplifier module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first voltage-stabilizing resistor, and a second voltage-stabilizing resistor; The sources of the first transistor, the second transistor, the third transistor and the fourth transistor all receive a power supply voltage, the gates of the first transistor, the second transistor, the third transistor and the fourth transistor all receive a bias voltage, the drain of the first transistor is coupled to the drain of the fifth transistor, the drain of the second transistor is coupled to the source of the sixth transistor and the source of the seventh transistor, the drain of the third transistor is coupled to the drain of the eighth transistor, the drain of the fourth transistor is coupled to the source of the ninth transistor and the source of the tenth transistor, the drain and gate of the fifth transistor are coupled to the drain of the sixth transistor and the drain of the eleventh transistor, the gate of the sixth transistor is the non-inverting input terminal, and is coupled to the non-inverting output terminal through the first resistor, and the gate of the seventh transistor is the inverting input terminal. The input terminal is coupled to the inverting output terminal through the second resistor, the drain of the seventh transistor and the drain of the twelfth transistor are both coupled to the gate of the eighth transistor, the gate of the ninth transistor is respectively coupled to the inverting output terminal and the positive output terminal through the first end of the first voltage-stabilizing resistor and the first end of the second voltage-stabilizing resistor, the second end of the first voltage-stabilizing resistor and the second end of the second voltage-stabilizing resistor, the drain of the ninth transistor is coupled to the drain and gate of the thirteenth transistor, the drain of the tenth transistor is coupled to the drain and gate of the fourteenth transistor, the gate of the tenth transistor is a common-mode adjustment terminal, the common-mode adjustment terminal receives the set voltage, and the sources of the fifth transistor, the eighth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are all grounded.

10. An electronic device, characterized in that: A current steering DAC circuit comprising any one of claims 1-9.

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