Continuous time sigma-delta modulator without excessive loop delay compensation

Abstract

The invention discloses a continuous time sigma-delta modulator without excessive loop time delay compensation, an analog-to-digital conversion method, electronic equipment and a storage medium, and relates to the technical field of sigma-delta modulators. The structure comprises a single operational amplifier double second-order loop filter, a second-order continuous time noise shaping SAR quantizer, a segmented current control digital-to-analog converter and a direct current and alternating current coupling negative resistance module which are connected in sequence. According to the continuous time sigma-delta modulator without excessive loop time delay compensation, the continuous time successive approximation analog-to-digital converter is used as the quantizer, and the output delay of the quantizer is shortened to one SAR (Synthetic Aperture Radar) period, so that additional loop delay does not need to be compensated; meanwhile, the negative resistance technology of the direct current and alternating current coupling negative resistance module is used, the performance requirement for the operational amplifier of the loop filter is lowered on the basis of low energy consumption, and the bandwidth requirement for the operational amplifier of the loop filter is relieved.

Description

Technical Field

[0001] The present invention relates to the technical field of Σ-Δ modulators, and in particular to a continuous-time Σ-Δ modulator without excessive loop delay compensation, an analog-to-digital conversion method, an electronic device and a storage medium. Background Art

[0002] With the development of the Internet of Things, the demand for high-resolution, wide-bandwidth, and low-power analog-to-digital converters (ADCs) in system-on-chip (SOC) solutions continues to grow. In such applications, continuous-time Σ-Δ modulators (CT SDMs) are the first choice due to their inherent anti-aliasing capabilities and relatively high and constant input impedance characteristics, which simplifies the ADC driver design compared to their discrete-time (DT) counterparts. For medium-to-high bandwidth and energy-saving design goals, the oversampling rate (OSR) is usually limited. In order to obtain sufficient signal-to-noise quantization ratio (SQNR), CT SDMs using multi-bit quantizers (QTZ) and high-order loop filters have emerged.

[0003] The traditional architecture of CT SDM shortens the first pulse time of the loop sampling pulse due to the delay of its feedback path, and requires additional loop delay compensation (ELDC) before quantization to ensure system stability. The traditional ELDC is composed of ELD DAC and summing amplifier, which is implemented by adding the pulse input signal to the feedback loop through an adder with a certain gain, so it requires high energy consumption. In addition, there are some other delay compensation implementation methods to reduce power consumption. For example, in K.Xing's A10.4mW50MHz-BW 80dB-DR Single-Opamp Third-Order CT SDM withSAB-ELD-Merged Integrator and 3-Stage Opamp, ELDC is embedded in the integrator through an additional feedforward path, eliminating the direct feedback DAC and summing amplifier, but at the same time leads to the use of a higher specification high power integrator. Alternatively, in YSShu's A 28fJ / conv-step CTΔΣ modulator with 78dB DR and18MHzBW in 28nm CMOS using a highly digital multi-bit quantizer, it is mentioned that comparator switching technology is used to implement ELDC to reduce power consumption, but such a design will lead to an increase in circuit area and the manufacture of more output loads.

[0004] All of the above designs generate some amount of additional loop delay, so there is always a trade-off between integration time and loop delay during Σ-Δ modulation, which ultimately requires a larger bandwidth for the amplifier used for loop filtering. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a continuous-time Σ-Δ modulator without excessive loop delay compensation, an analog-to-digital conversion method, an electronic device and a storage medium, which does not require compensation for additional loop delay and can alleviate the bandwidth requirements of an operational amplifier.

[0006] On the one hand, a continuous-time Σ-Δ modulator without excessive loop delay compensation according to an embodiment of the present invention includes:

[0007] A single operational amplifier dual second-order loop filter, the input terminal of which is used to connect an analog input signal;

[0008] A second-order continuous-time noise shaping SAR quantizer, the input of which is electrically connected to the output of the single operational amplifier biquad loop filter;

[0009] a segmented current controlled digital-to-analog converter, the input of which is electrically connected to the output of the second-order continuous-time noise shaping SAR quantizer, and the output of which is electrically connected to the input of the single operational amplifier dual second-order loop filter;

[0010] a DC and AC coupled negative resistance module, the output end of which is electrically connected to the output end of the segmented current controlled digital-to-analog converter and the input end of the single operational amplifier dual second-order loop filter;

[0011] The analog input signal is subtracted from the output of the segmented current controlled digital-to-analog converter and then input into the single operational amplifier dual second-order loop filter, which is then integrated by the single operational amplifier dual second-order loop filter and then output to the second-order continuous-time noise shaping SAR quantizer. The second-order continuous-time noise shaping SAR quantizer outputs a digital code, and the digital code is fed back to the segmented current controlled digital-to-analog converter. The digital code is converted by the segmented current controlled digital-to-analog converter and then sent to the single operational amplifier dual second-order loop filter. The DC and AC coupled negative resistance module is used to provide additional current to compensate for the bandwidth of the operational amplifier of the single operational amplifier dual second-order loop filter.

[0012] According to some embodiments of the present invention, the single operational amplifier biquad loop filter comprises:

[0013] An operational amplifier, wherein the operational amplifier has a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal, the non-inverting input terminal and the inverting input terminal are respectively connected to the analog input signal through corresponding input resistors, the inverting output terminal is electrically connected to the non-inverting input terminal through a first capacitor and a first resistor connected in parallel, the inverting output terminal is electrically connected to the inverting input terminal through a second resistor and a second capacitor connected in series, the non-inverting output terminal is electrically connected to the inverting input terminal through a third capacitor and a third resistor connected in parallel, and the non-inverting output terminal is electrically connected to the non-inverting input terminal through a fourth resistor and a fourth capacitor connected in series.

[0014] According to some embodiments of the present invention, the second-order continuous-time noise shaping SAR quantizer comprises:

[0015] An input tracking and reset module, the input end of which is electrically connected to the output end of the single operational amplifier biquad loop filter;

[0016] A capacitive DAC, the input end of which is electrically connected to the output end of the input tracking and reset module;

[0017] A sequential residual extraction module, the input end of which is electrically connected to the output end of the capacitive DAC;

[0018] A passive integration and comparison module, the input end of which is electrically connected to the output end of the sequential residual extraction module, the output end of the passive integration and comparison module is used to output the digital code, and is electrically connected to the input end of the segmented current controlled digital-to-analog converter, and is electrically connected to the input end of the capacitive DAC.

[0019] According to some embodiments of the present invention, the sequential residual extraction module includes:

[0020] a first switch, wherein a first end of the first switch is electrically connected to an output end of the capacitive DAC;

[0021] a second switch, wherein a first end of the second switch is electrically connected to a second end of the first switch, and a second end of the second switch is electrically connected to an input end of the passive integration and comparison module;

[0022] a first residual extraction capacitor, wherein a first end of the first residual extraction capacitor is electrically connected to a second end of the first switch and a first end of the second switch, and a second end of the first residual extraction capacitor is grounded;

[0023] a third switch, wherein a first end of the third switch is electrically connected to an output end of the capacitive DAC;

[0024] a fourth switch, wherein a first end of the fourth switch is electrically connected to a second end of the third switch, and a second end of the fourth switch is electrically connected to an input end of the passive integration and comparison module;

[0025] A second residual extraction capacitor, wherein a first end of the second residual extraction capacitor is electrically connected to the second end of the third switch and the first end of the fourth switch, and a second end of the second residual extraction capacitor is grounded.

[0026] According to some embodiments of the present invention, the passive integration and comparison module comprises:

[0027] a multi-input comparator, wherein a first non-inverting input terminal of the multi-input comparator is electrically connected to an output terminal of the sequential residual extraction module, a second non-inverting input terminal of the multi-input comparator is electrically connected to an output terminal of the sequential residual extraction module through a fifth switch, a third non-inverting input terminal of the multi-input comparator is electrically connected to an output terminal of the sequential residual extraction module through a sixth switch, an inverting input terminal of the multi-input comparator is grounded, and an output terminal of the multi-input comparator is used to output the digital code, and is electrically connected to an input terminal of the segmented current control digital-to-analog converter, and is electrically connected to an input terminal of the capacitive DAC;

[0028] A first integrated capacitor, wherein a first terminal of the first integrated capacitor is electrically connected to a second non-inverting input terminal of the multi-input comparator, and a second terminal of the first integrated capacitor is grounded;

[0029] A second integrated capacitor, wherein a first terminal of the second integrated capacitor is electrically connected to the third non-inverting input terminal of the multi-input comparator, and a second terminal of the second integrated capacitor is grounded.

[0030] According to some embodiments of the present invention, the segmented current control digital-to-analog converter divides the m+n-bit digital-to-analog converter into an m-bit MSB module and an n-bit LSB module, and a redundant bit is provided between the MSB module and the LSB module, and the current mirror size of the MSB module is twice the current mirror size of the LSB module. n times, the MSB module is used to obtain the highest bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer, and the LSB module is used to obtain the lowest bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer, and m and n are both positive integers.

[0031] According to some embodiments of the present invention, the DC and AC coupling negative resistance module includes:

[0032] A first MOS transistor, wherein a gate of the first MOS transistor is connected to a first differential input signal;

[0033] a second MOS transistor, wherein a gate of the second MOS transistor is connected to the first differential input signal, a drain of the second MOS transistor is electrically connected to a source of the first MOS transistor, and both the drain of the second MOS transistor and the source of the first MOS transistor are connected to the first output port via a fifth capacitor;

[0034] a third MOS tube, wherein the gate of the third MOS tube is connected to the second differential input signal, the drain of the third MOS tube is electrically connected to the drain of the first MOS tube, and the drain of the third MOS tube and the drain of the first MOS tube are both connected to a power supply;

[0035] a fourth MOS transistor, wherein a gate of the fourth MOS transistor is connected to the second differential input signal, a drain of the fourth MOS transistor is electrically connected to a source of the third MOS transistor, and both the drain of the fourth MOS transistor and the source of the third MOS transistor are connected to a second output port through a sixth capacitor, and a source of the fourth MOS transistor is electrically connected to a source of the second MOS transistor, and both the source of the fourth MOS transistor and the source of the second MOS transistor are grounded;

[0036] The DC and AC coupled negative resistance module is electrically connected to the output end of the segmented current controlled digital-to-analog converter and the input end of the single operational amplifier dual second-order loop filter through the first output port and the second output port.

[0037] On the other hand, according to an analog-to-digital conversion method of an embodiment of the present invention, based on the continuous-time Σ-Δ modulator without excessive loop delay compensation described in the above-mentioned embodiment, the method includes:

[0038] After the analog input signal is subtracted from the output of the segmented current control digital-to-analog converter, the analog input signal is input to the single operational amplifier biquad loop filter for integration;

[0039] The single operational amplifier dual second-order loop filter outputs the integrated signal to the second-order continuous-time noise shaping SAR quantizer;

[0040] The second-order continuous-time noise shaping SAR quantizer performs analog-to-digital conversion on the integrated signal, outputs a digital code, and feeds the digital code back to the segmented current controlled digital-to-analog converter;

[0041] The segmented current control digital-to-analog converter obtains the digital code according to the highest bit and the lowest bit respectively, performs digital-to-analog conversion on the digital code, and outputs the converted analog signal;

[0042] The DC and AC coupling negative resistance module provides an additional current to compensate for the bandwidth of the operational amplifier of the single operational amplifier biquad loop filter, and the additional current is input into the single operational amplifier biquad loop filter together with the analog signal.

[0043] On the other hand, an electronic device according to an embodiment of the present invention includes:

[0044] A memory for storing program instructions;

[0045] The processor is used to call the program instructions stored in the memory and execute the analog-to-digital conversion method of the above-mentioned embodiment according to the obtained program instructions.

[0046] On the other hand, according to the storage medium of the embodiment of the present invention, the storage medium stores computer executable instructions, and the computer executable instructions are used to enable a computer to execute the analog-to-digital conversion method described in the embodiment of the above aspect.

[0047] According to the continuous-time Σ-Δ modulator without excessive loop delay compensation, analog-to-digital conversion method, electronic device and storage medium of the embodiment of the present invention, there are at least the following beneficial effects: the traditional Σ-Δ modulator generally uses a discrete-time SAR ADC as a quantizer, so the quantizer output delay needs to add the loop delay of the digital code bit SAR cycle, while the second-order continuous-time noise shaping SAR quantizer 200 used in the embodiment of the present invention can shorten its output delay to 1 SAR cycle, so there is no need to compensate for the additional loop delay, and there is no need to introduce ELDC. The present invention proposes a CT SDM without ELDC, using a continuous-time successive approximation analog-to-digital converter (SAR ADC) as a quantizer, shortening the output delay of the quantizer to 1 SAR cycle, so there is no need to compensate for the additional loop delay; at the same time, the negative resistance technology of the DC and AC coupled negative resistance module is used, which reduces the performance requirements of the operational amplifier of the loop filter on the basis of low energy consumption, so as to ease the bandwidth requirements of the operational amplifier of the loop filter.

[0048] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0050] Figure 1 Schematic diagram of the structure of a continuous-time Σ-Δ modulator without excessive loop delay compensation according to an embodiment of the present invention;

[0051] Figure 2 1 is a circuit schematic diagram of a single operational amplifier dual second-order loop filter according to an embodiment of the present invention;

[0052] Figure 3 It is a circuit schematic diagram of a second-order continuous-time noise shaping SAR quantizer according to an embodiment of the present invention;

[0053] Figure 4 It is a circuit principle diagram of a sequential residual extraction module and a passive integration and comparison module according to an embodiment of the present invention;

[0054] Figure 5 4 is a timing diagram of a second-order continuous-time noise shaping SAR quantizer according to an embodiment of the present invention.

[0055] Figure 6 This is the circuit schematic diagram of the DC negative resistance module;

[0056] Figure 7 is a circuit schematic diagram of a DC and AC coupled negative resistance module according to an embodiment of the present invention;

[0057] Figure 8 The figure is a flowchart of the steps of the analog-to-digital conversion method according to an embodiment of the present invention.

[0058] Reference numerals:

[0059] A single operational amplifier dual second-order loop filter 100, a second-order continuous-time noise shaping SAR quantizer 200, an input tracking and reset module 210, a capacitive DAC 220, a sequential residual extraction module 230, a passive integration and comparison module 240, a segmented current controlled digital-to-analog converter 300, an MSB module 310, an LSB module 320, and a DC and AC coupled negative resistance module 400. DETAILED DESCRIPTION

[0060] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0061] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0062] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0063] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0064] With the development of the Internet of Things, the demand for high-resolution, wide-bandwidth, and low-power analog-to-digital converters (ADCs) in system-on-chip (SOC) solutions continues to grow. In such applications, continuous-time Σ-Δ modulators (CT SDMs) are the first choice due to their inherent anti-aliasing capabilities and relatively high and constant input impedance characteristics, which simplifies the ADC driver design compared to their discrete-time (DT) counterparts. For medium-to-high bandwidth and energy-saving design goals, the oversampling rate (OSR) is usually limited. In order to obtain sufficient signal-to-noise quantization ratio (SQNR), CT SDMs using multi-bit quantizers (QTZ) and high-order loop filters have emerged.

[0065] The traditional architecture of CT SDM shortens the first pulse time of the loop sampling pulse due to the delay of its feedback path, and requires additional loop delay compensation (ELDC) before quantization to ensure system stability. The traditional ELDC is composed of ELD DAC and summing amplifier, which is implemented by adding the pulse input signal to the feedback loop through an adder with a certain gain, so it requires high energy consumption. In addition, there are some other delay compensation implementation methods to reduce power consumption. For example, in K.Xing's A10.4mW50MHz-BW 80dB-DR Single-Opamp Third-Order CT SDM withSAB-ELD-Merged Integrator and 3-Stage Opamp, ELDC is embedded in the integrator through an additional feedforward path, eliminating the direct feedback DAC and summing amplifier, but at the same time leads to the use of a higher specification high power integrator. Alternatively, in YSShu's A 28fJ / conv-step CTΔΣ modulator with 78dB DR and18MHzBW in 28nm CMOS using a highly digital multi-bit quantizer, it is mentioned that comparator switching technology is used to implement ELDC to reduce power consumption, but such a design will lead to an increase in circuit area and the manufacture of more output loads.

[0066] All of the above designs generate some amount of additional loop delay, so there is always a trade-off between integration time and loop delay during Σ-Δ modulation, which ultimately requires a larger bandwidth for the amplifier used for loop filtering.

[0067] In order to solve the above problems, the embodiments of the present invention provide a continuous-time Σ-Δ modulator, an analog-to-digital conversion method, an electronic device and a storage medium without excessive loop delay compensation, using a continuous-time successive approximation analog-to-digital converter (SAR ADC) as a quantizer to shorten the output delay of the quantizer to 1 SAR cycle, so there is no need to compensate for the additional loop delay; at the same time, the negative resistance technology of the DC and AC coupled negative resistance module is used to reduce the performance requirements of the operational amplifier of the loop filter on the basis of low energy consumption, so as to alleviate the bandwidth requirements of the operational amplifier of the loop filter.

[0068] The following describes in detail a continuous-time Σ-Δ modulator without excessive loop delay compensation, an analog-to-digital conversion method, an electronic device, and a storage medium according to an embodiment of the present invention in conjunction with the accompanying drawings.

[0069] On the one hand, if Figure 1As shown, the continuous-time Σ-Δ modulator without excessive loop delay compensation according to an embodiment of the present invention includes a single operational amplifier dual second-order loop filter 100, a second-order continuous-time noise shaping SAR quantizer 200 (SAR: Successive Approximation Register, successive approximation analog-to-digital converter), segmented current controlled digital-to-analog converter 300 and DC and AC coupled negative resistance module 400; wherein, the input end of the single operational amplifier dual second-order loop filter 100 is used to connect the analog input signal, and the output end of the single operational amplifier dual second-order loop filter 100 is electrically connected to the input end of the second-order continuous-time noise shaping SAR quantizer 200; the output end of the second-order continuous-time noise shaping SAR quantizer 200 is electrically connected to the input end of the segmented current controlled digital-to-analog converter 300, and the output end of the segmented current controlled digital-to-analog converter 300 is electrically connected to the input end of the single operational amplifier dual second-order loop filter 100; the output end of the DC and AC coupled negative resistance module 400 is electrically connected to the output end of the segmented current controlled digital-to-analog converter 300 and the input end of the single operational amplifier dual second-order loop filter 100;

[0070] The analog input signal is subtracted from the output of the segmented current controlled digital-to-analog converter 300 and then input into the single operational amplifier dual second-order loop filter 100. After being integrated by the single operational amplifier dual second-order loop filter 100, the analog input signal is output to the second-order continuous-time noise shaping SAR quantizer 200. The second-order continuous-time noise shaping SAR quantizer 200 outputs a digital code and feeds the digital code back to the segmented current controlled digital-to-analog converter 300. The digital code is converted by the segmented current controlled digital-to-analog converter 300 and then sent to the single operational amplifier dual second-order loop filter 100. The DC and AC coupled negative resistance module 400 connected to the output end of the segmented current controlled digital-to-analog converter 300 is used to provide additional current to compensate for the bandwidth of the single operational amplifier dual second-order loop filter 100.

[0071] Traditional Σ-Δ modulators generally use discrete-time SAR ADC as quantizers. Therefore, the output delay of the quantizer needs to be added with the loop delay of the digital code bit number of SAR cycles. The second-order continuous-time noise shaping SAR quantizer 200 used in the embodiment of the present invention can shorten its output delay to 1 SAR cycle, so there is no need to compensate for the additional loop delay, and there is no need to introduce ELDC. The present invention proposes a CT SDM without ELDC, using a continuous-time successive approximation analog-to-digital converter (SAR ADC) as a quantizer to shorten the output delay of the quantizer to 1 SAR cycle, so there is no need to compensate for the additional loop delay; at the same time, the negative resistance technology of the DC and AC coupled negative resistance module is used to reduce the performance requirements of the operational amplifier of the loop filter on the basis of low energy consumption, so as to ease the bandwidth requirements of the operational amplifier of the loop filter. In addition, the present technology is combined with the second-order passive noise shaping technology, and the second-order continuous-time noise shaping SAR ADC as a quantizer can further reduce the ELD sensitivity of the modulator while reducing the number of operational amplifiers.

[0072] In some embodiments of the present invention, the single-amplifier biquad loop filter 100 includes a SAB integrator (SAB: Single-amplifier biquad, a single-amplifier biquad integrator is an operational amplifier consisting of a single amplifier and a capacitor-resistor network, having two poles and two zeros. By connecting the operational amplifiers in an integrator manner, an integrator with the same frequency response can be obtained), such as Figure 2 As shown, the SAB integrator includes an operational amplifier U1, which has a non-inverting input terminal (port 1), an inverting input terminal (port 2), a non-inverting output terminal (port 3), and an inverting output terminal (port 4). The non-inverting input terminal and the inverting input terminal are connected through corresponding input resistors (R p / R n ) connects the analog input signal (V I+ / V I- ), the inverting output terminal is connected in parallel with the first capacitor C p2 and the first resistor R p2 The inverting output terminal is electrically connected to the non-inverting input terminal and connected in series with the second resistor R p3 and the second capacitor C p3 The inverting input terminal is electrically connected to the inverting input terminal, and the non-inverting output terminal is connected in parallel to the third capacitor C p4 and the third resistor R p4 The inverting input terminal is electrically connected, and the non-inverting output terminal is connected in series with a fourth resistor R p1 and the fourth capacitor C p1 Electrically connected to the non-inverting input terminal.

[0073] The single operational amplifier dual second-order loop filter 100 is used to integrate the signal obtained by subtracting the analog input signal from the output of the segmented current control digital-to-analog converter 300, and at the same time, Figure 2 G f The DC and AC coupled negative resistance module 400 is used to provide an additional compensation current to compensate for the limited bandwidth of the operational amplifier U1 of the single operational amplifier biquad loop filter 100 .

[0074] like Figure 3 As shown, in some embodiments of the present invention, the second-order continuous-time noise shaping SAR quantizer 200 includes an input tracking and reset module 210, a capacitive DAC 220, a sequential residual extraction module 230 and a passive integration and comparison module 240, wherein the input end of the input tracking and reset module 210 is electrically connected to the output end of the single operational amplifier dual second-order loop filter 100, the output end of the input tracking and reset module 210 is electrically connected to the input end of the capacitive DAC 220, the output end of the capacitive DAC 220 is electrically connected to the input end of the sequential residual extraction module 230, the output end of the sequential residual extraction module 230 is electrically connected to the input end of the passive integration and comparison module 240, and the output end of the passive integration and comparison module 240 is used to output a digital code, and is electrically connected to the input end of the segmented current control digital-to-analog converter 300, and is electrically connected to the input end of the capacitive DAC 220.

[0075] The input tracking and reset module 210 performs input tracking and reset on the signal inputted by the single operational amplifier dual second-order loop filter 100 through the input capacitor and a set of switches. During input tracking, the input signal is directly connected to the switch capacitor array of the capacitive DAC 220 behind through the input capacitor. During reset, the connection between the input signal and the input capacitor is disconnected, and the top plate and the bottom plate of the input capacitor are short-circuited to the same potential. The capacitive DAC 220 is used to perform digital-to-analog conversion on the signal outputted by the input tracking and reset module 210.

[0076] like Figure 4 As shown, in some embodiments of the present invention, the sequential residual extraction module 230 includes a first switch S a , the second switch S b , the first residual extraction capacitor C c1 , the third switch S c , the fourth switch S d and the second residual extraction capacitor C c2 , the first switch S a The first end of the first switch S is electrically connected to the output end of the capacitive DAC 220. a The second end of the second switch S b The first end of the second switch Sb The second end of is electrically connected to the input end of the passive integration and comparison module 240, and the first residual extraction capacitor C c1 The first end of the first switch S a The second end and the second switch S b The first end is electrically connected to the first residual extraction capacitor C c1 The second end of the third switch S is grounded; c The first end of the third switch S is electrically connected to the output end of the capacitive DAC 220. c The second end of the fourth switch S d The first end of the fourth switch S is electrically connected to d The second end of is electrically connected to the input end of the passive integration and comparison module 240, and the second residual extraction capacitor C c2 The first end of the third switch S c The second end and the fourth switch S d The first end is electrically connected to the second residual extraction capacitor C c2 The second end of the first switch S is grounded. a and the fourth switch S d Residual reset signal Control, second switch S b and the third switch S c Residual reset signal control.

[0077] like Figure 4 As shown, in some embodiments of the present invention, the passive integration and comparison module 240 includes a multi-input comparator U2, a first integrated capacitor C j1 and the second integrated capacitor C j2 The first non-inverting input terminal (the first port) of the multi-input comparator U2 is electrically connected to the output terminal of the sequential residual extraction module 230, and the second non-inverting input terminal (the second port) of the multi-input comparator U2 is electrically connected to the output terminal of the sequential residual extraction module 230 through the fifth switch S e The third non-inverting input terminal (the third port) of the multi-input comparator U2 is electrically connected to the output terminal of the sequential residual extraction module 230, and the third non-inverting input terminal (the third port) of the multi-input comparator U2 is connected to the output terminal of the sequential residual extraction module 230 through the sixth switch S f The output terminal of the multi-input comparator U2 is electrically connected to the output terminal of the capacitive DAC 220, the inverting input terminal (the fourth port) of the multi-input comparator U2 is grounded, the output terminal of the multi-input comparator U2 is used to output the digital code, and is electrically connected to the input terminal of the segmented current control digital-to-analog converter 300, and is electrically connected to the input terminal of the capacitive DAC 220; the first integrated capacitor C j1 The first end of the first integrated capacitor C is electrically connected to the second non-inverting input terminal of the multi-input comparator U2. j1 The second end of the integrated capacitor C j2 The first end of the second integrated capacitor C is electrically connected to the third non-inverting input terminal of the multi-input comparator U2.j2 The second end is grounded.

[0078] The specific working process of the second-order continuous-time noise shaping SAR quantizer according to the embodiment of the present invention can be described as follows: During the reset period, the top plate and the bottom plate of the input capacitor of the input tracking and reset module 210 are reset to the required input common mode voltage, and under the control of the reset clock, the residual extraction capacitor (C c1 , C c2 ) are connected to the capacitive DAC220 (CDAC) and reset, and there is also a capacitor C j1 and C j2 Used to integrate signals. During reset, these groups of capacitors are integrated through the multi-input comparator U2. The weight of the input end of the multi-input comparator U2 can be adjusted according to the needs of the circuit. The conversion of the capacitor top plate of the capacitive DAC220 is controlled by the reset signal. When the reset signal is low, the conversion starts, and the input signal Vin enters the capacitive DAC220. At the same time, the multi-input comparator U2 is controlled by the comparator clock and gives a digital code output according to the SAR timing based on the input and integration results. Since the conversion is performed when the input on the capacitive DAC220 changes, it is necessary to insert redundant bits in the quantizer to ensure that the ADC can correctly follow the input signal. Among them, the first residual extraction capacitor C c1 and the second residual extraction capacitor C c2 The output of the capacitive DAC 220 and the subsequent passive integration and comparison module 240 are connected alternately. In each alternating sampling period, the capacitor C j1 With C j2 will be connected to the first residual extraction capacitor C in sequence c1 and the second residual extraction capacitor C c2 , and the capacitance is allocated according to the different capacitance ratios. The working sequence of the second-order continuous-time noise shaping SAR quantizer 200 is as follows: Figure 5 shown.

[0079] like Figure 1 As shown, in some embodiments of the present invention, the segmented current control digital-to-analog converter 300 divides the m+n-bit digital-to-analog converter into an m-bit MSB module 310 and an n-bit LSB module 320, and a redundant bit is set between the MSB module 310 and the LSB module 320, and the current mirror size of the MSB module 310 is twice the current mirror size of the LSB module 320. n The MSB module 310 is used to obtain the highest bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer 200, and the LSB module 320 is used to obtain the lowest bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer 200, where m and n are both positive integers. The redundant bits are used to compensate for the error of the second-order continuous-time noise shaping SAR quantizer 200.

[0080] like Figure 5 The DC negative resistance module shown is a circuit in which the current decreases as the input voltage increases. The specific implementation is based on an inverter. As the input voltage increases linearly, the inverter current will first increase and then decrease. Taking the second half as the working range of the negative resistance circuit, a negative differential resistance circuit can be obtained. For an inverter in general, the negative differential resistance circuit only has negative resistance characteristics in DC, and by adding a capacitor at the output end, such as Figure 6 As shown, the AC signal can also be coupled out, and this circuit is considered a DC and AC coupled negative resistance circuit. Figure 6 As shown, in some embodiments of the present invention, the DC and AC coupling negative resistance module 400 includes a first MOS transistor S11, a second MOS transistor S12, a third MOS transistor S13 and a fourth MOS transistor S14; the gate of the first MOS transistor S11 and the gate of the second MOS transistor S12 are both connected to the first differential input signal V GP , the drain of the first MOS tube S11 is electrically connected to the drain of the third MOS tube S13, and the drain of the third MOS tube S13 and the drain of the first MOS tube S11 are both connected to the power supply VDD; the source of the first MOS tube S11 is electrically connected to the drain of the second MOS tube S12, and the drain of the second MOS tube S12 and the source of the first MOS tube S11 are both connected to the first output port through the fifth capacitor C5; the gate of the third MOS tube S13 and the gate of the fourth MOS tube S14 are both connected to the second differential input signal V GN , the source of the third MOS tube S13 is electrically connected to the drain of the fourth MOS tube S14, and the drain of the fourth MOS tube S14 and the source of the third MOS tube S13 are connected to the second output port through the sixth capacitor C6, the source of the fourth MOS tube S14 is electrically connected to the source of the second MOS tube S12, and the source of the fourth MOS tube S14 and the source of the second MOS tube S12 are grounded; the source of the first MOS tube S11 and the source of the third MOS tube S13 are connected to the bias voltage V BP The DC and AC coupling negative resistance module 400 is electrically connected to the output end of the segmented current control digital-to-analog converter 300 and the input end of the single operational amplifier dual second-order loop filter 100 through the first output port and the second output port. The DC and AC coupling negative resistance module 400 is used to provide an additional current I COM , compensating for the limited bandwidth of the operational amplifier U1 used in the single operational amplifier biquad loop filter 100.

[0081] The present invention proposes a fourth-order continuous-time Σ-Δ modulator that uses a second-order continuous-time noise shaping SAR quantizer 200 and does not require additional time delay compensation. By using the proposed second-order continuous-time noise shaping SAR quantizer 200 with second-order passive integration, the power consumption is effectively reduced. At the same time, the negative resistance technology of the DC and AC coupled negative resistance module 400 is used to reduce the performance requirements of the operational amplifier of the single operational amplifier dual second-order loop filter 100 on the basis of low energy consumption. The ADC designed by the present invention has been verified by tape-out, and finally achieved an SNDR (signal-to-noise-distortion ratio) of 75.5db and a Schreyer quality factor of up to 174.1dB at a bandwidth of 20MHz.

[0082] On the other hand, based on the continuous-time Σ-Δ modulator without excessive loop delay compensation of the above-mentioned embodiment, the present invention also proposes an analog-to-digital conversion method, such as Figure 8 As shown, the method comprises the following steps:

[0083] Step S100: After the analog input signal is subtracted from the output of the segmented current control digital-to-analog converter 300, the analog input signal is input to the single operational amplifier biquad loop filter 100 for integration;

[0084] Step S200: the single operational amplifier dual second-order loop filter 100 outputs the integrated signal to the second-order continuous-time noise shaping SAR quantizer 200;

[0085] Step S300: the second-order continuous-time noise shaping SAR quantizer 200 performs analog-to-digital conversion on the integrated signal, outputs a digital code, and feeds the digital code back to the segmented current control digital-to-analog converter 300;

[0086] Step S400: the segmented current control digital-to-analog converter 300 obtains the digital code according to the highest bit and the lowest bit respectively, performs digital-to-analog conversion on the digital code, and outputs the converted analog signal;

[0087] Step S500 : the DC and AC coupling negative resistance module 400 provides an additional current to compensate for the bandwidth of the operational amplifier of the single operational amplifier biquad loop filter 100 , and the additional current is input to the single operational amplifier biquad loop filter 100 together with the analog signal.

[0088] It should be noted that the contents of the above method embodiments are all applicable to the present system embodiments, the functions specifically implemented by the present system embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0089] On the other hand, an embodiment of the present invention further provides an electronic device, including:

[0090] A memory for storing program instructions;

[0091] The processor is used to call the program instructions stored in the memory and execute the above-mentioned analog-to-digital conversion method according to the obtained program instructions.

[0092] The processor may be implemented by a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0093] The memory can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory, and the processor calls and executes the analog-to-digital conversion method of the embodiment of the present application; the memory and the processor can be connected through a bus or the like.

[0094] On the other hand, an embodiment of the present invention further provides a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the above-mentioned analog-to-digital conversion is realized.

[0095] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and are implemented to be located in one place, or may also be distributed to multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0096] Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any of the functions and / or processing capabilities described in conjunction with a particular device or component may be performed by any other device or component. In addition, although various exemplary implementations and architectures have been described according to embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0097] Some aspects of the present disclosure are described above with reference to the block diagram and flow chart of the system, method, system and / or computer program product according to the exemplary embodiments.It should be understood that the combination of one or more blocks in the block diagram and the flow chart and the blocks in the block diagram and the flow chart can be realized by executing computer executable program instructions respectively.Equally, according to some embodiments, some blocks in the block diagram and the flow chart may not need to be executed in the order shown, or may not need to be executed in full.In addition, additional components and / or operations beyond those components and / or operations shown in the blocks in the block diagram and the flow chart may be present in certain embodiments.

[0098] Therefore, the blocks in the block diagrams and flow charts support the combination of devices for performing the specified functions, the combination of elements or steps for performing the specified functions, and the program instruction devices for performing the specified functions. It should also be understood that each block in the block diagrams and flow charts and the combination of blocks in the block diagrams and flow charts can be implemented by a special-purpose hardware computer system or a combination of special-purpose hardware and computer instructions that performs a specific function, element or step.

[0099] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the illustrative methods described herein) to be performed.

[0100] Software components can be encoded with any of various programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or an operating system platform. The software component comprising assembly language instructions may need to be converted to executable machine code by an assembler before being executed by hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be transplanted across multiple architectures. The software component comprising a higher-level programming language may need to be converted to an intermediate representation by an interpreter or a compiler before execution. Other examples of programming languages ​​include but are not limited to macro languages, shells or command languages, job control languages, scripting languages, database queries or search languages ​​or report writing languages. In one or more exemplary embodiments, the software component comprising the instruction of one of the above-mentioned programming language examples can be directly executed by an operating system or other software components, without first being converted into another form.

[0101] Software components may be stored as files or other data storage structures. Software components of similar type or related functions may be stored together, such as in a specific directory, folder, or library. Software components may be static (e.g., preset or fixed) or dynamic (e.g., created or modified at execution time).

[0102] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. A continuous-time Σ-Δ modulator without excessive loop delay compensation, characterized in that: include: A single operational amplifier dual second-order loop filter, the input terminal of which is used to connect the analog input signal; a second-order continuous-time noise shaping SAR quantizer, the input of which is electrically connected to the output of the single operational amplifier biquad loop filter; a segmented current controlled digital-to-analog converter, the input of which is electrically connected to the output of the second-order continuous-time noise shaping SAR quantizer, the output of which is electrically connected to the input of the single operational amplifier biquad loop filter; a DC and AC coupled negative resistance module, the output end of which is electrically connected to the output end of the segmented current controlled digital-to-analog converter and the input end of the single operational amplifier biquad loop filter; The analog input signal is subtracted from the output of the segmented current-controlled digital-to-analog converter and then input into the single-op-amp biquad loop filter. The analog input signal is then integrated by the single-op-amp biquad loop filter and then output to the second-order continuous-time noise-shaping SAR quantizer. The second-order continuous-time noise-shaping SAR quantizer outputs a digital code, which is fed back to the segmented current-controlled digital-to-analog converter. The segmented current-controlled digital-to-analog converter performs digital-to-analog conversion on the digital code and then sends it to the single-op-amp biquad loop filter. The DC and AC coupled negative resistance module is used to provide additional current to compensate for the bandwidth of the operational amplifier of the single-op-amp biquad loop filter.

2. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 1, wherein: The single operational amplifier biquad loop filter comprises: An operational amplifier, the operational amplifier having a non-inverting input terminal, an inverting input terminal, a non-inverting output terminal and an inverting output terminal, the non-inverting input terminal and the inverting input terminal are respectively connected to the analog input signal through corresponding input resistors, the inverting output terminal is electrically connected to the non-inverting input terminal through a first capacitor and a first resistor connected in parallel, the inverting output terminal is electrically connected to the inverting input terminal through a second resistor and a second capacitor connected in series, the non-inverting output terminal is electrically connected to the inverting input terminal through a third capacitor and a third resistor connected in parallel, and the non-inverting output terminal is electrically connected to the non-inverting input terminal through a fourth resistor and a fourth capacitor connected in series.

3. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 1, wherein: The second-order continuous-time noise shaping SAR quantizer comprises: an input tracking and reset module, the input end of which is electrically connected to the output end of the single operational amplifier biquad loop filter; a capacitive DAC, an input end of which is electrically connected to an output end of the input tracking and reset module; a sequential residual extraction module, an input end of which is electrically connected to an output end of the capacitive DAC; A passive integration and comparison module, the input end of which is electrically connected to the output end of the sequential residual extraction module, the output end of the passive integration and comparison module is used to output the digital code, and is electrically connected to the input end of the segmented current control digital-to-analog converter, and is electrically connected to the input end of the capacitive DAC.

4. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 3, wherein: The sequential residual extraction module includes: a first switch, wherein a first end of the first switch is electrically connected to an output end of the capacitive DAC; a second switch, wherein a first end of the second switch is electrically connected to a second end of the first switch, and a second end of the second switch is electrically connected to an input end of the passive integration and comparison module; a first residual extraction capacitor, wherein a first end of the first residual extraction capacitor is electrically connected to the second end of the first switch and the first end of the second switch, and a second end of the first residual extraction capacitor is grounded; a third switch, wherein a first end of the third switch is electrically connected to an output end of the capacitive DAC; a fourth switch, wherein a first end of the fourth switch is electrically connected to a second end of the third switch, and a second end of the fourth switch is electrically connected to an input end of the passive integration and comparison module; A second residual extraction capacitor, wherein a first end of the second residual extraction capacitor is electrically connected to the second end of the third switch and the first end of the fourth switch, and a second end of the second residual extraction capacitor is grounded.

5. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 3, wherein: The passive integration and comparison module includes: a multi-input comparator, wherein a first non-inverting input terminal of the multi-input comparator is electrically connected to the output terminal of the sequential residual extraction module, a second non-inverting input terminal of the multi-input comparator is electrically connected to the output terminal of the sequential residual extraction module via a fifth switch, a third non-inverting input terminal of the multi-input comparator is electrically connected to the output terminal of the sequential residual extraction module via a sixth switch, an inverting input terminal of the multi-input comparator is grounded, and an output terminal of the multi-input comparator is used to output the digital code and is electrically connected to the input terminal of the segmented current control digital-to-analog converter and the input terminal of the capacitive DAC; a first integrated capacitor, wherein a first terminal of the first integrated capacitor is electrically connected to the second non-inverting input terminal of the multi-input comparator, and a second terminal of the first integrated capacitor is grounded; A second integrated capacitor, wherein a first terminal of the second integrated capacitor is electrically connected to the third non-inverting input terminal of the multi-input comparator, and a second terminal of the second integrated capacitor is grounded.

6. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 1, wherein: The segmented current control digital-to-analog converter divides the m+n-bit digital-to-analog converter into an m-bit MSB module and an n-bit LSB module, and a redundant bit is set between the MSB module and the LSB module. The current mirror size of the MSB module is twice the current mirror size of the LSB module. n times, the MSB module is used to obtain the most significant bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer, and the LSB module is used to obtain the least significant bit of the digital code output by the second-order continuous-time noise shaping SAR quantizer, where m and n are both positive integers.

7. The continuous-time Σ-Δ modulator without excessive loop delay compensation according to claim 1, wherein: The DC and AC coupled negative resistance module includes: a first MOS transistor, wherein a gate of the first MOS transistor is connected to a first differential input signal; a second MOS transistor, wherein a gate of the second MOS transistor is connected to the first differential input signal, a drain of the second MOS transistor is electrically connected to the source of the first MOS transistor, and both the drain of the second MOS transistor and the source of the first MOS transistor are connected to the first output port via a fifth capacitor; a third MOS transistor, wherein a gate of the third MOS transistor is connected to the second differential input signal, a drain of the third MOS transistor is electrically connected to the drain of the first MOS transistor, and both the drain of the third MOS transistor and the drain of the first MOS transistor are connected to a power supply; a fourth MOS transistor, wherein a gate of the fourth MOS transistor is connected to the second differential input signal, a drain of the fourth MOS transistor is electrically connected to the source of the third MOS transistor, and the drain of the fourth MOS transistor and the source of the third MOS transistor are both connected to the second output port via a sixth capacitor, and a source of the fourth MOS transistor is electrically connected to the source of the second MOS transistor, and the source of the fourth MOS transistor and the source of the second MOS transistor are both grounded; The DC and AC coupled negative resistance module is electrically connected to the output end of the segmented current controlled digital-to-analog converter and the input end of the single operational amplifier biquad loop filter through the first output port and the second output port.

8. An analog-to-digital conversion method, characterized in that: Based on the continuous-time Σ-Δ modulator without excessive loop delay compensation according to any one of claims 1 to 7, the method comprises: After the analog input signal is subtracted from the output of the segmented current control digital-to-analog converter, the analog input signal is input into the single operational amplifier biquad loop filter for integration; The single operational amplifier biquad loop filter outputs the integrated signal to the second-order continuous-time noise shaping SAR quantizer; The second-order continuous-time noise shaping SAR quantizer performs analog-to-digital conversion on the integrated signal, outputs a digital code, and feeds the digital code back to the segmented current control digital-to-analog converter; The segmented current control digital-to-analog converter obtains the digital code according to the highest bit and the lowest bit respectively, performs digital-to-analog conversion on the digital code, and outputs the converted analog signal; The DC and AC coupled negative resistance module provides an additional current to compensate for the bandwidth of the operational amplifier of the single operational amplifier biquad loop filter. The additional current is input to the single operational amplifier biquad loop filter together with the analog signal.

9. An electronic device, characterized in that: include: a memory for storing program instructions; A processor is used to call the program instructions stored in the memory and execute the analog-to-digital conversion method according to claim 8 according to the obtained program instructions.

10. A storage medium, characterized in that: The storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the analog-to-digital conversion method according to claim 8.

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