Turbo code decoder adopting new architecture, decoding method and Beidou receiver

Abstract

The invention relates to a Turbo code decoder adopting a new architecture, a Turbo code decoding method and a Beidou receiver. The decoder comprises a first interleaver, a second interleaver, a third interleaver and a fourth interleaver, wherein the first interleaver carries out interleaving processing on input system bit soft information and outputs the system bit soft information; the second interleaver performs interleaving processing on the L12 information output by the first decoder and outputs the L12 information; the de-interleaver is used for carrying out de-interleaving processing on the L21 information output by the second decoder and outputting the L21 information; the second decoder calculates L21 information and LLR information according to the system bit soft information, the L12 information and the check bit 2 soft information; the first decoder calculates L12 information according to the input soft information of the check bit 1, the soft information of the system bit and the de-interleaved L21 information; and the judgment module judges the LLR information meeting the iteration stopping condition and outputs a Turbo code decoding result. According to the invention, a new decoder architecture is adopted, the operation time is shortened, and the decoding efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of decoding and satellite navigation, and in particular to a Turbo code decoder, a decoding method and a Beidou receiver adopting a new architecture. Background Art

[0002] Turbo code is a channel error correction coding scheme that can approach the Shannon limit. Many communication systems, such as speech coding and decoding, 3G and 4G mobile communication systems supported by 3GPP, use Turbo code as their channel coding scheme. In recent years, with the popularity of LDPC code and Polar code, 5G NR uses LDPC code and Polar code as its channel coding scheme. However, many communication systems, especially some satellite communication systems, such as the RDSS subsystem in China's Beidou Satellite Navigation System BDS, still use the Turbo code coding scheme due to the good performance of the Turbo code scheme.

[0003] However, the decoder architecture of the traditional Turbo code is relatively complex. For example, after the last iterative processing, in order to output the hard-decision system bits, after the internal operation of sub-decoder 2 is completed, a deinterleaving operation is still required, which is unnecessary and also prolongs the module operation time of the decoder. Summary of the invention

[0004] In view of the above analysis, the present invention aims to disclose a Turbo code decoder, decoding method and Beidou receiver adopting a new architecture, improve the decoder architecture to solve the module operation time problem of traditional Turbo codes and improve decoding efficiency.

[0005] On one hand, the present invention discloses a Turbo code decoder using a new architecture, which is used to decode coded information that does not contain tail bits, and includes: a first decoder, a second decoder, a first interleaver, a second interleaver, a deinterleaver and a decision module; A first interleaver, configured to perform interleaving processing on input system bit soft information and output the interleaved system bit soft information; A second interleaver, used for interleaving the L12 information output by the first decoder, and outputting the interleaved L12 information; A deinterleaver, configured to perform deinterleaving processing on the L21 information output by the second decoder, and output the deinterleaved L21 information; A second decoder is used to calculate L21 information and LLR information according to the interleaved system bit soft information, L12 information, and check bit 2 soft information; A first decoder, configured to calculate L12 information based on the input check bit 1 soft information, the system bit soft information and the deinterleaved L21 information; The decision module is used to decide the LLR information that meets the conditions for stopping iteration and output the Turbo code decoding result.

[0006] Another aspect of the present invention further discloses a decoding method based on the Turbo code decoder adopting the new architecture as described above, comprising the following steps: Step S1, obtaining soft information corresponding to the system bit, check bits 1 and 2; setting the number of decoding iterations; Step S2, interleaving the system bit soft information, and sending the output result of the interleaver to the second decoder; Step S3, executing the operation of the second decoder; inputting the check bit 2 soft information, the interleaved system bit soft information and the interleaved L12 information sent from the first decoder into the second decoder to calculate and output the external information L21 information sent to the deinterleaver; the initial value of the L21 information is an all-0 sequence; Step S4, executing the operation of the first decoder; inputting the check bit 1 soft information, the system bit soft information and the deinterleaved L21 information into the first decoder to calculate and output the external information L12 information sent to the second interleaver, and the LLR information; the LLR information corresponds to the system bit; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the LLR information output by the first decoder, and output a Turbo code decoding result.

[0007] Another aspect of the present invention discloses another Turbo code decoder using a new architecture, which is used to decode coded information including tail bits, comprising: It includes: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision module; wherein the first and second decoders are tail bit subdecoders; A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision module is used to decide the first LLR information that meets the iteration stop condition and output the Turbo code decoding result.

[0008] Another aspect of the present invention further discloses a decoding method based on another Turbo code decoder adopting a new architecture as described above, comprising the following steps: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; inputting the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then outputting the L21 information including the tail bit; Step S4, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; inputting the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then outputting the L12 information including the tail bit; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the first LLR information output by the first decoder to output a Turbo code decoding result.

[0009] On the other hand, the present invention also discloses a Beidou receiver, which receives the RDSS subsystem signal in the Beidou satellite navigation system BDS. When performing Turbo code decoding, a Turbo code decoder with a new architecture as described above is used to decode the encoded information that does not contain tail bits; or, a Turbo code decoder with another new architecture as described above is used to decode the encoded information that contains tail bits.

[0010] The present invention can achieve one of the following beneficial effects: The Turbo code decoder, decoding method and Beidou receiver with a new architecture disclosed in the present invention adopt a new decoder architecture to decode the coded information not containing tail bits, and avoid the redundant operation of the deinterleaver before the decision module by adjusting the processing order of two sub-decoders, the first decoder and the second decoder, thereby reducing the execution time and improving the processing efficiency.

[0011] A new decoder architecture is adopted to decode the coded information containing tail bits. By adjusting the processing order of the two sub-decoders, the first decoder and the second decoder, the redundant operation of the deinterleaver is avoided before the decision module, the execution time is reduced, and the processing efficiency is improved. The tail bit information of the Turbo code is used for decoding, which improves the performance of the decoder. It is suitable for reliable data transmission under low signal-to-noise ratio (SNR) conditions, and the decoding accuracy can be gradually improved through iteration. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components; Figure 1 Schematic diagram of a coding scheme of a Turbo code in an embodiment of the present invention; Figure 2 is a diagram of the encoder architecture of a commonly used Turbo code listed in an embodiment of the present invention; Figure 3 A schematic diagram of the connection components of a Turbo code decoder using a new architecture in an embodiment of the present invention; Figure 4 is a flow chart of a decoding method of a Turbo code decoder using a new architecture in an embodiment of the present invention; Figure 5 A schematic diagram of coding of a Turbo code used in a CDMA2000 system in an embodiment of the present invention; Figure 6 is a schematic diagram of a signal processing structure of a sub-encoder in an embodiment of the present invention; Figure 7 A schematic diagram of the connection components of another Turbo code decoder using a new architecture in an embodiment of the present invention; Figure 8 This is a flow chart of another decoding method of a Turbo code decoder using a new architecture in an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used to illustrate the principles of the present invention together with the embodiments of the present invention.

[0014] Embodiment 1 An embodiment of the present invention discloses a Turbo code decoder using a new architecture, which is used to decode coded information that does not contain tail bits.

[0015] like Figure 1 As shown in FIG. 1 , the coding scheme of the Turbo code corresponding to the decoder of this embodiment mainly includes two sub-encoders, an interleaver, and a rate matching module. The rate matching module mainly performs the puncturing function, which punctures some check bits or repeated system bits to meet the requirements of the transmission data rate. We usually use Figure 2 The upper sub-encoder is called sub-encoder 1, and the lower sub-encoder is called sub-encoder 2. The structures of the two sub-encoders are the same, and they also output systematic bits and check bits, so the structures of their corresponding sub-decoders are also the same. The difference from sub-encoder 1 is that the input bits of sub-encoder 2 are interleaved.

[0016] It should be pointed out that in the solution of the embodiment of the present invention, rate matching is not the focus, and therefore, the rate matching solution submodule is not involved.

[0017] like Figure 2 The following is a commonly used Turbo code encoder architecture; the sub-decoder 1 corresponds to Figure 1 Sub-encoder 1 and sub-decoder 2 in Figure 2 Subcoder 2 in; Interleaver scheme and Figure 1 The scheme of the interleaver in is consistent; the deinterleaver corresponds to Figure 1 The interleaver in is the reverse process.

[0018] Figure 2 middle, The check bit 1 soft information refers to the soft information corresponding to the check bit of sub-decoder 1, and may include multiple parallel check bits; System bit soft information refers to the bits that have the same value as the input bits of the sub-encoder; The check bit 2 soft information refers to the soft information corresponding to the check bit of sub-decoder 2; Soft information can generally be represented by the log-likelihood ratio (LLR); L12 refers to external information transmitted from sub-decoder 1 to sub-decoder 2. Similarly, L21 refers to external information transmitted from sub-decoder 2 to sub-decoder 1.

[0019] Figure 2 The sub-decoder 2 in outputs two types of information, one is external information, and the other is LLR information corresponding to the system bit.

[0020] During the decoding process, the external information to be transmitted and the soft information corresponding to the system bit are output after grid reasoning and calculation according to the processing order of sub-decoder 1 first and then sub-decoder 2, and then processed by the interleaver and deinterleaver. The external information is iteratively transmitted between the two sub-decoders. After multiple iterations, the LLR information output by sub-decoder 2 is interleaved and hard-determined to obtain the output bits of the decoder.

[0021] After analyzing the traditional Turbo code decoder architecture, the following conclusions are drawn: The decoder architecture of the traditional Turbo code is partially unreasonable and has high complexity. For example, after the last iteration, in order to output the hard-decision system bits, the deinterleaving operation is still required after the internal operation of the sub-decoder 2 is completed, which is unnecessary and prolongs the module operation time of the decoder.

[0022] In view of the technical problems of the traditional Turbo code decoder architecture, this embodiment proposes a Turbo code decoder with a new architecture, such as Figure 3 As shown, including: A first decoder, a second decoder, a first interleaver, a second interleaver, a deinterleaver and a decision module; A first interleaver, configured to perform interleaving processing on input system bit soft information and output the interleaved system bit soft information; A second interleaver, used for interleaving the L12 information output by the first decoder, and outputting the interleaved L12 information; A deinterleaver, configured to perform deinterleaving processing on the L21 information output by the second decoder, and output the deinterleaved L21 information; A second decoder is used to calculate L21 information and LLR information according to the interleaved system bit soft information, L12 information, and check bit 2 soft information; A first decoder, configured to calculate L12 information based on the input check bit 1 soft information, the system bit soft information and the deinterleaved L21 information; The decision module is used to decide the LLR information that meets the iteration stop condition and output the Turbo code decoding result.

[0023] Specifically, the length of the input information of the first and second decoders is the same as the length K of the encoded input data block; the first and second decoders use decoding algorithms including the log-map algorithm and the max-log-map algorithm, and the operation cycle is K times, and the first decoder outputs the LLR information; During the decoding process, the decoding operation of the second decoder is first performed to obtain L21 information; the L21 information is deinterleaved in the deinterleaver and then input into the first decoder for decoding operation to obtain L12 information; the decoding operation of the second decoder is performed again; the process is iterated in this way until the maximum number of iterations is met; the decision module makes a decision on the LLR information output by the first decoder and outputs the Turbo code decoding result.

[0024] In this embodiment, the LLR output of the first decoder can be directly output as the output bit of the entire decoder through the decision module; and there is no need for further deinterleaving as in the traditional decoding architecture.

[0025] Therefore, in the decoder architecture of this embodiment, by adjusting the processing order of the first decoder and the second sub-decoder, it is avoided that the redundant operation of the deinterleaver needs to be performed before the decision module, which reduces the execution time and improves the processing efficiency.

[0026] Furthermore, it can be additionally pointed out that external information such as L12 information is also obtained by LLR calculation. In fact, it can be considered that the decoder only outputs one LLR item. If external information is needed, the calculation steps from LLR information to external information are executed.

[0027] Embodiment 2 This embodiment discloses a decoding method using the Turbo code decoder with a new architecture disclosed in the first embodiment, such as Figure 4 As shown, the following steps are included: Step S1, obtaining soft information corresponding to the system bit, check bits 1 and 2; setting the number of decoding iterations; Step S2, interleaving the system bit soft information, and sending the output result of the interleaver to the second decoder; Step S3, executing the operation of the second decoder; inputting the check bit 2 soft information, the interleaved system bit soft information and the interleaved L12 information sent from the first decoder into the second decoder to calculate and output the external information L21 information sent to the deinterleaver; the initial value of the L21 information is an all-0 sequence; Step S4, executing the operation of the first decoder; inputting the check bit 1 soft information, the system bit soft information and the deinterleaved L21 information into the first decoder to calculate and output the external information L12 information sent to the second interleaver, and the LLR information; the LLR information corresponds to the system bit; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the LLR information output by the first decoder, and output a Turbo code decoding result.

[0028] The specific technical details and beneficial effects of this embodiment are the same as those described in Embodiment 1. Please refer to them for details and will not be described in detail here.

[0029] Embodiment 3 An embodiment of the present invention discloses a Turbo code decoder using a new architecture, which is used to decode coded information including tail bits.

[0030] like Figure 5 The Turbo code used in the CDMA2000 system shown in the figure; for each information bit input, each sub-encoder of the encoder outputs 3 bits, X, Y, Z, where X is a systematic bit, and Y and Z are parity bits. The systematic bit is the same bit as the input bit of the sub-encoder; but the X bit sequence may include tail bits in addition to the bit sequence input by the sub-encoder.

[0031] The signal processing structure of the two sub-encoders is the same, please refer to Figure 6 .

[0032] like Figure 6 As shown, for each input bit I, the sub-encoder outputs three bits X, Y, and Z. Assuming that the length of each information data block, i.e., the sequence of the encoded input bit I, is K, then Figure 1 and Figure 2 The length of the interleaver in is also K, but due to the tail bit encoding mechanism, the lengths of the three output sequences X, Y and Z of the sub-encoder are all K+T. Here, the length of the tail bit sequence corresponding to each output bit sequence is T (e.g. Figure 2 T=3).

[0033] One more thing to note is that before each block of data is Turbo-coded, Figure 3 The initial values ​​of the three registers in are set to 0.

[0034] Specifically, Figure 6 For example, in the tail bit generation scheme, when a sequence of bit I is input, that is, when the first K bits are input, the switch branch is closed with the upper branch for encoding, and three output bit sequences X, Y and Z of length K are generated respectively; then, the switch branch is switched to the lower branch and closed with the lower branch, and the sub-encoder continues to operate, generating three tail bit sequences of length T (here T=3) respectively, and appending them to the X, Y and Z sequences respectively. In the end, the lengths of the X, Y and Z sequences are all K+T, that is, they are all K+3 bits. The role of the tail bit is to finally return the grid of the sub-encoder to zero, which is conducive to the correct decoding of the receiver. Therefore, the tail bit sequence also carries useful information that cannot be ignored.

[0035] For decoding of coded information including tail bits, this embodiment proposes a Turbo code decoder using a new architecture, such as Figure 7 As shown, including: It includes: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision module; wherein the first and second decoders are tail bit subdecoders; A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision module is used to decide the first LLR information that meets the iteration stop condition and output the Turbo code decoding result.

[0036] Specifically, the first and second decoders are tail bit subdecoders; the length of the input information of the tail bit subdecoder is K+T; K is the length of the encoded input data block, and T is the data length of the tail bit; the tail bit subdecoder adopts a decoding algorithm including a log-map algorithm and a max-log-map algorithm, and operates K+T times to obtain the LLR information of the decoded output; During the decoding process, the second decoder is first decoded to obtain L21 information; the L21 information is input into the first decoder for decoding to obtain L12 information; the second decoder is decoded again; the process is repeated in this manner until the maximum number of iterations is met; the decision module makes a decision on the LLR information output by the first decoder and outputs a Turbo code decoding result.

[0037] Specifically, the input information of the first decoder in this embodiment is the parity bit 1 soft information including the tail bit, L21 information and the first system bit soft information of length K+T; Among them, the check bit 1 soft information and the first system bit soft information are information for decoding transmitted by the system; the L21 information is external information with a length of K+T calculated by the L21 calculation module; The input information of the second bit sub-decoder in this embodiment is K+T including the soft information of the check bit 2 of the tail bit, the L12 information; and the second system bit soft information of the tail bit soft information after the information before the tail bit is interleaved and spliced; Among them, the check bit 2 soft information is the information for decoding transmitted by the system; the L12 information is the external information with a length of K+T calculated by the L12 calculation module; The solution of this embodiment also includes: further including: a first interleaver and a splicer, used to generate second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

[0038] Specifically, the L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The calculation method of the external information is: ; Among them, LLR ext1 is the external information output by the first external information calculation module in the current calculation, LLR 1 is the first LLR information output by the first decoder, LLR sys1 is the first systematic bit soft information of the first decoder input, LLR a1 is the external information input by the first decoder; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

[0039] Specifically, the L21 calculation module includes a second external information calculation module, a deinterleaver and a second zero-padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The calculation method of the external information is: ; Among them, LLR ext2 is the external information output by the second external information calculation module in the current calculation, LLR 2 is the second LLR information output by the second decoder, LLR sys2 is the second systematic bit soft information of the second decoder input, LLR a2 is the external information input by the second decoder; The deinterleaver is a K-bit deinterleaver, used to deinterleave the external data with a length of K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

[0040] The purpose of the calculation formula of the external information is to remove the influence of the prior information and the system bit soft information in the LLR information output by the first and second decoders, so as to obtain pure external information. This part of information will be passed to the next sub-decoder to improve the performance of the entire Turbo decoding process.

[0041] The input end of the decision module is connected to the output end of the first decoder, and the decision module outputs a Turbo code decoding result based on the first LLR information that meets the iteration stop condition; The condition for stopping iteration is that the iteration reaches a preset maximum number of iterations.

[0042] In the decoding operation of the tail bit sub-decoder of the present embodiment, the input data length is K+T, so the operation cycles in the tail bit sub-decoder are K+T times, instead of K cycles of the traditional sub-decoder; Referring to the max-log-map decoding algorithm, the tail bit decoder needs to perform the following operations: 1) Initialize variables; variables include branch metric values, forward state metric values, backward state metric values, and output LLR values, all of which are initialized to zero vectors; 2) Perform backward iteration: perform K+T bit-by-bit calculations on the input information from back to front to obtain the branch metric gamma and the backward state metric beta; Among them, the initial value of the backward state metric value utilizes the grid 0 state information brought by the tail bit; 3) Perform forward iteration; calculate the input information bit by bit from front to back to obtain the branch metric value gamma and the forward state metric value alpha; Among them, the initial value of the forward state metric value uses the state information that the initial value of the encoder register is 0; 4) Calculate the output LLR information; The LLR information is calculated using the forward state metric alpha and the backward state metric beta.

[0043] During the operation, the calculation methods of the branch metric value gamma, the backward state metric value beta, the forward state metric value alpha and the LLR information may all refer to the existing calculation methods.

[0044] In summary, the tail bit decoding device of the Turbo code disclosed in this embodiment uses the tail bit information of the Turbo code for decoding, thereby improving the performance of the decoder; it is suitable for realizing reliable data transmission under low signal-to-noise ratio (SNR) conditions, and can gradually improve the decoding accuracy through iteration; and, by adopting a new decoder architecture, by adjusting the processing order of the two sub-decoders, the first decoder and the second decoder, it avoids the need to perform redundant operations of the deinterleaver before the decision module, thereby reducing the execution time and improving the processing efficiency.

[0045] Embodiment 4 Another embodiment of the present invention discloses a decoding method using the Turbo code decoder with a new architecture disclosed in the third embodiment, such as Figure 8 As shown, the following steps are included: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; inputting the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then outputting the L21 information including the tail bit; Step S4, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; inputting the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then outputting the L12 information including the tail bit; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the first LLR information output by the first decoder to output a Turbo code decoding result.

[0046] Specifically, the external information calculation method in the L12 calculation module and the L21 calculation module is: ; Among them, LLR ext1 , LLR ext2 They are the external information of L12 and L21 calculation modules in the current calculation, LLR 1 , LLR 2 The first and second LLR information output by the first and second decoders are LLR sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

[0047] The specific technical details and beneficial effects of this embodiment are the same as those described in Embodiment 1. Please refer to them for details and will not be described in detail here.

[0048] Embodiment 5 Another embodiment of the present invention discloses a BeiDou receiver; the BeiDou receiver receives the RDSS subsystem signal in the BeiDou satellite navigation system BDS, and when performing Turbo code decoding, the Turbo code decoder with a new architecture in the first embodiment is used to decode the coded information that does not contain tail bits; or the Turbo code decoder with a new architecture in the third embodiment is used to decode the coded information that contains tail bits. The decoding performance is improved and the decoding efficiency is increased.

[0049] The specific technical details and beneficial effects of this embodiment are the same as those described in the previous embodiments. Please refer to them for details and will not be described in detail here.

[0050] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A Turbo code decoder using a new architecture for decoding coded information excluding tail bits, characterized in that: include: A first decoder, a second decoder, a first interleaver, a second interleaver, a deinterleaver and a decision module; A first interleaver, configured to perform interleaving processing on input system bit soft information and output the interleaved system bit soft information; A second interleaver, used for interleaving the L12 information output by the first decoder, and outputting the interleaved L12 information; A deinterleaver, configured to perform deinterleaving processing on the L21 information output by the second decoder, and output the deinterleaved L21 information; A second decoder is used to calculate L21 information and LLR information according to the interleaved system bit soft information, L12 information, and check bit 2 soft information; A first decoder, configured to calculate L12 information based on the input check bit 1 soft information, the system bit soft information and the deinterleaved L21 information; The decision module is used to decide the LLR information that meets the conditions for stopping iteration and output the Turbo code decoding result.

2. The Turbo code decoder using a new architecture according to claim 1, characterized in that: The length of the input information of the first and second decoders is the same as the length K of the coded input data block; the first and second decoders use decoding algorithms including log-map algorithm and max-log-map algorithm, and the operation cycle is K times, and the first decoder outputs LLR information; In the decoding process, the decoding operation of the second decoder is first performed to obtain the L21 information; After deinterleaving the L21 information in the deinterleaver, the information is input into the first decoder for decoding to obtain the L12 information; the decoding operation of the second decoder is performed again; the process is iterated in this way until the maximum number of iterations is met; the decision module makes a decision on the LLR information output by the first decoder and outputs the Turbo code decoding result.

3. A decoding method based on a Turbo code decoder using a new architecture as claimed in any one of claims 1 to 2, characterized in that: The following steps are involved: Step S1, obtaining soft information corresponding to the system bit, check bits 1 and 2; Set the number of decoding iterations; Step S2, interleaving the system bit soft information, and sending the output result of the interleaver to the second decoder; Step S3, executing the operation of the second decoder; The check bit 2 soft information, the interleaved system bit soft information and the interleaved L12 information sent from the first decoder are input into the second decoder to calculate and output the external information L21 information sent to the deinterleaver; The initial value of L21 information is a sequence of all 0s; Step S4, executing the operation of the first decoder; inputting the check bit 1 soft information, the system bit soft information and the deinterleaved L21 information into the first decoder to calculate and output the external information L12 information sent to the second interleaver, and the LLR information; the LLR information corresponds to the system bit; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the LLR information output by the first decoder, and output a Turbo code decoding result.

4. A Turbo code decoder using a new architecture for decoding coded information including tail bits, characterized in that: include: It includes: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision module; wherein the first and second decoders are tail bit subdecoders; A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision module is used to decide the first LLR information that meets the iteration stop condition and output the Turbo code decoding result.

5. The Turbo code decoder using a new architecture according to claim 4, characterized in that: It also includes: a first interleaver and a splicer, which are used to generate second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

6. The Turbo code decoder using a new architecture according to claim 5, characterized in that: The L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

7. The Turbo code decoder using a new architecture according to claim 5, characterized in that: The L21 calculation module includes a second external information calculation module, a deinterleaver and a second zero-padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The deinterleaver is a K-bit deinterleaver, used to deinterleave the external data with a length of K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

8. The Turbo code decoder using a new architecture according to claim 6 or 7, characterized in that: The calculation method of the external information is: ； Among them, LLR ext1 , LLR ext2 are the external information calculated by the first and second external information calculation modules at the current time, LLR1 and LLR2 are the first and second LLR information output by the first and second decoders, respectively. sys1 , LLR sys2 The first and second system bit soft information of the first and second decoders are input respectively, LLR a1 , LLR a2 It is the external information input by the first and second decoders.

9. A decoding method based on a Turbo code decoder using a new architecture as claimed in any one of claims 4 to 8, characterized in that: The following steps are involved: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; Input the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then output the L21 information including the tail bits; Step S4, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; Input the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then output the L12 information including the tail bits; Step S5, jump to step S3, execute the operation of the second sub-decoder, and then execute the operation of the first decoder, and iterate in this way until a preset maximum number of iterations is reached; Step S6: Perform hard decision on the first LLR information output by the first decoder to output a Turbo code decoding result.

10. A Beidou receiver, characterized in that: The Beidou receiver receives the RDSS subsystem signal in the Beidou satellite navigation system BDS, and when performing Turbo code decoding, uses the Turbo code decoder with a new architecture as described in any one of claims 1-2 to decode the encoded information that does not contain tail bits; or uses the Turbo code decoder with a new architecture as described in any one of claims 4-8 to decode the encoded information containing tail bits.

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