Method and device for timing adjustment based on integration

Abstract

A method and apparatus for integration-based timing adjustment is provided in which at least one data limiter of a receiver samples a signal based on a clock sampling position to obtain a first data sample and a second data sample. An integrator of the receiver integrates a signal from the first data sample to the second data sample to generate an integrated voltage. A first data limiter of the receiver samples the integrated voltage at a time when the second data sample is obtained to obtain an integrated sample. A phase discriminator of the receiver determines whether the clock sampling position needs to be adjusted based on the symbol of the integrated sample.

Description

[0001] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 591,231, filed on October 18, 2023, and U.S. Application No. 18 / 539,638, filed on December 14, 2023, the disclosures of which are incorporated herein by reference in their entirety as if fully set forth herein. Technical Field

[0002] The disclosure relates generally to high speed communication links. More specifically, the subject matter disclosed herein relates to improvements to methods of adjusting the phase of data samples in a receiver of a high speed communication link. Background Art

[0003] In a high-speed communication link, a receiving device may include a timing recovery module responsible for providing a sampling clock that samples data in a received signal from a position determined relative to a telecommunication eye diagram. An eye diagram shows a series of "eyes" between a pair of tracks when a repeatedly sampled digital signal is applied to the y-axis and the data rate is applied to the x-axis. The timing recovery module of the receiving device may be referred to as a clock and data recovery (CDR) module. An advanced clock sampling position or a delayed clock sampling position within the eye diagram may result in less than ideal voltage margins and timing margins.

[0004] To solve this problem, the CDR module can determine a preferred clock sampling position with a larger voltage margin and timing margin. Therefore, the CDR module can determine whether the current clock position is advanced or delayed, and adjust the clock position to the center position of the "eye" in the eye diagram based on this determination.

[0005] Problems with conventional approaches include the use of more clock phases than are required for data sampling (e.g., "baud rate" operation), the need for inter-symbol interference (ISI) of the incoming data, and / or the required transition pattern. A transition represents a change in the data (D n ≠D n+1 ), and specific conversion patterns have additional requirements on the data adjacent to the conversion. Conventional methods may also require uncertain threshold voltages and more than one sampler dedicated to phase detection.

[0006] To overcome these problems, the present disclosure uses an integrator on the timing path to determine the correct clock sampling phase in the receiver, which eliminates the need for additional clock sampling phases, ISI, specific transition patterns, and digital-to-analog converters (DACs) or adaptations. Summary of the invention

[0007] In one embodiment, a method is provided in which at least one data slicer of a receiver samples a signal based on a clock sampling position to obtain a first data sample and a second data sample. An integrator of the receiver integrates the signal from the first data sample to the second data sample to generate an integrated voltage. The first data slicer of the receiver samples the integrated voltage at a time when the second data sample is obtained to obtain an integrated sample. A phase detector of the receiver determines whether the clock sampling position needs to be adjusted based on the sign of the integrated sample.

[0008] In one embodiment, a device is provided, the device having at least one data slicer configured to sample a signal based on a clock sampling position to obtain a first data sample and a second data sample. The device also includes an integrator configured to integrate the signal from the first data sample to the second data sample to generate an integrated voltage. The device also includes a first data slicer configured to sample the integrated voltage at a time when the second data sample is obtained to obtain an integrated sample. The device also includes a phase detector configured to determine whether the clock sampling position needs to be adjusted based on the sign of the integrated sample.

[0009] In one embodiment, a device is provided, the device comprising: a processor; and a non-transitory computer-readable storage medium storing instructions. When executed, the instructions cause the processor to perform the following processing: sampling a signal based on a clock sampling position to obtain a first data sample and a second data sample, and integrating the signal from the first data sample to the second data sample to generate an integrated voltage. The instructions also cause the processor to sample the integrated voltage at the time when the second data sample is obtained to obtain an integrated sample, determine whether the clock sampling position needs to be adjusted based on the sign of the integrated sample, and adjust the clock sampling position to increase the timing margin and the voltage margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following section, aspects of the subject matter disclosed herein will be described with reference to exemplary embodiments illustrated in the accompanying drawings.

[0011] Figure 1 is a diagram illustrating a high-speed communication link according to an embodiment.

[0012] Figure 2A is a diagram illustrating an advanced clock sampling position on a telecommunication eye diagram according to an embodiment.

[0013] Figure 2B is a diagram illustrating a delayed clock sampling position on a telecommunication eye diagram according to an embodiment.

[0014] Figure 3is a diagram illustrating preferred clock sampling positions on a telecommunication eye diagram according to an embodiment.

[0015] Figure 4 is a diagram illustrating phase detection according to an embodiment.

[0016] Figure 5 is a diagram illustrating phase detection with a preferred clock sampling position according to an embodiment.

[0017] Fig. 6A is a diagram illustrating phase detection with an advanced clock sampling position according to an embodiment.

[0018] Figure 6B is a diagram illustrating phase detection with a delayed clock sampling position according to an embodiment.

[0019] Figure 7 is a logic diagram illustrating phase detection according to an embodiment.

[0020] Figure 8 is a flow chart illustrating a method for adjusting a clock sampling position according to an embodiment.

[0021] Fig. 9 is a block diagram of an electronic device in a network environment according to an embodiment. DETAILED DESCRIPTION

[0022] In the following detailed description, many specific details are set forth in order to provide a thorough understanding of the disclosure. However, those skilled in the art will appreciate that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the subject matter disclosed herein.

[0023] References throughout this specification to "one embodiment" or "an embodiment" indicate that a particular feature, structure, or characteristic described in conjunction with that embodiment may be included in at least one embodiment disclosed herein. Thus, the phrases "in one embodiment" or "in an embodiment" or "according to an embodiment" (or other phrases with similar meanings) appearing in various places throughout this specification may not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" should not be construed as necessarily being preferred or advantageous over other embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context discussed herein, a singular term may include a corresponding plural form, and a plural term may include a corresponding singular form. Similarly, hyphenated terms (e.g., "two-dimensional," "pre-determined," "pixel-specific," etc.) may occasionally be used interchangeably with corresponding non-hyphenated versions (e.g., "two-dimensional," "pre-determined," "pixel-specific," etc.), and capitalized terms (e.g., "counter clock," "row select," "pixel output," etc.) may be used interchangeably with corresponding non-capitalized versions (e.g., "counter clock," "row select," "pixel output," etc.). Such occasional interchangeable usage should not be considered inconsistent with one another.

[0024] In addition, singular terms may include corresponding plural forms, and plural terms may include corresponding singular forms, depending on the context discussed herein. It should also be noted that the various drawings (including component drawings) shown and discussed herein are for illustrative purposes only and are not drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, reference numerals are repeated in the drawings to indicate corresponding and / or similar elements, if deemed appropriate.

[0025] The terms used herein are only used for the purpose of describing some example embodiments and are not intended to limit the claimed subject matter. As used herein, unless the context clearly indicates otherwise, the singular form is intended to also include the plural form. It will also be understood that when used in this specification, the terms "comprise" and / or "include" specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0026] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bound to" another element or layer, it may be directly on, directly connected to, or directly bound to another element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly bound to" another element or layer, there are no intervening elements or layers. The same reference numerals always refer to the same element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0027] Unless explicitly defined as such, the terms "first", "second", etc., as used herein, are used as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). In addition, the same reference numerals may be used across two or more figures to represent parts, components, blocks, circuits, units, or modules having the same or similar functions. However, such usage is only for convenience of illustration and ease of description; this does not mean that the construction or architectural details of such components or units are the same in all embodiments, or that such commonly referenced components / modules are the only way to implement some example embodiments disclosed herein.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter belongs. It will also be understood that, unless expressly so defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.

[0029] As used herein, the term "module" means any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. For example, software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" as used in any embodiment described herein may include, for example, individually or in any combination, components, hardwired circuits, programmable circuits, state machine circuits, and / or firmware storing instructions executed by programmable circuits. Modules may be implemented collectively or individually as circuits that form part of a larger system (e.g., but not limited to, integrated circuits (ICs), systems on chips (SoCs), components, etc.).

[0030] Figure 11 is a diagram showing a high-speed communication link according to an embodiment. The transmitter 102 and the receiver 104 may be connected via a high-speed channel or link 106. The receiver 104 may include an analog front end (AFE) module 108 that receives a data signal via the high-speed channel or link 106. The AFE may provide an equalization stage and a gain stage, which are used to optimize the data signal for symbol detection or quantization. After front-end processing, the signal may be provided to a data slicer 110 (or sampler), which samples the data signal based on a clock sampling position (Clk) and compares the sampled signal to a threshold. A CDR module 112 including a phase detector may correct and recover the clock sampling position (Clk), which may be provided back to the data slicer 110 for data sampling.

[0031] Figure 2A is a diagram showing an early clock sampling position on a telecommunications eye diagram according to an embodiment. The eye diagram shows an "eye" 202 formed from the voltage of a repeatedly sampled digital signal 204 on the y-axis and the data transmission rate (% unit interval (UI)) on the x-axis. The UI is the time spent in the data stream by each subsequent pulse or symbol. The clock sampling position is shown at approximately 20% UI, which shows a reduced timing margin from the starting point of the "eye" 202 in the x-domain and a reduced voltage margin within the "eye" 202 in the y-domain when compared to the preferred clock sampling position at the center of the "eye" 202.

[0032] Figure 2B 202 is a diagram showing a late clock sampling position on a telecommunications eye diagram according to an embodiment. The clock sampling position is shown at approximately 80% UI, which shows a reduced timing margin from the end point of the "eye" in the x-domain and a reduced voltage margin within the "eye" in the y-domain when compared to the preferred clock sampling position at the center of the "eye" 202.

[0033] Figure 3 302 is a diagram showing a preferred clock sampling position on a telecommunications eye diagram according to an embodiment. The clock sampling position is shown at approximately 50% UI, which shows the preferred maximum timing margin from the start and end points of the "eye" 302 in the x-domain and the preferred maximum voltage margin within the "eye" 302 in the y-domain.

[0034] The present disclosure provides a phase detection technique using an integrator on a timing path. Figure 4 Described in more detail, the phase detector receives a first sample (D n ), receiving the second sample from the data path (Dn+1 ), and receives samples from the integration path (T n ). Each of the received variables may have a value between -1 and 1, but the embodiment is not limited thereto.

[0035] Figure 4 is a diagram illustrating phase detection according to an embodiment. An oversampled digital signal 402 is shown, which forms a corresponding "eye". Figure 4 The embodiment shows a half-rate CDR circuit with two clock sampling positions, however, the embodiments are not limited to this rate and other rates may be applied to different numbers of clock sampling positions (eg, quarter rate).

[0036] The first data slicer 404 of the receiver can be triggered at the clock sampling position CK to obtain the first data sample D from the digital signal 402. 0 As D Odd The second data slicer 406 of the receiver can be triggered at the clock bar sampling position CKb to obtain the second data sample D from the digital signal 402. 1 As D Even The phase detector integrator 408 can be used to “start at CK and end at CKb or from D 0 To D 1 The received signal is integrated to generate an integrated voltage. The integrated voltage starts at 0 at CK, and the third data slicer 410 of the phase detector can obtain the integrated sample T from the integrated voltage at CKb. 0 . As shown below Figure 5 , Fig. 6A and Figure 6B In more detail, based on the sample T 0 The sign of CK and CKb determines whether they have an advanced, delayed, or preferred position relative to the "eye" of the received signal.

[0037] The integrator 408 may be reset after performing the integration so that subsequent integrations may also start at zero. The first data slicer 404 may be triggered again at CK to obtain a third data sample D from the digital signal 402. 2 As D Odd The second data slicer 406 may be triggered again at CKb to obtain a fourth data sample D from the digital signal 402. 3 As D Even The integrator 408 can be used to calculate the “starting at CK and ending at CKb or starting from D 2 To D 3 The received signal of the "is integrated to generate an integrated voltage. The third data slicer 410 can obtain a sample T from the integrated voltage at CKb. 2 Based on sample T 2The sign of CK and CKb determines whether they have an advanced, delayed or preferred position relative to the "eye" of the received signal. The integrator 408 may trigger the first data slicer 404 to obtain the fifth data sample D from the received signal. 4 As D Odd Previously reset.

[0038] Figure 5 is a diagram illustrating phase detection with preferred clock sampling positions according to an embodiment. The receiver input 502 is shown as having a magnitude that varies over time (eg, between 1 and -1). The first data sample D n The second data sample D is sampled at a clock sampling position CK having a negative amplitude (eg, -1), and n+1 The sample is sampled at a clock bar sampling position CKb having a positive amplitude (e.g., 1). The area of ​​the first region 504, which is negative between CK and CKb, is approximately equal to the area of ​​the second region 506, which is positive between CK and CKb. This is represented in the integrator output 508, which is shown as having an amplitude that varies over time. Specifically, the integrator output 508 starts at 0 at CK and returns to 0 at CKb. This results in an integrator output sample of 0 at CKb, indicating a preferred CK sampling position and CKb sampling position.

[0039] Fig. 6A is a diagram illustrating phase detection with an advanced clock sampling position according to an embodiment. The receiver input is shown as having a magnitude that varies over time (eg, between 1 and -1). The first data sample D n The second data sample D is sampled at a clock sampling position CK having a negative amplitude (eg, -1), and n+1 The clock bar sampling position CKb is sampled at a clock bar sampling position CKb having a positive amplitude (e.g., 1). The area of ​​the first region 604, which is negative between CK and CKb, is shown to be greater than the area of ​​the second region 606, which is positive between CK and CKb. This is represented in the integrator output 608, which is shown to have an amplitude that varies over time. Specifically, the integrator output 608 starts at 0 at CK and remains negative at CKb. This results in a negative integrator output sample at CKb, indicating an advanced CK sampling position and CKb sampling position.

[0040] Figure 6B is a diagram illustrating phase detection with a delayed clock sampling position according to an embodiment. The receiver input is shown as having a magnitude that varies over time (eg, between 1 and -1). The first data sample D n The second data sample D is sampled at a clock sampling position CK having a negative amplitude (eg, -1), and n+1The second clock sampling position CKb is sampled with a positive amplitude (e.g., 1). The area of ​​the first region 614, which is negative between CK and CKb, is shown to be smaller than the area of ​​the second region 616, which is positive between CK and CKb. This is represented in the integrator output 618, which is shown to have an amplitude that varies over time. Specifically, the integrator output starts at 0 at CK and rises to a positive value at CKb. This results in a positive integrator output sample at CKb, indicating a lagged CK sampling position and CKb sampling position.

[0041] Figure 7 is a logic diagram showing phase detection according to an embodiment. The phase detector determines whether the data sample D n ≠D n+1 If they are not equal, this indicates a data transition, and if T n The symbol =D n The sign of D n and D n+1 The clock sampling position is determined to be advanced, or if T n The symbol =D n+1 The sign of , the clock sampling position is determined to be delayed.

[0042] like Figure 7 As shown in FIG. 7 , a data signal may be received at a receiver via link 702. In a first path, a first data slicer 704 may sample the received data signal at a clock sampling position CK, which is similar to Figure 4 The second data slicer 706 can convert the sample into the clock bar sampling position CKb domain, thereby generating D Odd .

[0043] In the second path, the third data slicer 708 can sample the received data signal at CKb, which is consistent with Figure 4 The fourth data slicer 710 can keep the sample in the CKb domain and output D Even .

[0044] In the third path, integrator 712 may perform integration on the received signal from CK to CKb, which is similar to Figure 4 The fifth data slicer 714 can sample the integrator output at CKb, which corresponds to the integrator 408. Figure 4 The fifth data slicer 716 may keep the samples in the CKb domain and output T.

[0045] D Odd and D Even may be input to a first XOR gate 718. The first XOR gate 718 may beOdd and D Even Output 0 when they have the same sign and can be Odd and D Even Output 1 when they have different signs. This indicates whether D n ≠D n+1 Determination of T and D Even is input to the second XOR gate 720. The second XOR gate 720 can be Even Output 0 when they have the same sign, and can be on T and D Even Output 1 when they have different signs.

[0046] The output from the first XOR gate 718 may be provided to a first AND gate 722 and a second AND gate 724. The output from the second XOR gate 720 may be provided to the first AND gate 722 and a NOT gate (or inverter) 726. The NOT gate 726 outputs a bit opposite to the bit of the input. The output from the NOT gate 726 may be provided to the second AND gate 724. When both values ​​input to the first AND gate 722 are 1 (indicating D n ≠D n+1 And the sign of T and D Even The first AND gate 722 may output 1, indicating that the clock sampling position is advanced. In addition, the output from the second AND gate is 0. When the two values ​​input to the second AND gate 724 are 1 (indicating that Dn≠Dn+1 and the sign of T and D Even The second AND gate 724 may output 1, indicating that the clock sampling position is delayed. In addition, the output from the first AND gate is 0.

[0047] Therefore, in determining whether the clock sampling position is preferred, advanced, or delayed, embodiments do not require additional clock phases, do not require the presence of ISI, do not require a specific transition pattern, do not require a DAC to generate a threshold voltage, and do not require an adaptive loop to find the correct threshold voltage.

[0048] Figure 8 802, a signal may be sampled to obtain a first data sample. For example, a first data slicer of a receiver may sample a digital signal at a first clock sampling position. At 804, a signal may be sampled to obtain a second data sample. For example, a second data slicer of a receiver may sample the digital signal at a second clock sampling position or at the same first clock sampling position.

[0049] At 806, an integrator of a phase detector of the receiver may integrate a received signal from a first data sample to a second data sample (e.g., during a first clock sampling position to a second clock sampling position) to generate an integrated voltage. The integration may start from zero at a time when the first data sample is obtained (e.g., the first clock sampling position). At 808, a third data slicer of the phase detector may sample the integrated voltage at a time when the second data sample is obtained (e.g., the second clock sampling position) to obtain an integrated sample.

[0050] At 810, a phase detector may determine whether at least one clock sampling position needs to be adjusted based on the sign of the integrated sample. The phase detector may determine that the first data sample is not equal to the second data sample. When the integrated sample has the same sign as the second data sample, at least one clock sampling position may be determined to be delayed. When the integrated sample has a different sign than the second data sample, at least one clock sampling position may be determined to be advanced.

[0051] At 812, based on the signs of the integrated samples, the phase detector may adjust at least one clock sampling position to increase timing margin and voltage margin.

[0052] Fig. 9 is a block diagram of electronic devices in a network environment 900 according to an embodiment.

[0053] Reference Fig. 9 , an electronic device 901 in a network environment 900 may communicate with an electronic device 902 via a first network 998 (e.g., a short-range wireless communication network), or communicate with an electronic device 904 or a server 908 via a second network 999 (e.g., a long-range wireless communication network). The electronic device 901 may communicate with the electronic device 904 via the server 908. The electronic device 901 may include a processor 920, a memory 930, an input device 950, a sound output device 955, a display device 960, an audio module 970, a sensor module 976, an interface 977, a haptic module 979, a camera module 980, a power management module 988, a battery 989, a communication module 990, a subscriber identification module (SIM) card 996, or an antenna module 997. In one embodiment, at least one of the components (e.g., the display device 960 or the camera module 980) may be omitted from the electronic device 901, or one or more other components may be added to the electronic device 901. A portion of the components may be implemented as a single integrated circuit (IC). For example, the sensor module 976 (eg, a fingerprint sensor, an iris sensor, or an illumination sensor) may be embedded in the display device 960 (eg, a display).

[0054] The processor 920 may execute software (eg, program 940 ) for controlling at least one other component (eg, hardware or software component) of the electronic device 901 in combination with the processor 920 , and may perform various data processing or calculations.

[0055] As at least part of data processing or calculation, the processor 920 may load commands or data received from another component (e.g., the sensor module 976 or the communication module 990) into the volatile memory 932, process the commands or data stored in the volatile memory 932, and store the resultant data in the non-volatile memory 934. The processor 920 may include a main processor 921 (e.g., a central processing unit (CPU) or an application processor (AP)) and an auxiliary processor 923 (e.g., a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that may operate independently of the main processor 921 or in conjunction with the main processor 921. Additionally or alternatively, the auxiliary processor 923 may be adapted to consume less power than the main processor 921, or to perform a specific function. The auxiliary processor 923 may be implemented to be separate from the main processor 921 or to be a part of the main processor 921.

[0056] The auxiliary processor 923 may control at least part of the functions or states related to at least one component (e.g., display device 960, sensor module 976, or communication module 990) among the components of the electronic device 901 instead of the main processor 921 when the main processor 921 is in an inactive (e.g., sleep) state, or the auxiliary processor 923 may control at least part of the functions or states related to at least one component (e.g., display device 960, sensor module 976, or communication module 990) among the components of the electronic device 901 together with the main processor 921 when the main processor 921 is in an active state (e.g., executing an application). The auxiliary processor 923 (e.g., an image signal processor or a communication processor) may be implemented as a part of another component (e.g., a camera module 980 or a communication module 990) that is functionally related to the auxiliary processor 923.

[0057] The memory 930 may store various data used by at least one component of the electronic device 901 (e.g., the processor 920 or the sensor module 976). The various data may include, for example, software (e.g., program 940) and input data or output data for commands related to the software (e.g., program 940). The memory 930 may include a volatile memory 932 or a nonvolatile memory 934. The nonvolatile memory 934 may include an internal memory 936 and / or an external memory 938.

[0058] The program 940 may be stored in the memory 930 as software, and may include, for example, an operating system (OS) 942 , middleware 944 , or an application 946 .

[0059] The input device 950 may receive a command or data to be used by another component (eg, processor 920) of the electronic device 901 from outside the electronic device 901 (eg, a user). The input device 950 may include, for example, a microphone, a mouse, or a keyboard.

[0060] The sound output device 955 can output a sound signal to the outside of the electronic device 901. The sound output device 955 may include, for example, a speaker or a receiver. The speaker may be used for general purposes (such as playing multimedia or recording), and the receiver may be used to receive an incoming call. The receiver may be implemented as a part of the speaker or as a separate speaker.

[0061] The display device 960 may visually provide information to the outside of the electronic device 901 (e.g., a user). The display device 960 may include, for example, a display, a hologram device, or a projector, and a control circuit for controlling a corresponding one of the display, the hologram device, and the projector. The display device 960 may include a touch circuit suitable for detecting a touch or a sensor circuit (e.g., a pressure sensor) suitable for measuring the strength of a force caused by a touch.

[0062] The audio module 970 may convert sound into an electrical signal and vice versa. The audio module 970 may obtain sound via the input device 950 or output sound via the sound output device 955 or an earphone of an external electronic device 902 directly (eg, wired) or wirelessly coupled to the electronic device 901.

[0063] The sensor module 976 may detect an operating state (e.g., power or temperature) of the electronic device 901 or an environmental state (e.g., a user's state) outside the electronic device 901, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 976 may include, for example, a gesture sensor, a gyroscope sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0064] The interface 977 may support one or more designated protocols for the electronic device 901 to be directly (e.g., wired) or wirelessly coupled with the external electronic device 902. The interface 977 may include, for example, a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0065] The connection terminal 978 may include a connector via which the electronic device 901 may be physically connected to the external electronic device 902. The connection terminal 978 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

[0066] The haptic module 979 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus that can be recognized by a user via a sense of touch or a sense of movement. The haptic module 979 may include, for example, a motor, a piezoelectric element, or an electrical stimulator.

[0067] The camera module 980 may capture still images or moving images. The camera module 980 may include one or more lenses, an image sensor, an image signal processor, or a flash. The power management module 988 may manage the power provided to the electronic device 901. The power management module 988 may be implemented as at least a part of a power management integrated circuit (PMIC), for example.

[0068] The battery 989 may supply power to at least one component of the electronic device 901. The battery 989 may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0069] The communication module 990 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 901 and an external electronic device (e.g., electronic device 902, electronic device 904, or server 908), and perform communication via the established communication channel. The communication module 990 may include one or more communication processors that can operate independently of the processor 920 (e.g., AP) and support direct (e.g., wired) communication or wireless communication. The communication module 990 may include a wireless communication module 992 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 994 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). The corresponding communication modules among these communication modules may communicate via a first network 998 (e.g., a short-range communication network (such as, Bluetooth TM, Wireless Fidelity (Wi-Fi) Direct, or Infrared Data Association (IrDA) standards)) or a second network 999 (e.g., a long-distance communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or a wide area network (WAN))))) to communicate with an external electronic device. These various types of communication modules may be implemented as a single component (e.g., a single IC), or may be implemented as multiple components separated from each other (e.g., multiple ICs). The wireless communication module 992 may use user information (e.g., an International Mobile Subscriber Identity (IMSI)) stored in the user identification module 996 to identify and authenticate the electronic device 901 in a communication network (such as, the first network 998 or the second network 999).

[0070] As about Figure 1 , Figure 4 and Figure 7 As shown and described, the communication module 990 may include a receiver having a phase detector, a CDR, and a data slicer.

[0071] The antenna module 997 may transmit a signal or power to the outside of the electronic device 901 (e.g., an external electronic device), or receive a signal or power from the outside of the electronic device 901 (e.g., an external electronic device). The antenna module 997 may include one or more antennas, and thus, at least one antenna suitable for a communication scheme used in a communication network (such as the first network 998 or the second network 999) may be selected, for example, by the communication module 990 (e.g., the wireless communication module 992). Then, a signal or power may be transmitted or received between the communication module 990 and the external electronic device via the selected at least one antenna.

[0072] The command or data may be sent or received between the electronic device 901 and the external electronic device 904 via the server 908 combined with the second network 999. Each of the electronic devices 902 and 904 may be a device of the same type or a different type as the electronic device 901. All or part of the operation to be performed by the electronic device 901 may be performed in one or more of the external electronic devices 902, 904 or 908. For example, if the electronic device 901 should automatically or in response to a request from a user or another device to perform a function or service, the electronic device 901 may request one or more external electronic devices to perform at least a part of the function or service, instead of performing the function or service, or in addition to performing the function or service, the electronic device 901 may also request one or more external electronic devices to perform at least a part of the function or service. The one or more external electronic devices receiving the request may perform at least a part of the requested function or service, or an additional function or additional service related to the request, and transmit the result of the execution to the electronic device 901. The electronic device 901 may provide the result as at least a part of the reply to the request with or without further processing the result. To this end, for example, cloud computing, distributed computing, or client-server computing techniques may be used.

[0073] The embodiments of the subject matter and operations described in this specification may be implemented in digital electronic circuits, or in computer software, firmware or hardware including the structures disclosed in this specification and their structural equivalents, or in a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs (i.e., one or more modules of computer program instructions) encoded on a computer storage medium for execution by a data processing device or for controlling the operation of a data processing device. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical signal, optical signal, or electromagnetic signal) that is "generated to encode information for transmission to a suitable receiver device for execution by a data processing device". The computer storage medium may be a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof, or is included in a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination thereof. In addition, although a computer storage medium is not a propagation signal, a computer storage medium may be a source or destination of computer program instructions encoded in an artificially generated propagation signal. The computer storage medium may also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). In addition, the operations described in this specification may be implemented as operations performed by a data processing device on data stored on one or more computer-readable storage devices or received from other sources.

[0074] Although this specification may contain many specific implementation details, the implementation details should not be interpreted as a limitation on the scope of any claimed subject matter, but rather as a description of features specific to a particular embodiment. Specific features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although features may be described as working in a particular combination as above and even initially claimed as such, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0075] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired results. In certain circumstances, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products.

[0076] Thus, specific embodiments of the subject matter have been described herein. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in a different order and still achieve the desired results. Furthermore, the processing depicted in the accompanying drawings does not necessarily require the particular order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous.

[0077] As those skilled in the art will recognize, the innovative concepts described herein may be modified and varied over a wide range of applications.Accordingly, the scope of the claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but rather is defined by the appended claims.

Claims

1. A method for timing adjustment based on integration, comprising: sampling the signal based on the clock sampling position by at least one data slicer of the receiver to obtain a first data sample and a second data sample; In an integrator of the receiver, integrating the signal from the first data sample to the second data sample to generate an integrated voltage; sampling the integrated voltage by a first data slicer of the receiver at a time when a second data sample is obtained to obtain an integrated sample; as well as The receiver's phase detector determines whether the clock sampling position needs to be adjusted based on the sign of the integrated sample.

2. The method according to claim 1, further comprising: Based on the sign of the integrated sample, the clock sampling position is adjusted through the phase detector to increase the timing margin and voltage margin.

3. The method according to claim 1, wherein: The step of sampling the signal comprises: Sampling the signal at a first clock sampling position by a second data slicer of the receiver to obtain a first data sample; and The signal is sampled at a second clock sampling position by a third data slicer of the receiver to obtain a second data sample.

4. The method according to claim 3, wherein: The steps to determine whether the clock sampling position needs to be adjusted include: Determining, by a phase detector, that the first data sample is not equal to the second data sample; and By means of the phase detector, based on the fact that the integrated sample has the same sign as the second data sample, it is determined that the first clock sampling position and the second clock sampling position are lagging.

5. The method according to claim 3, wherein: The steps to determine whether the clock sampling position needs to be adjusted include: Determining, by a phase detector, that the first data sample is not equal to the second data sample; and Through the phase detector, based on the fact that the integrated sample and the second data sample have different signs, it is determined that the first clock sampling position and the second clock sampling position are advanced.

6. The method according to claim 1, wherein: Integration begins at zero at the time the first data sample is acquired.

7. The method according to claim 1, further comprising: Resets the integrator to zero for subsequent integration.

8. The method according to any one of claims 1 to 7, wherein: The step of determining whether the clock sampling position needs to be adjusted is performed independently of the data transmission mode, inter-symbol interference and the additional clock phase.

9. A device for timing adjustment based on integration, comprising: at least one data slicer configured to: sample the signal based on a clock sampling position to obtain a first data sample and a second data sample; an integrator configured to: integrate a signal from a first data sample to a second data sample to generate an integrated voltage; A first data slicer configured to: sample the integrated voltage at a time when the second data sample is obtained to obtain an integrated sample; as well as The phase detector is configured to determine whether the clock sampling position needs to be adjusted based on the sign of the integrated sample.

10. The device according to claim 9, wherein: The phase detector is further configured to adjust a clock sampling position based on a sign of the integrated sample to increase a timing margin and a voltage margin.

11. The device according to claim 9, wherein: The at least one data slicer comprises: A second data slicer is configured to: sample the signal at a first clock sampling position to obtain a first data sample; and The third data slicer is configured to sample the signal at a second clock sampling position to obtain a second data sample.

12. The device according to claim 11, wherein When determining whether the clock sampling position needs to be adjusted, the phase detector is configured as follows: determining that the first data sample is not equal to the second data sample; and Based on the integrated sample having the same sign as the second data sample, it is determined that the first clock sampling position and the second clock sampling position are lagged.

13. The device according to claim 11, wherein: When determining whether the clock sampling position needs to be adjusted, the phase detector is configured as follows: determining that the first data sample is not equal to the second data sample; and Based on the fact that the integrated sample and the second data sample have different signs, it is determined that the first clock sampling position and the second clock sampling position are advanced.

14. The apparatus according to claim 9, wherein: The integrator begins integrating from zero at the time the first data sample is acquired.

15. The apparatus according to claim 9, wherein: The phase detector is also configured to reset the integrator to zero for subsequent integration.

16. The apparatus according to any one of claims 9 to 15, wherein: The phase detector determines whether the clock sampling position needs to be adjusted regardless of the data transmission mode, inter-symbol interference and additional clock phase.

17. A device for timing adjustment based on integration, comprising: processor; as well as A non-transitory computer-readable storage medium storing instructions that, when executed, cause a processor to: Sampling the signal based on the clock sampling position to obtain a first data sample and a second data sample; integrating a signal from a first data sample to a second data sample to generate an integrated voltage; sampling the integrated voltage at a time when a second data sample is obtained to obtain an integrated sample; determining whether the clock sampling position needs to be adjusted based on the sign of the integrated sample; as well as Adjust the clock sampling position to increase the timing margin and voltage margin.

18. The apparatus according to claim 17, wherein: When sampling the signal, the instructions further cause the processor to: Sampling the signal at a first clock sampling position to obtain a first data sample; and The signal is sampled at a second clock sampling position to obtain a second data sample.

19. The apparatus according to claim 18, wherein: When determining whether the clock sampling position needs to be adjusted, the instructions further cause the processor to: determining that the first data sample is not equal to the second data sample; and Based on the integrated sample having the same sign as the second data sample, it is determined that the first clock sampling position and the second clock sampling position are lagged.

20. The apparatus of claim 18, wherein: When determining whether the clock sampling position needs to be adjusted, the instructions further cause the processor to: determining that the first data sample is not equal to the second data sample; and Based on the fact that the integrated sample and the second data sample have different signs, it is determined that the first clock sampling position and the second clock sampling position are advanced.

Images