SC-FDE timing synchronization method and system with low FPGA hardware resource consumption

Abstract

The invention provides an SC-FDE timing synchronization method and system with low FPGA hardware resource consumption, and the method comprises the steps: S1, generating an SC-FDE timing synchronization sequence, and naming the SC-FDE timing synchronization sequence as a short synchronization sequence SC-FDE signal; s2, performing timing synchronization based on a short synchronization sequence SC-FDE signal; and S3, realizing short synchronization sequence SC-FDE signal timing synchronization based on low FPGA hardware resource consumption. Compared with other SC-FDE timing synchronization based on cross-correlation, the SC-FDE timing synchronization method and the SC-FDE timing synchronization system with low FPGA hardware resource consumption have the advantages that a large number of complex operations such as complex multiplication, accumulation and division are omitted, a large number of FPGA programmable hardware resources can be saved, and the SC-FDE timing synchronization method and the SC-FDE timing synchronization system have high usability.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a SC-FDE timing synchronization method and system with low FPGA hardware resource consumption. Background Art

[0002] Single Carrier-Frequency Domain Equalization (SC-FDE) technology is a high-speed, high-capacity communication method with strong ability to combat frequency selective fading channels. Signal timing synchronization is a very critical step in the SC-FDE communication system. Its processing performance directly affects the normal implementation of subsequent processing steps such as channel estimation, channel equalization, and information decoding, and plays a significant role in the reliability of the communication system.

[0003] However, at the same time, as the SC-FDE communication system becomes increasingly complex, the demand for hardware resources in the communication system is also increasing. As a commonly used hardware carrier in the deployment of SC-FDE communication systems, each Field-Programmable Gate Array (FPGA) chip has an upper limit on the programmable hardware resources that can be provided. FPGA chips with more programmable resources are often accompanied by defects such as large area, high power consumption, and high cost. Therefore, it is urgent to study and design a SC-FDE timing synchronization algorithm and a corresponding FPGA implementation solution that has both high timing synchronization performance and low programmable hardware resource consumption.

[0004] Patent document CN105007150B (application number: 201510350857.0) discloses a low signal-to-noise ratio SC-FDE system synchronization method and synchronization device, which improves the poor performance of the SC-FDE system synchronization algorithm under low signal-to-noise ratio. However, the algorithm uses two sets of extremely long synchronization sequences, of which the first set of sequences uses a Zadoff-chu sequence with a length of 4 to 12 and is repeated 3000 to 5000 times; the second set of sequences uses a Zadoff-chu sequence with a length of 1024 to 3072 and is repeated 2 to 6 times. Although the use of such a long and complex synchronization sequence enables the synchronization technology to achieve extremely high performance, it consumes extremely high transmission resources and computational complexity.

[0005] Patent document CN111865859B (application number: 202010543418.2) discloses a timing synchronization method based on 2x oversampling of SC-FDE burst signals. This method obtains accurate timing deviation estimation results by performing group accumulation, conjugate complex multiplication, and inverse tangent operations on the 2x oversampled SC-FDE signals. However, the calculation steps involved in this method are very complicated and difficult to actually deploy in hardware.

[0006] Patent document CN112217625B (application number: 202011295097.5) discloses a method and device for implementing SC-FDE timing coarse synchronization based on FPGA. The invention uses sliding window accumulation and amplitude simplification techniques to reduce hardware overhead and computational complexity during the FPGA implementation process. However, the amplitude estimation method used in the invention has a greater impact on accuracy; the judgment method used in the invention is threshold comparison, which is prone to false detection and missed detection. Summary of the invention

[0007] In view of the defects in the prior art, the object of the present invention is to provide a SC-FDE timing synchronization method and system with low FPGA hardware resource consumption.

[0008] According to the present invention, a SC-FDE timing synchronization method with low FPGA hardware resource consumption is provided, comprising:

[0009] Step S1: Generate a SC-FDE timing synchronization sequence and name it a short synchronization sequence SC-FDE signal;

[0010] Step S2: Perform timing synchronization based on the short synchronization sequence SC-FDE signal;

[0011] Step S3: Implement short synchronization sequence SC-FDE signal timing synchronization based on low FPGA hardware resource consumption.

[0012] Preferably, the SC-FDE timing synchronization sequence includes 3 sub-synchronization sequences of equal length and identical content; wherein the sub-synchronization sequence uses a pseudo-random sequence.

[0013] Preferably, step S2 comprises:

[0014] Step S2.1: The SC-FDE signal receiver receives the short synchronization sequence SC-FDE signal through the antenna according to a preset sampling rate;

[0015] Step S2.2: Determine the total length N of the short synchronization sequence SC-FDE signal, and generate a cross-correlation window with a length of N / 3;

[0016] Step S2.3: Calculate the cross-correlation value R(d) between the short synchronization sequence SC-FDE signal sent by the sender and received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally by the receiver;

[0017] Step S2.4: Put the cross-correlation value R(d) into two buffers and delay them respectively until the position of the cross-correlation window moves to and The positions correspond to and The moment when the value of is obtained;

[0018] Step S2.5: By formula The sum of the cross-correlation values ​​of the three groups of m sequences before and after is obtained by cumulative addition R′(d);

[0019] Step S2.6: Calculate the modulus |R′(d)| of R′(d), and set the timing metric function M(d) = |R′(d)|;

[0020] Step S2.7: In a time window equal to the frame length of the short synchronization sequence SC-FDE signal, search for the maximum value M(d) of the timing metric function. The symbol position where the maximum value is located is The best synchronization position.

[0021] Preferably, the preset sampling rate in step S2.1 includes:

[0022] T s =n·T symbol

[0023] Among them, T s represents the sampling rate, T symbol represents the symbol period, and n represents the oversampling ratio.

[0024] Preferably, the step S2.3 comprises:

[0025]

[0026] Wherein, d represents the number of symbols offset between the cross-correlation window and the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received signal, and R(d) represents the cross-correlation calculation result.

[0027] Preferably, step S3 comprises:

[0028] Step S3.1: Store the short synchronization sequence SC-FDE signal data received from the sender through the antenna into a length In the shift register group, n represents the oversampling ratio of the receiver;

[0029] Step S3.2: Take out bits from the shift register at intervals of n individual data;

[0030] Step S3.3: input the retrieved data into the symbol converter respectively, and the symbol converter converts the symbols of the data according to the locally stored m-sequence;

[0031] Step S3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d);

[0032] Step S3.5: Store the accumulated results of the real part and the imaginary part into two sets of FIFO memories respectively, and wait for After the clock cycles, the output of the two FIFO groups is equivalent to

[0033] Step S3.6: Store the output results of the two FIFOs into the other two FIFOs with the same configuration. The output results of the two FIFOs are

[0034] Step S3.7: R(d), Add up, get The value of

[0035] Step S3.8: Calculate by CORDIC calculator The modulus value of the shifted timing metric function is obtained

[0036] Step S3.9: Search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames through a set of maximum value finders. The position where the maximum value appears is Add the number of the position Output the best synchronization position

[0037] According to the present invention, a SC-FDE timing synchronization system with low FPGA hardware resource consumption is provided, comprising:

[0038] Module M1: Generates the SC-FDE timing synchronization sequence and names it as the short synchronization sequence SC-FDE signal;

[0039] Module M2: timing synchronization based on short synchronization sequence SC-FDE signal;

[0040] Module M3: Implement timing synchronization of short synchronization sequence SC-FDE signals based on low FPGA hardware resource consumption.

[0041] Preferably, the SC-FDE timing synchronization sequence includes 3 sub-synchronization sequences of equal length and identical content; wherein the sub-synchronization sequence uses a pseudo-random sequence.

[0042] Preferably, the module M2 comprises:

[0043] Module M2.1: SC-FDE signal receiver receives short synchronization sequence SC-FDE signal through antenna according to preset sampling rate;

[0044] Module M2.2: determine the total length N of the short synchronization sequence SC-FDE signal and generate a cross-correlation window with a length of N / 3;

[0045] Module M2.3: Calculate the cross-correlation value R(d) between the short synchronization sequence SC-FDE signal sent by the sender received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally by the receiver;

[0046] Module M2.4: put the cross-correlation value R(d) into two buffers and delay them respectively until the position of the cross-correlation window moves to and The positions correspond to and The moment when the value of is obtained;

[0047] Module M2.5: By formula The sum of the cross-correlation values ​​of the three groups of m sequences before and after is obtained by cumulative addition R′(d);

[0048] Module M2.6: Find the modulus |R′(d)| of R′(d), and let the timing metric function M(d) = |R′(d)|;

[0049] Module M2.7: Search for the maximum value M(d) of the timing metric function in a time window equal to the frame length of the short synchronization sequence SC-FDE signal. The symbol position of the maximum value is is the best synchronization position;

[0050] The preset sampling rates in the module M2.1 include:

[0051] T s =n·T symbol

[0052] Among them, T s represents the sampling rate, T symbol represents the symbol period, n represents the oversampling ratio;

[0053] The module M2.3 includes:

[0054]

[0055] Wherein, d represents the number of symbols offset between the cross-correlation window and the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received signal, and R(d) represents the cross-correlation calculation result.

[0056] Preferably, the module M3 comprises:

[0057] Module M3.1: Store the short synchronization sequence SC-FDE signal data received from the sender through the antenna into a length In the shift register group, n represents the oversampling ratio of the receiver;

[0058] Module M3.2: Take out bits from the shift register at intervals of n individual data;

[0059] Module M3.3: input the retrieved data into the symbol converter respectively, and the symbol converter converts the symbols of the data according to the locally stored m sequence;

[0060] Module M3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d);

[0061] Module M3.5: Store the accumulated results of the real and imaginary parts into two sets of FIFO memories respectively, and wait for After the clock cycles, the output of the two FIFO groups is equivalent to

[0062] Module M3.6: Store the output results of the two FIFOs into the other two FIFOs with the same configuration. The output results of the two FIFOs are

[0063] Module M3.7: R(d), Add up, get The value of

[0064] Module M3.8: Calculation via CORDIC calculator The modulus value of the shifted timing metric function is obtained

[0065] Module M3.9: Search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames through a set of maximum value finders. The position where the maximum value appears is Add the number of the position Output the best synchronization position

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] 1. Simple synchronization sequence structure: The present invention relates to a synchronization sequence structure of a short synchronization sequence SC-FDE signal. The synchronization sequence is formed by splicing three m-sequences with the same content. Therefore, the generated sequence only contains +1 and -1. The structure of the sequence is simple, and its generation and processing do not require a large number of complex operations, such as complex number operations, floating point operations, and division, and it is easy to generate and store through hardware;

[0068] 2. The synchronization algorithm has a small amount of computation and a low false detection rate: Since the m sequence is used as the synchronization sequence, the proposed synchronization algorithm saves a lot of multiplication and division operations and has a small amount of computation; at the same time, under the condition of a low signal-to-noise ratio Gaussian white noise channel (the signal-to-noise ratio is less than 0dB), the performance loss of the present invention is only 0.5dB compared with the performance of the long sequence SC-FDE timing synchronization algorithm;

[0069] 3. Low resource consumption of the synchronization algorithm hardware implementation plan: Compared with other SC-FDE timing synchronization based on cross-correlation, the SC-FDE timing synchronization method and system with low FPGA hardware resource consumption provided by the present invention saves a large number of complex operations such as complex multiplication, accumulation, and division, can save a large amount of FPGA programmable hardware resources, and has strong usability. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0071] Figure 1 The synchronization sequence structure of the short synchronization sequence SC-FDE signal

[0072] Figure 2 The short sequence algorithm for signal normalization is compared with the short sequence algorithm and the long sequence SC-FDE timing synchronization algorithm.

[0073] Figure 3 FPGA implementation of short synchronization sequence SC-FDE timing synchronization algorithm for signal normalization

[0074] Figure 4 Functional demonstration diagram of the counter and maximum value search module

[0075] Figure 5 This is a schematic diagram of the SC-FDE data frame format.

[0076] Figure 6 This is the maximum value detection simulation waveform. DETAILED DESCRIPTION

[0077] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0078] Example 1

[0079] The present invention discloses a SC-FDE timing synchronization method with low FPGA hardware resource consumption, including: a SC-FDE timing synchronization sequence design scheme, a de-signaled normalized short sequence SC-FDE timing synchronization algorithm design scheme, and a de-signaled normalized short sequence SC-FDE timing synchronization hardware implementation scheme;

[0080] First, the present invention provides a design scheme of a SC-FDE timing synchronization sequence, and names it as a short synchronization sequence SC-FDE signal. The designed timing synchronization sequence has a total length of N, and N≥96, N is a multiple of 3, and the SC-FDE timing synchronization sequence contains 3 sub-synchronization sequences of equal length and the same content, and the sub-synchronization sequence is implemented using the most commonly used m-sequence in the pseudo-random sequence.

[0081] Secondly, the present invention provides a timing synchronization algorithm based on a short synchronization sequence SC-FDE signal, which uses the design of the SC-FDE timing synchronization sequence provided by the present invention and removes the signal energy normalization calculation step. The present invention refers to the algorithm as a de-signal normalized short sequence SC-FDE timing synchronization algorithm, and the specific steps include:

[0082] Step 2.1: SC-FDE signal receiver according to T s =n·T symbol The sampling rate of the short synchronization sequence SC-FDE signal is received through the antenna. s represents the sampling rate, T symbol represents the symbol period, and n represents the oversampling ratio.

[0083] Step 2.2: Determine the total length N of the short synchronization sequence SC-FDE signal, and generate a cross-correlation window with a length of N / 3, which is used to determine the length of the cross-correlation calculation in step 3.

[0084] Step 2.3: By formula Obtain the cross-correlation value between the short synchronization sequence SC-FDE signal sent by the sender received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally by the receiver, where d represents the number of symbols offset between the cross-correlation window and the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received short synchronization sequence SC-FDE signal, and R(d) represents the cross-correlation calculation result.

[0085] Step 2.4: Put the obtained R(d) value into the two-way cache and delay it until the position of the cross-correlation window moves to and The positions correspond to and The moment when the value of is obtained.

[0086] Step 2.5: By formula The sum R'(d) of the cross-correlation values ​​of the three groups of m sequences before and after is obtained by cumulative addition.

[0087] Step 2.6: Find the modulus |R'(d)| of R'(d), and let the timing metric function M(d) = |R'(d)|.

[0088] Step 2.7: In a time window equal to the length of the SC-FDE signal frame, search for the maximum value M(d) of the timing metric function. The symbol position where the maximum value is located is The best synchronization position.

[0089] Finally, the present invention provides a hardware implementation scheme of a timing synchronization algorithm based on a short synchronization sequence SC-FDE signal, which specifically includes the following steps:

[0090] Step 3.1: Store the data into a in the shift register group.

[0091] Step 3.2: Take out bits from the shift register at intervals of n data.

[0092] Step 3.3: The retrieved data are input into the symbol converter respectively, and the symbol converter converts the symbols of the data according to the locally stored m-sequence.

[0093] Step 3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d).

[0094] Step 3.5: Store the accumulated results of the real part and the imaginary part into two sets of FIFO memories respectively, and wait for The output is output after one clock cycle. At this time, the output results of these two groups of FIFOs are equivalent to

[0095] Step 3.6: Store the input results of the two FIFOs in step 3.5 into two other FIFOs with the same configuration. The output results of these two FIFOs are

[0096] Step 3.7: R(d), Add up, get The value of .

[0097] Step 3.8: Calculate using the CORDIC calculator The modulus value of the shifted timing metric function is obtained

[0098] Step 3.9: Use a set of maximum value finders to search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames. The position where the maximum value appears is Add the number of the position Output the best synchronization position

[0099] The present invention also provides an SC-FDE timing synchronization system with low FPGA hardware resource consumption. The SC-FDE timing synchronization system with low FPGA hardware resource consumption can be implemented by executing the process steps of the SC-FDE timing synchronization method with low FPGA hardware resource consumption, that is, those skilled in the art can understand the SC-FDE timing synchronization method with low FPGA hardware resource consumption as a preferred implementation of the SC-FDE timing synchronization system with low FPGA hardware resource consumption.

[0100] Example 2

[0101] Embodiment 2 is a preferred embodiment of Embodiment 1

[0102] According to the present invention, a SC-FDE timing synchronization method with low FPGA hardware resource consumption is provided, including: a design scheme for an SC-FDE timing synchronization sequence, a design scheme for a de-signaled normalized short sequence SC-FDE timing synchronization algorithm, and a hardware implementation scheme for a de-signaled normalized short sequence SC-FDE timing synchronization.

[0103] In this embodiment, the SC-FDE timing synchronization sequence is designed and named as a short synchronization sequence SC-FDE signal.

[0104] The schematic diagram of the short synchronization sequence SC-FDE signal is as follows Figure 1As shown, (1) the total length of the sequence is N. In this embodiment, N is 96, which satisfies the requirement that N ≥ 96 and N is a multiple of 3; (2) the sequence contains 3 sub-synchronization sequences of equal length and identical content; (3) the sub-synchronization sequence is implemented using the m-sequence which is the most commonly used pseudo-random sequence.

[0105] The three sub-synchronization sequences of equal length and identical content are used. In the algorithm and FPGA hardware implementation, the length of the cross-correlation window to be implemented directly depends on the length of the synchronization sequence specified by the frame structure. If a sequence with a certain periodic property is used, the length of the cross-correlation window can be reduced to the period length of the synchronization sequence. The shorter the cross-correlation window length, the smaller the amount of calculation required to obtain a complete cross-correlation value or energy value, and the fewer hardware resources required for FPGA implementation.

[0106] The use of the m-sequence as the wireless signal synchronization sequence can greatly simplify the complexity of the FPGA hardware implementation of the receiver synchronization module. The principle is that the m-sequence is a binary sequence with only two real number symbols, 1 and -1, corresponding to two fixed phases, 0 and π. Compared with the synchronization scheme using the ZC sequence and other forms of complex sequences, the use of the m-sequence simplifies the complex multiplication operation when calculating the cross-correlation value in various synchronization algorithms to the change of the complex sign, greatly reducing the calculation complexity; the use of the m-sequence can replace the original complex multiplier in the FPGA hardware implementation of the timing synchronization with a minus operator, saving a lot of hardware resources.

[0107] Secondly, in this embodiment, a timing synchronization algorithm based on a short synchronization sequence SC-FDE signal is provided, including: (1) using the SC-FDE timing synchronization sequence design scheme provided by the present invention; (2) removing the signal energy normalization step included in many other technical solutions. The present invention refers to the algorithm as a de-signal normalized short sequence SC-FDE timing synchronization algorithm, and its specific steps include:

[0108] Step 2.1: SC-FDE signal receiver according to T s =n·T symbol The short synchronization sequence SC-FDE signal is received through the antenna at a sampling rate of , and quantized into a complex signal with 16 bits in real and imaginary parts. s represents the sampling rate, T symbol represents the symbol period, and n represents the oversampling ratio. In this embodiment, the oversampling ratio n is 4, and the symbol period T symbol for

[0109] Step 2.2: Determine the total length N of the synchronization sequence and generate a cross-correlation window of length N / 3.

[0110] Step 2.3: By formula Obtain the cross-correlation value between the short synchronization sequence SC-FDE signal sent by the sender received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally at the receiver. Here, d represents the number of symbols by which the cross-correlation window is offset relative to the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received signal, and R(d) represents the cross-correlation calculation result.

[0111] Step 2.4: Put the obtained R(d) values into two buffers and delay them respectively until the position of the cross-correlation window moves to and positions, corresponding to the moments when the values of and are obtained respectively.

[0112] Step 2.5: Accumulate through the formula to obtain the sum R'(d) of the cross-correlation values of three groups of m sequences before and after.

[0113] Step 2.6: Calculate the modulus |R'(d)| of R'(d), and let the timing metric function M(d) = |R'(d)|.

[0114] Step 2.7: Search for the maximum value M(d) of the timing metric function within a time window with a length equal to the duration of the SC-FDE signal frame, and find the obtained which represents the symbol position where the maximum value is located. Obviously, this position is the optimal synchronization position.

[0115] In step 2.6 described above, directly using R'(d) as the timing metric function is different from using the normalized R(d) of the signal energy as the timing metric function in other synchronization techniques. The timing metric function with signal energy normalization is usually in the form of , where The reason for omitting signal normalization in the present invention is as follows: Assume the length of the transmitted signal is L, and the transmitted signal containing the timing synchronization sequence can be denoted as s(k), and the received signal at the receiver is r(k), where 0 ≤ k < L. Then, under the condition of an additive white Gaussian noise (AWGN) channel, r(k) and s(k) satisfy the equation r(k) = s(k) + n(k), 0 ≤ k < L. In the equation, n(k) represents the noise. Under the condition of a low signal-to-noise ratio AWGN channel, that is, when E(s(k) 2 ) << E(n(k) 2 ) case, at this time, can be expanded as follows:

[0116]

[0117] Since the noise signal power is significantly greater than the signal power at this time, there is no benefit in normalizing the cross-correlation value. Therefore, it is possible to consider removing this step and expressing the timing metric function and the optimal synchronization point in the form provided by the present invention.

[0118] In order to fully illustrate the performance characteristics of the short sequence SC-FDE timing synchronization algorithm without signal normalization provided by the present invention, the present invention compares the short sequence SC-FDE timing synchronization algorithm including signal normalization, the long sequence SC-FDE timing synchronization algorithm (m sequence with sequence length equal to N as synchronization sequence) with the algorithm proposed by the present invention through MATLAB simulation. Specifically, the simulation condition is MATLAB R2014a version. The simulation results are shown in the attached figure. Figure 2 shown.

[0119] Depend on Figure 2 It can be seen that the performance of the de-signaled normalized short sequence SC-FDE timing synchronization algorithm in low signal-to-noise ratio conditions is comparable to that of the short sequence SC-FDE timing synchronization algorithm, and the performance gap between the algorithm and the long sequence SC-FDE timing synchronization algorithm is controlled below 0.5dB.

[0120] Finally, in this embodiment, a hardware implementation scheme of the timing synchronization algorithm based on the short synchronization sequence SC-FDE signal is provided, as shown in the attached Figure 3 The specific advantages are (1) simple structure; (2) low consumption of hardware resources. The parameters such as oversampling ratio in the scheme are consistent with the parameters in the timing synchronization algorithm, and specifically include the following steps:

[0121] Step 3.1: Store the data into a For this embodiment, n=4, N=96, that is, the length of the shift register is 32*4-3=125.

[0122] Step 3.2: Take out bits from the shift register at intervals of n data.

[0123] Step 3.3: Input the retrieved data into the symbol converter respectively. The symbol converter converts the sign of the data according to the locally stored m-sequence. If the data is a and the m-sequence at the corresponding position is 1, the output result of the symbol converter is a; if the m-sequence at the corresponding position is -1, the output result is -a.

[0124] Step 3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d).

[0125] Step 3.5: Store the accumulated results of the real part and the imaginary part into two sets of FIFO memories respectively, where the depth of the FIFO is The FIFO read signal is connected to the FIFO's "almost full" signal. The "almost full" signal is when the number of data stored in the FIFO reaches The output of these two sets of FIFOs is equivalent to

[0126] Step 3.6: Store the input results of the two FIFOs in step 3.5 into two other FIFOs with the same configuration. The output results of these two FIFOs are

[0127] Step 3.7: R(d), Add up, get The value of .

[0128] Step 3.8: Calculate using the CORDIC calculator The modulus value of the shifted timing metric function is obtained

[0129] Step 3.9: Use a set of maximum value finders to search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames, and record the position where the maximum value occurs. The recorded position is When the current search window has passed, the recorded data is compensated and the desired optimal synchronization position is output

[0130] Step 3.10: In the next search window, A synchronization signal is sent out at each sampling point to instruct the operation of subsequent modules.

[0131] In step 3.9, the data search, data output and reset of the maximum value search module are controlled by a timing counter. Its working sequence is shown in the attached figure. Figure 4 As shown, the counting cycle of the counter module is consistent with the time length of the frame, and the start time of the counter is independent of the arrival time of the wireless frame. Assuming that a SC-FDE signal frame requires a total of t sampling points to complete sampling, and the counter starts counting continuously from 0 at a certain sampling point t0, then at the t1 sampling point (t1=t0+t), the count value returns to zero. During the counting period, the maximum value search module will continuously monitor the value of M" (d). When the value of M" (d) is greater than the maximum value recorded in the maximum value search module, the module will record the maximum value and the position value d of the sampling point. When the counter returns to zero, the maximum value search module uses the d value corresponding to the maximum value of M" (d) recorded as the optimal synchronization point. Output, and clear the currently recorded information. If the best synchronization point found by the maximum value search module between the sampling points t0 and t1 is Then, between sampling points t1 and t2 (t2=t1+t), the behavior of the subsequent modules at the receiving end needs to be synchronized with the arrival time of the sampling point t1+d.

[0132] The effect of the hardware implementation can be illustrated by Vivado simulation and synthesis. Specifically, the simulation condition of the hardware implementation is Vivado Simulator 2019.1, and the synthesis condition is Vivado High Level Synthesis 2019.1. The specific SC-FDE frame structure is shown in the attached figure. Figure 5 As shown. Among them, the length of the protection filling random code is 5000 symbols; the length of the timing synchronization sequence is 96 symbols; the length of the filling random code is 576 symbols; the frame structure is equipped with 6 groups of load information, each group of load information is divided into training sequence and data symbols, where the length of the training sequence is 576 symbols, of which the first 64 symbols are cyclic prefixes, and there are 9 groups of data symbols with a length of 576 symbols, of which the first 64 symbols are cyclic prefixes; the tail padding is 152 symbols in total. Therefore, the length of the entire SC-FDE frame structure is 40960 symbols, the sampling rate is 20.48MHz, and the FPGA system clock is 81.92MHz.

[0133] The simulation results of the maximum value detection function implemented in FPGA are shown in the attached figure. Figure 6 As shown, the timing_eval_func signal in the figure represents the timing metric function. When the timing metric function reaches its maximum value, the maximum value search module records the maximum value of the timing metric function and the sampling point number corresponding to the maximum value.

[0134] Table 1 compares the resource consumption of FPGA implementation schemes of various timing synchronization algorithms. Among them, the operation steps of the de-signalized short sequence SC-FDE timing synchronization algorithm proposed in this paper are the simplest, so its implementation scheme consumes significantly less FPGA lookup tables, registers, and digital signal processing units than other algorithms. Compared with the short sequence algorithm without de-signalization, the de-signalized short sequence algorithm saves 42.1% of lookup tables, 26.4% of registers, 60% of block random access memories, and 100% of digital signal processing units while maintaining similar performance; compared with the long sequence SC-FDE timing synchronization algorithm, the de-signalized short sequence algorithm saves 70.2% of lookup tables, 60.4% of registers, and 100% of digital signal processing units at the cost of 0.5dB performance at low signal-to-noise ratio.

[0135] Table 1 Resource consumption of various timing synchronization algorithm FPGA implementation schemes with timing synchronization sequence length 96

[0136]

[0137] It can be seen from the above simulation and comprehensive results that the design scheme of the SC-FDE timing synchronization sequence, the design scheme of the de-signaled normalized short sequence SC-FDE timing synchronization algorithm, and the hardware implementation scheme of the de-signaled normalized short sequence SC-FDE timing synchronization proposed in the present invention can save a large amount of hardware resources without consuming a large amount of channel transmission resources in the low signal-to-noise ratio AWGN channel and ensuring a certain synchronization accuracy, and have certain advantages.

[0138] Those skilled in the art know that, in addition to realizing the system and its various devices, modules, and units provided by the present invention in a purely computer-readable program code, it is entirely possible to realize the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system and its various devices, modules, and units provided by the present invention can be considered as a hardware component, and the devices, modules, and units included therein for realizing various functions can also be regarded as structures within the hardware component; the devices, modules, and units for realizing various functions can also be regarded as both software modules for realizing the method and structures within the hardware component.

[0139] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A SC-FDE timing synchronization method with low FPGA hardware resource consumption, characterized in that: include: Step S1: Generate a SC-FDE timing synchronization sequence and name it a short synchronization sequence SC-FDE signal; Step S2: Perform timing synchronization based on the short synchronization sequence SC-FDE signal; Step S3: Implement short synchronization sequence SC-FDE signal timing synchronization based on low FPGA hardware resource consumption.

2. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 1, characterized in that: The SC-FDE timing synchronization sequence includes three sub-synchronization sequences of equal length and identical content; wherein the sub-synchronization sequence uses a pseudo-random sequence.

3. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 1, characterized in that: The step S2 comprises: Step S2.1: The SC-FDE signal receiver receives the short synchronization sequence SC-FDE signal through the antenna according to a preset sampling rate; Step S2.2: Determine the total length N of the short synchronization sequence SC-FDE signal, and generate a cross-correlation window with a length of N / 3; Step S2.3: Calculate the cross-correlation value R(d) between the short synchronization sequence SC-FDE signal sent by the sender and received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally by the receiver; Step S2.4: Put the cross-correlation value R(d) into two buffers and delay them respectively until the position of the cross-correlation window moves to and The positions correspond to and The moment when the value of is obtained; Step S2.5: By formula The sum of the cross-correlation values ​​of the three groups of m sequences before and after is obtained by cumulative addition R′(d); Step S2.6: Calculate the modulus |R′(d)| of R′(d), and set the timing metric function M(d) = |R′(d)|; Step S2.7: In a time window equal to the frame length of the short synchronization sequence SC-FDE signal, search for the maximum value M(d) of the timing metric function. The symbol position where the maximum value is located is The best synchronization position.

4. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 3, characterized in that: The preset sampling rate in step S2.1 includes: T s =n·T symbol Among them, T s represents the sampling rate, T symbol represents the symbol period, and n represents the oversampling ratio.

5. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 3, characterized in that: The step S2.3 comprises: Wherein, d represents the number of symbols offset between the cross-correlation window and the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received signal, and R(d) represents the cross-correlation calculation result.

6. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 1, characterized in that: The step S3 comprises: Step S3.1: Store the short synchronization sequence SC-FDE signal data received from the sender through the antenna into a length In the shift register group, n represents the oversampling ratio of the receiver; Step S3.2: Take out bits from the shift register at intervals of n individual data; Step S3.3: input the retrieved data into the symbol converter respectively, and the symbol converter converts the symbols of the data according to the locally stored m-sequence; Step S3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d); Step S3.5: Store the accumulated results of the real part and the imaginary part into two sets of FIFO memories respectively, and wait for After the clock cycles, the output of the two FIFO groups is equivalent to Step S3.6: Store the output results of the two FIFOs into the other two FIFOs with the same configuration. The output results of the two FIFOs are Step S3.7: R(d), Add up, and get The value of Step S3.8: Calculate by CORDIC calculator The modulus value of the shifted timing metric function is obtained Step S3.9: Search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames through a set of maximum value finders. The position where the maximum value appears is Add the number of the position Output the best synchronization position 7. A SC-FDE timing synchronization system with low FPGA hardware resource consumption, characterized in that: include: Module M1: Generates the SC-FDE timing synchronization sequence and names it as the short synchronization sequence SC-FDE signal; Module M2: timing synchronization based on short synchronization sequence SC-FDE signal; Module M3: Implement timing synchronization of short synchronization sequence SC-FDE signals based on low FPGA hardware resource consumption.

8. The SC-FDE timing synchronization system with low FPGA hardware resource consumption according to claim 7, characterized in that: The SC-FDE timing synchronization sequence includes three sub-synchronization sequences of equal length and identical content; wherein the sub-synchronization sequence uses a pseudo-random sequence.

9. The SC-FDE timing synchronization method with low FPGA hardware resource consumption according to claim 7, characterized in that: The module M2 comprises: Module M2.1: SC-FDE signal receiver receives short synchronization sequence SC-FDE signal through antenna according to preset sampling rate; Module M2.2: determine the total length N of the short synchronization sequence SC-FDE signal and generate a cross-correlation window with a length of N / 3; Module M2.3: Calculate the cross-correlation value R(d) between the short synchronization sequence SC-FDE signal sent by the sender received through the antenna and the original short synchronization sequence SC-FDE sequence pre-stored locally by the receiver; Module M2.4: put the cross-correlation value R(d) into two buffers and delay them respectively until the position of the cross-correlation window moves to and The positions correspond to and The moment when the value of is obtained; Module M2.5: By formula The sum of the cross-correlation values ​​of the three groups of m sequences before and after is obtained by cumulative addition R′(d); Module M2.6: Find the modulus |R′(d)| of R′(d), and let the timing metric function M(d) = |R′(d)|; Module M2.7: Search for the maximum value M(d) of the timing metric function in a time window equal to the frame length of the short synchronization sequence SC-FDE signal. The symbol position of the maximum value is is the best synchronization position; The preset sampling rates in the module M2.1 include: T s =n·T symbol Among them, T s represents the sampling rate, T symbol represents the symbol period, n represents the oversampling ratio; The module M2.3 includes: Wherein, d represents the number of symbols offset between the cross-correlation window and the starting position of the received signal, c(k) represents the local timing synchronization sequence, c*(k) represents the conjugate of c(k), r(d) represents the received signal, and R(d) represents the cross-correlation calculation result.

10. The SC-FDE timing synchronization system with low FPGA hardware resource consumption according to claim 7, characterized in that: The module M3 comprises: Module M3.1: Store the short synchronization sequence SC-FDE signal data received from the sender through the antenna into a length In the shift register group, n represents the oversampling ratio of the receiver; Module M3.2: Take out bits from the shift register at intervals of n individual data; Module M3.3: input the retrieved data into the symbol converter respectively, and the symbol converter converts the symbols of the data according to the locally stored m sequence; Module M3.4: The real and imaginary parts of the data after the sign transformation are separated and accumulated to obtain the value of R(d); Module M3.5: Store the accumulated results of the real and imaginary parts into two sets of FIFO memories respectively, and wait for After the clock cycles, the output of the two FIFO groups is equivalent to Module M3.6: Store the output results of the two FIFOs into the other two FIFOs with the same configuration. The output results of the two FIFOs are Module M3.7: R(d), Add up, and get The value of Module M3.8: Calculation via CORDIC calculator The modulus value of the shifted timing metric function is obtained Module M3.9: Search for the maximum value of the timing metric function within the time length of the previous and next SC-FDE frames through a set of maximum value finders. The position where the maximum value appears is Add the number of the position Output the best synchronization position

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