Low-complexity OCDM modulation and demodulation implementation method based on FPGA

Abstract

The invention relates to an FPGA (Field Programmable Gate Array)-based low-complexity OCDM (Optical Code Division Multiplexing) modulation and demodulation implementation method, and belongs to the technical field of electronic communication. According to the method, DFnT or IDFnT is split into steps of twice twiddle factor multiplication, FFT (Fast Fourier Transform) or IFFT (Inverse Fast Fourier Transform) and phase and amplitude adjustment so as to realize OCDM modulation and demodulation. IQ data to be subjected to DFnT or IDFnT conversion is input through an IQ data input module; a first twiddle factor multiplication module is adopted to multiply the first twiddle factor after phase rotation with input data; carrying out FFT (Fast Fourier Transform) or IFFT (Inverse Fast Fourier Transform) on an output result of the first twiddle factor multiplication through an FFT or IFFT module; second twiddle factor multiplication is carried out on the data; and finally, phase and amplitude adjustment is carried out to complete OCDM modulation or demodulation. According to the OCDM modulation and demodulation scheme based on the FPGA, the storage capacity is reduced under the condition that the complexity is not changed.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic communications and relates to a low-complexity OCDM modulation and demodulation implementation method based on FPGA. Background Art

[0002] OCDM (Orthogonal Chirp Division Multiplexing, OCDM) is a multi-carrier modulation scheme proposed in recent years. OCDM constructs a multi-carrier waveform with linear frequency modulation signals as subcarriers through discrete Fresnel transform (Discrete Fresnel Transform, DFnT). By selecting appropriate parameters, the orthogonality between subcarriers is ensured to achieve error-free transmission of information. Compared with the current mainstream orthogonal frequency division multiplexing (Orthogonal Frequency Division Multiplexing, OFDM), OCDM has stronger robustness to frequency selective channels, shows lower bit error rate under various equalization methods, and has better performance against multipath propagation, inter-symbol interference and narrowband interference. Therefore, OCDM has become one of the representative new technologies of the physical layer of wireless communications in recent years. The study of OCDM modulation and demodulation is not only of great significance to the current 5G communication, but also has guiding value for the technical indicators of higher spectrum efficiency, higher reliability and lower latency for future 6G and non-terrestrial network communications.

[0003] At present, most of the scholars at home and abroad are still in the stage of software theory simulation in the research of OCDM technology, and there is no better solution for the hardware realization of its modulation and demodulation. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a low-complexity OCDM modulation and demodulation implementation method based on FPGA. The present invention takes into account the complexity and structural optimization issues, and uses a more efficient FPGA (Field Programmable Gate Array, FPGA) tool to preferentially implement OCDM modulation and demodulation, and encapsulates its interface, so that the number of OCDM subcarriers can be configured from the outside. As a semi-custom circuit in integrated circuits, FPGA has the advantages of low cost and high flexibility. It is more suitable as a hardware simulation verification platform in the early stage of wireless communication principle prototype research, which brings more convenience to the design of digital communication circuits.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A low-complexity OCDM modulation and demodulation implementation method based on FPGA, the method splits discrete Fresnel transform DFnT or inverse discrete Fresnel transform IDFnT into two rotation factor multiplications, fast Fourier transform FFT or inverse fast Fourier transform IFFT, phase and amplitude adjustment steps to realize OCDM modulation and demodulation, which includes the following steps:

[0007] S1. Input IQ data to be transformed by DFnT or IDFnT through the IQ data input module;

[0008] S2, setting a first rotation factor multiplication module, selecting a rotation factor, performing phase rotation on the rotation factor, and then multiplying the first rotation factor after phase rotation with the input data to obtain an output result;

[0009] S3, setting an FFT or IFFT module to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication;

[0010] S4, setting a second rotation factor multiplication module to perform a second rotation factor multiplication on the data after FFT or IFFT transformation;

[0011] S5. Set a phase and amplitude adjustment module to adjust the phase and amplitude of the data after the second rotation factor multiplication to complete OCDM modulation or demodulation.

[0012] Further, in step S1, for OCDM modulation, the data input to the input IQ data module is the received IQ time domain data obtained by sampling the receiver, and the amplitude is normalized; for OCDM demodulation, the data input to the input IQ data module is the in-phase and quadrature component data of the modulation symbol after constellation point mapping of the transmitter;

[0013] Among them, for N IQ data to be transformed by DFnT or IDFnT, the input IQ data module is represented in the following manner:

[0014] in_signal[n]=i_insgn[n]+jq_insign[n]

[0015] Where n represents the index of the input data, ranging from 0 to N-1; i_insgn[n], q_insgn[n] are signed fixed-point numbers or floating-point numbers.

[0016] Further, in step S2, the first rotation factor multiplication module is provided to include a conjugate submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule and a complex multiplication combination output submodule, wherein:

[0017] The conjugate submodule determines whether to conjugate the input IQ data according to the DFnT flag DFnT_flag;

[0018] The counter submodule is used to generate two signals, namely the index counter index and the address counter addr_cnt;

[0019] The RAM submodule stores the rotation factor IQ data and fetches the rotation factor of the corresponding address according to the value of the address counter addr_cnt;

[0020] The phase rotation selection submodule uses the index counter index to obtain the phase adjustment mode phase_mode of the rotation factor through combinational logic;

[0021] The complex multiplication combination output submodule completes the complex multiplication of the input IQ data and the rotation factor according to the phase adjustment mode phase_mode to obtain a calculation result.

[0022] Further, the conjugate submodule of the first rotation factor multiplication module determines whether the input IQ data needs to be conjugated according to the DFnT flag DFnT_flag, wherein:

[0023] For DFnT conversion, DFnT_flag is set to 1, and the input IQ data is directly output:

[0024] in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n]

[0025] For IDFnT transformation, DFnT_flag is set to 0, and the input IQ data is conjugated and output:

[0026] in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n]

[0027] The index counter index generated by the counter submodule accumulates 1 when the input IQ data in_signal is valid, and the counting range is 0 to N-1, so the index counter index has log2(N) bits; the address counter addr_cnt counts in positive order when the log2(N)-2th bit of the index counter index is 0; and counts in reverse order when the log2(N)-2th bit of index is 1, and the counting range is 0 to N / 8-1; it obtains the address data of the rotation factor RAM table;

[0028] The RAM submodule stores N / 8 rotation factor IQ data, and fetches the rotation factor θ1(n)=i_dw[n]+jq_dw[n] of the corresponding address according to the value of the address counter addr_cnt.

[0029] Furthermore, the phase adjustment mode phase_mode obtained by the phase rotation selection submodule of the first rotation factor multiplication module has four conditions:

[0030] Case 1: When the high 3 bits of the index counter are 000 or 111, phase_mode is always 0;

[0031] Case 2: When the high 3 bits of the index counter index are 001 or 010, m is the value of index minus the high 3 bits, phase_mode = m%4;

[0032] Case 3: When the high 3 bits of the index counter index are 011 or 100, m is the value of index minus the high 3 bits, phase_mode = (m%2)*2;

[0033] Case 4: When the upper 3 bits of the index counter index are 101 or 110, m is the value of index minus the upper 3 bits, and phase_mode=3-(m%2)*2.

[0034] Furthermore, the complex multiplication combination output submodule of the first rotation factor multiplication module obtains four output results according to the four phase adjustment modes of the phase rotation selection submodule:

[0035] Case 1: When phase_mode is 0, the calculation result Out_DFnT[n] is i_dout[n] = i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n] = i_din[n]*q_dw[n]+q_din[n]*i_dw[n];

[0036] Case 2: When phase_mode is 1, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0037] Case 3: When phase_mode is 2, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0038] Case 4: When phase_mode is 3, the calculation result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n].

[0039] Further, in the first rotation factor multiplication module, for DFnT transformation, the input IQ data is multiplied by the required rotation factor to obtain the output result; for IDFnT transformation, the input IQ data is conjugated and then multiplied by the required rotation factor to obtain the output result;

[0040] Among them, the input IQ data of DFnT transformation is expressed as:

[0041] in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n]

[0042] The input IQ data of the IDFnT transform is conjugated and expressed as:

[0043] in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n]

[0044] The rotation factor is expressed as:

[0045]

[0046] The output is expressed as:

[0047] Out_DFnT[n]=i_dout[n]+jq_dout[n].

[0048] Further, in step S3, the FFT or IFFT module performs FFT transformation on DFnT and performs IFFT on IDFnT; the number of points of the FFT or IFFT transformation is N, which is the same as the number of points of the DFnT or IDFnT transformation.

[0049] Further, in step S4, the second rotation factor multiplication module is also provided including a conjugate submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule and a complex multiplication combination output submodule, which performs a second rotation factor multiplication on the output data of the FFT or IFFT module.

[0050] Further, in step S5, the phase and amplitude adjustment module performs phase and amplitude adjustment on the data output by the second rotation factor multiplication module, wherein:

[0051] For DFnT transformation, the IQ data output by the second rotation factor multiplication module is complex multiplied by exp(-j*pi / 4), and the result is reduced by right shift. times;

[0052] For IDFnT, the IQ data is conjugated and then complex multiplied by exp(-j*pi / 4), and the result is amplified by left shift. times;

[0053] Output the phase and amplitude adjusted results to complete OCDM modulation or demodulation.

[0054] The beneficial effects of the present invention are:

[0055] The present invention utilizes the properties of OCDM modulation to design a method for quickly implementing DFnT / IDFnT using FFT / IFFT. The rotation factor multiplication module reduces the storage capacity by 8 times by only adding some control circuits while ensuring that the calculation complexity remains unchanged by observing the properties of the rotation factors.

[0056] The present invention provides an interface that is compatible with different DFnT modulation points, and the cost is only to add some control circuits. At the same time, the pipeline FFT is adopted, and the entire DFnT can also be pipelined, and the data rate of the entire DFnT can be compatible with some high-speed application scenarios.

[0057] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0059] Figure 1It is a schematic diagram of the overall design of the low-complexity OCDM modulation and demodulation implementation method based on FPGA of the present invention;

[0060] Figure 2 Schematic diagram of the design structure of the first rotation factor multiplication module of the present invention;

[0061] Figure 3 It is an overall flow chart of the low-complexity OCDM modulation and demodulation implementation method based on FPGA of the present invention;

[0062] Figure 4 It is a schematic diagram of the structure of a verification platform for a method for realizing low-complexity OCDM modulation and demodulation based on FPGA under an embodiment;

[0063] Figure 5 The block diagram of the 1024-point IDFnT design under the embodiment;

[0064] Figure 6 Schematic diagram of OCDM bit error probability under the embodiment;

[0065] Figure 7 Schematic diagram of FPGA and matlab waveform comparison under the embodiment, wherein: Figure 7 (a) is a schematic diagram of the real part waveform comparison. Figure 7 (b) is a schematic diagram of the comparison of imaginary part waveforms. DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0067] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0068] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0069] See also Figure 1 to Figure 7 , which is a low-complexity OCDM modulation and demodulation implementation method based on FPGA.

[0070] Example

[0071] The purpose of the present invention is to provide a low-complexity OCDM modulation and demodulation implementation method based on FPGA. OCDM modulation and demodulation are implemented using Discrete Fresnel Transform (DFnT) and Inverse Discrete Fresnel Transform (IDFnT) respectively. The DFnT transformation formula is as follows:

[0072]

[0073] Where s(n) represents the OCDM time domain signal, x(k) represents the Fresnel domain signal after DFnT transformation, n, k∈[0,N=1], N is the number of points of DFnT transformation.

[0074] Therefore, the present invention splits the discrete Fresnel transform DFnT and the inverse discrete Fresnel transform IDFnT into two steps of rotation factor multiplication, fast Fourier transform / inverse fast Fourier transform FFT / IFFT, and phase / modulus adjustment for implementation, wherein the properties of the rotation factor are utilized and a low storage space and low complexity OCDM modulation and demodulation implementation method is proposed in combination with FPGA. The design block diagram of the present invention is shown in FIG. Figure 1 shown.

[0075] like Figure 1 The FPGA design block diagram of the DFnT / IDFnT shown in the figure consists of an input IQ data module, a two-twiddle factor multiplication module, an FFT / IFFT module, and a phase and amplitude adjustment module.

[0076] Input IQ data module: For IDFnT transformation, the input IQ data is the in-phase and quadrature component data (referred to as: IQ data) of the modulation symbol after constellation point mapping by the transmitter, and IDFnT transformation is required to generate the OCDM time domain waveform. For DFnT transformation, the input IQ data is the received IQ time domain data obtained by receiver sampling, which is input for DFnT transformation after amplitude normalization. Input IQ data in_signal[n]=i_insgn[n]+jq_insign[n], n represents the index of the input data, ranging from 0 to N-1; i_insgn[n], q_insgn[n] are signed fixed-point numbers or floating-point numbers.

[0077] First rotation factor multiplication module: For DFnT transformation, the input IQ data in_DFnT[n] = i_din[n] + jq_din[n] = in_signal[n] = i_insgn[n] + jq_insgn[n] is multiplied by the required rotation factor The output result is: Out_DFnT[n] = i_dout[n] + jq_dout[n]. For IDFnT transformation, the input IQ data needs to be conjugated in_DFnT[n] = i_din[n] + jq_din[n] = i_insgn[n] - jq_insgn[n], and then multiplied by the required rotation factor Get the output result: Out_DFnT[n].

[0078] The first rotation factor multiplication module consists of five submodules, namely, the conjugate submodule, the counter submodule, the RAM submodule, the phase rotation selection submodule and the complex multiplication combination output submodule. Figure 2 shown.

[0079] The conjugate submodule determines whether the input IQ data needs to be conjugated according to the DFnT flag DFnT_flag. For DFnT transformation, DFnT_flag is set to 1, and the input IQ data is directly output in_DFnT[n] = i_din[n] + jq_din[n] = in_signal[n] = i_insgn[n] + jq_insgn[n]. For IDFnT transformation, DFnT_flag is set to 0, and the input IQ data is conjugated and output in_DFnT[n] = i_din[n] + jq_din[n] = i_insgn[n] - jq_insgn[n].

[0080] Counter submodule: The counter submodule generates two signals, namely the index counter index and the address counter addr_cnt. The index counter index accumulates 1 when the input IQ data in_signal is valid (data_valid is 1), and the counting range is 0 to N-1, so the index counter index has log2(N) bits; the address counter addr_cnt counts in the positive sequence when the log2(N)-2th bit of the index counter index is 0; and counts in the reverse sequence when the log2(N)-2th bit of the index is 1, and the counting range is 0 to N / 8-1. It is used to generate the address data of the rotation factor RAM table.

[0081] RAM submodule: stores N / 8 rotation factor IQ data, and takes out the rotation factor θ1(n)=i_dw[n]+jq_dw[n] of the corresponding address according to the value of the address counter addr_cnt.

[0082] Phase rotation selection submodule: According to the nature of DFnT / IDFnT transformation, the rotation factor data interval N / 8 points will be the same or have a fixed phase offset. Therefore, the phase adjustment mode phase_mode of the rotation factor is obtained by combinatorial logic using the index counter index. Finally, there are 4 cases for the phase adjustment mode phase_mode, which are 0, 1, 2, and 3. The following will describe the method of calculating the phase_mode by the index counter index in different cases.

[0083] Case 1: When the high 3 bits of the index counter are 000 or 111, phase_mode is always 0;

[0084] Case 2: When the high 3 bits of the index counter index are 001 or 010, m is the value of index minus the high 3 bits, phase_mode = m%4;

[0085] Case 3: When the high 3 bits of the index counter index are 011 or 100, m is the value of index minus the high 3 bits, phase_mode = (m%2)*2;

[0086] Case 4: When the high 3 bits of the index counter index are 101 or 110, m is the value of index minus the high 3 bits, phase_mode = 3-(m%2)*2;

[0087] Complex multiplication combined output submodule: According to the phase adjustment mode phase_mode, the complex multiplication of the input IQ data in_DFnT[n]=i_din[n]+jq_din[n] and the rotation factor θ1(n)=i_dw[n]+jq_dw[n] is completed. The module can complete the phase adjustment of the rotation factor and the complex multiplication with the input IQ data in_DFnT[n] by only four phase adjustment modes while ensuring that the complexity of the multiplication operation remains unchanged, thereby obtaining the calculation result Out_DFnT[n]=i_dout[n]+jq_dout[n]. The results of the complex multiplication combined output submodule will be described in detail below.

[0088] Case 1: When phase_mode is 0, the calculation result Out_DFnT[n] is i_dout[n] = i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n] = i_din[n]*q_dw[n]+q_din[n]*i_dw[n];

[0089] Case 2: When phase_mode is 1, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0090] Case 3: When phase_mode is 2, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0091] Case 4: When phase_mode is 3, the calculation result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n];

[0092] FFT / IFFT module: uses radix 2 2048-64 point fast Fourier transform / inverse fast Fourier transform (FFT / IFFT) to perform FFT on DFnT and IFFT on IDFnT. The number of FFT / IFFT transformation points is N, which is the same as the number of DFnT / IDFnT transformation points.

[0093] Second rotation factor multiplication module: This module has the same structure as the first rotation factor multiplication module, and completes the second rotation factor multiplication of the FFT / IFFT module output data. In the non-pipeline case, it can be reused with the first rotation factor multiplication module to save resources. In the pipeline case, only one identical module needs to be instantiated.

[0094] Phase and amplitude adjustment module: For DFnT, the IQ data output by the second rotation factor multiplication module is complex multiplied by exp(-j*pi / 4), and the result is reduced by right shift For IDFnT, the IQ data is conjugated and then complex multiplied with exp(-j*pi / 4), and the result is amplified by left shift. times.

[0095] The process of DFnT / IDFnT implemented by the present invention is as follows: Figure 3 shown.

[0096] Step 1: Input N IQ data that need to complete DFnT or IDFnT. Figure 3 Middle 1 step.

[0097] Step 2: Take the required rotation factor from the RAM table through the counter, complete the phase rotation of the rotation factor and the complex multiplication with the input data, and complete the first rotation factor multiplication. Figure 3 Middle 2 steps.

[0098] Step 3: Perform FFT / IFFT on the data that has completed the first phase rotation. Figure 3 Middle 3 steps.

[0099] Step 4: Multiply the FFT / IFFT data by the second rotation factor, the process is the same as step 2. Figure 3 Middle 4 steps.

[0100] Step 5: Adjust the phase and amplitude of the data that has completed the second phase rotation and output it to complete the entire DFnT / IDFnT transformation. Figure 3 5 steps in.

[0101] In order to verify the feasibility of the present invention, a theoretical analysis is first performed. OCDM modulation and demodulation are implemented using DFnT and IDFnT respectively, and the DFnT and IDFnT formulas are as follows.

[0102]

[0103] Where x(k) represents the IQ data of the constellation point mapped in the Fresnel domain, and s(n) represents the OCDM time domain signal data after IDFnT modulation. N is an odd number and N is an even number, and the subsequent implementation method will use FFT. Therefore, N is an even number as an example to design the OCDM modulation and demodulation scheme. Although DFnT has a complete set of definitions, there is no fast DFnT algorithm. If the matrix multiplication method is used, the calculation complexity is too high and the cost is too high. Therefore, it is found through derivation that DFnT can be quickly implemented through FFT.

[0104]

[0105] DFnT can be obtained by adding two quadratic phases to FFT. The two diagonal rotation factors are: and Therefore, DFnT can be quickly implemented by the fast Fourier transform algorithm FFT in three steps:

[0106] (1) The signal is multiplied by the quadratic phase θ1;

[0107] (2) Perform N-point FFT;

[0108] (3) Multiply by another quadratic phase θ2

[0109] The fast implementation of DFnT reduces the computational complexity of discrete Fresnel transform, making the communication system using Fresnel transform better integrated into the communication system using Fourier transform. IDFnT is very similar to DFnT and can be quickly implemented in three steps using IFFT:

[0110] (1) The signal is multiplied by the quadratic phase

[0111] (2) Perform N-point IFFT;

[0112] (3) Multiply by another quadratic phase

[0113] The key optimization point of the present invention is the multiplication module of the rotation factor. Discover When the number of modulation points is greater than 4, we get θ1(n+N / 2)=θ1(n)exp(jπn). Similarly, we can get θ1(n+N / 4)=θ1(n)exp(jπn / 2)θ1(N / 4-n)=θ1(n)exp(-jπn / 2). Therefore, we can know that the rotation factor data will be the same as the original data or have a fixed phase offset when the interval is N / 8 points. At the same time, in order to be compatible with DFnT at different points, it is observed that Therefore, when making a DFnT with fewer points, the rotation factors can be directly taken from the DFnT table with more points. The present invention uses this method to be compatible with DFnTs at different points, thereby avoiding the defect that different RAM tables are required for making DFnTs at different points in the conventional method.

[0114] Secondly, verify the practicability of the present invention in a practical environment. Figure 4 As shown, vivado and matlab platforms are used for simulation. The data input to IDFnT uses the bit number randomly generated by the matlab platform. After QPSK modulation, the generated IQ data signal is sent to the IDFnT module, and then the OCDM data modulated by IDFnT is sent to the DFnT module for demodulation, and QPSK demodulation. Finally, the data is written back to matlab by writing a file for comparison and verification. At the same time, the OCDM data generated by the matlab software is compared with the OCDM data generated by the FPGA to check the size of the error. The simulation platform of the specific embodiment is shown in FIG. Figure 6 shown.

[0115] In this embodiment, N is specified as 1024 and 256 points. The following is a detailed description of N as 1024 points. In matlab, first use the random number function to generate 2048*1000 bits and write them into a txt file. On the vivado platform, write a testbench to read the bit data in the txt file and instantiate each module.

[0116] The QPSK modulation module modulates the input bit data into QPSK IQ data and inputs it into the IDFnT module, where the quantization bit width of the IQ data is a signed number of 12 bits. Together with the IQ data in_mod[n]=i_mod[n]+jq_mod[n], a valid signal data_valid is also output.

[0117] The IDFnT modulation module is mainly divided into four modules: the first rotation factor multiplication, IFFT, the second rotation factor multiplication, and the phase and amplitude adjustment module.

[0118] The first rotation factor multiplication module consists of five submodules, namely, the conjugate submodule, the counter submodule, the RAM submodule, the phase rotation selection submodule and the complex multiplication combination output submodule. The design block diagram of the module is shown in the figure. Figure 5 As shown. Take the conjugate submodule: The input DFnT_flag is set to 0, so the input IQ data takes the conjugate output in_DFnT[n]=i_din[n]+jq_din[n]=i_mod[n]-jq_mod[n], where n is 0 to 1023;

[0119] Counter submodule: The counter submodule generates two control signals, namely the index counter index and the address counter addr_cnt. The index counter index accumulates 1 when the input IQ data in_signal is valid (data_valid is 1), and the counting range is 0 to 1023. The index counter index has 10 bits; the address counter addr_cnt counts in the positive sequence when the 8th bit of index is 0; and counts in the reverse sequence when the 8th bit of index is 1, and the counting range is from 0 to 127. It is to generate the address data of the rotation factor RAM table.

[0120] RAM submodule: stores 128 rotation factor IQ data, and takes out the rotation factor θ1(n)=i_dw[n]+jq_dw[n] of the corresponding address according to the value of the address counter addr_cnt.

[0121] Phase rotation selection submodule: Use the index counter index to obtain the actual phase adjustment mode phase_mode through combinational logic. There are four cases for the phase adjustment mode phase_mode, which are 0, 1, 2, and 3. The following describes the method of calculating the phase_mode by the index counter index in different cases. The operations mentioned in the operation, such as taking the high bit, taking the low bit, and taking the remainder, can all be completed by truncation.

[0122] Case 1: When the 10th, 9th, and 8th bits of the index counter are 000 or 111, phase_mode is always 0;

[0123] Case 2: When the 10th, 9th, and 8th bits of the index counter index are 001 or 010, m is the value of the 7th bit of index, and phase_mode = m%4;

[0124] Case 3: When the 10th, 9th, and 8th bits of the index counter index are 011 or 100, m is the value of the 7th bit of index, and phase_mode = (m%2)*2;

[0125] Case 4: When the 10th, 9th, and 8th bits of the index counter index are 101 or 110, m is the value of the 7th bit of index, and phase_mode = 3-(m%2)*2;

[0126] Complex multiplication combined output submodule: According to the phase adjustment mode phase_mode, the complex multiplication of the input IQ data in_DFnT[n]=i_din[n]+jq_din[n] and the rotation factor θ1(n)=i_dw[n]+jq_dw[n] is completed. The module can complete the phase adjustment of the rotation factor and the complex multiplication with the IQ data by only four phase adjustment results while ensuring that the complexity of the multiplication operation remains unchanged, thereby obtaining the calculation result Out_DFnT[n]=i_dout[n]+jq_dout[n]. The results of the complex multiplication combined output submodule will be described in detail below.

[0127] Case 1: When phase_mode is 0, the calculation result Out_DFnT[n] is i_dout[n] = i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n] = i_din[n]*q_dw[n]+q_din[n]*i_dw[n];

[0128] Case 2: When phase_mode is 1, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0129] Case 3: When phase_mode is 2, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n])q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n];

[0130] Case 4: When phase_mode is 3, the calculation result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n]q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n];

[0131] IFFT module: uses radix 2 2048-64 point inverse fast Fourier transform IFFT, and the IFFT transform is configured with 1024 points.

[0132] Second rotation factor multiplication module: The IQ data after completing IFFT needs to be multiplied by the second rotation factor. The specific process is similar to the above content and will not be described in detail.

[0133] Phase and amplitude adjustment module: conjugate the IQ data after the second phase rotation, perform complex multiplication with exp(jpi / 4), and shift the result left by 6 bits to complete IDFnT modulation;

[0134] DFnT module: It is very similar to the IDFnT module mentioned above. You only need to set the DFnT_flag flag to 1 and replace the FFT module with the IFFT module.

[0135] The QPSK demodulation module normalizes the IQ data output by the DFnT module, demodulates it into bit data through phase detection, and writes it into a txt text.

[0136] This embodiment compares the data comparison between FPGA and matlab under different data conditions. Figure 6 As shown in the figure, when 1000 frames of OCDM data are modulated by IDFnT and then demodulated by DFnT, the bit error rate of each frame is 0%. At the same time, a frame of data is captured and compared with the data after matlab modulation. It is found that the data after FPGA modulation can fully cover the data modulated by matlab, with only a small deviation in the integer part, and the data after FPGA modulation is limited. The real and imaginary waveforms are shown as follows: Figure 7 (a) and Figure 7 (b) shows the effectiveness of the present invention.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A low-complexity OCDM modulation and demodulation implementation method based on FPGA, characterized in that: The method splits the discrete Fresnel transform DFnT or the inverse discrete Fresnel transform IDFnT into two rotation factor multiplications, a fast Fourier transform FFT or an inverse fast Fourier transform IFFT, and a phase and amplitude adjustment step to realize OCDM modulation and demodulation, and includes the following steps: S1. Input IQ data to be transformed by DFnT or IDFnT through the IQ data input module; S2, setting a first rotation factor multiplication module, selecting a rotation factor, performing phase rotation on the rotation factor, and then multiplying the rotation factor after the phase rotation with the input data to obtain an output result; S3, setting an FFT or IFFT module to perform FFT or IFFT transformation on the output result of the first rotation factor multiplication; S4, setting a second rotation factor multiplication module to perform a second rotation factor multiplication on the data after FFT or IFFT transformation; S5. Set a phase and amplitude adjustment module to adjust the phase and amplitude of the data after the second rotation factor multiplication to complete OCDM modulation or demodulation.

2. The method for implementing low-complexity OCDM modulation and demodulation based on FPGA according to claim 1, characterized in that: In step S1, for OCDM modulation, the data input to the input IQ data module is the received IQ time domain data obtained by sampling the receiver, and the amplitude is normalized; for OCDM demodulation, the data input to the input IQ data module is the in-phase and quadrature component data of the modulation symbol after constellation point mapping of the transmitter; Among them, for N IQ data to be transformed by DFnT or IDFnT, the input IQ data module is represented in the following manner: in_signal[n]=i_insgn[n]+jq_insign[n] Where n represents the index of the input data, ranging from 0 to N-1; i_insgn[n], q_insgn[n] are signed fixed-point numbers or floating-point numbers.

3. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 2, characterized in that: In step S2, the first rotation factor multiplication module is provided, including a conjugate submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule and a complex multiplication combination output submodule, wherein: The conjugate submodule determines whether to conjugate the input IQ data according to the DFnT flag DFnT_flag; The counter submodule is used to generate two signals, namely the index counter index and the address counter addr_cnt; The RAM submodule stores the rotation factor IQ data and fetches the rotation factor of the corresponding address according to the value of the address counter addr_cnt; The phase rotation selection submodule uses the index counter index to obtain the phase adjustment mode phase_mode of the rotation factor through combinational logic; The complex multiplication combination output submodule completes the complex multiplication of the input IQ data and the rotation factor according to the phase adjustment mode phase_mode to obtain a calculation result.

4. The method for implementing low-complexity OCDM modulation and demodulation based on FPGA according to claim 3, characterized in that: The conjugate submodule of the first rotation factor multiplication module determines whether the input IQ data needs to be conjugated according to the DFnT flag DFnT_flag, where: For DFnT conversion, DFnT_flag is set to 1, and the input IQ data is directly output: in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n] For IDFnT transformation, DFnT_flag is set to 0, and the input IQ data is conjugated and output: in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n] The index counter index generated by the counter submodule accumulates 1 when the input IQ data in_signal is valid, and the counting range is 0 to N-1, so the index counter index has log2(N) bits; the address counter addr_cnt counts in positive order when the log2(N)-2th bit of the index counter index is 0; and counts in reverse order when the log2(N)-2th bit of index is 1, and the counting range is 0 to N / 8-1; it obtains the address data of the rotation factor RAM table; The RAM submodule stores N / 8 rotation factor IQ data, and fetches the rotation factor θ1(n)=i_dw[n]+jq_dw[n] of the corresponding address according to the value of the address counter addr_cnt.

5. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 4, characterized in that: There are four phase adjustment modes phase_mode obtained by the phase rotation selection submodule of the first rotation factor multiplication module: Case 1: When the high 3 bits of the index counter are 000 or 111, phase_mode is always 0; Case 2: When the high 3 bits of the index counter index are 001 or 010, m is the value of index minus the high 3 bits, phase_mode = m%4; Case 3: When the high 3 bits of the index counter index are 011 or 100, m is the value of index minus the high 3 bits, phase_mode = (m%2)*2; Case 4: When the upper 3 bits of the index counter index are 101 or 110, m is the value of index minus the upper 3 bits, and phase_mode=3-(m%2)*2.

6. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 5, characterized in that: The complex multiplication combination output submodule of the first rotation factor multiplication module obtains four output results according to the four phase adjustment modes of the phase rotation selection submodule: Case 1: When phase_mode is 0, the calculation result Out_DFnT[n] is i_dout[n] = i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n] = i_din[n]*q_dw[n]+q_din[n]*i_dw[n]; Case 2: When phase_mode is 1, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n]; Case 3: When phase_mode is 2, the calculation result Out_DFnT[n] is i_dout[n] = -(i_din[n]*i_dw[n]+q_din[n]*q_dw[n]), q_dout[n] = i_din[n]*q_dw[n]-q_din[n]*i_dw[n]; Case 4: When phase_mode is 3, the calculation result Out_DFnT[n] is i_dout[n]=i_din[n]*i_dw[n]+q_din[n]*q_dw[n], q_dout[n]=q_din[n]*i_dw[n]-i_din[n]*q_dw[n].

7. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 6, characterized in that: In the first rotation factor multiplication module, for DFnT transformation, the input IQ data is multiplied by the required rotation factor to obtain the output result; for IDFnT transformation, the input IQ data is conjugated and then multiplied by the required rotation factor to obtain the output result; Among them, the input IQ data of DFnT transformation is expressed as: in_DFnT[n]=i_din[n]+jq_din[n]=in_signal[n]=i_insgn[n]+jq_insgn[n] The input IQ data of the IDFnT transform is conjugated and expressed as: in_DFnT[n]=i_din[n]+jq_din[n]=i_insgn[n]-jq_insgn[n] The rotation factor is expressed as: The output is expressed as: Out_DFnT[n]=i_dout[n]+jq_dout[n].

8. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 7, characterized in that: In step S3, the FFT or IFFT module performs FFT transformation on DFnT and performs IFFT on IDFnT; the number of points of the FFT or IFFT transformation is N, which is the same as the number of points of the DFnT or IDFnT transformation.

9. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 8, characterized in that: In step S4, the second rotation factor multiplication module is also provided, which includes a conjugate submodule, a counter submodule, a RAM submodule, a phase rotation selection submodule and a complex multiplication combination output submodule, which performs a second rotation factor multiplication on the output data of the FFT or IFFT module.

10. The method for realizing low-complexity OCDM modulation and demodulation based on FPGA according to claim 9, characterized in that: In step S5, the phase and amplitude adjustment module performs phase and amplitude adjustment on the data output by the second rotation factor multiplication module, wherein: For DFnT transformation, the IQ data output by the second rotation factor multiplication module is complex multiplied by exp(-j*pi / 4), and the result is reduced by right shift. times; For IDFnT, the IQ data is conjugated and then complex multiplied by exp(-j*pi / 4), and the result is amplified by left shift. times; Output the phase and amplitude adjusted results to complete OCDM modulation or demodulation.

Images