Multi-channel comprehensive processing platform based on VPX architecture

Abstract

The invention discloses a multi-channel comprehensive processing platform based on a VPX framework, and relates to the technical field of terminal equipment. The system comprises a backboard, and two power supply modules, N signal processing modules, two master control switching modules and a clock interface module which are carried on the backboard, the backboard realizes module signal interconnection and MARK address setting; the power supply module supplies power to each module; the clock interface module provides timing information for each module and completes level conversion between the master control exchange module and an external equipment information data interface; the master control exchange module completes information data processing, receives a remote control instruction of the upper computer, forwards the remote control instruction, summarizes state information of each module and transmits the state information to the upper computer, and the network exchange capability realizes remote debugging and program updating of each module and completes reporting of health information of each module; and the signal processing module carries out signal processing such as coding modulation or demodulation decoding on the information data. According to the invention, the architecture and interconnection interfaces of multiple types of modules are uniformly specified, and the reusability and universality of the platform and hardware are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of terminal equipment in wireless communications, and in particular to a multi-channel integrated processing platform based on a VPX architecture. Background Art

[0002] In wireless communications, antennas and radio frequency devices are used to receive and transmit wireless signals for specific targets, and terminal processing devices are used for signal processing and data processing. After signal processing, intermediate frequency signals are transmitted between the radio frequency devices, and after data processing, data is exchanged with the host computer. In some scenarios, there is a one-to-many demand for terminal processing devices, but most existing devices only support one-to-one communication. If one-to-many is to be achieved, it can only be achieved by adding terminal processing devices or modules inside the devices, which poses a great challenge to the size, weight, cost, reliability, and maintainability of the equipment, especially when the terminal processing equipment does not meet a certain waveform system or other requirements and needs to be upgraded and improved, the time and price costs are high. It is an urgent need to design and implement a highly integrated, universal, and highly reliable multi-channel integrated processing platform. Summary of the invention

[0003] In view of this, the present invention proposes a multi-channel integrated processing platform based on the VPX architecture. The platform uniformly specifies the architecture and interconnection interface of multiple types of modules, effectively improving the reusability and versatility of the platform and hardware.

[0004] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0005] A multi-channel integrated processing platform based on VPX architecture, including a backplane and two power modules, N signal processing modules, two main control switching modules and a clock interface module mounted on the backplane;

[0006] The back panel is designed with a MARK address, which can realize parameter configuration and IP address configuration;

[0007] The two power modules are connected in parallel for current sharing control to supply power to other modules;

[0008] The clock interface module provides other modules with reference clock, second pulse and B code timing information, and completes the level conversion of the information data interface between the main control switching module and other devices;

[0009] The master control switching module is used to receive information data transmitted by the clock interface module or directly receive information data transmitted by the host computer, and transmit it to each signal processing module; or receive information data transmitted by each signal processing module, and transmit it to the clock interface module or the host computer; in addition, it is also used to receive remote control instructions from the host computer and pass them to the clock interface module and each signal processing module, receive demodulated data from each signal processing module and then process the payload information of the target, transmit remote online debugging and program update information, and transmit the status of each module to the host computer. The master control switching module adopts a master-slave redundant configuration to improve equipment reliability;

[0010] The N signal processing modules are used to encode and modulate the information data transmitted by the main control switching module, and perform DA conversion to an analog intermediate frequency signal or send it to the radio frequency device through a digital intermediate frequency interface, or receive the digital intermediate frequency signal of the radio frequency device, or perform AD conversion on the analog intermediate frequency signal, and then perform demodulation and decoding and transmit it to the main control switching module.

[0011] Furthermore, the main control switching module includes a network switching chip and a PHY chip, a main control CPU, a main control FPGA chip and a main control timing circuit;

[0012] The timing signal input port of the master timing circuit is connected to the clock interface module, and the timing signal output port of the master timing circuit is connected to the master FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the master FPGA chip;

[0013] The network switching chip and the PHY chip include a Gigabit Ethernet interface, an SGMII+XVC interface, and an RGMII interface. The Gigabit Ethernet interface is used to interact with the host computer, receive remote control instructions from the host computer, send the target's payload information to the host computer, transmit remote online debugging and program update information, and send status reports of each module to the host computer; the SGMII+XVC interface is used to transmit remote online debugging and program update information to the clock interface module and each signal processing module; the RGMII interface is used to interact with the main control CPU and transmit other data on the Gigabit Ethernet interface except remote online debugging and program update information;

[0014] The main control CPU includes an RGMII interface, an XVC interface, and a plurality of reserved bus daughter card interfaces. The RGMII interface of the main control CPU is used to connect to a network switching chip, and the plurality of reserved bus daughter card interfaces are used to interact with a host computer to receive or transmit information data; the XVC interface is used for remote online debugging and program update information of the main control FPGA chip;

[0015] The master control FPGA chip includes a timing signal interface, an XVC interface and a GTH interface. The XVC interface is used for remote online debugging and program update information. The timing signal interface receives the reference clock, second pulse and B code transmitted by the master control timing circuit. The GTH interface interacts with the signal processing module and the clock interface module to receive or transmit information data and receive control feedback from each module.

[0016] The main control CPU and the main control FPGA chip interact with each other through interconnected PCIE and GPIO to receive or transmit information data and send control feedback of each module;

[0017] For information data, the main control FPGA chip is used to provide encryption and decryption channels to communicate with external security devices, and the main control CPU is used to perform combining and splitting operations on it.

[0018] Furthermore, the clock interface module includes a clock SOC chip, and an interface circuit and a clock timing circuit respectively connected to the clock SOC chip;

[0019] The interface circuit realizes level conversion of different information data interfaces;

[0020] The clock SOC chip includes a signal input port, an SGMII+XVC interface, a timing signal port, and a GTX interface; the signal input port is connected to an interface circuit for receiving or transmitting information data; the GTX interface of the clock SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for receiving or sending information data and sending control feedback; the SGMII+XVC interface of the clock SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the timing signal port is connected to the input port of the clock timing circuit to provide the timing information of the reference clock, second pulse and B code, and the clock SOC chip can also switch the reference clock in the clock timing circuit;

[0021] The output port of the clock timing circuit is connected to N signal processing modules and the timing signal input port of the master timing circuit in the two master switching modules to provide the timing information of the reference clock, second pulse and B code.

[0022] Furthermore, the N signal processing modules each include an AD / DA daughter card, a signal processing FPGA chip, a signal processing SOC chip and a signal processing timing circuit;

[0023] The timing signal input port of the signal processing timing circuit is connected to the output port of the clock timing circuit in the clock interface module, and the timing signal output port of the signal processing timing circuit is connected to the signal processing FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the signal processing FPGA chip;

[0024] The AD / DA subcard is connected to the signal processing FPGA chip via a Jesd204B interface for AD and DA conversion of modulated coded signals; the input / output port of the AD / DA subcard is used for the RF interface with the RF device and for transmitting modulated data with the signal processing FPGA;

[0025] The signal processing FPGA chip includes a Jesd204B interface, a GTH interface, a time signal interface, an interconnected GTH / GTX, LVDS, a GPIO interface and a SelectMap interface; the Jesd204B interface of the signal processing FPGA chip is connected to the AD / DA subcard, the GTH interface of the signal processing FPGA chip is connected to the GTH interface of the main control FPGA chip in the main control switching module, and is used for receiving and transmitting information data, or as a digital intermediate frequency interface and transmitting modulated and coded information data between the radio frequency device, and the time signal interface of the signal processing FPGA chip is connected to the time signal output port of the signal processing time circuit; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing FPGA chip are all connected to the signal processing SOC chip, and are used to realize control feedback and program loading respectively;

[0026] The signal processing SOC chip includes interconnected GTH / GTX, LVDS, GPIO interface, SelectMap interface, SGMII+XVC interface and GTX interface; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing SOC chip are used to connect with the signal processing FPGA chip; the SGMII+XVC interface of the signal processing SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the GTX interface of the signal processing SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for sending control feedback;

[0027] The signal processing FPGA chip encodes, modulates, demodulates and decodes the information data.

[0028] Furthermore, the N signal processing modules, the two main control switching modules and the one clock interface module all include a single chip microcomputer;

[0029] The single-chip microcomputer in the signal processing module is connected to the signal processing SOC chip, the single-chip microcomputer in the main control switching module is connected to the main control CPU, and the single-chip microcomputer in the clock interface module is connected to the clock SOC chip; the single-chip microcomputers in the signal processing module and the clock interface module are connected to the single-chip microcomputer IIC interface in the main control switching module through the IIC interface, which is used for the health management of each module;

[0030] After the single-chip microcomputer in the main control switching module summarizes the health management, it interacts with the host computer through the Gigabit Ethernet interface of the main control CPU, network switching chip and PHY chip.

[0031] Furthermore, the two power modules, N signal processing modules, two main control switching modules and one clock interface module are all in the form of 6U or 4U VPX boards.

[0032] Due to the adoption of the above technical solution, the beneficial effects of the present invention compared with the prior art are:

[0033] 1. The standardized design of the present invention can effectively avoid the reliability and maintainability problems caused by cable interconnection and disassembly and assembly during the design and implementation of non-standard chassis; it is more universal and can significantly improve the maintenance efficiency of equipment and reduce time and price costs.

[0034] 2. The functional division between modules in the present invention makes it possible to load different waveform algorithms, assemble different numbers of modules, and select modules of different types or modules of the same type with different capabilities in different application scenarios, which greatly improves the reuse of platforms and modules; more integrated, cable-free and high-speed interconnection design can effectively reduce the size of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The figure is a schematic diagram of the overall structure of a multi-channel integrated processing platform based on the VPX architecture in an embodiment of the present invention.

[0036] Figure 2 Schematic diagram of the structure of the signal processing module in an embodiment of the present invention.

[0037] Figure 3 Schematic diagram of the structure of the main control switching module in an embodiment of the present invention.

[0038] Figure 4 Schematic diagram of the structure of the clock interface module in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0040] A multi-channel integrated processing platform based on VPX architecture, such as Figure 1As shown, it includes a backplane and two power modules mounted on the backplane, N signal processing modules, two main control switching modules and a clock interface module;

[0041] The back panel is designed with a MARK address, which can realize parameter configuration and IP address configuration;

[0042] The two power modules are connected in parallel for current sharing control to supply power to other modules;

[0043] The clock interface module provides other modules with reference clock, second pulse and B code timing information, and completes the level conversion of the information data interface between the main control switching module and other devices;

[0044] The master control switching module is used to receive information data transmitted by the clock interface module or directly receive information data transmitted by the host computer, and transmit it to each signal processing module; or receive information data transmitted by each signal processing module, and transmit it to the clock interface module or the host computer; in addition, it is also used to receive remote control instructions from the host computer and pass them to the clock interface module and each signal processing module, receive demodulated data from each signal processing module and then process the payload information of the target, transmit remote online debugging and program update information, and transmit the status of each module to the host computer. The master control switching module adopts a master-slave redundant configuration to improve equipment reliability;

[0045] The N signal processing modules are used to encode and modulate the information data transmitted by the main control switching module, and perform DA conversion to an analog intermediate frequency signal or send it to the radio frequency device through a digital intermediate frequency interface, or receive the digital intermediate frequency signal of the radio frequency device, or perform AD conversion on the analog intermediate frequency signal, and then perform demodulation and decoding and transmit it to the main control switching module.

[0046] Furthermore, if Figure 3 As shown, the main control switching module includes a network switching chip and a PHY chip, a main control CPU, a main control FPGA chip and a main control timing circuit;

[0047] The timing signal input port of the master timing circuit is connected to the clock interface module, and the timing signal output port of the master timing circuit is connected to the master FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the master FPGA chip;

[0048] The network switching chip and the PHY chip include a Gigabit Ethernet interface, an SGMII+XVC interface, and an RGMII interface. The Gigabit Ethernet interface is used to interact with the host computer, receive remote control instructions from the host computer, send the target's payload information to the host computer, transmit remote online debugging and program update information, and send status reports of each module to the host computer; the SGMII+XVC interface is used to transmit remote online debugging and program update information to the clock interface module and each signal processing module; the RGMII interface is used to interact with the main control CPU and transmit other data on the Gigabit Ethernet interface except remote online debugging and program update information;

[0049] The main control CPU includes an RGMII interface, an XVC interface, and a plurality of reserved bus daughter card interfaces. The RGMII interface of the main control CPU is used to connect to a network switching chip, and the plurality of reserved bus daughter card interfaces are used to interact with a host computer to receive or transmit information data; the XVC interface is used for remote online debugging and program update information of the main control FPGA chip;

[0050] The master control FPGA chip includes a timing signal interface, an XVC interface and a GTH interface. The XVC interface remotely debugs online and updates program information. The timing signal interface receives the reference clock, second pulse and B code transmitted by the master control timing circuit. The GTH interface interacts with the signal processing module and the clock interface module to receive or transmit information data and receive control feedback from each module.

[0051] The main control CPU and the main control FPGA chip interact with each other through interconnected PCIE and GPIO to receive or transmit information data and send control feedback of each module;

[0052] For information data, the main control FPGA chip is used to provide encryption and decryption channels to communicate with external security devices, and the main control CPU is used to perform combining and splitting operations on it.

[0053] Furthermore, if Figure 4 As shown, the clock interface module includes a clock SOC chip, and an interface circuit and a clock timing circuit respectively connected to the clock SOC chip;

[0054] The interface circuit realizes level conversion of different information data interfaces;

[0055] The clock SOC chip includes a signal input port, an SGMII+XVC interface, a timing signal port, and a GTX interface; the signal input port is connected to an interface circuit for receiving or transmitting information data; the GTX interface of the clock SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for receiving or sending information data and sending control feedback; the SGMII+XVC interface of the clock SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the timing signal port is connected to the input port of the clock timing circuit to provide the timing information of the reference clock, second pulse and B code, and the clock SOC chip can also switch the reference clock in the clock timing circuit;

[0056] The output port of the clock timing circuit is connected to N signal processing modules and the timing signal input port of the master timing circuit in the two master switching modules to provide the timing information of the reference clock, second pulse and B code.

[0057] Furthermore, if Figure 2 As shown, the N signal processing modules each include an AD / DA daughter card, a signal processing FPGA chip, a signal processing SOC chip and a signal processing timing circuit;

[0058] The timing signal input port of the signal processing timing circuit is connected to the output port of the clock timing circuit in the clock interface module, and the timing signal output port of the signal processing timing circuit is connected to the signal processing FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the signal processing FPGA chip;

[0059] The AD / DA subcard is connected to the signal processing FPGA chip via a Jesd204B interface for AD and DA conversion of modulated coded signals; the input / output port of the AD / DA subcard is used for the RF interface with the RF device and for transmitting modulated data with the signal processing FPGA;

[0060] The signal processing FPGA chip includes a Jesd204B interface, a GTH interface, a time signal interface, an interconnected GTH / GTX, LVDS, a GPIO interface and a SelectMap interface; the Jesd204B interface of the signal processing FPGA chip is connected to the AD / DA subcard, the GTH interface of the signal processing FPGA chip is connected to the GTH interface of the main control FPGA chip in the main control switching module, and is used for receiving and transmitting information data, or as a digital intermediate frequency interface and transmitting modulated and coded information data between the radio frequency device, and the time signal interface of the signal processing FPGA chip is connected to the time signal output port of the signal processing time circuit; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing FPGA chip are all connected to the signal processing SOC chip, and are used to realize control feedback and program loading respectively;

[0061] The signal processing SOC chip includes interconnected GTH / GTX, LVDS, GPIO interface, SelectMap interface, SGMII+XVC interface and GTX interface; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing SOC chip are used to connect with the signal processing FPGA chip; the SGMII+XVC interface of the signal processing SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the GTX interface of the signal processing SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for sending control feedback;

[0062] The signal processing FPGA chip encodes, modulates, demodulates and decodes the information data.

[0063] Specifically, in this embodiment, each signal processing module has two intermediate frequency transmission interfaces and two intermediate frequency receiving interfaces, or can have a digital intermediate frequency transceiver interface through the expansion of the clock interface module, on which processors such as V7 can dynamically load multiple waveform algorithms. Therefore, signal processing of multiple target links can be realized through multiple signal processing modules, and multiple waveforms such as continuous waveforms and burst waveforms can be loaded.

[0064] Furthermore, the N signal processing modules, the two main control switching modules and the one clock interface module all include a single chip microcomputer;

[0065] The single-chip microcomputer in the signal processing module is connected to the signal processing SOC chip, the single-chip microcomputer in the main control switching module is connected to the main control CPU, and the single-chip microcomputer in the clock interface module is connected to the clock SOC chip; the single-chip microcomputers in the signal processing module and the clock interface module are connected to the single-chip microcomputer IIC interface in the main control switching module through the IIC interface, which is used for the health management of each module;

[0066] After the single-chip microcomputer in the main control switching module summarizes the health management, it interacts with the host computer through the Gigabit Ethernet interface of the main control CPU, network switching chip and PHY chip.

[0067] Specifically, in this embodiment, each module sends its own temperature, voltage, clock lock status, network connection status, FLASH storage status, SDRAM storage status and other hardware status and software version information to the main control switch module and then reports to the host computer. At the same time, the module panel is designed with a status indicator connected to the chip inside the module, which can indicate the current working status of the module in real time through program assignment.

[0068] Furthermore, the two power modules, N signal processing modules, two main control switching modules and one clock interface module are all in the form of 6U or 4U VPX boards.

[0069] Specifically, in this embodiment, the FPGA chip of the signal processing module and the main control switching module adopts a V7 chip; the main control CPU adopts a Feiteng processor; the integrated processing platform is in the form of a standard VPX chassis, and the internal modules are all in 6U or 4UVPX form;

[0070] The VPX connector P0 cavity of the signal processing module is for power supply, debug interface and MARK address, the differential P1 cavity is for MLVDS bus, universal low-speed interface and timing interface, the differential P2~P3 cavity is for SGMII+XVC and universal low-speed interface, the differential P4~P5 cavity is for GTH / GTX interface, and the RF P6 cavity is for analog intermediate frequency interface. In the 4U VPX form, the mixed P0 cavity is for power supply, MARK address, universal low-speed interface and GTH / GTX, the differential P1 cavity is for SGMII, MLVDS bus and universal low-speed interface, modem control feedback interface, and the RF P2 cavity is for analog intermediate frequency transmission and reception interface;

[0071] For analog IF scenarios, the analog IF interface on the device panel is connected to the AD / DA subcard on the module through the RF cable and the P6 cavity of the signal processing module. After the subcard completes AD sampling, it sends the sampled signal to the V7 chip through interfaces such as JESD204B for demodulation and decoding, and then sends the demodulated information data to the main control switching module through the GTH interface of the V7 chip for branch processing, or the V7 chip receives the combined data through the GTH interface and sends it to the AD / DA subcard for DA conversion. For digital IF scenarios, the digital IF interface on the device panel connects the electrical signal to the signal processing module after photoelectric conversion through optical fiber and the clock interface module, and the subsequent processing is consistent with the analog IF interface;

[0072] For the multi-channel scenario required for N-target communication, each signal processing module can correspond to one target signal processing, or each signal processing module can correspond to two target signal processing using the analog intermediate frequency interface of the signal processing module or the digital intermediate frequency interface on the clock interface module, with other modules as backup. For the communication scenario of N / 2 target dual links, the processing method is similar. For the communication scenario of <N targets, the number of signal processing modules to be assembled can be determined comprehensively from the perspective of cost and backup.

[0073] The VPX connector of the main control switch module has a mixed P0 cavity for power, debug interface and MARK address, differential P1~P3 cavities for SGMII+XVC and reserved expansion interface, differential P4~P5 cavities for GTH / GTX interface, and differential P6 cavity for MLVDS bus, general low-speed interface and time system interface. In the 4U VPX form, the mixed P0 cavity is for power, MARK address, general low-speed interface and GTH / GTX, the differential P1 cavity is for SGMII+XVC, MLVDS bus, reserved bus interface and general low-speed interface, and the differential P2 cavity is for Ethernet, general command control and status reporting interface.

[0074] Furthermore, the clock interface module completes the level conversion of external interfaces such as image, optical fiber, Ethernet, 1394 bus, 1553B bus, RS422, and transmits it to the V7 chip of the main control switch module through GTX, and then sends it to the signal processing module. At the same time, each module in the platform is connected to the network switch chip of the main control switch module through SGMII+XVC. Combined with the application of XVC technology on each module, remote debugging and program updates of all modules can be achieved through an external Ethernet interface of the platform.

[0075] The VPX connector P0 cavity of the clock interface module is for power supply, debug interface and MARK address, the differential P1 cavity is for SGMII+XVC interface, the differential P2~P3 cavity is for GTX interface, the differential P4 cavity is for MLVDS bus, universal low-speed interface and time system interface, the optical fiber P5 cavity is for optical fiber MT interface, and the RF P6 cavity is for RF interface. In the 4U VPX form, the mixed P0 cavity is for power supply, MARK address, universal low-speed interface and GTX, the differential P1 cavity is for SGMII+XVC, MLVDS bus, reserved bus interface and universal low-speed interface, Ethernet, and the RF P2 cavity is for RF interface.

[0076] Furthermore, the device's external image, optical fiber, Ethernet, 1394 bus, 1553B bus, and RS422 interfaces are connected to the interface circuit on the clock interface module through the RF module, optical fiber module, and differential module on the VPX connector, and then sent to the main control switch module through GTX, universal low-speed interface, etc. For the time system interface, the switching circuit, attenuation amplifier circuit, and branch circuit inside the module can realize the switching of the reference clock inside and outside, the adaptation of the external reference clock level, and the level conversion of the external time system information and the internal module.

[0077] The high-power power contacts of the power module VPX connector are used for external power input and power supply to other modules in the platform. The low-power power contacts are used to power the fan (when necessary). The signal contacts are used to transmit status information, remote compensation settings, module enable and shutdown, parallel current sharing control, etc.

[0078] Furthermore, the status information includes input voltage detection, output voltage and current detection, internal temperature and other information; the remote compensation setting ensures the input voltage value of the module farthest from the power module in the platform; the parallel current sharing control allows the two modules to evenly share the output working current when the redundant power module is working normally. In the case of any power abnormality, the other power module outputs at full capacity to ensure the normal operation of the equipment and improve equipment reliability. At the same time, the power module is designed with anti-reverse connection, anti-short circuit and other functions, which can effectively isolate the front-end and back-end faults.

[0079] In this embodiment, the signal processing module, main control switching module, clock interface module, power module, backplane and chassis are all 100% domestically produced. At the same time, the raw materials and electromechanical components on the chassis are also 100% domestically produced, getting rid of the dependence on imported components and raw materials.

[0080] In short, the unified architecture of the present invention facilitates subsequent expansion and reduction, especially for multi-channel signal processing. The universalization of modules can improve the module reuse rate, indirectly reduce labor costs, procurement costs and maintenance costs, and interface customization can meet the external interface requirements of different scenarios. At the same time, VPX equipment following the design method described in the present invention has been applied in a variety of use environments such as ground, shipboard, and airborne. The module size ranges from 4U to 6U, the heat dissipation form ranges from air cooling to liquid cooling, and the target number ranges from 1 to 8, which verifies the universality of the design method described in the present invention.

[0081] Those skilled in the art will appreciate that the embodiments described are intended to help readers understand the principles of the present invention, and should be understood that the scope of protection of the present invention is not limited to the embodiments described. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A multi-channel integrated processing platform based on VPX architecture, characterized in that: It includes a backplane and two power modules, N signal processing modules, two main control switching modules and a clock interface module mounted on the backplane; The back panel is designed with a MARK address, which can realize parameter configuration and IP address configuration; The two power modules are connected in parallel for current sharing control to supply power to other modules; The clock interface module provides other modules with reference clock, second pulse and B code timing information, and completes the level conversion of the information data interface between the main control switching module and other devices; The master control switching module is used to receive information data transmitted by the clock interface module or directly receive information data transmitted by the host computer, and transmit it to each signal processing module; or receive information data transmitted by each signal processing module, and transmit it to the clock interface module or the host computer; in addition, it is also used to receive remote control instructions from the host computer and transmit them to the clock interface module and each signal processing module, receive demodulated data from each signal processing module and then process the payload information of the sending target, transmit remote online debugging and program update information, and transmit the status of each module to the host computer; the master control switching module adopts a master-slave redundant configuration; The N signal processing modules are used to encode and modulate the information data transmitted by the main control switching module, and perform DA conversion to an analog intermediate frequency signal or send it to the radio frequency device through a digital intermediate frequency interface, or receive the digital intermediate frequency signal of the radio frequency device, or perform AD conversion on the analog intermediate frequency signal, and then perform demodulation and decoding and transmit it to the main control switching module.

2. A multi-channel integrated processing platform based on VPX architecture according to claim 1, characterized in that: The main control switching module includes a network switching chip and a PHY chip, a main control CPU, a main control FPGA chip and a main control timing circuit; The timing signal input port of the master timing circuit is connected to the clock interface module, and the timing signal output port of the master timing circuit is connected to the master FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the master FPGA chip; The network switching chip and the PHY chip include a Gigabit Ethernet interface, an SGMII+XVC interface, and an RGMII interface. The Gigabit Ethernet interface is used to interact with the host computer, receive remote control instructions from the host computer, send the target's payload information to the host computer, transmit remote online debugging and program update information, and send status reports of each module to the host computer; the SGMII+XVC interface is used to transmit remote online debugging and program update information to the clock interface module and each signal processing module; the RGMII interface is used to interact with the main control CPU and transmit other data on the Gigabit Ethernet interface except remote online debugging and program update information; The main control CPU includes an RGMII interface, an XVC interface, and a plurality of reserved bus daughter card interfaces. The RGMII interface of the main control CPU is used to connect to a network switching chip, and the plurality of reserved bus daughter card interfaces are used to interact with a host computer to receive or transmit information data; the XVC interface is used for remote online debugging and program update information of the main control FPGA chip; The master control FPGA chip includes a timing signal interface, an XVC interface and a GTH interface. The XVC interface is used for remote online debugging and program update information. The timing signal interface receives the reference clock, second pulse and B code transmitted by the master control timing circuit. The GTH interface interacts with the signal processing module and the clock interface module to receive or transmit information data and receive control feedback from each module. The main control CPU and the main control FPGA chip interact with each other through interconnected PCIE and GPIO to receive or transmit information data and send control feedback of each module; For information data, the main control FPGA chip is used to provide encryption and decryption channels to communicate with external security devices, and the main control CPU is used to perform combining and splitting operations on it.

3. A multi-channel integrated processing platform based on VPX architecture according to claim 2, characterized in that: The clock interface module includes a clock SOC chip, and an interface circuit and a clock timing circuit respectively connected to the clock SOC chip; The interface circuit realizes level conversion of different information data interfaces; The clock SOC chip includes a signal input port, an SGMII+XVC interface, a timing signal port, and a GTX interface; the signal input port is connected to an interface circuit for receiving or transmitting information data; the GTX interface of the clock SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for receiving or sending information data and sending control feedback; the SGMII+XVC interface of the clock SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the timing signal port is connected to the input port of the clock timing circuit to provide the timing information of the reference clock, second pulse and B code, and the clock SOC chip can also switch the reference clock in the clock timing circuit; The output port of the clock timing circuit is connected to N signal processing modules and the timing signal input port of the master timing circuit in the two master switching modules to provide the timing information of the reference clock, second pulse and B code.

4. The multi-channel integrated processing platform based on VPX architecture according to claim 3, characterized in that: The N signal processing modules each include an AD / DA daughter card, a signal processing FPGA chip, a signal processing SOC chip and a signal processing timing circuit; The timing signal input port of the signal processing timing circuit is connected to the output port of the clock timing circuit in the clock interface module, and the timing signal output port of the signal processing timing circuit is connected to the signal processing FPGA chip, which is used to transmit the reference clock, second pulse and B code transmitted by the clock interface module to the signal processing FPGA chip; The AD / DA subcard is connected to the signal processing FPGA chip via a Jesd204B interface for AD and DA conversion of modulated coded signals; the input / output port of the AD / DA subcard is used for the RF interface with the RF device and for transmitting modulated data with the signal processing FPGA; The signal processing FPGA chip includes a Jesd204B interface, a GTH interface, a time signal interface, an interconnected GTH / GTX, LVDS, a GPIO interface and a SelectMap interface; the Jesd204B interface of the signal processing FPGA chip is connected to the AD / DA subcard, the GTH interface of the signal processing FPGA chip is connected to the GTH interface of the main control FPGA chip in the main control switching module, and is used for receiving and transmitting information data, or as a digital intermediate frequency interface and transmitting modulated and coded information data between the radio frequency device, and the time signal interface of the signal processing FPGA chip is connected to the time signal output port of the signal processing time circuit; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing FPGA chip are all connected to the signal processing SOC chip, and are used to realize control feedback and program loading respectively; The signal processing SOC chip includes interconnected GTH / GTX, LVDS, GPIO interface, SelectMap interface, SGMII+XVC interface and GTX interface; the interconnected GTH / GTX, LVDS, GPIO interface and SelectMap interface of the signal processing SOC chip are used to connect with the signal processing FPGA chip; the SGMII+XVC interface of the signal processing SOC chip is connected to the SGMII+XVC interface of the network switching chip and the PHY chip in the main control switching module for remote online debugging and program update information; the GTX interface of the signal processing SOC chip is connected to the GTH interface of the main control FPGA chip in the main control switching module for sending control feedback; The signal processing FPGA chip encodes, modulates, demodulates and decodes the information data.

5. The multi-channel integrated processing platform based on VPX architecture according to claim 4, characterized in that: The N signal processing modules, the two main control switching modules and the one clock interface module all include a single chip microcomputer; The single-chip microcomputer in the signal processing module is connected to the signal processing SOC chip, the single-chip microcomputer in the main control switching module is connected to the main control CPU, and the single-chip microcomputer in the clock interface module is connected to the clock SOC chip; the single-chip microcomputers in the signal processing module and the clock interface module are connected to the single-chip microcomputer IIC interface in the main control switching module through the IIC interface, which is used for the health management of each module; After the single-chip microcomputer in the main control switching module summarizes the health management, it interacts with the host computer through the Gigabit Ethernet interface of the main control CPU, network switching chip and PHY chip.

6. The multi-channel integrated processing platform based on VPX architecture according to claim 5, characterized in that: The two power modules, N signal processing modules, two main control switching modules and one clock interface module are all in the form of 6U or 4U VPX boards.

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