Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a core layer; a plurality of first wirings disposed on the core layer; a first pad disposed on the core layer, the first pad including an adjacent portion and an open portion, a side of the adjacent portion being disposed substantially parallel to a side of a first wiring adjacent to the first pad among the plurality of first wirings, the open part is arranged to be not parallel to a first wire adjacent to the first bonding pad in the plurality of first wires; and a first build-up insulating layer disposed on the core layer, the first build-up insulating layer covering at least a portion of the plurality of first wirings and the first pad. The core layer includes an insulating material that is different from an insulating material of the first build-up insulating layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0138399 filed on October 17, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Multi-chip packages, including memory chips such as high bandwidth memory (HBM), processor chips such as central processing units (CPUs), graphics processing units (GPUs), and logic chips such as application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), etc., have been used to process data, which has been growing exponentially due to the recent development of artificial intelligence (AI) technology. In particular, the number of CPU cores and GPU cores in server products has grown rapidly, and the number of layers of multilayer boards has been increasing to handle the increased number of CPU cores and GPU cores. Therefore, continuous efforts have been made to improve reliability while reducing the number of layers of the board and achieving fine-pitch patterns and interlayer connections between pads. Summary of the invention

[0004] An aspect of the present disclosure provides a printed circuit board including a pattern having a fine pitch and a pad.

[0005] Another aspect of the present disclosure provides a printed circuit board capable of preventing defects from being generated in patterns and pads even when a low-cost construction method is used.

[0006] Another aspect of the present disclosure provides a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a core layer; a plurality of first wirings disposed on the core layer; a first pad disposed on the core layer, the first pad comprising an adjacent portion and an open portion, the side of the adjacent portion being disposed substantially parallel to the side of a first wiring adjacent to the first pad among the plurality of first wirings, the open portion being disposed non-parallel to a first wiring adjacent to the first pad among the plurality of first wirings; and a first buildup insulating layer disposed on the core layer, the first buildup insulating layer covering at least a portion of the plurality of first wirings and the first pad. The core layer may include an insulating material different from an insulating material of the first buildup insulating layer.

[0008] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a first insulating layer; a plurality of first wirings, respectively arranged on the upper surface and the lower surface of the first insulating layer; and a pad, arranged on each of the upper surface and the lower surface of the first insulating layer, the pad comprising an adjacent portion and an open portion, the side of the adjacent portion being arranged to be substantially parallel to the side of an adjacent first wiring adjacent to the pad among the plurality of first wirings, and the open portion being arranged to be non-parallel to the adjacent first wiring. The distance between the adjacent portion of the pad and the adjacent first wiring may be substantially equal to the distance between the adjacent first wiring and the first wiring adjacent to the adjacent first wiring.

[0009] According to one aspect of the present disclosure, a printed circuit board is provided, the printed circuit board comprising: a core layer; a first wiring arranged on the core layer; a pad arranged on the core layer, the pad having a rectangular shape, so that: a pair of first sides of the pad are substantially parallel to the sides of the adjacent first wiring adjacent to the pad, and a second side of the pad extending from the pair of first sides and connecting the pair of first sides is not parallel to the side of the adjacent first wiring. The distance between two adjacent first wirings between which the pad is not arranged may be substantially the same as the distance between the first side and the adjacent first wiring.

[0010] According to example embodiments of the present disclosure, a printed circuit board may include patterns and pads having a fine pitch.

[0011] The printed circuit board is protected from defects in patterns and pads even when using low-cost construction methods.

[0012] The printed circuit board may have improved reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic block diagram of an example of an electronic device system; Figure 2 is a schematic perspective view of an example of an electronic device; Figure 3 is a schematic cross-sectional view of a printed circuit board according to an example; Figure 4A and Figure 4B are respectively a schematic design plan view and a schematic image plan view of a first wiring layer of a printed circuit board according to the prior art; Figure 5A , Fig. 6A and Fig. 7Ais a schematic plan view of a portion of a design of a first wiring layer of a printed circuit board according to the prior art; Figure 5B , Figure 6B and Figure 7B is a schematic plan view of a portion of a design of a first wiring layer of a printed circuit board according to an example; and Figure 8 is a schematic cross-sectional view of a printed circuit board according to another example. DETAILED DESCRIPTION

[0014] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of components in the drawings may be exaggerated or reduced.

[0015] Electronic Devices Figure 1 is a schematic block diagram of an example of an electronic device system.

[0016] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010. Chip-related components 1020, network-related components 1030, and other components 1040 may be physically and / or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below via various signal lines 1090.

[0017] The chip-related components 1020 may include: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM) or a flash memory); an application processor chip, such as a central processing unit (e.g., a central processing unit (CPU)), a graphics processor (e.g., a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor or a microcontroller; and a logic chip, such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). However, the chip-related components 1020 are not limited thereto and may include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0018] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (Wireless LAN), Third Generation Mobile Communication Technology (3G) Protocol, Fourth Generation Mobile Communication Technology (4G) Protocol, and Fifth Generation Mobile Communication Technology (5G) Protocol, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, and may also include components compatible with or operating according to various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0019] The other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, the other components 1040 are not limited thereto and may also include passive components for various other purposes, etc. In addition, the other components 1040 may be combined with each other together with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0020] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or are not physically and / or electrically connected to the mainboard 1010. The other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0021] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data.

[0022] Figure 2 is a schematic perspective view of an example of an electronic device.

[0023] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. A portion of the component 1120 may be the above-mentioned chip-related component (e.g., a component package 1121), but the present disclosure is not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. The electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0024] Printed Circuit Board Figure 3 is a schematic cross-sectional view of a printed circuit board according to an example.

[0025] Reference Figure 3 , a printed circuit board according to an example may include: a core layer 110; a first wiring layer 120 disposed on the core layer 110; and a through via 130 penetrating the core layer 110 to connect the first wiring layers 120 disposed on opposite surfaces of the core layer 110 to each other. The first wiring layer 120 may include a first wiring 126, a first pad 121, a second pad 122, and a first pattern.

[0026] The core layer 110 may include an insulating material. The insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by mixing a thermosetting resin or a thermoplastic resin with an inorganic filler (such as silica), or a material prepared by impregnating a core material (such as glass fiber (for example, glass fabric with glass cloth as an example)) and an inorganic filler in a thermosetting resin or a thermoplastic resin, for example, an organic insulating material such as a prepreg, but the present disclosure is not limited thereto. The core layer 110 may be a copper clad laminate (CCL) in which copper foil is stacked on the upper and lower sides of a resin impregnated with a core material (such as glass fiber), but the present disclosure is not limited thereto. As needed, the core layer 110 may include other insulating materials other than the organic insulating material, such as a glass plate, etc.

[0027] The first wiring layer 120 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. The first wiring layer 120 may perform various functions according to its design. For example, a signal pattern, a power pattern, a ground pattern, etc. may be included, but the present disclosure is not limited thereto. Each of the above patterns may have various forms, such as a line, a plane, a pad, etc.

[0028] The first wiring layer 120 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 120 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 120 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). As required, a sputtering layer may be included instead of an electroless plating layer (e.g., a chemical copper plating layer), or both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) may be included. Since the core layer 110 may be a CCL with copper foil formed on the upper and lower sides of the resin, each component of the first wiring layer 120 may be formed using a single layer of copper, and electroplating may be performed in the form of a panel on the core layer 110 using the copper foil as a seed. The first wiring layer 120 may be formed using any method for patterning the circuit layer on the core layer 110. However, when the core layer 110 is a CCL, the printed circuit board according to the example may be formed using one of a subtractive method and a sealing method, but the present disclosure is not limited thereto. The subtractive method or the sealing method may be performed on a copper foil or a wide metal plate in the form of a panel by marking the required portion and then removing the unnecessary portion. In this case, the copper foil may be removed using a physical method or a chemical method. As a non-limiting example, chemical etching may be used.

[0029] The through via 130 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof. The metal may preferably include copper (Cu), but the present disclosure is not limited thereto. The through via may be conformally formed by plating the above-mentioned metal material on the wall of the through hole passing through the core layer 110, and may be a plated through hole (PTH) filled with an insulating material, but the present inventive concept is not limited thereto. The through via 130 may perform various functions according to its design. For example, a ground via, a power via, a signal via, etc. may be included. The through via 130 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included.

[0030] The first wiring layer 120 may include a first wiring 126, a first pad 121, and a second pad 122, but may also include various patterns. The first pad 121 and the second pad 122 may be connected to a via for interlayer connection, and the first wiring 126 may be used as a signal transmission path. The first pad 121 may be connected to a through via 130. The first wiring layer 120 may be disposed on each of the upper and lower surfaces of the core layer 110, and the first wiring 126, the first pad 121, and the second pad 122 may be disposed on each of the upper and lower surfaces of the core layer 110 to protrude from the upper and lower surfaces of the core layer 110. Each component of the first wiring layer 120 protrudes from the upper or lower surface of the core layer 110, which may mean that one surface of each component of the first wiring layer 120 is disposed in contact with the upper or lower surface of the core layer 110, and the other surfaces of each component of the first wiring layer 120 except the one surface are not covered by the core layer 110. That is, the first wiring layer 120 may be provided to protrude on the opposite surface of the core layer 110. Such a configuration may be a result of forming the first wiring layer 120 by removing a portion of a copper foil or a plating layer stacked on the opposite surface of the core layer 110, and may be different from a configuration in which a build-up wiring layer is provided only on one surface of a build-up insulating layer.

[0031] The first wiring 126 may be a linear pattern, and the first pad 121 and the second pad 122 may be a pattern having a predetermined shape. In addition, the first wiring layer 120 is not limited thereto, and may further include a first pattern 124 having a different planar shape (refer to Figure 7B ).

[0032] The first pad 121 and the second pad 122 may have a plurality of pads, respectively, and the first wiring 126 may include a plurality of wirings. The first pad 121 and the second pad 122 may be connected to one of the plurality of first wirings 126, respectively.

[0033] The width W1 of the first pad 121 may be greater than the width W2 of the second pad 122. The first pad 121 may be designed to have a width W1 greater than the width W2 of the second pad 122, and the first pad 121 may be connected to the through via 130. The width of each of the first pad 121 and the second pad 122 may be greater than the width (or line width) W3 of the first wiring 126. That is, the width W1 of the first pad 121 may be greater than the width W3 of the first wiring 126, and the width W2 of the second pad 122 may be greater than the width W3 of the first wiring 126. Each of the first pad 121 and the second pad 122 (components of the via connected to the first stacked via layer 143) may have a width greater than the width W3 of the first wiring 126 to facilitate connection to the via.

[0034] The width W1 of the first pad 121 and the width W2 of the second pad 122 can be measured by photographing a cut section of the printed circuit board using a scanning microscope. The width W3 of the first wiring 126 can also be measured by photographing a cut section of the printed circuit board using a scanning microscope. The width W1 of the first pad 121 and the width W2 of the second pad 122 can be measured by cutting the printed circuit board to include the first stacked via layer 143. In addition, when the first pad 121 and the second pad 122 do not have a circular shape, the width of the pad can be measured by cutting the printed circuit board in a direction that is the same as or parallel to the cutting direction used to measure the width of the wiring. The width can be calculated as the average value of the distances measured at any five points.

[0035] Even when the first pad 121, the second pad 122 and the first wiring 126 have different widths, the distance d1 between the first pad 121 and the first wiring 126, the distance d2 between the second pad 122 and the first wiring 126, the distance d3 between two adjacent first wirings 126, and the distance d4 between the first pad 121 and the second pad 122 may be substantially the same.

[0036] The first pad 121 and the second pad 122 may respectively include: an adjacent portion disposed substantially parallel to an adjacent first wiring 126 among the plurality of first wirings 126; and an open portion disposed not parallel to an adjacent first wiring 126 among the plurality of first wirings 126. The first pad 121 and the second pad 122 may respectively include the adjacent portion and the open portion so that even when the etchant is concentrated in an area of ​​each of the first pad 121 and the second pad 122 that is not adjacent to the first wiring 126, defects do not occur in the first pad 121 and the second pad 122. The adjacent portion and the open portion, the shape of the pad, and the distance between components will be described in detail below.

[0037] The printed circuit board according to the example may include a first buildup insulating layer 141 disposed on the core layer, the first buildup insulating layer 141 covering at least a portion of the first wiring layer 120. The first wiring layer 120 may be disposed on each of the upper and lower surfaces of the core layer 110 to protrude from the core layer 110, and at least a portion of the first wiring layer 120 may be embedded in the first buildup insulating layer 141.

[0038] In addition, according to the example, the printed circuit board may include: a first stacking wiring layer 142, which is arranged on the first stacking insulating layer 141; and a first stacking via layer 143, which passes through at least a portion of the first stacking insulating layer 141 to connect the first stacking wiring layers 142 to each other and connect the first stacking wiring layers 142 and the first wiring layer 120 to each other.

[0039] The printed circuit board according to the example may also include: a second stacking insulation layer 151, which is arranged on the first stacking insulation layer 141; a second stacking wiring layer 152, which is arranged on the second stacking insulation layer 151; and a second stacking via layer 153, which passes through at least a portion of the second stacking insulation layer 151 to connect the second stacking wiring layers 152 to each other and connect the second stacking wiring layers 152 and the first stacking wiring layers 142 to each other.

[0040] The first buildup insulating layer 141 and the second buildup insulating layer 151 may include insulating materials, respectively. The insulating material may include a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by mixing a thermosetting resin or a thermoplastic resin with an inorganic filler (such as silica), or a material prepared by impregnating a core material (such as glass fiber) and an inorganic filler in a thermosetting resin or a thermoplastic resin, for example, an insulating material such as Ajinomoto build-up film (ABF), a prepreg, a resin coated copper (RCC), a photosensitive dielectric (PID), etc., but the present disclosure is not limited thereto. The first buildup insulating layer 141 and the second buildup insulating layer 151 may include the same insulating material, but the present disclosure is not limited thereto, and the second buildup insulating layer 151 may include a material that is more conducive to realizing a wiring layer with a fine pitch than the material of the first buildup insulating layer 141. The thickness of the second buildup insulating layer 151 may be less than the thickness of the first buildup insulating layer 141. The first stacked insulating layer 141 and the second stacked insulating layer 151 may include a plurality of insulating layers or a single insulating layer, respectively.

[0041] The first buildup insulating layer 141 may include an insulating material different from the insulating material of the core layer 110. The core layer 110 may include an insulating material having excellent rigidity and a fixed thickness as a core material of a printed circuit board. Any insulating layer that can be used as a laminated insulating layer of a printed circuit board may be used as the first buildup insulating layer 141 without limitation. In some cases, one of the material groups of the core layer 110 may be selected as the material of the first buildup insulating layer 141, and one of the material groups of the first buildup insulating layer 141 may be selected as the material of the core layer 110. However, even in this case, the core layer 110 and the first buildup insulating layer 141 may have different physical properties, such as the thickness of the first buildup insulating layer 141 is less than the thickness of the core layer 110, or the rigidity of the core layer 110 is greater than the rigidity of the first buildup insulating layer 141, etc. In addition, the difference between the core layer 110 and the first buildup insulating layer 141 may be that a copper foil is laminated on the core layer 110, or panel plating is performed on the core layer 110. In the printed circuit board according to the example, even if a copper foil laminate is used as the core layer 110, a first wiring layer 120 with a fine pitch can be implemented on the core layer 110, and a first buildup insulating layer 141 and a second buildup insulating layer 151 other than the core layer 110 can be distinguished from the core layer 110.

[0042] The first buildup wiring layer 142 and the second buildup wiring layer 152 may include metals, respectively. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and may preferably include copper (Cu), but the present disclosure is not limited thereto. The first buildup wiring layer 142 and the second buildup wiring layer 152 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), respectively, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. In addition, copper foil may also be included. The first buildup wiring layer 142 and the second buildup wiring layer 152 may perform various functions, respectively, according to the design of the corresponding layers. For example, a ground pattern, a power pattern, a signal pattern, etc. may be included. The above patterns may include line patterns, plane patterns, and / or pad patterns, respectively. The first buildup wiring layer 142 and the second buildup wiring layer 152 may include a plurality of wiring layers, respectively. The second buildup wiring layer 152 may include wirings finer than those of the first buildup wiring layer 142. For example, the second buildup wiring layer 152 may be thinner than the first buildup wiring layer 142 and may have a narrow pitch and a smaller line width / space ratio, such as a high wiring density. That is, the second buildup wiring layer 152 may be a redistribution layer for connecting to a semiconductor chip.

[0043] The first stacked via layer 143 and the second stacked via layer 153 may include micro vias, respectively. The micro vias may be filled vias that fill the via holes, or may be conformal vias arranged along the wall surface of the via holes. The micro vias may be arranged as stacked vias and / or staggered vias. The first stacked via layer 143 and the second stacked via layer 153 may include metals, respectively, and the metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or alloys thereof, and may preferably include copper (Cu), but the inventive concept is not limited thereto. The first stacked via layer 143 and the second stacked via layer 153 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), respectively, but the present disclosure is not limited thereto. A sputtering layer may be formed instead of the electroless plating layer, or both the sputtering layer and the electroless plating layer may be included. The first stacked via layer 143 and the second stacked via layer 153 may perform various functions according to the design of the corresponding layers, for example, they may include ground vias, power vias, signal vias, etc. The first stacked via layer 143 and the second stacked via layer 153 may include a plurality of via layers.

[0044] The printed circuit board according to the example may further include a solder resist layer 160 located at the outermost side thereof. The solder resist layer 160 may be disposed on each of the first buildup insulating layer 141 and the second buildup insulating layer 151. The solder resist layer 160 may include an insulating material and may be a liquid type solder resist layer or a film type solder resist layer, but the present disclosure is not limited thereto and may include other types of insulating materials. The solder resist layer 160 may have an opening that exposes at least a portion of the first buildup wiring layer 142 and at least a portion of the second buildup wiring layer 152.

[0045] The printed circuit board according to the example may further include a surface treatment layer 170 disposed on the first buildup wiring layer 142 and the second buildup wiring layer 152 exposed through the opening of the solder resist layer 160. The surface treatment layer 170 may include at least one metal of nickel (Ni), palladium (Pd) and gold (Au), and the surface treatment layer 170 may include a plurality of layers having the above metals. For example, the surface treatment layer 170 may be at least a portion of an electroless nickel electroless palladium immersion gold (ENEPIG) structure, or may be at least a portion of an electroless nickel immersion gold (ENIG) structure. The surface treatment layer 170 may include an organic solder passivation (OSP) structure including an organic material, but the present disclosure is not limited thereto.

[0046] exist Figure 3 , it is shown that the second buildup insulating layer 151 and the second buildup wiring layer 152 are disposed on the first buildup insulating layer 141, but the present disclosure is not necessarily limited thereto, and in some cases, the second buildup insulating layer 151 and the second buildup wiring layer 152 may be omitted.

[0047] In addition, the printed circuit board according to the example is not limited to Figure 3 In some cases, other components may be included, or the components shown may be omitted. That is, the printed circuit board may also include components that may be used by those skilled in the art.

[0048] Figure 4A and Figure 4B 1 and 2 are respectively a schematic design plan view and a schematic image plan view of a first wiring layer of a printed circuit board according to the prior art.

[0049] When chemical etching is used in the operation of forming the first wiring layer (including the first wiring 126', the first pattern 124', the first pad 121' and the second pad 122'), it may not be easy to finely remove a portion of the copper foil formed on the core layer 110' in the form of a panel. In particular, when the first wiring 126' with a fine line width is formed, a defect that the first wiring 126' is broken and disconnected in the middle may occur, and two adjacent first wirings 126' may not be completely separated from each other, resulting in a defect that a short circuit occurs. Using such a method of removing a portion of the copper foil, it may be difficult to achieve wiring with a fine line width.

[0050] In addition, difficulties may arise in realizing the first and second pads 121' and 122' with fine width and pitch. In particular, in the case of pads, wiring is not formed around the pads, so that the etchant may be concentrated around the first and second pads 121' and 122'. Therefore, the first and second pads 121' and 122' may have the same Figure 4A The shapes designed in different shapes, such as Figure 4B As shown. That is, compared with the designed situation, a larger portion of the first pad 121' and the second pad 122' can be removed from the area of ​​the first pad 121' and the second pad 122' that is not adjacent to the first wiring 126', so that the first pad 121' and the second pad 122' can have an area smaller than the designed area. However, the existing defects are not limited to this, and the etchant may not be able to uniformly penetrate into the area of ​​the first pad 121' and the second pad 122' adjacent to the first wiring 126'. In this case, the first pad 121' and the second pad 122' may not be separated from the adjacent first wiring 126', resulting in a short circuit defect.

[0051] That is, when an etchant is introduced for patterning, it may not be easy to remove the first pad 121' and the second pad 122' from the area of ​​the first pad 121' and the second pad 122' adjacent to the first wiring 126'. On the contrary, in the area of ​​the first pad 121' and the second pad 122' that is not adjacent to the first wiring 126', over-etching of the first pad 121' and the second pad 122' may occur. The first pad 121' and the second pad 122' may have a shape and position different from the designed shape and position. Therefore, when the first stacked via layer 143' is formed on the first pad 121' and the second pad 122', misalignment defects may occur, and interlayer connection may not be smoothly performed.

[0052] Figure 5A , Fig. 6A and Fig. 7A is a schematic plan view of a portion of a design of a first wiring layer of a printed circuit board according to the prior art.

[0053] Reference Figure 5A and Fig. 6A , in terms of the amount of etchant that flows, the area of ​​the second pad 122' connected to the first wiring 126' may be different from the area of ​​the second pad 122' that is not connected to the first wiring 126'. That is, with reference to the area of ​​the second pad 122' connected to the first wiring 126', the etchant may be restricted by the first wiring 126' connected to the second pad 122', and may penetrate toward the second pad 122'. On the contrary, with reference to the opposite side of the area of ​​the second pad 122' connected to the first wiring 126', the second pad 122' may have an open area, so that the etchant may be concentrated in the open area of ​​the second pad 122'. Therefore, the above-mentioned defects may occur.

[0054] Reference Fig. 7A , the first pad 121' may be adjacent to the first wiring 126' and the first pattern 124'. In this case, the etchant may not move smoothly due to the first wiring 126' and the first pad 121'. On the contrary, the etchant may be concentrated in the area of ​​the first pad 121' that is not adjacent to the first wiring 126' and the first pattern 124'. Therefore, even in this case, the above-mentioned defects may occur.

[0055] Figure 5B , Figure 6B and Figure 7B is a schematic plan view of a portion of a design of a first wiring layer of a printed circuit board according to an example.

[0056] Reference Figure 5B and Figure 6BThe second pad 122 may include an adjacent portion 122-1 and an open portion 122-2, wherein the adjacent portion 122-1 is a region of the second pad 122 adjacent to the first wiring 126, and the open portion 122-2 is a region of the second pad 122 that is not adjacent to the first wiring 126 and is not connected to other wirings. The second pad 122 may have a rectangular shape, for example, Figure 5B Part (a) and part (b) in the figure respectively show that the second pad 122 has a rounded rectangular shape and a right-angled rectangular shape, but the present disclosure is not limited thereto, and the second pad 122 may also have other shapes, such as a triangle, a square, a trapezoid, etc. In this document, "adjacent first wiring" may refer to a first wiring that is adjacent to and spaced from the corresponding pad (or the adjacent portion of the corresponding pad). In addition, "the distance between two adjacent first wirings" may refer to the distance between any two adjacent first wirings among a plurality of first wirings, for example, it may refer to the distance between a first wiring adjacent to a pad and a first wiring adjacent to the first wiring among a plurality of first wirings.

[0057] The adjacent portion 122-1 of the second pad 122 may include a portion substantially parallel to the first wiring 126 adjacent to the second pad 122. That is, the adjacent portion 122-1 of the second pad 122 may be substantially parallel to the adjacent first wiring 126, which may mean that the adjacent portion 122-1 of the second pad 122 has an edge parallel to a wiring path (i.e., a linear pattern) of the adjacent first wiring 126. For example, the side of the adjacent portion 122-1 is set to be substantially parallel to the side of the first wiring 126 adjacent to the second pad 122. The present disclosure is not limited thereto, and substantially parallel may be based on a rough concept, for example, a concept including errors occurring in a manufacturing operation or a measurement method.

[0058] The open portion 122-2 of the second pad 122 may mean an area of ​​the second pad 122 that is not adjacent to the first wiring 126. The open portion 122-2 of the second pad 122 may mean an area of ​​the second pad 122 that is not parallel to the adjacent first wiring 126, and may mean that a virtual extension line of the edge of the open portion 122-2 of the second pad 122 may contact the adjacent first wiring 126. The open portion 122-2 of the second pad 122 may be located on the opposite side of the area of ​​the second pad 122 connected to the first wiring 126. The open portion 122-2 of the second pad 122 may be positioned to extend in a direction away from the area where the first stacking via layer 143 is located. That is, the second pad 122 may be designed to have a larger area than the area required to connect the second pad 122 to the first stacking via layer 143. Furthermore, the plurality of first wirings 126 may include a first wiring 126 connected to the second pad 122 and remaining first wirings 126 , wherein the first wiring 126 connected to the second pad 122 may be disposed closer to the first stacked via layer 143 than the open portion 122 - 2 of the second pad 122 .

[0059] In addition, in the case where the second pad 122 has a rectangular shape, a pair of first sides of the second pad 122 are substantially parallel to sides of adjacent first wirings 126, and a second side of the second pad 122 extending from and connecting the pair of first sides is not parallel to sides of adjacent first wirings 126, wherein a distance between two adjacent first wirings 126 between which the second pad 122 is not disposed is substantially the same as a distance between the first side and the adjacent first wiring 126. The second pad 122 may have a third side opposite to the second side, the third side being directly connected to the first wiring 126 extending substantially parallel to the first side. The via in the first stacked via layer 143 is disposed away from the second side relative to the center of the second pad 122.

[0060] When the etchant flows along the first wiring 126, since the second pad 122 includes the adjacent portion 122-1 and the open portion 122-2, the printed circuit board according to the example can prevent the etchant from being concentrated on the second pad 122. In particular, unlike the case where the second pad has a circular shape, the adjacent portion 122-1 may be substantially parallel to the adjacent first wiring 126, thereby preventing the etchant from being concentrated on the second pad 122. In addition, the second pad 122 has the adjacent portion 122-1, and the open portion 122-2 may extend in a direction away from the position where the second pad 122 is connected to the first wiring 126. That is, in the printed circuit board according to the example, the second pad 122 may be asymmetric with respect to the first stacked via layer 143. Thus, since the second pad 122 has the adjacent portion 122-1 and the open portion 122-2, it is possible to prevent defects from occurring in the second pad 122 in the operation of the etchant penetrating to form the second pad 122.

[0061] The distance d2 between the adjacent portion 122-1 of the second pad 122 and the first wiring 126 adjacent to the second pad 122 may be substantially equal to the distance d3 between the two adjacent first wirings 126. The distance between the adjacent portion 122-1 of the second pad 122 and the adjacent first wiring 126 may be measured by photographing the cut section of the printed circuit board using a scanning microscope. The distance between a specific component may be the average value of the values ​​obtained by measuring at any five points, but the present disclosure is not necessarily limited thereto. The adjacent portion 122-1 of the second pad 122 may be substantially parallel to the adjacent first wiring 126, so that the distance d2 between the adjacent portion 122-1 of the second pad 122 and the adjacent first wiring 126 may mean the average distance between the adjacent portion 122-1 of the second pad 122 and the adjacent first wiring 126. In the same sense, the distance d3 between the two adjacent first wirings 126 may mean the average distance between the two adjacent first wirings 126. The distance d2 between the adjacent portion 122-1 of the second pad 122 and the adjacent first wiring 126 and the distance d3 between the two adjacent first wirings 126 can be measured on substantially the same plane. That is, the distance between the two adjacent first wirings 126 can be measured as the distance between the adjacent first wiring 126 adjacent to the adjacent portion 122-1 of the second pad 122 and the extension line of the virtual line of the first wiring 126 adjacent to the adjacent first wiring 126.

[0062] Reference Figure 7B, the first pad 121 may include an adjacent portion 121-1 and an open portion 121-2, the adjacent portion 121-1 being an area of ​​the first pad 121 adjacent to the first wiring 126, and the open portion 121-2 being an area of ​​the first pad 121 not adjacent to the first wiring 126 and not connected to other wirings. In addition, the first pad 121 may be adjacent to the first pattern 124 having a planar shape. The open portion 121-2 of the first pad 121 is not adjacent to the first pattern 124 yet.

[0063] The distance d1 between the adjacent portion 121-1 of the first pad 121 and the adjacent first wiring 126 may be substantially equal to the distance d3 between two adjacent first wirings 126. In addition, the distance between the first pattern 124 and the first pad 121 may also be substantially equal to the distance d1 between the adjacent portion 121-1 of the first pad 121 and the adjacent first wiring 126.

[0064] Since the first pad 121 has the adjacent portion 121-1 and the open portion 121-2, the printed circuit board according to the example can prevent the defect that the etchant is concentrated on the first pad 121 and the first pad 121 is over-etched, and the first pad 121 can also have an asymmetric shape relative to the position where the first stacked via layer 143 is formed.

[0065] Figure 5B , Figure 6B and Figure 7B Only a portion of the first wiring layer 120 of the printed circuit board according to the example is shown, and the arrangement and shape of the first wiring 126, the first pad 121, the second pad 122 and the first pattern 124 are not limited thereto. The first pad 121 and the second pad 122 may be connected to the first stacked via layer 143, and the first pad 121 may include an adjacent portion 121-1 and an open portion 121-2, the adjacent portion 121-1 being a region of the first pad 121 substantially parallel to the adjacent first wiring 126, and the open portion 121-2 being a region of the first pad 121 not adjacent to the first wiring 126; the second pad 122 may include an adjacent portion 122-1 and an open portion 122-2, the adjacent portion 122-1 being a region of the second pad 122 substantially parallel to the adjacent first wiring 126, and the open portion 122-2 being a region of the second pad 122 not adjacent to the first wiring 126. Therefore, when the etchant is concentrated on the first pad 121 and the second pad 122, it is ensured that the area of ​​the pad on which the first stacked via layer 143 is to be formed is not etched, thereby realizing the first wiring layer 120 including a fine pattern at a low cost on the core layer 110. In addition, the content described in this article about the first pad 121 can also be applied to the second pad 122, and vice versa.

[0066] Figure 8is a schematic cross-sectional view of a printed circuit board according to another example.

[0067] Reference Figure 8 According to another example, the side surface of the first pad 121, the side surface of the second pad 122, and the side surface of the first wiring 126 of the printed circuit board may be a curved surface. Such a configuration may be a result of forming a first wiring layer on the core layer 110 using one of a subtractive method and a sealing method, but the present disclosure is not limited thereto. In addition, there may be at least one first pad 121, at least one second pad 122, and / or at least one first wiring 126 that satisfies the width relationship described below.

[0068] The width W11 of the lower surface of the first pad 121 may be greater than or equal to the width W12 of the upper surface of the first pad 121, and the width W13 of the central portion of the first pad 121 may be less than the width W12 of its upper surface. That is, the first pad 121 may satisfy the relationship: W11≥W12>W13. Such a configuration may be the result of adjusting the penetration degree of the etchant in the operation of removing the unnecessary portion by setting an etching mask and then injecting an etchant to form the first pad 121. The shape of the pad may be adjusted using an etching additive in the etchant, and the width W12 of the upper surface of the first pad 121 may be formed to be greater than the width W13 of its central portion, so that when the first stacked via layer 143 is disposed on the first pad 121, alignment may be more favorable.

[0069] In the same sense, the width W21 of the lower surface of the second pad 122 may also be greater than or equal to the width W22 of the upper surface of the second pad 122, and the width W23 of the central portion of the second pad 122 may be less than the width W22 of the upper surface thereof. In other words, the second pad 122 may satisfy the relationship: W21 ≥ W22 > W23. Therefore, when the first stacked via layer 143 is disposed on the second pad 122, alignment may also be more favorable.

[0070] When patterning the first pad 121 and the second pad 122, the first wiring 126 may be formed simultaneously so that the width W31 of the lower surface of the first wiring 126 may also be greater than or equal to the width W32 of the upper surface of the first wiring 126, and the width W33 of the central portion of the first wiring 126 may be less than the width W32 of the upper surface thereof. That is, the first wiring 126 may satisfy the relationship: W31≥W32>W33.

[0071] The first buildup wiring layer 142 and the second buildup wiring layer 152 may be manufactured using a method different from the method of the first wiring layer 120, so that the first buildup wiring layer 142 and the second buildup wiring layer 152 may not have the same side surface shape as the side surface shape of the first wiring layer 120. However, the present disclosure is not necessarily limited thereto. When the first buildup wiring layer 142 and / or the second buildup wiring layer 152 are formed using the method of forming the first wiring layer 120, the first buildup wiring layer 142 and / or the second buildup wiring layer 152 may also have the same side surface shape as the side surface shape of the first wiring layer 120.

[0072] Except for the shape of the side surface of the first wiring layer 120, the configuration of the printed circuit board according to the example, such as the configuration of the first pad 121, the second pad 122 and the first wiring 126, can be applied to the printed circuit board according to another example, so repeated description thereof will be omitted.

[0073] As used herein, the shape in a cross section may refer to the cross-sectional shape of an object in a cross section formed by vertically cutting the object, or may refer to the shape of the object when the object is viewed from a side perspective. In addition, the shape on a plane may be the shape of the object in a cross section formed by horizontally cutting the object, or may be the plane shape of the object when the object is viewed from a top or bottom perspective.

[0074] As used herein, for convenience, upper side, upper part, upper surface, etc. are used to indicate an upward direction toward a surface on which an electronic component can be mounted based on a cross section of the drawings, and lower side, lower part, lower surface, etc. are used to indicate the opposite direction. However, the above directions are defined for convenience of description. Therefore, it should be understood that the scope of the claims is not particularly limited by the above directions.

[0075] As used herein, the term "connected" may refer not only to "direct connection" but also to "indirect connection" through an adhesive layer or the like. The term "electrically connected" may include both the case where components are "physically connected" and the case where components are "not physically connected." In addition, the terms "first," "second," and the like may be used to distinguish one component from another, and may not limit the order and / or importance associated with the components, etc. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the examples.

[0076] As used herein, process errors or position deviations, measurement errors, etc. occurring in the manufacturing process may be included. For example, "substantially vertical" may include not only the case of "completely vertical" but also the case of "approximately vertical". In addition, "substantially coplanar" may include not only the case of "completely coplanar" but also the case of "approximately coplanar".

[0077] As used herein, the same insulating material may mean not only the same insulating material, but also the same type of insulating material. Therefore, the same insulating material may also mean that the composition of the insulating material may be substantially the same, but its specific composition ratio may vary slightly.

[0078] As used herein, the term "example" is provided to emphasize a particular feature, structure, or characteristic, and does not necessarily refer to the same example. In addition, in one or more examples, the particular characteristics or features may be combined in any suitable manner. For example, the content described in a particular example may also be used in other examples even if it is not described in other examples unless it is described as being contrary to or inconsistent with the content in other examples.

[0079] The terms used herein are only used to describe specific examples, and the present disclosure is not limited thereby. Unless the context clearly indicates otherwise, the singular forms as used herein are intended to include the plural forms as well.

[0080] While examples have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Core layer; A plurality of first wirings are arranged on the core layer; A first pad is disposed on the core layer, the first pad includes an adjacent portion and an open portion, the side of the adjacent portion is disposed substantially parallel to the side of a first wiring adjacent to the first pad among the plurality of first wirings, and the open portion is disposed non-parallel to a first wiring adjacent to the first pad among the plurality of first wirings; as well as a first buildup insulating layer, disposed on the core layer, the first buildup insulating layer covering at least a portion of the plurality of first wirings and the first pad; The core layer includes an insulating material different from an insulating material of the first buildup insulating layer.

2. The printed circuit board according to claim 1, wherein: The plurality of first wirings and the first pads are disposed on each of an upper surface and a lower surface of the core layer.

3. The printed circuit board according to claim 2, wherein: The plurality of first wirings and the first pads protrude from each of the upper surface and the lower surface of the core layer and are embedded in the first buildup insulating layer.

4. The printed circuit board according to claim 1, further comprising: A second pad is disposed on the core layer, the second pad includes an adjacent portion and an open portion, the side of the adjacent portion of the second pad is disposed substantially parallel to the side of a first wiring adjacent to the second pad among the plurality of first wirings, and the open portion of the second pad is disposed non-parallel to the first wiring adjacent to the second pad among the plurality of first wirings; as well as A through via is connected to the second pad, and the through via passes through the core layer.

5. The printed circuit board according to claim 4, wherein: The width of the first pad is smaller than the width of the second pad, and A line width of each of the plurality of first wirings is smaller than a width of the first pad.

6. The printed circuit board according to claim 4, wherein: The width of the upper surface of the first pad is less than or equal to the width of the lower surface of the first pad, and the width of the central portion of the first pad is less than the width of the upper surface of the first pad, and A width of an upper surface of the second pad is less than or equal to a width of a lower surface of the second pad, and a width of a central portion of the second pad is less than a width of the upper surface of the second pad.

7. The printed circuit board according to claim 6, wherein: The width of the upper surface of at least one first wiring among the multiple first wirings is less than or equal to the width of the lower surface of the at least one first wiring, and the width of the central portion of the at least one first wiring is less than the width of the upper surface of the at least one first wiring.

8. The printed circuit board according to claim 4, wherein: A distance between an adjacent portion of the first pad and an adjacent first wiring adjacent to the first pad is equal to a distance between the adjacent first wiring and a first wiring adjacent to the adjacent first wiring, and A distance between an adjacent portion of the second pad and another adjacent first wiring adjacent to the second pad is equal to a distance between the another adjacent first wiring and a first wiring adjacent to the another adjacent first wiring.

9. The printed circuit board according to claim 1, further comprising: A first buildup wiring layer, disposed on the first buildup insulating layer; as well as A first buildup via layer passes through at least a portion of the first buildup insulating layer to connect the first buildup wiring layer and the first pad to each other.

10. The printed circuit board according to claim 9, further comprising: a second stacked insulating layer, disposed on the first stacked insulating layer; a second buildup wiring layer, disposed on the second buildup insulating layer; as well as A second buildup via layer passes through at least a portion of the first buildup insulating layer to connect the second buildup wiring layer and the first buildup wiring layer to each other.

11. The printed circuit board according to claim 1, further comprising: a second wiring connected to the first pad, The open portion of the first pad is disposed on an opposite side of a region of the first pad connected to the second wiring.

12. The printed circuit board according to claim 11, further comprising: a first stacked via, connected to the first pad, The second wiring is arranged closer to the first stacked via than the open portion of the first pad.

13. A printed circuit board, comprising: a first insulating layer; A plurality of first wirings are respectively arranged on the upper surface and the lower surface of the first insulating layer; as well as a pad disposed on each of the upper surface and the lower surface of the first insulating layer, the pad comprising an adjacent portion and an open portion, the side of the adjacent portion being disposed substantially parallel to the side of an adjacent first wiring line adjacent to the pad among the plurality of first wiring lines, and the open portion being disposed non-parallel to the adjacent first wiring line, The distance between the adjacent portion of the pad and the adjacent first wiring is equal to the distance between the adjacent first wiring and a first wiring adjacent to the adjacent first wiring.

14. The printed circuit board according to claim 13, further comprising: a second insulating layer disposed on each of the upper surface and the lower surface of the first insulating layer, the second insulating layer covering at least a portion of the plurality of first wirings and the pad; as well as A first via hole passes through at least a portion of the second insulating layer, and the first via hole is connected to the pad.

15. The printed circuit board according to claim 14, further comprising: a second wiring, connected to the pad, The open portion of the pad is disposed on an opposite side of a region of the pad connected to the second wiring.

16. The printed circuit board according to claim 15, further comprising: The first stacked via, connected to the pad, The second wiring is arranged closer to the first stacked via than the open portion of the pad.

17. The printed circuit board according to claim 13, further comprising: a first pattern, disposed on the first insulating layer, wherein the first pattern has a planar shape, The distance between the first pattern and the pad is equal to the distance between an adjacent portion of the pad and the adjacent first wiring.

18. A printed circuit board, comprising: Core layer; A first wiring is arranged on the core layer; A pad is disposed on the core layer, and the pad has a rectangular shape, such that: A pair of first sides of the pad are substantially parallel to sides of an adjacent first wiring adjacent to the pad, and The second side of the pad extending from and connecting the pair of first sides is not parallel to the side of the adjacent first wiring, The distance between two adjacent first wirings between which the pad is not arranged is the same as the distance between the first side and the adjacent first wirings.

19. The printed circuit board according to claim 18, wherein The pad has a third side opposite to the second side, the third side being directly connected to a second wiring disposed on the core layer, the second wiring extending substantially parallel to the first side. 20 . The printed circuit board of claim 18 , further comprising a via hole connected to the pad and disposed away from the second side relative to a center of the pad.

21. The printed circuit board of claim 18, further comprising a through via penetrating the core layer and connected to the pad.

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