Semiconductor element structure with reduced critical dimension and preparation method thereof

Abstract

The invention provides a semiconductor element structure and a preparation method of the semiconductor element structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate; a first dielectric layer disposed over the first conductive layer; an energy removable layer conformally deposited on the first dielectric layer in a pattern dense region; a patterned mask disposed over the first dielectric layer and the energy removable layer, where the patterned mask includes a first pattern disposed in the pattern dense region, a second pattern disposed over a sidewall of the first pattern, and a third pattern disposed in a pattern sparse region; and a plurality of processing regions disposed on an upper surface of the energy removal layer between two adjacent first patterns and also disposed on the first patterns. A second critical dimension of the second pattern is smaller than a first critical dimension of the first pattern.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. patent application No. 18 / 380,312 (i.e., the priority date is "October 16, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device structure and a method for manufacturing the same, and more particularly to a semiconductor device structure with a reduced critical dimension and a method for manufacturing the same. Background Art

[0004] Semiconductor components are essential to many modern applications. As electronic technology advances, semiconductor components are becoming smaller and smaller while providing more powerful functions and containing more integrated circuits. Due to the miniaturization of semiconductor component size, various types and sizes of semiconductor components providing different functions are integrated and packaged into a single module. In addition, many manufacturing steps are implemented to integrate various types of semiconductor elements.

[0005] Reducing the size of integrated circuits (ICs) can improve performance, increase capacity and / or reduce costs. Each reduction in size requires more complex technology to form the IC. Photolithography is generally used to pattern ICs on a substrate. An example feature of an IC is a line of a material, which can be a metal, semiconductor or insulator. The line width is the width of the line, and the pitch is the distance between two adjacent lines. The pitch is defined as the distance between the same point on two adjacent lines. The pitch is equal to the sum of the line width and the pitch. However, due to factors such as optics and the wavelength of light or radiation, photolithography has a minimum pitch below which a particular photolithography may not be able to reliably form multiple features. Therefore, the minimum pitch of photolithography limits the reduction of feature size. Similarly, patterning tools designed to create vias or line interconnects of 100nm or wider are generally unable to create smaller vias. Therefore, as component sizes decrease to such small sizes, current photolithography processes face the challenge of creating patterns with the required critical dimensions (CD).

[0006] Currently, the fabrication techniques for reducing the critical dimension of conformal layers (e.g., size-reduced patterns in hard masks) include atomic layer deposition (ALD) using an etchable material (e.g., silicon oxide). However, the quality of the deposited material can be difficult to control, resulting in low density, poor mechanical strength, and reduced tolerance to subsequent etching chemistries. High stress in the ALD oxide can also cause bowing and deformation of multiple underlying layers, as well as delamination due to poor adhesion and insufficient chemical compatibility. In addition, the oxide material requires a wet cleaning process to be removed after etching. Wet cleaning is an isotropic process that typically results in CD loss and undercut issues. In order to avoid redesigning current lithography tools, new methods are needed to reduce the critical dimensions of IC lines and through-hole interconnects etched into a substrate.

[0007] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present disclosure. Summary of the invention

[0008] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer, which is disposed above a semiconductor substrate; a first dielectric layer, which is disposed above the first conductive layer; an energy removable layer, which is conformally deposited above a first dielectric layer in a pattern-dense area, wherein an upper surface of the energy removable layer is substantially coplanar with an upper surface of the first dielectric layer; a patterned mask, which is disposed above the first dielectric layer and the energy removable layer, wherein the patterned mask includes a first pattern, a second pattern, and a third pattern, wherein the first pattern is disposed in the pattern-dense area, the second pattern is disposed above a side wall of the first pattern, and the third pattern is disposed in a pattern-sparse area; and a plurality of processing areas, which are disposed on the upper surface of the energy removal layer and are located between two adjacent first patterns, and are disposed on a pattern upper surface of the first pattern.

[0009] In one embodiment, the first pattern has a first critical dimension and the second pattern has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension. In one embodiment, a material of the first pattern is silicon, which is one of amorphous silicon or polycrystalline silicon. In one embodiment, a material of the second pattern is silicon oxide. In one embodiment, a material of the first pattern is the same as a material of the third pattern.

[0010] In one embodiment, the second pattern is made by a non-photolithography technique. In one embodiment, the second pattern is made by thermal oxidation.

[0011] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate; an energy removable layer disposed on the first conductive layer; a plurality of first patterns independently disposed on the energy removable layer; a plurality of second patterns disposed on the sidewalls of the first patterns; and a plurality of processing areas disposed on an upper surface of the energy removable layer and between two adjacent first patterns, and also disposed on a pattern upper surface of the first patterns.

[0012] In one embodiment, each first pattern has a first critical dimension and each second pattern has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension. In one embodiment, a material of each first pattern is silicon, which is one of amorphous silicon or polycrystalline silicon. In one embodiment, a material of the second pattern is silicon oxide.

[0013] In one embodiment, the second patterns are fabricated using a non-photolithography technique. In one embodiment, the second patterns are fabricated using a thermal oxidation technique.

[0014] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a first conductive layer above a semiconductor substrate; forming a first dielectric layer above the first conductive layer; replacing a portion of the first dielectric layer with an energy-removable layer; forming a first pattern above the energy-removable layer, wherein the first pattern has a first critical dimension; forming a plurality of processing areas on a pattern upper surface of the first pattern and on a portion of an upper surface of the energy-removable layer exposed by the first pattern; and forming a second pattern on each sidewall of the first pattern but outside the processing areas, wherein the second pattern has a second critical dimension that is smaller than the first critical dimension.

[0015] In one embodiment, a material of the first pattern is silicon, which is one of amorphous silicon or polycrystalline silicon. In one embodiment, a material of the second pattern is silicon oxide. In one embodiment, the manufacturing technology of the second pattern is non-photolithography technology. In one embodiment, the manufacturing technology of the second pattern is thermal oxidation. In one embodiment, the preparation method also includes forming a third pattern above the first dielectric layer while forming the first pattern. In one embodiment, the first pattern is formed in a pattern-dense area, and the third pattern is formed in a pattern-sparse area. In one embodiment, the preparation method also includes performing an etching process to form a first opening in the energy removable layer and forming a second opening in the first dielectric layer, wherein the first opening is located in the pattern-dense area and the second opening is located in the pattern-sparse area. In one embodiment, a patterned mask is composed of a first pattern, a second pattern, and a third pattern, wherein after the first opening and the second opening are formed, the patterned mask is removed. In one embodiment, the first opening has a first width defined as a top-most width of the first opening, and the second opening has a second width defined as a top-most width of the second opening, wherein the second width is greater than the first width. In one embodiment, the preparation method further includes depositing a first lining layer on the energy removable layer and the dielectric layer, wherein the first lining layer completely fills the first opening to form a first conductive plug, and after removing the patterned mask, the first lining layer partially fills the second opening. In one embodiment, the first lining layer is integrally formed with the first conductive plug, and the first lining layer and the first conductive plug include the same material. In one embodiment, the material of the first lining layer and the first conductive plug includes a manganese-containing material. In one embodiment, the material of the first lining layer and the first conductive plug includes copper manganese.

[0016] In one embodiment, the preparation method further includes forming a second conductive plug in a remaining portion of the second opening. In one embodiment, the preparation method further includes forming a second conductive layer above the first lining layer and the second conductive plug. In one embodiment, the etching process further forms a third opening in the pattern dense area and adjacent to the first opening, and forms a fourth opening in the pattern sparse area and adjacent to the second opening, wherein the third opening has a third width defined as a topmost width of the third opening, the fourth opening has a fourth width defined as a topmost width of the fourth opening, and the fourth width is greater than the third width. In one embodiment, the fourth opening in the pattern sparse area is wider than the third opening in the pattern dense area. In one embodiment, a material of the first conductive plug includes copper manganese (CuMn), and a material of the second conductive plug includes copper (Cu). In one embodiment, the preparation method further includes partially removing the lining layer in the second opening to expose the first conductive layer before forming the second conductive plug. In one embodiment, the second conductive plug and the second conductive layer are formed simultaneously in the same process step. In one embodiment, the manufacturing method further includes performing a heat treatment process after forming the second conductive layer to partially transform the energy removable layer into an air gap.

[0017] The present disclosure provides an embodiment of a semiconductor element structure and a method for making the same. The upper surface of the pattern and the upper surface exposed by the first pattern are processed (for example, damaged by ion implantation), so that the second pattern is selectively formed only on the sidewalls of the first pattern, excluding the processed areas. Therefore, the second pattern reduces the multiple gaps between the multiple features of the first pattern. That is, the first pattern and the second pattern are combined to form a new pattern with smaller gaps. Therefore, the resulting combined pattern of the semiconductor structure has a smaller critical dimension than the original first pattern. Since the manufacturing technology of the second pattern can include processes well known in the art, such as thermal oxidation, the methods and structures disclosed in the present disclosure can significantly reduce the critical dimensions of the pattern without the need for new technologies or tools, which can be very expensive and problematic. Therefore, by using the methods and structures provided by the present disclosure, ICs with reduced size features can be manufactured without significantly increasing costs.

[0018] In some embodiments, a semiconductor device structure includes a first conductive plug that penetrates a dielectric layer in a pattern-dense area; a lining layer that covers the dielectric layer and the first conductive plug; and a second conductive plug that penetrates the lining layer and the dielectric layer in a pattern-sparse area. The lining layer and the first conductive plug contain manganese, and the second conductive plug is separated from the dielectric layer by the lining layer. The manganese-containing conductive plug (i.e., the first conductive plug in the pattern-dense area) and the lining layer can be formed integrally, thereby reducing manufacturing costs. In addition, the lining layer can reduce or prevent the formation of voids in the subsequently formed conductive plug (i.e., the second conductive plug in the pattern-sparse area), thereby reducing contact resistance. As a result, the operating speed of the semiconductor device structure can be increased, which significantly improves overall device performance.

[0019] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] When with Figure 1 When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0021] Figure 1 is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0022] Figure 2 It is a schematic flow chart illustrating a method for preparing a semiconductor element according to some embodiments of the present disclosure.

[0023] Figure 3 is a schematic cross-sectional view illustrating an intermediate stage of sequentially forming a first conductive layer and a first dielectric layer on a semiconductor substrate during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0024] Figure 4 is a schematic cross-sectional view illustrating an intermediate stage of etching a first dielectric layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0025] Figure 5is a schematic cross-sectional view illustrating an intermediate stage of forming an energy removable layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0026] Figure 6 is a schematic cross-sectional view illustrating an intermediate stage of partially removing an energy removable layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0027] Fig. 7A is a schematic cross-sectional view illustrating an intermediate stage of forming a first pattern over an energy removable layer and a first dielectric layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 7B is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of processing regions above a first pattern and an energy removable layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 7C is a schematic cross-sectional view illustrating an intermediate stage of forming a second pattern on a sidewall of a first pattern during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0030] Figure 8 2 is a schematic cross-sectional view illustrating an intermediate stage of etching an energy removable layer and a first dielectric layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0031] Fig. 9 is a schematic cross-sectional view illustrating an intermediate stage of removing a first pattern and a second pattern during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0032] Fig.10 is a schematic cross-sectional view illustrating an intermediate stage of depositing a first liner layer and forming a plurality of first conductive plugs during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0033] Fig.11 is a schematic cross-sectional view illustrating an intermediate stage of forming a patterned mask over a first liner layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0034] Fig.12 is a schematic cross-sectional view illustrating an intermediate stage of partially removing the first liner layer to expose the first conductive layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0035] Fig.13 is a schematic cross-sectional view illustrating an intermediate stage of removing a first patterned mask during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0036] Fig.142 is a schematic cross-sectional view illustrating an intermediate stage of forming a plurality of second conductive plugs and a second conductive layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0037] Fig.15 is a schematic cross-sectional view illustrating an intermediate stage of forming a second dielectric layer over a second conductive layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0038] Fig.16 is a schematic cross-sectional view illustrating an intermediate stage of etching a second dielectric layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0039] Fig.17 is a schematic cross-sectional view illustrating an intermediate stage of forming a second liner layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0040] Fig.18 is a schematic cross-sectional view illustrating an intermediate stage of forming a third liner layer during formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0041] Fig.19 is a schematic cross-sectional view illustrating an intermediate stage of forming a first conductive structure, a second conductive structure, and a third conductive layer during the formation of a semiconductor device structure according to some embodiments of the present disclosure.

[0042] Fig. 20 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0043] Fig.21 is a partial schematic diagram illustrating an example integrated circuit including a memory cell array according to some embodiments of the present disclosure.

[0044] Description of reference numerals:

[0045] 10: Preparation method

[0046] 50: Memory unit

[0047] 51: Field Effect Transistor

[0048] 53: Capacitor

[0049] 55: Drain

[0050] 57: Source

[0051] 59: Gate

[0052] 100: Semiconductor component structure

[0053] 101: Semiconductor substrate

[0054] 103: First conductive layer

[0055] 105: First dielectric layer

[0056] 110: Opening

[0057] 113: Energy Removable Layer

[0058] 113': Energy Removable Structure

[0059] 115: Patterned Mask

[0060] 120a: Open

[0061] 120b: Open

[0062] 123: First lining layer

[0063] 123a: first conductive plug

[0064] 125: Patterned Mask

[0065] 127: Second conductive plug

[0066] 129: Second conductive layer

[0067] 130: Processing area

[0068] 131: Second dielectric layer

[0069] 140a: Opening

[0070] 140b: Opening

[0071] 143: Second lining layer

[0072] 145: Third lining layer

[0073] 147a: first conductive structure

[0074] 147b: Second conductive structure

[0075] 149: The third conductive layer

[0076] 160: Air Gap

[0077] 200: Semiconductor component structure

[0078] 1000: Memory element

[0079] 1051: Upper surface

[0080] 1131: Upper surface

[0081] 1151: The First Pattern

[0082] 1152: Second Pattern

[0083] 1153: The third pattern

[0084] 1154: Sidewall

[0085] 1155: Patterned upper surface

[0086] A: Pattern-dense area

[0087] B: Sparse pattern area

[0088] BL: Bit Line

[0089] CD1: First critical dimension

[0090] CD2: Second critical dimension

[0091] D1: Distance

[0092] D2: Distance

[0093] D3: Distance

[0094] D4: Distance

[0095] D5: Depth

[0096] D6: Depth

[0097] H1: Height

[0098] H2: Height

[0099] S11: Steps

[0100] S13: Steps

[0101] S15: Steps

[0102] S17: Steps

[0103] S19: Steps

[0104] S21: Steps

[0105] S23: Steps

[0106] S25: Steps

[0107] S27: Steps

[0108] S151: Steps

[0109] S153: Steps

[0110] S155: Steps

[0111] W1: Width

[0112] W2: Width

[0113] W3: Width

[0114] W4: Width

[0115] W5: Width

[0116] W6: Width

[0117] WL: character line DETAILED DESCRIPTION

[0118] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0119] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0120] Figure 1 FIG. 1 is a cross-sectional view schematically illustrating a semiconductor device 100 according to some embodiments of the present disclosure. Figure 1 As shown, the semiconductor device structure 100 includes a first conductive layer 103 disposed on a semiconductor substrate 101, a first dielectric layer 105 disposed on the first conductive layer 103, an energy removable layer 113 conformally deposited on the first dielectric layer 105, and a patterned mask 115 disposed on the first dielectric layer 105 and the energy removable layer 113. According to some embodiments, Figure 1 In addition, the semiconductor device structure 100 has a pattern-dense region A and a pattern-sparse region B. In order to clearly illustrate the present invention, Figure 1 The dotted line in the middle indicates a boundary between the pattern-dense area A and the pattern-sparse area B. In some embodiments, an upper surface 1131 of the energy-removable layer 113 is substantially coplanar with an upper surface 1051 of the first dielectric layer 105 .

[0121] In some embodiments, the patterned mask 115 has a first pattern 1151, a second pattern 1152, and a third pattern 1153. The first pattern 1151 is disposed in the pattern-dense area A, the second pattern 1152 is disposed above a sidewall 1154 of the first pattern 1151, and the third pattern 1153 is disposed in the pattern-sparse area B. In some embodiments, the patterned mask 115 has a plurality of first patterns 1151, a plurality of second patterns 1152, and a plurality of third patterns 1153. The first patterns 1151 are individually disposed in the pattern-dense area A, each second pattern 1152 is disposed above a sidewall 1154 of one of the first patterns 1151, and the third patterns 1153 are individually disposed in the pattern-sparse area B.

[0122] As Figure 1 shown, the first pattern 1151 is disposed on the upper surface 1131 of the energy-removable layer 113. The energy-removable layer 113 has a plurality of processing regions 130 that are disposed on the upper surface 1131 and are located between adjacent pairs of the first patterns 1151. The first pattern 1151 has a pattern upper surface 1155 and sidewalls 1154. The plurality of processing regions 130 are disposed on the pattern upper surface 1155. The first pattern 1151 has a first critical dimension CD1, which can be defined as a minimum distance between a plurality of features of the first pattern 1151.

[0123] The second pattern 1152 is disposed on the sidewall 1154 of the first pattern 1151. The second pattern 1152 has a second critical dimension CD2, which is smaller than the first critical dimension CD1 of the first pattern 1151. The second pattern 1152 reduces the gap between the features of the first pattern 1151, which results in a smaller second critical dimension CD2 (CD2 < CD1), thereby reducing the critical dimension CD. The method for fabricating the semiconductor element structure 100 according to some embodiments of the present invention is described in detail below.

[0124] Fig. 20 is a cross-sectional schematic diagram illustrating a semiconductor element structure according to some embodiments of the present disclosure. As Fig. 20 shown, according to some embodiments, the semiconductor element structure 200 includes a first conductive layer 103 disposed above a semiconductor substrate 101, a first dielectric layer 105 disposed above the first conductive layer 103, a second conductive layer 129 disposed above the first dielectric layer 105, a second dielectric layer 131 disposed above the second conductive layer 129, and a third conductive layer 149 disposed above the second dielectric layer 131. In addition, the semiconductor element structure 200 has a pattern-dense area A and a pattern-sparse area B. For the sake of clearly illustrating the present invention, Fig.19 the dashed line in the middle is used to indicate a boundary between the pattern-dense area A and the pattern-sparse area B.

[0125] The semiconductor device structure 200 includes a plurality of first conductive plugs 123a penetrating the first dielectric layer 105 in the pattern-dense area A. In addition, the semiconductor device structure 200 includes a plurality of energy-removable structures 113' disposed in the first dielectric layer 105 in the pattern-dense area A. In some embodiments, the first conductive plugs 123a are surrounded by the energy-removable structures 113', and each energy-removable structure 113' includes an air gap 160.

[0126] In some embodiments, the air gap 160 is surrounded by the energy removable structure 113'. Fig. 20 The cross-sectional view of FIG. 1 shows four energy removable structures 113', but the four energy removable structures 113' may be connected to each other in different cross-sectional views. Similar to the energy removable structure 113', Fig. 20 The four air gaps 160 shown in the cross-sectional view may also be connected to each other in different cross-sectional views. It should be understood that the number of energy removable structures 113 ′ and air gaps 160 may be adjusted according to the design requirements of the semiconductor device structure 200 .

[0127] Please still refer to Fig. 20 The semiconductor device structure 200 includes a first liner layer 123 disposed between the first dielectric layer 105 and the second conductive layer 129, wherein the energy removable structure 113' and the first conductive plug 123a are covered by the first liner layer 123. In some embodiments, a dotted line indicating a boundary between the first conductive plug 123a and the first liner layer 123 is used to illustrate the present disclosure. There is no obvious interface between the first conductive plug 123a and the first liner layer 123.

[0128] The semiconductor device structure 200 further includes a plurality of second conductive plugs 127 located in the pattern sparse region B, and the second conductive plugs 127 penetrate the first liner layer 123 and the first dielectric layer 105. In some embodiments, in the pattern sparse region B, the first liner layer 123 extends between the first dielectric layer 105 and the second conductive plugs 127. In some embodiments, the second conductive plugs 127 are separated from the first dielectric layer 105 by the first liner layer 123.

[0129] In addition, the semiconductor device structure 200 includes a second liner layer 143, a third liner layer 145, a first conductive structure 147a, and a second conductive structure 147b, all of which are disposed between the second conductive layer 129 and the third conductive layer 149. In some embodiments, the first conductive structure 147a is located in the pattern-dense region A, and the second conductive structure 147b is located in the pattern-sparse region B. In some embodiments, portions of the second liner layer 143 and the third liner layer 145 are sandwiched between the second dielectric layer 131 and the third conductive layer 149. In some embodiments, the third liner layer 145 is disposed above the second liner layer 143, and the sidewalls and lower surfaces of the first conductive structure 147a and the second conductive structure 147b are covered by the third liner layer 145.

[0130] In some embodiments, the semiconductor device structure 200 is a dynamic random access memory (DRAM). In such embodiments, the conductive layers (e.g., the first conductive layer 103, the second conductive layer 129, and the third conductive layer 149) can be used as bit lines (BL), storage nodes, and / or wiring layers of the DRAM, and the conductive plugs (e.g., the first conductive plug 123a and the second conductive plug 127) and the conductive structures (e.g., the first conductive structure 147a and the second conductive structure 147b) can be used as bit line contact plugs, capacitor contact plugs, and / or interconnect structures of the DRAM.

[0131] In some embodiments, the first conductive plug 123a in the pattern dense area A is integrally formed with the first liner layer 123. In some embodiments, the first conductive plug 123a and the first liner layer 123 include a same material, and the first conductive plug 123a and the second conductive plug 127 include different materials. In some embodiments, the first conductive plug 123a and the first liner layer 123 include a manganese-containing material.

[0132] For example, according to some embodiments, the first liner layer 123 and the first conductive layer 123a both contain (or include) copper manganese (CuMn), and the first conductive layer 103, the second conductive layer 129, and the second conductive plug 127 all contain (or include) copper (Cu). In addition, in some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 all contain (or include) copper (Cu), the second liner layer 143 contains (or includes) manganese-rich manganese silicon (MnSi) or manganese (Mn), and the third liner layer 145 contains (or includes) copper manganese (CuMn).

[0133] Figure 21 is a flow chart illustrating a method 10 for preparing a semiconductor device (i.e., a semiconductor device structure 100 / 200) according to some embodiments of the present disclosure. According to some embodiments, the method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, and S27. Figure 2 Steps S11 to S27 are described in detail.

[0134] Figures 3 to 8 A cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure 100 according to some embodiments, Figures 9 to 19 A cross-sectional view illustrating an intermediate stage of forming a semiconductor device structure 200 . The semiconductor device structure 100 is an intermediate portion of the semiconductor device structure 200 .

[0135] like Figure 3 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP.

[0136] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a GOI substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0137] Please still refer to Figure 3 According to some embodiments, a first conductive layer 103 is formed on the semiconductor substrate 101, and a first dielectric layer 105 is formed on the first conductive layer 103. Figure 2 As shown in steps S11 and S13 of the preparation method 10 shown.

[0138] In some embodiments, the first conductive layer 103 includes copper (Cu), and the manufacturing technology of the first conductive layer 103 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or other applicable processes. In some embodiments, the first dielectric layer 105 includes silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials, and the manufacturing technology of the first dielectric layer 105 includes a deposition process, such as a CVD process, a PVD process, an ALD process, a spin coating process, or other applicable processes.

[0139] Next, according to some embodiments, Figure 4 As shown, the first dielectric layer 105 is etched to form an opening 110 exposing the first conductive layer 103. In some embodiments, the opening 110 is located in the pattern-dense area A. The formation of the opening 110 may include forming a patterned mask (not shown) over the first dielectric layer 105, and etching the first dielectric layer 105 while using the patterned mask as a mask. In addition, the etching process for forming the opening 110 may be a wet etching process, a dry etching process, or a combination thereof.

[0140] Then, according to some embodiments, Figure 5 As shown, the energy removable layer 113 is conformally deposited over the first dielectric layer 105. In some embodiments, the opening 110 (see Figure 4 )'s side walls and a lower surface are covered by the energy removable layer 113.

[0141] In some embodiments, the material of the energy removable layer 113 includes a base material and a decomposable porogen material that is substantially removed upon exposure to an energy source (e.g., heat). In some embodiments, the base material includes hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon oxide (SiO2), and the decomposable porogen material includes a porogen organic compound that can provide porosity to a space originally occupied by the energy removable layer 113 in a subsequent process. In addition, the energy removable layer 113 can be deposited by a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable processes.

[0142] Next, according to some embodiments, Figure 6As shown, a planarization process is performed on the energy removable layer 113 to remove a portion of the energy removable layer 113. The planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, or other applicable processes. After the planarization process, the upper surface 1131 of the energy removable layer 113 is substantially coplanar with the upper surface 1051 of the first dielectric layer 105. In some embodiments, Figures 4 to 6 During the intermediate stage shown, a portion of the first dielectric layer 105 in the pattern-dense area A is replaced by the energy-removable layer 113, and each step is as follows: Figure 2 As shown in step S15 of the preparation method 10 shown.

[0143] Next, according to some embodiments, Figures 7A to 7C As shown, a patterned mask 115 is formed over the energy removable layer 113 and the dielectric layer 105. In some embodiments, a portion of the energy removable layer 113 in the pattern-dense region A and a portion of the first dielectric layer 105 in the pattern-sparse region B are exposed through the patterned mask 115. The patterned mask 115 is composed of a first pattern 1151, a second pattern 1152, and a third pattern 1153.

[0144] In step S151, according to some embodiments, Fig. 7A As shown in , the first pattern 1151 is formed above the energy removable layer 113 in the pattern dense area A, and the third pattern 1153 is formed above the dielectric layer 105 in the pattern sparse area B. In some embodiments, the first pattern 1151 and the third pattern 1153 are formed simultaneously. As described above, the material of the first pattern 1151 can be silicon, more specifically amorphous silicon or polycrystalline silicon. The material of the third pattern 1153 can be silicon, more specifically amorphous silicon or polycrystalline silicon. In some embodiments, the material of the first pattern 1151 is the same as the material of the third pattern 1153. Step S151 can be performed using conventional photolithography technology, and the first critical dimension CD1 of the first pattern 1151 is limited by the photolithography technology used. Each step is as follows Figure 2 As shown in step S151 of the preparation method 10 shown.

[0145] In step S153, according to some embodiments, Figure 7BAs shown, a plurality of processing regions 130 are formed on the pattern upper surface 1155 of the first pattern 1151 and on the portion of the upper surface of the energy removable layer 113 exposed by the first pattern 1151. In one embodiment of the present disclosure, the formation of the processing region 130 may include an ion implantation process. Compared with conventional ion implantation for doping, the purpose of the ion implantation in this embodiment is to destroy the horizontal surface of the previously formed semiconductor structure, that is, the pattern upper surface 1155 and the upper surface 1131 exposed by the first pattern 1151, to form the processing region 130, so that the second pattern 1152 formed subsequently can exclude the processing region 130. Each step is as follows: Figure 2 As shown in step S153 of the preparation method 10 shown.

[0146] In step S155, according to some embodiments, Figure 7C As shown, the second pattern 1152 is formed on the sidewalls 1154 of the first pattern 1151. As previously described, the processing area 130 including all exposed horizontal surfaces is damaged, so the second pattern 1152 cannot be formed thereon. Therefore, the second pattern 1152 is formed only on the sidewalls 1154 of the first pattern 1151. In one embodiment, the formation of the second pattern 1152 may include thermal oxidation, and the first pattern 110 may include silicon. In some embodiments, the second pattern 1152 may be used as a gate oxide, which is typically silicon oxide. Thermal oxidation oxidizes the sidewalls 1154 of the first pattern 110 and forms a layer of silicon dioxide including the second pattern 1152; while other surfaces, such as the pattern upper surface 1155 and the exposed upper surface 1131 of the first pattern 110, are processed so that silicon dioxide cannot be formed thereon. In this embodiment, the aforementioned ion implantation may be used to damage the processing area 130 to limit the oxidation of the sidewalls 1154 of the first pattern 1151. The steps are as follows. Figure 2 As shown in step S155 in the preparation method 10 shown.

[0147] Since the manufacturing technology of the second pattern 1152 is not a photolithography technology, the second critical dimension CD2 is not limited by the technology used. For example, in the above embodiment, because thermal oxidation is well known to those skilled in the art, the manufacturing technology of the second pattern 115 includes thermal oxidation, so that the oxide layer of the sidewall 1154 of the first pattern 1151 can be easily controlled to reduce the first critical dimension CD1 of the first pattern 1151 to the second critical dimension CD2 of the second pattern 1152. That is, the second critical dimension CD2 is smaller than the first critical dimension CD1. Therefore, a smaller critical dimension can be achieved without adopting a new (and potentially defective and expensive) photolithography technology.

[0148] Then, according to some embodiments, Figure 8As shown, the energy removable layer 113 and the first dielectric layer 105 are etched using the patterned mask 115 as a mask, so that an opening (e.g., a first opening) 120a is formed in the energy removable layer 113, and an opening (e.g., a second opening) 120b is formed in the dielectric layer 105. In some embodiments, the opening 120a is located in the pattern dense area A, and the opening 120b is located in the pattern sparse area B. In some embodiments, the first conductive layer 103 is partially exposed through the openings 120a and 120b. The etching process can be a wet etching process, a dry etching process, or a combination thereof. Each step is as follows. Figure 2 As shown in step S17 of the preparation method 10 shown.

[0149] According to some embodiments, Fig. 9 As shown, after the openings 120a and 120b are formed, the patterned mask 115 is removed. In some embodiments, each opening 120a has a width W1, and each opening 120b has a width W2, wherein the width W2 is greater than the width W1. In some embodiments, the widths W1 and W2 are defined as the topmost widths of the openings 120a and 120b. In addition, in some embodiments, each adjacent pair of openings 120a has a distance D1 between them, and each adjacent pair of openings 120b has a distance D2 between them, wherein the distance D2 is greater than the distance D1.

[0150] Next, according to some embodiments, Fig.10 As shown, the first liner layer 123 is deposited over the energy removable layer 113 and the first dielectric layer 105. It should be understood that the opening 120a is completely filled with the first liner layer 123, and the portion of the first liner layer 123 located within the opening 120a forms a first conductive plug 123a. At the same time, each opening 120b is partially filled with the first liner layer 123, so that the remaining portion of the opening 120b is formed over the first liner layer 123. Each step is as follows: Figure 2 As shown in step S19 of the preparation method 10 shown.

[0151] In some embodiments, since the first liner layer 123 and the first conductive plug 123a are integrally formed, the first liner layer 123 and the first conductive plug 123a include the same material, such as a manganese-containing material. In some embodiments, the first liner layer 123 and the first conductive plug 123a contain (or include) copper manganese (CuMn). In addition, the manufacturing technology of the first liner layer 123 may include a deposition process, such as a CVD process, a PVD process, an ALD process, or other applicable processes.

[0152] Then, according to some embodiments, Fig.11As shown, a patterned mask 125 is formed on the first liner layer 123. In some embodiments, portions of the first liner layer 123 at the bottom of the opening 120b are exposed through the patterned mask 125.

[0153] Next, according to some embodiments, Fig.12 As shown, the patterned mask 125 is used as a mask to etch the first liner layer 123, so that the first conductive layer 103 is partially exposed through the opening 120b. The etching process can be a wet etching process, a dry etching process or a combination thereof. Each step is as follows Figure 2 As shown in step S21 of the preparation method 10 shown.

[0154] According to some embodiments, Fig.13 As shown, after the first conductive layer 103 is partially exposed through the opening 120 b in the pattern sparse region B, the patterned mask 125 is removed.

[0155] Next, according to some embodiments, Fig.14 As shown, the second conductive plug 127 is formed in the opening 120b in the pattern sparse area B (refer to Fig.13 ), and the second conductive layer 129 is formed on the first lining layer 123 and the second conductive plug 127. In some embodiments, the second conductive plug 127 and the second conductive layer 129 are integrally formed. Figure 2 As shown in step S23 of the preparation method 10 shown.

[0156] Specifically, in some embodiments, the second conductive plug 127 and the second conductive layer 129 are formed simultaneously in the same process step, such as a deposition process and a subsequent planarization process. The deposition process may be a CVD process, a PVD process, an ALD process, an MOCVD process, a sputtering process, an electroplating process, or other applicable processes. The planarization process may include a CMP process, an etch-back process, or other applicable processes. In addition, in some embodiments, the second conductive plug 127 and the second conductive layer 129 contain (or include) copper (Cu). In addition, in some embodiments, each pair of adjacent first conductive plugs 123a in the pattern dense area A has a distance D3, and each pair of adjacent second conductive plugs 127 in the pattern sparse area B has a distance D4, wherein the distance D4 is greater than the distance D3.

[0157] Then, according to some embodiments, Fig.15 As shown, the second dielectric layer 131 is formed on the second conductive layer 129. Some materials and processes for forming the second dielectric layer 131 are similar or the same as those for forming the first dielectric layer 105, and are not described in detail herein.

[0158] Next, according to some embodiments, Fig.16As shown, the second dielectric layer 131 is etched to form an opening 140a in the pattern dense area A and an opening 140b in the pattern sparse area B. In some embodiments, each of the openings 140a and 140b exposes a portion of the second conductive layer 129. The etching process used to form the openings 140a and 140b can be a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the opening 140a has a width W3, and the opening 140b has a width W4, wherein the width W4 is greater than the width W3. In some embodiments, the widths W3 and W4 are defined as the top widths of the openings 140a and 140b, respectively.

[0159] According to some embodiments, Fig.17 As shown, after the openings 140a and 140b are formed, the second liner layer 143 is conformally deposited over the dielectric layer 131 and covers the sidewalls and lower surfaces of the openings 140a and 140b. In some embodiments, the second liner layer 143 contains (or includes) manganese-rich manganese silicon (MnSi) or manganese (Mn). The manufacturing technology of the second liner layer 143 may include a deposition process, such as CVD, PVD, ALD, MOCVD, sputtering or electroplating.

[0160] Next, according to some embodiments, Fig.18 As shown, the third liner layer 145 is conformally deposited on the second liner layer 143. In some embodiments, the third liner layer 145 contains (or includes) copper manganese (CuMn). Some processes for forming the third liner layer 145 are similar or the same as the processes for forming the second liner layer 143, and are not described again.

[0161] Then, according to some embodiments, Fig.19 As shown, the first conductive structure 147a is formed in a remaining portion of the opening 140a, the second conductive structure 147b is formed in a remaining portion of the opening 140b, and the third conductive layer 149 is formed over the third liner layer 145, the first conductive structure 147a, and the second conductive structure 147b. In some embodiments, the first conductive structure 147a, the second conductive structure 147b, and the third conductive layer 149 are integrally formed.

[0162] In some embodiments, the first conductive structure 147a, the second conductive structure 147b and the third conductive layer 149 are formed simultaneously in the same process steps, such as a deposition process and a subsequent planarization process. The deposition process can be a CVD process, a PVD process, an ALD process, an MOCVD process, a sputtering process, an electroplating process or other applicable processes. The planarization process may include a CMP process, an etch-back process or other applicable processes. In addition, in some embodiments, the first conductive structure 147a, the second conductive structure 147b and the third conductive layer 149 contain (or include) copper (Cu).

[0163] In some embodiments, the opening 140b in the sparse pattern region B is wider than the opening 140a in the dense pattern region A (eg, Fig.16 As shown, the width W4 is greater than the width W3). Therefore, after forming the third liner layer 145, the width W6 of the remaining portion of the opening 140b is greater than the width W5 of the remaining portion of the opening 140a, and a depth D6 of the remaining portion of the opening 140b is greater than a depth D5 of the remaining portion of the opening 140a. As a result, according to some embodiments, Fig.19 As shown, a width W6 of the second conductive structure 147b is greater than a width W5 of the first conductive structure 147a, and a height H2 of the second conductive structure 147b is greater than a height H1 of the first conductive structure 147a.

[0164] According to some embodiments, please refer to Fig. 20 , a heat treatment process is performed to transform the energy removable layer 113 into the air gap 160 and the energy removable structure 113' surrounding the air gap 160. The energy removable structure 113' is the remaining portion of the energy removable layer 113 after the heat treatment process. In some embodiments, the air gap 160 is surrounded by the energy removable structure 113'. Each step is as follows Figure 2 As shown in step S27 of the preparation method 10 shown.

[0165] In some embodiments, the heat treatment process may be replaced by a light treatment process, an electron beam treatment process, a combination thereof, or other suitable energy treatment processes. After the air gap 160 is formed, the semiconductor device structure 200 is obtained.

[0166] Fig.21 1 is a partial schematic diagram illustrating an exemplary integrated circuit including an array of memory cells 50, such as a memory element 1000, in some embodiments of the present disclosure. In some embodiments, the memory element 1000 includes a DRAM. In some embodiments, the memory element 1000 includes a plurality of memory cells 50 arranged in a grid pattern and including a plurality of rows and columns. The number of memory cells 50 may vary depending on system requirements and manufacturing techniques.

[0167] In some embodiments, each memory cell 50 includes an access element and a storage element. The access element is configured to provide controlled access to the storage element. Specifically, according to some embodiments, the access element is a field effect transistor (FET) 51 and the storage element is a capacitor 53. In each memory cell 50, the field effect transistor 51 includes a drain 55, a source 57 and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the field effect transistor 51, and the other terminal of the capacitor 53 can be electrically connected to the ground. In addition, in each memory cell 50, the gate 59 of the field effect transistor 51 is electrically connected to the word line WL, and the drain 55 of the field effect transistor 51 is electrically connected to the bit line BL.

[0168] The above description mentions that the terminal of the field effect transistor 51 electrically connected to the capacitor 53 is the source 57, and the terminal of the field effect transistor 51 electrically connected to the bit line BL is the drain 55. However, during read and write operations, the terminal of the field effect transistor 51 electrically connected to the capacitor 53 may be the drain, and the terminal of the field effect transistor 51 electrically connected to the bit line BL may be the source. That is, depending on how the field effect transistor 51 is controlled by voltages applied to the source, drain, and gate, any terminal of the field effect transistor 51 may be the source or the drain.

[0169] By controlling the voltage at gate 59 via word line WL, a potential can be generated across field effect transistor 51, allowing charge to flow from drain 55 to capacitor 53. Therefore, the charge stored in capacitor 53 can be interpreted as a binary data value in memory cell 50. For example, a positive charge stored in capacitor 53 above a threshold voltage can be interpreted as a binary "1". If the charge in capacitor 53 is below the threshold value, a binary value "0" is stored in memory cell 50.

[0170] The bit line BL is configured to read data from the memory cell 50 and write data to the memory cell 50. The word line WL is configured to enable the field effect transistor 51 to access a specific column of the memory cell 50. Therefore, the memory device 1000 also includes a surrounding circuit area, which may include an address buffer, a column decoder, and a row decoder. The column decoder and the row decoder selectively access the memory cell 50 in response to the address signal provided to the address buffer during the read, write, and update operations. The address signal is usually provided by an external controller, such as a microprocessor or other type of memory controller.

[0171] Please refer back Fig. 20, the first conductive plug 123a (i.e., the manganese-containing conductive plug) is formed in the pattern-dense region A, and the second conductive plug 127 (i.e., the copper-containing conductive plug) is formed in the pattern-sparse region B. The pattern-dense region A may be any region of the memory cell 50 in the memory element 1000, and the pattern-sparse region B may be any region of the address buffer, the column decoder, or the row decoder in the memory element 1000.

[0172] The present invention provides an embodiment of a semiconductor device structure 100 / 200 and a method for manufacturing the same. In some embodiments, the semiconductor device structure 200 includes a first conductive plug 123a penetrating the first dielectric layer 105 in a pattern-dense area A, a first lining layer 123 covering the first dielectric layer 105 and the first conductive plug 123a, and a second conductive plug 127 penetrating the lining layer 123 and the first dielectric layer 105 in a pattern-sparse area B. The first lining layer 123 and the first conductive plug 123a contain manganese, and the second conductive plug 127 is separated from the first dielectric layer 105 by the first lining layer 123. The manganese-containing conductive plug (i.e., the first conductive plug 123a in the pattern-dense area A) and the first lining layer 123 can be integrally formed, thereby reducing manufacturing costs. In addition, the first lining layer 123 can reduce or prevent the formation of voids in the conductive plug (i.e., the second conductive plug 127 in the pattern-sparse area B) formed subsequently, thereby reducing contact resistance. As a result, the operating speed of the semiconductor device structure 200 may be increased, which significantly improves overall device performance.

[0173] Since the manufacturing technology of the second pattern 1152 is not a photolithography technology, the second critical dimension CD2 is not limited by the technology used. For example, in the above embodiment, because thermal oxidation is well known to those skilled in the art, the manufacturing technology of the second pattern 115 includes thermal oxidation, so that the oxide layer of the sidewall 1154 of the first pattern 1151 can be easily controlled to reduce the first critical dimension CD1 of the first pattern 1151 to the second critical dimension CD2 of the second pattern 1152. That is, the second critical dimension CD2 is smaller than the first critical dimension CD1. Therefore, a smaller critical dimension can be achieved without adopting a new (and potentially defective and expensive) photolithography technology.

[0174] An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer, which is disposed above a semiconductor substrate; a first dielectric layer, which is disposed above the first conductive layer; an energy removable layer, which is conformally deposited above a first dielectric layer in a pattern-dense area, wherein an upper surface of the energy removable layer is substantially coplanar with an upper surface of the first dielectric layer; a patterned mask, which is disposed above the first dielectric layer and the energy removable layer, wherein the patterned mask includes a first pattern, a second pattern, and a third pattern, wherein the first pattern is disposed in the pattern-dense area, the second pattern is disposed above a side wall of the first pattern, and the third pattern is disposed in a pattern-sparse area; and a plurality of processing areas, which are disposed on the upper surface of the energy removal layer and are located between two adjacent first patterns, and are disposed on a pattern upper surface of the first pattern.

[0175] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed on a semiconductor substrate; an energy removable layer disposed on the first conductive layer; a plurality of first patterns independently disposed on the energy removable layer; a plurality of second patterns disposed on the sidewalls of the first patterns; and a plurality of processing areas disposed on an upper surface of the energy removable layer and between two adjacent first patterns, and also disposed on a pattern upper surface of the first patterns.

[0176] Another embodiment of the present disclosure provides a method for preparing a semiconductor device structure. The preparation method includes forming a first conductive layer above a semiconductor substrate; forming a first dielectric layer above the first conductive layer; replacing a portion of the first dielectric layer with an energy-removable layer; forming a first pattern above the energy-removable layer, wherein the first pattern has a first critical dimension; forming a plurality of processing areas on a pattern upper surface of the first pattern and on a portion of an upper surface of the energy-removable layer exposed by the first pattern; and forming a second pattern on each sidewall of the first pattern but outside the processing areas, wherein the second pattern has a second critical dimension that is smaller than the first critical dimension.

[0177] The embodiments of the present disclosure have some advantageous features. The upper surface of the pattern and the upper surface exposed by the first pattern are processed (for example, damaged by ion implantation) so that the second pattern is selectively formed only on the sidewalls of the first pattern, excluding the processed area. Therefore, the second pattern reduces the gap between the features of the first pattern. That is, the first pattern and the second pattern are combined to form a new pattern with a smaller gap. Therefore, the resulting combined pattern of the semiconductor element structure has a smaller critical dimension than the original first pattern. That is, the second pattern 1152 is arranged on the sidewall 1154 of the first pattern 1151 and reduces the gap between the features of the first pattern 1151, which results in a smaller second critical dimension CD2 (CD2<CD1), that is, the critical dimension (CD) is reduced.

[0178] In addition, by integrally forming the manganese-containing conductive plug and the manganese-containing lining layer in the pattern-dense area, the manufacturing cost can be reduced. In addition, the resistance value of the conductive plug in the pattern-sparse area surrounded by the manganese-containing lining layer can be reduced. This increases the operating speed of the semiconductor device structure, thereby significantly improving the overall device performance.

[0179] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure defined by the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0180] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, these processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor device structure, comprising: A first conductive layer is disposed on a semiconductor substrate; a first dielectric layer disposed above the first conductive layer; an energy removable layer, conformally deposited on a first dielectric layer in a pattern-dense area, wherein an upper surface of the energy removable layer is substantially coplanar with an upper surface of the first dielectric layer; a patterned mask, disposed on the first dielectric layer and the energy removable layer, wherein the patterned mask comprises a first pattern, a second pattern and a third pattern, the first pattern being disposed in the pattern-dense area, the second pattern being disposed on a sidewall of the first pattern, and the third pattern being disposed in a pattern-sparse area; as well as A plurality of processing areas are disposed on the upper surface of the energy removal layer and between two adjacent first patterns, and are disposed on a pattern upper surface of the first pattern. 2 . The semiconductor device structure as claimed in claim 1 , wherein the first pattern has a first critical dimension and the second pattern has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension. 3 . The semiconductor device structure as claimed in claim 1 , wherein a material of the first pattern is silicon, which is one of amorphous silicon and polycrystalline silicon. The semiconductor device structure as claimed in claim 1 , wherein a material of the second pattern is silicon oxide. The semiconductor device structure as claimed in claim 1 , wherein a material of the first pattern is the same as a material of the third pattern. The semiconductor device structure as claimed in claim 1 , wherein the second pattern is fabricated using a non-photolithography technique. 7 . The semiconductor device structure as claimed in claim 1 , wherein the second pattern is fabricated by thermal oxidation.

8. A semiconductor device structure, comprising: A first conductive layer is disposed on a semiconductor substrate; an energy removable layer disposed above the first conductive layer; a plurality of first patterns independently disposed on the energy removable layer; A plurality of second patterns, disposed above each sidewall of the plurality of first patterns; as well as A plurality of processing areas are disposed on an upper surface of the energy removable layer and between two adjacent first patterns, and are also disposed on a pattern upper surface of the plurality of first patterns. 9 . The semiconductor device structure as claimed in claim 8 , wherein each of the first patterns has a first critical dimension and each of the second patterns has a second critical dimension, wherein the second critical dimension is smaller than the first critical dimension. 10 . The semiconductor device structure as claimed in claim 8 , wherein a material of each first pattern is silicon, which is one of amorphous silicon and polycrystalline silicon. 11 . The semiconductor device structure as claimed in claim 8 , wherein a material of the second pattern is silicon oxide. 12 . The semiconductor device structure as claimed in claim 8 , wherein the second patterns are fabricated using a non-photolithography technique.

13. The semiconductor device structure as claimed in claim 8, wherein the second pattern is formed by thermal oxidation.

Images