Semiconductor structure and manufacturing method thereof
By forming grooves in the peripheral region of the semiconductor structure and building a recessed gate structure, the leakage problem caused by the reduction of the size of the semiconductor device is solved, and the process yield is improved.
Patent Information
- Application Number
- CN202410074007.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-10-17
- Filing Date
- 2024-01-18
- Publication Date
- 2025-04-18
AI Technical Summary
With the high integration and reduction of semiconductor devices, components in semiconductor structures are prone to leakage due to too close spacing, resulting in a decrease in process yield.
A recessed gate structure is formed by forming grooves in the peripheral region and depositing a gate dielectric layer and a conductive layer on its inner surface to reduce leakage.
This method effectively reduces leakage, improves the process yield of semiconductor structures, and solves the leakage problem caused by size reduction without increasing production costs.
Smart Images
Figure CN119855138A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor structure having a recessed gate structure in a peripheral region and a method for manufacturing the same. Background Art
[0002] As electronic devices become lighter and thinner, semiconductor devices such as dynamic random access memory (DRAM) are becoming more highly integrated. In addition, the performance of DRAM is improved by shortening the pitch between semiconductor structures in DRAM. As the size of semiconductor structures decreases, in addition to increasing the difficulty of the process, the components in the semiconductor structure are also prone to leakage due to the close pitch.
[0003] Therefore, in the semiconductor manufacturing process, how to reduce leakage to improve the process yield of the semiconductor structure becomes an important issue. Summary of the invention
[0004] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, the method comprising the following steps. A substrate is provided, wherein the surface of the substrate is defined with an array region and a peripheral region, and the substrate comprises a first barrier layer located in the array region and a second barrier layer located in the peripheral region. The substrate is etched toward the peripheral region to form a plurality of grooves, and the bottom surface of each groove is lower than the bottom surface of the second barrier layer. A gate dielectric layer is deposited on the inner surface of the groove. A first gate conductive layer is deposited on the gate dielectric layer. The first gate conductive layer is etched. A second gate conductive layer is formed on the first gate conductive layer. A capping insulating layer is deposited on the second gate conductive layer to form a gate structure.
[0005] In some embodiments, forming a groove in the peripheral region includes the following steps: forming a cover layer on the substrate; forming a pad oxide layer having a second thickness on the cover layer; forming a mask layer on the pad oxide layer to expose a first portion of the pad oxide layer and cover a second portion of the pad oxide layer; performing a photolithography process; removing the second portion of the pad oxide layer, the cover layer of multiple portions covered by the second portion of the pad oxide layer, and multiple portions of the second barrier layer to form a first opening; and etching the substrate in the peripheral region to a first depth at the same position of each first opening to form a groove.
[0006] In some embodiments, forming the groove in the peripheral region comprises the following steps: removing the first portion of the pad oxide layer after performing a photolithography process; and forming a barrier layer with a third thickness on the capping layer to completely cover the second portion of the pad oxide layer.
[0007] In some embodiments, the third thickness is greater than the second thickness.
[0008] In some embodiments, forming a groove in the peripheral region comprises the following steps: after forming the plurality of first openings, removing the barrier layer to form a second opening at the same position as the first opening, and the second opening has a first height; etching the substrate of the peripheral region to a first depth at the same position as the second opening to form the groove.
[0009] In some embodiments, the method further includes performing doping by self-aligned implantation according to the location of the recess to form lightly doped regions on opposite sides of the recess in the substrate.
[0010] In some embodiments, the method further includes forming a contact plug between the gate structures in the dielectric layer in the peripheral region to contact the lightly doped region.
[0011] In some embodiments, forming a contact plug in the peripheral region includes the following steps: After forming the gate structure, removing the capping layer and the second barrier layer to expose the upper portion of the gate structure and multiple portions of the substrate in the peripheral region. Depositing a dielectric layer on the substrate in the peripheral region to completely cover the gate structure. Forming contact openings between the gate structures in the dielectric layer by passing through the dielectric layer to the lightly doped region. Forming contact plugs in the contact openings respectively.
[0012] In some embodiments, the interface between the substrate and the dielectric layer in the peripheral region is higher than the bottom surface of the contact opening.
[0013] In some embodiments, a bottom surface of the gate structure is lower than an interface between the substrate and the dielectric layer in the peripheral region.
[0014] The present invention also provides a semiconductor structure. The semiconductor structure includes a substrate, a word line structure, a first dielectric layer, a second dielectric layer and a gate structure. The substrate defines an array region and a peripheral region, and the substrate includes a first barrier layer on the surface of the array region, and the substrate includes a second barrier layer on the surface of the peripheral region, and the array region of the substrate includes a plurality of active regions and a plurality of isolation regions between the active regions, and the substrate includes a source / drain region between the active region and the isolation region. The word line structure is disposed in the active region and the isolation region. The first dielectric layer is disposed on the word line structure in the array region. The second dielectric layer is disposed on the substrate in the peripheral region. The gate structure includes a lower portion and an upper portion, and the lower portion is disposed in the substrate in the peripheral region, and the upper portion is disposed in the second dielectric layer in the peripheral region, and the gate structure includes a first gate conductive layer, a second gate conductive layer, a cover insulating layer and a gate dielectric layer. The second gate conductive layer is disposed on the first gate conductive layer. The cover insulating layer is disposed on the second gate conductive layer. The gate dielectric layer is disposed around the first gate conductive layer, the second gate conductive layer and the cover insulating layer. In addition, the bottom surface of the gate structure is arc-shaped or tapered.
[0015] In some embodiments, a top surface of the first gate conductive layer is concave.
[0016] In some embodiments, a bottom surface of the second gate conductive layer is arc-shaped or tapered.
[0017] In some embodiments, the semiconductor structure further includes a first contact plug disposed between the word line structures of the first dielectric layer, and the first contact plug contacts the source / drain region.
[0018] In some embodiments, a first interface between the first barrier layer and the source / drain region is higher than a first contact interface between the first contact plug and the source / drain region.
[0019] In some embodiments, the semiconductor structure further includes a lightly doped region disposed on a side of the substrate opposite to the gate structure.
[0020] In some embodiments, a portion of an outer surface of the lower portion of the gate structure contacts the lightly doped region.
[0021] In some embodiments, a portion of an outer surface of a lower portion of the gate structure contacts the lightly doped region.
[0022] In some embodiments, the semiconductor structure further includes a second contact plug disposed between the gate structures of the second dielectric layer, and the second contact plug contacts the lightly doped region.
[0023] In some embodiments, a second contact surface of the second contact plug is higher than a bottom surface of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] The following embodiments are read in conjunction with the accompanying drawings to clearly understand the concept of the present invention. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion.
[0025] Figures 1 to 15 are cross-sectional views of different stages of a method for fabricating a semiconductor structure according to some embodiments of the present invention. DETAILED DESCRIPTION
[0026] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0027] In addition, for ease of description, spatially relative terms such as "on", "above", "below", "between", etc. may be used in the present invention to describe the relationship of one element or feature to another element as shown in the drawings) or function. In addition to the orientation depicted in the drawings, spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used in the present invention should be interpreted accordingly.
[0028] The terms "including", "having", "comprising" and the like used in the present invention are open terms, meaning including but not limited to.
[0029] It should be noted that when the following drawings (such as Figures 1 to 15 ) is described and illustrated as a series of operations or steps, the order in which these operations or steps are described should not be limited. For example, some operations or steps may be performed in a different order than in the present invention, or some operations or steps may occur simultaneously, or some operations may not be performed, and / or some operations or steps may be repeated. In addition, the actual operations or steps of the process stage may need to be performed before the semiconductor structure (e.g., Fig.15 Additional operations or steps are performed before, during, or after the semiconductor structure 100 in the embodiment to complete the semiconductor structure 100. Therefore, the present invention may briefly describe some of these additional operations or steps. In addition, unless otherwise specified, for the following figures (e.g. Figures 1 to 15 )The same explanations discussed above can be directly applied to the other figures.
[0030] The following combination Figures 1 to 15 Various embodiments of the present invention are described in detail. Figure 1 In the embodiment, a substrate 102 is provided. The substrate 102 is defined with an array region 110 and a peripheral region 120. More specifically, the surface of the substrate 102 in the array region 110 includes a barrier layer, and the barrier layer includes a first barrier layer 104A in the array region 110 and a second barrier layer 104P in the peripheral region 120. The substrate 102 in the array region 110 includes a plurality of active regions 140 and a plurality of isolation regions 130 located between the active regions 140. In addition, a source / drain (S / D) region 142 is formed in each active region 140 and is located between the active region 140 and the isolation region 130.
[0031] In addition, a plurality of trenches 106 are formed in the active region 140 and the isolation region 130. After the trenches 106 are formed, dielectric materials are deposited in the trenches 106 and on the surface of the substrate 102 in the array region 110 and the peripheral region 120 to form a first liner dielectric layer 152A and a second liner dielectric layer 152P, respectively. Figure 1As shown, a conductive layer 154 is deposited on the first liner dielectric layer 152A in the trenches 106 of the array region 110. In some embodiments, the dielectric material may include an oxide, such as silicon oxide. In some embodiments, after the conductive layer 154 is formed in each trench 106, an intermediate dielectric layer 156 is deposited on the conductive layer 154 in the trench 106.
[0032] In some embodiments, the substrate 102 may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The substrate 102 may include an elemental semiconductor, such as germanium. In some embodiments, the substrate 102 may include an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium indium phosphide, or other suitable materials. In some embodiments, the substrate 102 may include a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), or other suitable materials. In addition, in some embodiments, the substrate 102 may selectively have a semiconductor-on-insulator (SOI) structure.
[0033] exist Figure 2 In the embodiment of the present invention, a capping layer is deposited over the substrate 102. The capping layer includes a first capping layer 158A deposited on the first liner dielectric layer 152A in the array region 110 and the conductive layer 154 in the trench 106, and a second capping layer 158P deposited on the second liner dielectric layer 152P in the peripheral region 120. The capping layer has a first thickness TH1. In some embodiments, the material of the capping layer may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.
[0034] Then, in Figure 3 In the embodiment of the present invention, a pad oxide layer 160 having a second thickness TH2 is formed on the capping layer. In some embodiments, the material of the pad oxide layer 160 is SiO2. Then, a mask layer 162 is formed on the pad oxide layer 160 to expose a first portion of the pad oxide layer 160 and cover a second portion of the pad oxide layer 160. In addition, the mask layer 162 is a photoresist mask layer.
[0035] Further, in Figure 4In the embodiment, a patterned pad oxide layer 160A is formed on the second cover layer 158P in the peripheral region 120 by a photolithography process, and a barrier layer 164 is formed on the first cover layer 158A and the second cover layer 158P. Specifically, after the mask layer 162 is formed, the pad oxide layer 160 covered with the mask layer 162 is subjected to a photolithography process. Then, the first portion of the pad oxide layer 160 is removed, and the second portion of the pad oxide layer 160 is retained. In other words, the patterned pad oxide layer 160A is formed on the second cover layer 158P in the peripheral region 120. Then, the barrier layer 164 is formed on the first cover layer 158A and the second cover layer 158P to a third thickness TH3 to completely cover the patterned pad oxide layer 160A. Figure 4 As shown, the third thickness TH3 is greater than the second thickness TH2. In some embodiments, the mask layer 162 is removed after the photolithography process. In some embodiments, the material of the barrier layer 164 may include Si.
[0036] Then, in Figure 5 In the process, a planarization process is performed to make the top surface of the barrier layer 164 and the top surface of the patterned pad oxide layer 160A coplanar. In some embodiments, after the planarization process, the thickness of the barrier layer 164 and the patterned pad oxide layer 160A is the second thickness TH2 or less than the second thickness TH2 (for example, Figure 4 In some embodiments, the planarization process is an etch-back process.
[0037] Next, see Figure 6 , a plurality of first openings OP1 are formed in the barrier layer 164, the second capping layer 158P, the second liner dielectric layer 152P and the second barrier layer 104P of the peripheral region 120 through an etching process. In some embodiments, the etching process may be a wet etching process or a dry etching process. Figure 6 The number of the first openings OP1 is three, but the present invention is not limited thereto.
[0038] exist Figure 7 , removing the remaining barrier layer 164 (eg Figure 6 As shown in FIG. 1 , a plurality of second openings OP2 are formed in the substrate 102 of the peripheral region 120 at the same position as the first opening OP1. In addition, each second opening OP2 has a first height H1 measured from the top surface of the substrate 102 to the top surface of the second capping layer 158P. In some embodiments, the remaining barrier layer 164 is removed by a photoresist stripping process. Although Figure 7 The number of the second openings OP2 is three, but the present invention is not limited thereto.
[0039] Further, in Figure 8 In the second opening OP2 (eg, Figure 7 A plurality of grooves RS are formed at positions (as shown). In addition, the groove RS located in the peripheral area 120 has a first depth D1 measured from the bottom of the groove RS to the top surface of the substrate 102. In some embodiments, the total depth of the groove RS is a second depth D2, and the second depth D2 is equal to the first height H1 plus the first depth D1. In some embodiments, the first covering layer 158A serves as a protective mask for the active area 140 and the isolation area 130 in the array area 110. In some embodiments, after forming the second opening OP2 or forming the groove RS, a protective mask (not shown) is formed on the first covering layer 158A in the array area 110. In addition, the bottom surface of the groove RS is arc-shaped or conical. Although Figure 8 The number of the grooves RS is three, but the present invention is not limited thereto.
[0040] Then, in Fig. 9 In the embodiment of the present invention, after forming the groove RS, a plurality of lightly doped drain regions 171 are formed on opposite sides of each groove RS in the substrate 102 of the peripheral region 120 using an ion implantation mask (not shown). In some embodiments, the lightly doped (LDD) region 171 is formed according to the position of the groove RS by self-aligned doping. In some embodiments, each LDD region 171 in the substrate 102 has a third depth D3. In some embodiments, the third depth D3 is the same as the depth of the second depth D2. In some embodiments, the second depth D2 is deeper than the third depth D3.
[0041] Next, see Fig.10 , a gate dielectric layer 172 is formed on the inner surface of each recess RS in the peripheral region 120. In some embodiments, the gate dielectric layer 172 is conformally deposited on the inner surface of the recess RS in the peripheral region 120. In some embodiments, the material of the gate dielectric layer 172 is oxide.
[0042] exist Fig.11 In the embodiment, the first gate conductive layer 174 is formed on the gate dielectric layer 172 in the recess RS in the peripheral region 120. In some embodiments, the material of the first gate conductive layer 174 may include polysilicon or doped polysilicon.
[0043] Further, in Fig.12In the embodiment, the gate structure 170 is formed in the substrate 102 of the peripheral region 120. Specifically, the first gate conductive layer 174 is etched to a desired depth by an isotropic etching process. As a result, after etching, the top surface of the first gate conductive layer 174 is concave, and the bottom surface of the first gate conductive layer 174 is arc-shaped or conical. In addition, the first gate conductive layer 174 is disposed between the LDD regions 171. In some embodiments, the desired depth of the first gate conductive layer 174 may be related to the third depth D3 of each LDD region 171.
[0044] The second gate conductive layer 176 is deposited on the first gate conductive layer 174, and the second gate conductive layer 176 is deposited along the top shape of the first gate conductive layer 174. The second gate conductive layer 176 is etched by an isotropic etching process, so that the top of the second gate conductive layer 176 is concave, and the bottom surface of the second gate conductive layer 176 is arc-shaped or conical. In some embodiments, in the cross-sectional view (e.g. Fig.12 ), the bottom of the second gate conductive layer 176 is U-shaped or V-shaped. In some embodiments, the material of the second gate conductive layer 176 can be a metal-containing material, including silicide metal (eg, WSi2), metal, or a combination thereof.
[0045] In addition, a capping insulating layer 178 is formed on the second gate conductive layer 176 in each groove RS. Similarly, the capping insulating layer 178 is deposited on the second gate conductive layer 176, and the capping insulating layer 178 is deposited along the top shape on the second gate conductive layer 176, so that the bottom surface of the capping insulating layer 178 is arc-shaped or tapered. In some embodiments, in the cross-sectional view (e.g. Fig.12 ), the bottom of the capping insulating layer 178 is U-shaped or V-shaped. In some embodiments, the material of the capping insulating layer 178 is a nitrogen-containing material, such as silicon nitride. In addition, a planarization process is performed to make the top surface of the capping insulating layer 178 and the top surface of the second capping layer 158P coplanar. Similarly, after the planarization process, the gate structure 170 is formed in the peripheral region 120. In some embodiments, the planarization process can be an etching process or a chemical mechanical planarization (CMP) process. Although in Fig.12 The number of the gate structures 170 is three, but the invention is not limited thereto.
[0046] Then, in Fig.13 In the embodiment, the covering layer (including the first covering layer 158A of the array area 110 and the second covering layer 158P of the peripheral area 120) is removed by an etching process (such as Fig.12 In addition, the second liner dielectric layer 152P and the second barrier layer 104P (as shown in Fig.1214 (shown) can also be removed by an etching process. It is worth mentioning that after the etching process, the upper portion of each gate structure 170 is exposed. In addition, after the etching process, the word line structure 150 in the array region 110 is formed.
[0047] Later, in Fig.14 In the embodiment, a dielectric material is deposited on the first liner dielectric layer 152A of the array area 110 and on the surface of the substrate 102 of the peripheral area 120 to form a first dielectric layer 181A and a second dielectric layer 181P covering the gate structure 170, respectively. In some embodiments, the dielectric material can be silicon oxide. In some embodiments, the dielectric material is deposited by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or high density plasma CVD (HDP-CVD). In some embodiments, the second dielectric layer 181P has a fourth thickness TH4 measured from the second interface INS2 between the substrate 102 and the second dielectric layer 181P to the top surface of the second dielectric layer 181P. Furthermore, the fourth thickness TH4 is greater than a second height H2 measured from a second interface INS2 between the substrate 102 (particularly the LDD region 171) and the second dielectric layer 181P to a top surface of the capping insulating layer 178 of the gate structure 170. In some embodiments, a portion of an outer surface of an upper portion of the gate structure 170 contacts each LDD region 171. In some embodiments, an outer surface of a lower portion of each gate structure 170 contacts the LDD region 171. The gate structure 170 contacts each LDD region 171.
[0048] Next, in the array region 110, a plurality of third openings (also referred to as contact openings) OP3 are formed between the word line structures 150 in the same active region 140 in the first dielectric layer 181A by penetrating the first dielectric layer 181A, the first liner dielectric layer 152A, and the first barrier layer 104A to the source / drain region 142. In some embodiments, the first interface INS1 between the first barrier layer 104A and the S / D region 142 is higher than the first bottom surface OPS1 of the third opening OP3.
[0049] In addition, a plurality of fourth openings (also referred to as contact openings) OP4 are formed between the gate structures 170 in the second dielectric layer 181P, passing through the second dielectric layer 181P to each lightly doped region 171. In an embodiment, a second interface INS2 between the substrate 102 and the second dielectric layer 181P is higher than a second bottom surface OPS2 of the fourth openings OP4.
[0050] In addition, Fig.15 In the embodiment, a first contact plug 180 is formed in the array region 110, and a second contact plug 190 is formed in the peripheral region 120. Specifically, barrier metal materials are deposited on the inner sidewalls of the third opening OP3 and the fourth opening OP4 respectively by deposition to form a first barrier metal layer 183 and a second barrier metal layer 193 respectively. In some embodiments, the barrier metal material includes titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), titanium / titanium nitride (Ti / TiN), cobalt (Co), nickel (Ni), hafnium (Hf), platinum (Pt), tungsten (W), titanium tungsten (TiW), titanium / titanium nitride, tantalum (Ta) and tantalum nitride (TaN). In some embodiments, the deposition process is atomic layer deposition (ALD), CVD, physical vapor deposition (PVD) process.
[0051] Next, a conductive metal material is deposited to fill the third opening OP3 having the first barrier metal layer 183 and the fourth opening OP4 having the second barrier metal layer 193 to form a first conductive metal layer 185 and a second conductive metal layer 195, respectively. In some embodiments, the conductive metal material is tungsten (W). In some embodiments, the deposition process of the conductive metal material is ALD, CVD, or PVD process. Fig.15 The number of the first contact plugs 180 is two and the number of the second contact plugs 190 is two, but the present invention is not limited thereto.
[0052] In addition, an insulating material is deposited on the first dielectric layer 181A and the second dielectric layer 181P to form a first interlayer dielectric (ILD) layer 191A and a second interlayer dielectric layer 191P, respectively. In some embodiments, the insulating material is an oxide, a nitride, or a combination thereof.
[0053] Through the manufacturing method of the semiconductor structure 100 of the embodiment of the present invention, the recessed gate structure 170 can solve the leakage problem of the semiconductor device in the prior art due to the reduction in size resulting in the reduction in the distance between the gate channels. In addition, the operation of the manufacturing method of the embodiment of the present invention is not very complicated. Therefore, the leakage problem can be improved without increasing the production cost.
[0054] An embodiment of the present invention also provides a semiconductor structure, such as Fig.15 As shown. Fig.15 In the embodiment, the semiconductor structure 100 includes a substrate 102 , a plurality of word line structures 150 , a first dielectric layer 181A, a second dielectric layer 181P and a plurality of gate structures 170 .
[0055] The substrate 102 defines an array region 110 and a peripheral region 120. The substrate 102 in the array region 110 includes a plurality of active regions 140 and a plurality of isolation regions 130 between the active regions 140. In addition, the semiconductor structure 100 further includes a source / drain (S / D) region 142 disposed in each active region 140 and between the isolation regions 130.
[0056] The word line structure 150 is disposed in the active region 140 and the isolation region 130. Further, the word line structure 150 includes a conductive layer 154, a first capping layer 158A disposed on the conductive layer 154, and a first liner dielectric layer 152A surrounding the conductive layer 154 and the first capping layer 158A. In some embodiments, the word line structure 150 also includes an intermediate dielectric layer 156 disposed between the conductive layer 154 and the first capping layer 158A. In some embodiments, the depth of the word line structure 150 in the isolation region 130 is greater than the depth of the word line structure 150 in the active region 140. In addition, the S / D region 142 is disposed on opposite sides of the word line structure 150.
[0057] The first dielectric layer 181A is disposed on the word line structure 150 in the array region 110. The second dielectric layer 181P is disposed on the substrate 102 in the peripheral region 120. In some embodiments, the top surface of the first capping layer 158A of the word line structure 150 and the top surface of the first liner dielectric layer 152A on the first barrier layer 104A are coplanar.
[0058] Further, the gate structure 170 includes a lower portion and an upper portion. The lower portion of the gate structure 170 is disposed in the substrate 102 of the peripheral area 120, and the upper portion of each gate structure 170 is disposed in the second dielectric layer 181P of the peripheral area 120. The gate structure 170 includes a first gate conductive layer 174, a second gate conductive layer 176 disposed on the first gate conductive layer 174, a covering insulating layer 178 disposed on the second gate conductive layer 176, and a gate dielectric layer 172 surrounding the first gate conductive layer 174, the second gate conductive layer 176, and the second gate conductive layer 176. It is worth mentioning that the top of the first gate conductive layer 174 is concave, the top of the second gate conductive layer 176 is concave, the bottom of the second gate conductive layer 176 is arc-shaped or conical, and the bottom of the covering insulating layer 178 is arc-shaped or conical. In addition, in the cross-sectional view (such as Fig.15 ), the bottom of the second gate conductive layer 176 and the covering insulating layer 178 are U-shaped or V-shaped.
[0059] In addition, the semiconductor structure 100 includes a plurality of lightly doped (LDD) regions 171 . The LDD regions 171 are disposed at opposite sides of each gate structure 170 in the substrate 102 .
[0060] In some embodiments, the semiconductor structure 100 includes a first contact plug 180 in the array region 110 and a second contact plug 190 in the peripheral region 120. Specifically, the first contact plug 180 is disposed between the word line structures 150 and is located in the first dielectric layer 181A, and the first contact plug 180 contacts the S / D region 142. Similarly, the second contact plug 190 is disposed between the gate structures 170 and is located in the second dielectric layer 181P, and the second contact plug 190 contacts the LDD region 171. In some embodiments, the first contact plug 180 includes a first conductive metal layer 185 and a first barrier metal layer 183 surrounding a sidewall of the first conductive metal layer 185. In some embodiments, the second contact plug 190 includes a second conductive metal layer 195 and a second barrier metal layer 193 surrounding a sidewall of the second conductive metal layer 195.
[0061] In some embodiments, the first interface INS1 between the first barrier layer 104A and the S / D region 142 is higher than the first contact interface 180S between the first contact plug 180 and the S / D region 142. In some embodiments, the second interface INS2 between the substrate 102 and the second dielectric layer 181P is higher than the second contact surface 190S of the second contact plug 190. In some embodiments, the second contact surface 190S of the second contact plug 190 is higher than the bottom surface 170B of the gate structure 170.
[0062] In some embodiments, the semiconductor structure 100 includes an interlayer dielectric layer. The interlayer dielectric layer is disposed on the first dielectric layer 181A and the second dielectric layer 181P. In some embodiments, a third interface 191S between the second dielectric layer 181P and the second interlayer dielectric layer 191P is higher than the top surface 170T of the gate structure 170. In some embodiments, the top surface of the first contact plug 180 contacts the bottom surface of the first interlayer dielectric layer 191A. In some embodiments, the top surface of the second contact plug 190P contacts the bottom surface of the second interlayer dielectric layer 191P.
[0063] The semiconductor structure 100 with the recessed gate structure 170 provided in the embodiment of the present invention can solve the leakage problem in the prior art caused by the reduction in the size of the semiconductor device and the reduction in the distance between the gate channels. Therefore, even if the semiconductor device continues to shrink and the channels in the semiconductor device become shorter, the leakage problem can be improved.
[0064] Although some embodiments of the present invention have been described in considerable detail, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0065] The above briefly describes the features of multiple embodiments of the present invention, so that those skilled in the art can more easily understand the present invention. Any person skilled in the art should understand that the present invention can easily serve as a basis for the change or design of other structures or processes to achieve the same purpose and / or obtain the same advantages as the embodiments of the present invention. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of the present invention, and can be changed, replaced and modified without departing from the spirit and scope of the present invention.
[0066]
Explanation of symbols
[0067] 100:Semiconductor structure
[0068] 102:Substrate
[0069] 104A: First barrier layer
[0070] 104P: Second barrier layer
[0071] 106: Groove
[0072] 110: Array area
[0073] 120: Surrounding area
[0074] 130: Quarantine
[0075] 140: Active Zone
[0076] 142: Source / Drain Region / S / D Region
[0077] 150: Character line structure
[0078] 152A: first liner dielectric layer
[0079] 152P: Second liner dielectric layer
[0080] 154: Conductive layer
[0081] 156: Intermediate dielectric layer
[0082] 158A: First covering layer
[0083] 158P: Second covering layer
[0084] 160,160A: Pad oxide layer
[0085] 162: Mask layer
[0086] 164: Barrier layer
[0087] 170: Gate structure
[0088] 170B: Bottom surface
[0089] 170T: Top surface
[0090] 171: Lightly doped region / LDD region
[0091] 172: Gate dielectric layer
[0092] 174: first gate conductive layer
[0093] 176: second gate conductive layer
[0094] 178: Covering insulation layer
[0095] 180: first contact plug
[0096] 180S: First contact interface
[0097] 181A: first dielectric layer
[0098] 181P: Second dielectric layer
[0099] 183: first barrier metal layer
[0100] 185: first conductive metal layer
[0101] 190: second contact plug
[0102] 190S: Second contact surface
[0103] 191: Interlayer dielectric layer
[0104] 191A: First interlayer dielectric layer
[0105] 191P: Second interlayer dielectric layer
[0106] 191S: The third interface
[0107] 193: second barrier metal layer
[0108] 195: second conductive metal layer
[0109] D1: First Depth
[0110] D2: Second Depth
[0111] D3: Third Depth
[0112] H1: First Height
[0113] H2: Second Height
[0114] INS1: First interface
[0115] INS2: Second interface
[0116] OP1: First opening
[0117] OP2: Second opening
[0118] OP3: The third opening
[0119] OP4: The fourth opening
[0120] OPS1: First bottom surface
[0121] OPS2: Second bottom surface
[0122] RS: Groove
[0123] TH1: First thickness
[0124] TH2: Second thickness
[0125] TH3:Third thickness
[0126] TH4: Fourth thickness.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, wherein a surface of the substrate is defined with an array region and a peripheral region, and the substrate comprises a first barrier layer located in the array region and a second barrier layer located in the peripheral region; Etching the substrate toward the peripheral region to form a plurality of grooves, wherein a bottom surface of each of the grooves is lower than a bottom surface of the second barrier layer; Depositing a gate dielectric layer on the inner surface of each of the grooves; depositing a first gate conductive layer on the gate dielectric layer; etching the first gate conductive layer; forming a second gate conductive layer on the first gate conductive layer; and A capping insulating layer is deposited on the second gate conductive layer to form a plurality of gate structures.
2. The method according to claim 1, characterized in that Wherein forming the plurality of grooves in the peripheral area comprises: forming a capping layer over the substrate; forming a pad oxide layer on the capping layer, wherein the pad oxide layer has a second thickness; forming a mask layer on the pad oxide layer to expose a plurality of first portions of the pad oxide layer and cover a plurality of second portions of the pad oxide layer; Performing a photolithography process; removing the plurality of second portions of the pad oxide layer, portions of the capping layer covered by the plurality of second portions of the pad oxide layer, and portions of the second barrier layer to form a plurality of first openings; and At the same position of each of the first openings, the substrate in the peripheral area is etched to a first depth to form the plurality of grooves.
3. The method according to claim 2, characterized in that Wherein forming the plurality of grooves in the peripheral region comprises: After performing the photolithography process, removing the plurality of first portions of the pad oxide layer; and A barrier layer having a third thickness is formed on the capping layer to completely cover the plurality of second portions of the pad oxide layer.
4. The method according to claim 3, characterized in that The third thickness is greater than the second thickness.
5. The method according to claim 3, characterized in that: Wherein forming the plurality of grooves in the peripheral region comprises: After forming the plurality of first openings, removing the barrier layer to form a plurality of second openings at the same positions as the plurality of first openings, wherein each of the second openings has a first height; and The substrate in the peripheral region is etched to a first depth at the same position of each of the second openings to form the plurality of grooves.
6. The method according to claim 2, characterized in that Further including: According to the positions of the plurality of grooves, doping is performed by self-aligned implantation to form a plurality of lightly doped regions on opposite sides of each of the grooves in the substrate.
7. The method according to claim 6, characterized in that Further including: A plurality of contact plugs are formed between the plurality of gate structures in the dielectric layer in the peripheral region to contact each of the lightly doped regions.
8. The method according to claim 7, characterized in that Wherein forming the plurality of contact plugs in the peripheral region comprises: After forming the plurality of gate structures, removing the capping layer and the second barrier layer to expose upper portions of each of the gate structures and a plurality of portions of the substrate in the peripheral region; depositing the dielectric layer on the substrate in the peripheral region to completely cover the plurality of gate structures; Forming a plurality of contact openings between the plurality of gate structures in the dielectric layer by penetrating the dielectric layer to each of the lightly doped regions; and The plurality of contact plugs are formed in the plurality of contact openings, respectively.
9. The method according to claim 8, characterized in that The interface between the substrate and the dielectric layer in the peripheral area is higher than the bottom surface of each contact opening.
10. The method according to claim 8, characterized in that The bottom surface of each gate structure is lower than the interface between the substrate and the dielectric layer in the peripheral area.
11. A semiconductor structure, characterized in that: include: A substrate, defined with an array region and a peripheral region, wherein the substrate comprises a first barrier layer on a surface of the array region, and the substrate comprises a second barrier layer on the surface of the peripheral region, wherein the substrate comprises a plurality of active regions and a plurality of isolation regions between the plurality of active regions in the array region, and the substrate comprises a source / drain region between each of the active regions and each of the isolation regions; A plurality of word line structures are disposed in the plurality of active regions and the plurality of isolation regions; A first dielectric layer is disposed on the plurality of word line structures in the array region; A second dielectric layer is disposed on the substrate in the peripheral region; as well as A plurality of gate structures, including a lower portion and an upper portion, wherein the lower portion is disposed in the substrate in the peripheral region, and the upper portion is disposed in the second dielectric layer in the peripheral region, and wherein each of the gate structures comprises: a first gate conductive layer; A second gate conductive layer is disposed on the first gate conductive layer; A covering insulating layer is disposed on the second gate conductive layer; and A gate dielectric layer is disposed around the first gate conductive layer, the second gate conductive layer and the cover insulating layer, Wherein, the bottom surface of each gate structure is arc-shaped or conical.
12. The semiconductor structure according to claim 11, characterized in that: The top surface of the first gate conductive layer is concave.
13. The semiconductor structure according to claim 11, characterized in that: The bottom surface of the second gate conductive layer is arc-shaped or conical.
14. The semiconductor structure according to claim 11, characterized in that: Further including: The first contact plug is disposed between the plurality of word line structures of the first dielectric layer, wherein the first contact plug contacts the source / drain region.
15. The semiconductor structure according to claim 14, characterized in that: The first interface between the first barrier layer and the source / drain region is higher than the first contact interface between the first contact plug and the source / drain region.
16. The semiconductor structure according to claim 11, characterized in that Further including: A plurality of lightly doped regions are disposed on opposite sides of the substrate to each of the gate structures.
17. The semiconductor structure according to claim 16, characterized in that: A portion of the outer surface of the lower portion of each gate structure contacts each lightly doped region.
18. The semiconductor structure according to claim 16, characterized in that The outer surface of the lower portion of each gate structure contacts each lightly doped region.
19. The semiconductor structure according to claim 16, characterized in that Further including: The second contact plug is disposed between the plurality of gate structures of the second dielectric layer, wherein the second contact plug contacts each of the lightly doped regions.
20. The semiconductor structure according to claim 19, characterized in that The second contact surface of the second contact plug is higher than the bottom surface of each gate structure.