Memory device having hexagonal memory cells with all-around gate transistors

Abstract

Various applications may include a memory device having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate-all-around (GAA) transistor coupled to a capacitor. Digital lines to the memory cells may be angularly arranged with respect to a set of access lines at an angle different from 90 degrees. The digital shielded lines may be structured between adjacent digital lines. The memory devices may be arranged in a wafer-to-wafer interconnect architecture in which the array on an array wafer is connected to and below a control circuitry wafer in an array-above circuit architecture.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to integrated circuits, and more particularly, to memory devices and the formation thereof. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices (ICs). There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (e.g., phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc. The properties of memory devices and other electronic devices can be improved by enhancing the design and fabrication of components of the electronic devices, such as, but not limited to, memory devices used in ICs of the electronic devices. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed in this document by way of example and not by way of limitation.

[0004] Figure 1 Cross-sectional views illustrating representations of components of a dynamic random access memory device having an above-array circuit architecture in accordance with various embodiments, wherein memory cells of the array may include all-around-gate transistors coupled to capacitors.

[0005] Figure 2 According to various embodiments, Figure 1 An arrangement of a memory cell having an access transistor and a capacitor implemented in a dynamic random access memory device of the present invention is presented.

[0006] Figure 3 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0007] Figures 4 to 22 The invention describes forming a memory device (eg, a memory cell array) having a hexagonal shape in a wafer-to-wafer interconnect architecture according to various embodiments. Figure 1 An example method of a dynamic random access memory device).

[0008] Fig.23 is a flow chart of features of an example method of forming a memory device in accordance with various embodiments.

[0009] Fig.24 is a schematic diagram of an electrical arrangement of components of an embodiment of an example dynamic random access memory device that may include an architecture having hexagonal memory cells with all-around gate transistors in accordance with various embodiments. DETAILED DESCRIPTION

[0010] The following detailed description refers to the accompanying drawings that show various embodiments that can be implemented in an illustrative manner. These embodiments are described in sufficient detail to enable those skilled in the art to practice these and other embodiments. Other embodiments may be utilized, and structural changes, logical changes, mechanical changes, and electrical changes may be made to these embodiments. The term "horizontal" used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above, and may be in a direction from horizontal or to horizontal. Various features may have a vertical component relative to the direction of their structure. Various embodiments are not necessarily mutually exclusive, because some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a restrictive sense.

[0011] In various embodiments, a memory device may be structured to have an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a gate-all-around (GAA) transistor coupled to a capacitor. A hexagonal memory cell is a memory cell surrounded by six other memory cells, such that the other memory cells are located at the vertices of a hexagonal structure formed by connecting the centers of the neighboring memory cells of these other memory cells. A GAA transistor is a transistor structured such that the gate of the transistor is coupled to the channel structure of the transistor on all sides of the channel structure. The GAA structure may allow a critical dimension (CD) as low as about 5 nm. The GAA transistor may be structured into a columnar arrangement containing an active region (source and drain) and a channel structure, with the gate structured around the channel structure. The columnar structure of the GAA transistor may be structured as a semiconductor nanowire. A nanowire is a nanostructure having a nanometer-scale diameter. A GAA nanowire transistor as an access device to a capacitor in a memory cell of a DRAM may provide an enhanced I ON capability and the transistor threshold voltage (V T ) can be adjusted flexibly. ON is the on-state current of the transistor, where the current I OFF is the off-state current of the transistor. ON / I OFFIt is the quality factor of the transistor for high performance and low leakage power. High performance and more I ON associated with low leakage power and less I OFF Associated.

[0012] A memory device having hexagonal memory cells of GAA transistors may be implemented with control logic and sensing circuitry positioned above a memory array in a circuit-over-array (CoA) architecture. The control logic and sensing circuitry may be arranged to sense the programmed data states of memory cells of one or more memory arrays of a memory device, and may enhance the reduction of die size or increase the utilization of space in a die or die combination. CoA generally refers to a circuitry positioned in a memory die above a memory array of a memory die. CoA may also be referred to as CMOS above an array by virtue of the control logic and sensing circuitry fabricated above a memory array using semiconductor processing that may include CMOS (complementary metal oxide semiconductor) processing technology. The CoA architecture may be implemented with a wafer-to-wafer architecture, in which the control logic and sensing circuitry are formed on one wafer, and one or more memory arrays are formed on another wafer, in which the two wafers are combined. The wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture. The wafer-to-wafer bonding of back-to-back wafers in the CoA architecture may provide movement of capacitor modules for data storage in DRAM to the bottom of a wafer stack. This arrangement may reduce interconnect congestion between stacked wafers. Alternatively, other design considerations may be implemented with such memory arrays using a circuit under the array (CuA) architecture.

[0013] A memory device may include a set of access lines, wherein each access line in the set of access lines may be coupled to the gates of a first set of multiple GAA transistors of a memory cell of a memory array. With the double-sided access lines to the GAA transistors of the memory cells, control of the access line resistance-capacitance (RC) of the access lines immediately adjacent to the access lines may be obtained. The memory device may include a set of digit lines, wherein each digit line in the set of digit lines may be coupled to a second set of multiple GAA transistors of the memory cells. The set of digit lines may be angled at an angle other than 90 degrees relative to the set of access lines, wherein the relative orientation may be observed when the access lines and the digit lines are projected onto the same plane. Control of the digit line RC of the immediately adjacent digit lines may be obtained with a digital shield line between the digit lines. The digital shield line may be arranged as a conductive line. The conductive shield line may be a metal digital shield line.

[0014] The memory device may have 4F 2 Memory array configuration. Using nF 2The formula measures the memory cell size, where 'n' is a constant derived from the cell design and 'F' is the feature size of the process technology. For the same feature size, as the cell size gets smaller, the memory capacity increases. 2 In the memory cell, the access line pitch and the digit line pitch may be equal to 2F.

[0015] Figure 1 A cross-sectional view illustrating a representation of components of a DRAM 100 having a CoA architecture, where a memory cell of the array may include a GAA transistor coupled to a capacitor. For ease of presentation, the Figure 1 And similar multiple features in subsequent figures without marking all similar features. The memory cell can be structured as GAA 4F 2 Hexagonal unit. The CoA architecture may include a control circuit system wafer 102 above the array wafer 101. The control circuit system wafer 102 may be positioned above the array wafer 101 by docking the bonding layer 112-1 in the control circuit system wafer 102 with the bonding layer 112-2 in the array wafer 101. The bonding layer 112-1 and the bonding layer 112-2 may be oxide layers, such as but not limited to silicon oxide layers. The bonding layer 112-1 and the bonding layer 112-2 may be a single bonding layer formed to the control circuit system wafer 102 or formed to the array wafer 101. The array wafer 101 may include a carrier portion 103 above which the capacitor 129 is positioned, or may include a carrier portion 103 of a carrier wafer to which a module of the capacitor 129 is bonded.

[0016] Control circuit system wafer 102 may include a number of transistors 119. Some of transistors 119 may include transistors arranged as CMOS devices. Transistor 119 may be arranged above bonding layer 112-1 through isolation region 149. The isolation region may be a dielectric, such as a dielectric oxide, a dielectric nitride, or a combination of a dielectric oxide and a dielectric nitride. Control circuit system wafer 102 may include a number of metallization lines, as illustrated by metal lines 141 and 147. Metal lines 147 and 141 are shown in FIG. Figure 11 and 2. An illustration of metal lines routed in the plane and out-of-plane directions of the view of FIG. Metal lines 147 are the first metal layer of the back-end-of-line (BEOL) processing. Metal lines 141 are the zeroth level metal layer, ensuring that the bonding contacts are routed to the appropriate circuits on top of the wafer 102. BEOL is a portion of the IC manufacturing process that generally involves interconnecting the individual devices of the IC with conductive paths, such as, but not limited to, conductive traces or wires. The conductive traces or wires may include metals, such as, but not limited to, copper, aluminum, ruthenium, or tungsten. The temperatures used in BEOL compatible processes may be substantially lower than the temperatures used when constructing the active devices of the IC in the front-end-of-line (FEOL) processing. The control circuit system wafer 102 may include a number of bonding contacts 143 to provide an electrical signal path from and through the control circuit system wafer 102 to the array wafer 101 and to provide contacts through the wafer bonding of the two wafer portions. The bonding contacts 143 are structured through the bonding interface between the control circuit system wafer 102 and the array wafer 101, thereby anchoring the bonded wafers together.

[0017] exist Figure 1 , two views of the array wafer 101 are shown, with the view to the left of the dashed line along the access line (WL) 130 and the view to the right of the dashed line along the digit line (BL) 135. Examples of WLs include word lines and digit lines include bit lines. Bonding contacts 143 from the control circuit system wafer 102 can be connected to landing pads 144 of the array wafer 101. In the left view, the landing pad 144 is coupled to the WL 130 through a line contact 146. The WL 130 is coupled to an active region 106 (source / drain) and an active region 108 having a fully surrounding gate 127 and a channel 107, wherein the channel 107 can be provided as a columnar configuration. The WL 130 can be integrated with the fully surrounding gate 127 of the GAA transistor to which the WL is coupled, wherein the fully surrounding gate 127 can be coupled to the channel 107 through a dielectric. In Figure 1 In the cross-sectional view of FIG. 1 , only one WL 130 of the multiple WLs of DRAM 100 is shown. Each active region 106 is coupled to an individual BL 135, and each active region 108 is coupled to an individual capacitor 129. Figure 1 In the cross-sectional view of FIG. 1 , only one BL 135 of the plurality of BLs of DRAM 100 is marked. BL 135 is separated from adjacent ones of BL 135 by conductive shielding wires 136, wherein shielding wires 136 are separated from each other by dielectric material. Shielding wires 136 may be metal shielding wires. Shielding wires 136 may extend vertically from body shield 117. Body shield 117 may be implemented as a conductive plate. Body shield 117 may be a metal plate-like structure. Buried dielectric 109 may be positioned between body shield 117 and BL 135.

[0018] In the right side view, the landing pad 144 is coupled to the BL 135 through the wire contact 146. In this right side view, the WL 130 is not shown in this plane. The GAA transistor with the all-around gate 127 and the active regions 106, 108 can be constructed as a thin film transistor (TFT). The TFT is a type of metal oxide semiconductor field effect transistor (MOSFET). The GAA transistor can be structured as a nanowire in the vertical direction. The GAA transistor can be structured as appropriately doped silicon, such as appropriately doped epitaxial silicon.

[0019] Figure 2 is available in Figure 1 1 is a representation of an arrangement of a memory cell 200 with an access transistor 221 and a capacitor 229 implemented in a DRAM 100 of FIG. The access transistor 221 may include a fully surrounding gate 227 surrounding a channel structure in a vertical pillar having a first active region 206 and a second active region 208. The vertical pillar may be a nanowire. The fully surrounding gate 227 is connected to a WL 230. The material of the WL 230 may be integrated with the material of the fully surrounding gate 227. Alternatively, the WL 230 may contact the fully surrounding gate 227 at a location of the top of the fully surrounding gate 227 or at a location of the bottom of the fully surrounding gate 227. The second active region 208 may be coupled to the capacitor 229 at a junction contact, and the second active region 206 may be coupled to the BL 235 at a junction contact to the BL 235. Figure 2 The illustration BL 235 may have one of different orientations relative to the WL 230 and the vertical column containing the first active area 206 and the second active area 208, such as but not limited to orientations 235-1 and 235-2. In a projection onto a common plane, orientation 235-2 may be oriented at an angle relative to the WL 230, which may be an angle different from 90 degrees. For example, the angle may be, but is not limited to, 60 degrees.

[0020] Figure 3 is a flow chart of features of an embodiment of an example method 300 of forming a memory device. The example method 300 may be used to manufacture Figure 1 DRAM 100. At 310, an array wafer is prepared. The preparation of the array wafer includes forming a GAA transistor array connected to WL and BL. The BL may be angled at an angle other than 90 degrees relative to the WL. The GAA transistor array may be formed as 4F 2 Hexagonal memory cells in the architecture.

[0021] At 320, a control circuit system wafer is prepared. The preparation of the control wafer may include forming a sense amplifier (SA) or a sub-word line driver (SWD) for the memory array. At 330, the array wafer and the control circuit system wafer are bonded together. Various contacts that connect the memory array of the array wafer to the upper circuit of the control circuit system wafer may be patterned. For example, the patterning of the contacts may include one or more SA to BL or one or more SWD to one or more WL. At 340, after bonding the array wafer and the control circuit system wafer together, BEOL processing of the control circuit system wafer is performed.

[0022] Variations of method 300 or methods similar to method 300 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of systems including memory devices implementing such methods.Such methods may include forming the GAA transistor as a thin film transistor.

[0023] A variation of method 300 or a method similar to method 300 may include preparing an array wafer with several processes after forming the GAA transistors and the WLs to the GAA transistors. Capacitors vertically coupled to the GAA transistors may be formed, after which the array wafer may be flipped and bonded to a carrier wafer. The carrier wafer may be thinned. A digit line may be coupled to the capacitor with a shield line formed between the BLs.

[0024] A variation of method 300 or a method similar to method 300 may include forming a bonding interconnect in preparation for bonding the array wafer to the control circuit system wafer. In the preparation of the control circuit system wafer, a bonding contact coupled to the bonding interconnect may be formed. Bonding the array wafer to the control circuit system wafer may include fusing oxide regions on the array wafer to oxide regions on the control circuit system wafer. Other bonding techniques may be used.

[0025] A variation of method 300 or a method similar to method 300 may include forming a bonding interconnect between a WL on an array wafer and a SWD on a control circuitry wafer through a triangular WL slot structure placed at an edge of an array tile of a memory device. A variation may include aligning one or more SA circuits on a control circuitry wafer over a BL slot placed on the array wafer, and aligning one or more SWD circuits on a control circuitry wafer over a WL slot on the array wafer. A variation may include efficiently distributing BL connections and WL connections in a BL exit slot area and a WL exit slot area to reduce interconnect parasitics and congestion.

[0026] Figures 4 to 24 A memory device (e.g., Figure 1The example method of the DRAM 100 of FIG. 100 is an example embodiment of the method of the DRAM 100 of FIG. 100. The wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture. The memory cell may be arranged with 4F 2 Architecture. For the processes discussed herein, the choice of process materials may depend on the materials selected to form the various components of the memory device and the contacts to the components of the memory device. The process materials may be selected to allow removal of one or more materials while retaining one or more other materials. In addition, deposition techniques that are typical for the materials being formed, the dimensions of the materials being formed, and the architecture in which the materials are formed may be used.

[0027] Figure 4 Structure 400 is shown after pillars 407 have been formed from wafer 404. Pillars 407 may be formed in a subtractive process, where a subtractive process includes removing material from a solid block of starting material. Pillars 407 may be silicon or epitaxial silicon. A hard mask 413 has been formed on a top portion of pillars 407. A hard mask is a material that can be used as an etch mask in an etching process, where the material is different from a polymer or other relatively soft material, such as a relatively soft resist material. A hard mask is typically a high density material used in an etching process to protect certain areas of the structure being processed from the etching chemicals used in the etching process.

[0028] Figure 5 Display in processing Figure 4 Structure 500 is a structure subsequent to structure 400. Dielectric 518 has been formed on wafer 404 around the bottom of pillar 407. Dielectric 518 may be an oxide, such as but not limited to silicon oxide. Dielectric 518 provides insulation to the region of the junction that will be the active region of the GAA transistor formed using pillar 407.

[0029] Figure 6 Display in processing Figure 5 4. The structure 600 after the structure 500 of FIG. 4 is shown. Dielectric 628 has been deposited over hard mask 413, pillar 407, and dielectric 518 of structure 500. Portions of dielectric 628 will provide gate dielectric for the GAA transistor being formed. Dielectric 628 may be an oxide, such as, but not limited to, silicon oxide.

[0030] Figure 7 Display in processing Figure 6 The structure 700 is a structure after the structure 600 of FIG. The conductive material has been formed on the dielectric 628 and the conductive material has been recessed, leaving the conductive material for the gate 727 of the GAA transistor, wherein the pillar 407 is covered by the dielectric 628 extending over the conductive material of the gate 727. The conductive material can be formed by a suitable deposition technique, which can be chemical vapor deposition (CVD) or atomic layer deposition (ALD). The conductive material of the gate 727 can be a metal material.

[0031] Figure 8 Display in processing Figure 7 700. The dielectric has been formed to provide insulation for the WL and is recessed, leaving a dielectric region 818 around the conductive material for the gate 727. The formation of the dielectric material can be formed by an appropriate deposition technique. The dielectric region 818 can be an oxide region, such as but not limited to a silicon oxide region, or other suitable dielectric for the memory device being formed. In the recess process, the pillar 407 and the mask 413 have been exposed above the conductive material for the gate 727. Optionally, the exposure of the pillar 407 and the mask 413 can be performed when the structure 700 is formed. Although not shown, the dielectric 628 remains around the pillar 407, which is surrounded by the conductive material for the gate 727.

[0032] Fig. 9 A top view of the structure 800 of a GAA transistor showing memory cells 925 in a hexagonal memory cell array. Each memory cell 925 includes a pillar 407 covered by a mask 413 in this view, a dielectric 628 for the gate dielectric of the GAA transistor, and a conductive material for a gate 727. As shown, the centers of the immediately adjacent memory cells surrounding the memory cells 925 form a hexagon 933 with connected vertices.

[0033] Fig.10 Display in processing Figure 8 The structure 1000 is a structure subsequent to the structure 800 of FIG. A bottom layer 1028 for forming WLs has been formed between the rows of conductive material for gates 727. The bottom layer is a carbon-based hard mask placed under the photoresist. Fig.11 yes Fig.10 , which shows the bottom layer 1028 between several pairs of rows of conductive material for gates 727.

[0034] Fig.12 Display in processing Fig.10 1000. The material to be used for the WL has been formed using the bottom layer 1028. The material can be formed by an appropriate deposition technique for the material and the memory device formed. The material has been recessed, removing the bottom layer 1028 and leaving the material for the WL 1230. When the bottom layer 1028 is removed, portions of the pillars 407 and the hard mask 413 have been exposed. The material for the WL 1230 can be a metal material. In this view, the first pillars 1, 2, 3 and 4 indicate rows of pillars 407, where the rows of pillars 407 are in the direction of the dotted lines. As shown in FIG. Fig.13, the material for WL 1230 contacts pairs of rows of conductive material for gate 727. The material for WL 1230 is formed between a row having first pillar 1 and an adjacent row having first pillar 2 in the direction of the dashed line. The material for WL 1230 is formed between a row having first pillar 3 and an adjacent row having first pillar 4 in the direction of the dashed line. Fig.13 is a top view of structure 1200. Region 1337-1 shows a first side of a formed GAA transistor, and region 1337-2 shows a second side of a formed GAA transistor. Using two sides of the conductive material for gate 727 can provide control to reduce WL resistance.

[0035] Fig.14 Display in processing Fig.12 1200. A dielectric 1418 has been formed to provide insulation for WL 1230. A chemical mechanical polishing (CMP) process has been applied to remove the mask 413 and pillars 407 above the top of the dielectric 1418. The formation of the dielectric 1418 can be formed by a suitable deposition technique. The dielectric 1418 can be an oxide region, such as but not limited to a silicon oxide region or other suitable dielectric for the memory device being formed. Fig.14 Not shown or labeled is the portion of dielectric 628 that separates pillar 407 from the conductive material for gate 727 and provides a gate dielectric for the conductive material for gate 727.

[0036] Fig.15 Display in processing Fig.14 1400. Capacitor modules 1529 have been formed over nitride barrier regions 1526 on the top surface of structure 1400. This process flow of capacitor formation allows the use of redistribution layers (RDLs) to be skipped. Typical DRAMs use RDL interconnects to rotate the cell contacts into a hexagonal form for capacitor landing. The capacitor is preferably in hexagonal form because it has the highest surface area (and therefore storage capacity) when it is hexagonal. Having a hexagonal active area removes the need for patterning hexagonal RDL modules. Avoiding the use of several RDLs can reduce the manufacturing cost of the memory device.

[0037] Fig.16 Display in processing Fig.15 Structure 1500 is followed by structure 1600. Structure 1500 has been flipped and bonded to carrier wafer 1603 to form structure 1600. The flipped and bonded structure has been subjected to a CMP process.

[0038] Fig.17 Display in processing Fig.161700. BL 1735 has been formed and patterned on top of structure 1600. The formation of BL 1735 may include using a subtractive process. Hard mask 1738 has been formed on each of BL 1735. Hard mask 1738 has been used to pattern BL 1735. During the subtractive process, hard mask 1738 may be patterned together with the material used for BL 1735 metal. Hard mask 1738 may be, but is not limited to, a nitride hard mask. The pattern of BL 1735 and hard mask 1738 has been formed with a space between BL 1735 and hard mask 1738. BL 1735 may be formed by a deposition technique suitable for the material of the BL and the design of the memory device. BL 1735 may be a conductive line, such as, but not limited to, a metal line.

[0039] Fig.18 Display in processing Fig.17 1700. After patterning to produce structure 1700, dielectric spacers 1838 have been formed that cover the sidewalls of BL 1735 and on top of hard mask 1738. Dielectric spacers 1838 may be, but are not limited to, oxides formed by appropriate oxide deposition techniques. Dielectric spacers 1838 do not completely fill the spaces between BL 1735. Shielding lines 1836 have been formed in the spaces between dielectric spacers 1838 covering the combination of BL 1735 and hard mask 1738, and have been formed vertically downward from body shield 1817. Shielding lines 1836 may be structured so that the bottom of shielding lines 1836 is aligned with the bottom of BL 1735. Shielding lines 1836 may be formed to have a height equal to or greater than the height of BL 1735. Body shield 1817 may be formed above the combined hard mask 1738. The shield wire 1836 may be a conductive shield wire, such as but not limited to a metal shield wire. The main shield 1817 may be formed as a conductive plate-like structure, such as but not limited to a metal plate-like structure. The material used for the main shield 1817 may be the same or similar to the material used for the shield wire 1836. The shield wire 1836 and the main shield 1817 may be formed using deposition techniques suitable for the conductive materials used for these structures.

[0040] Fig.19 Display in processing Fig.18 1800. A bonding layer 1912 has been formed on top of structure 1900. Bonding layer 1912 may be an oxide layer, such as but not limited to silicon oxide. Bonding layer 1912 may be formed by a deposition technique suitable for the material used for bonding layer 1912. With bonding layer 1912 formed, structure 1900 is ready to be bonded to the top of a control circuit system wafer, where the control circuit system wafer is on top of structure 1900 and capacitor module 1529 extends downward, as shown in FIG. Figure 1 Displayed in.

[0041] Fig. 20 The display can be similar to Figure 1 101 (which is the bottom wafer of DRAM 100) is arranged like an array wafer 2001 as a bottom wafer, and can be arranged according to Figures 4 to 19 Although multiple transistors are shown, only one transistor 2021 is marked for ease of representation. Figures 17 to 19 The BL1735 is used for Fig.12 and 14 The material of WL 1230 of the memory cell may be constructed at an angle other than 90 degrees. BL 1735 may be constructed at an angle of, but not limited to, 60 degrees relative to the material used for WL 1230. The center of BL 1735 may be aligned with the center of the active area of ​​transistor 2021 used for the memory cell. BL 1735 is not shared with adjacent transistors 2021. The material used for WL 1230 may be shared with adjacent transistors 2021, and WL 1230 may become WL 130 (e.g., Figure 1 1230), where each transistor 2021 can be associated with a bit. For example, the all-around gate of a transistor 2021 along one line of material for WL 1230 can be material integrated with one line of material for WL 1230. The center of the material for WL 1230 can be aligned in the middle of two adjacent transistors 2021.

[0042] Fig.21 The display can be similar to Figure 1 1, which is a top wafer of DRAM 100. Control circuit wafer 2102 may include SWD 2139-1, SWD 2139-2, SA 2140-1, and SA 2140-2. Control circuit wafer 2102 may be bonded to Fig. 20 1735, with SWD 2139-1 and SWD 2139-2 aligned with selected material lines for WL 1230, and SA 2140-1 and SA 2140-2 aligned with selected lines of BL 1735. The wafer-to-wafer arrangement of control circuitry wafer 2102 with array wafer 2001 having angled BL 1735 may include exits between wafers at selected ones in triangle 2034 providing interconnect distribution.

[0043] Fig. 22 Display for Fig.21 The control circuit system chip 2102 and Fig. 20 2200 of the connections of the array core in a wafer-to-wafer arrangement of an array wafer 2001 of FIG. 2200. The array core is a sub-array of memory cells of a memory array of a memory, wherein the sub-array is associated with one or more SWDs for the WLs of the sub-array and one or more SAs for the BLs of the sub-array. A memory array may be constructed with one or more sub-arrays. The array core may be arranged with SAs along one axis relative to the sub-arrays, and SWDs arranged along another direction. Representation 2200 shows an angled arrangement of tiles 2205 for the BLs 1735 and WLs 1230 of the sub-arrays of memory cells that may be implemented in the array wafer 2001. Tiles may also be referred to as pads. Tiles 2205 in the array wafer 2001 may be positioned below components SWDs 2139-1 and 2139-2 and SAs 2140-1 and 2140-2 of the control circuitry wafer 2102. In this two-dimensional view, the tile 2205 may be arranged with BL slot regions 2215-1 and 2215-2 along one axis direction, and with WL slot regions 2216-1 and 2216-2 along another axis direction.

[0044] BL slot region 2215-1 may include interconnects for BL 1735 of array wafer 2001 to SA 2140-1 of control circuitry wafer 2102. The interconnects may include triangular BL slots 2214-1 at the edge of array tile 2205. BL slot region 2215-2 may include interconnects for BL 1735 of array wafer 2001 to SA 2140-2 of control circuitry wafer 2102. The interconnects may include triangular BL slots 2214-2 at the edge of array tile 2205. WL slot region 2216-1 may include interconnects for WL 1230 of array wafer 2001 to SWD 2139-1 of control circuitry wafer 2102. The interconnects may include triangular WL slots 2211-1 at the edge of array tile 2205. The WL slot area 2216-2 may include interconnects for the WL 1230 of the array wafer 2001 to the SWD 2139-2 of the control circuitry wafer 2102. The interconnects may be triangular WL slots 2211-2 at the edge of the array tile 2205. The BL 1735 may be formed as Figure 1 The BL 135 and WL 1230 of the DRAM 100 are formed as Figure 1In the case of WL 130 of DRAM 100 of FIG. 1 , the triangular BL slots 2214-1 and 2214-2 and the WL slots 2211-1 and 2211-2 can provide connections with the line contacts 146, the landing pads 144, the bonding contacts 143, and the metal wires 141 of the DRAM 100. The triangular WL slots and BL slots can be formed at the edge of the array tile when preparing an array wafer, which can be prepared before preparing a control circuit system wafer in the manufacturing process flow.

[0045] Various deposition techniques that are typical for the components in the process flow discussed herein may be used for the materials formed, the sizes of the materials formed, and the architecture of the materials formed in the manufacture of the memory device. The materials and structures may be formed by suitable processes, such as but not limited to deposition processes, including but not limited to physical vapor deposition (PVD), CVD, ALD or other deposition processes. Other processes may be used. Selective etching may be used to remove selected areas in the processing discussed with respect to the process flow. Selective etching is a process in which one or more materials are removed from the structure while one or more other materials remain in the structure without removal or very little removal. Selective etching may depend on the material to be etched, the material not to be etched, the etchant used, and the method for etching. The types of etching include wet etching and dry etching, each of which includes several different etching processes in these two basic methods. In addition, conventional masking techniques that provide protection zones in the process may be used to remove selected areas when forming components of the memory device.

[0046] Fig.23 23 is a flow chart of features of an embodiment of an example method 2300 of forming a memory device. At 2310, an array of memory cells is formed. Each memory cell of the array is formed as a gate all around (GAA) transistor having a hexagonal vertical channel transistor arranged to couple to a capacitor, wherein the capacitor has a hexagonal arrangement.

[0047] At 2320, a set of WLs is formed. A WL in the set of WLs is coupled to gates of a first plurality of GAA transistors of a memory cell.

[0048] At 2330, a set of BLs are formed to be angled relative to the set of WLs at an angle different from 90 degrees. The angle may be, but is not limited to, 60 degrees. The BLs in the set of BLs are coupled to a second plurality of GAA transistors of the memory cell.

[0049] Variations of method 2300 or methods similar to method 2300 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture of systems including memory devices implementing such methods. Such methods may include forming control logic, decoders, drivers, and sensing circuitry over an array.

[0050] A variation of method 2300 or a method similar to method 2300 may include forming a metal shielding wire between adjacent BLs in the set of BLs. The metal shielding wire may be formed to extend vertically from the metal body shield.

[0051] A variation of method 2300 or a method similar to method 2300 may include forming a vertical nanowire extending above a substrate, wherein the vertical nanowire may be structured with a channel structure around which a gate of a GAA transistor is formed.

[0052] In various embodiments, a memory device may include an array of memory cells, wherein each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor, wherein the capacitor has a hexagonal arrangement. The memory device may include a set of WLs, wherein a WL in the set of WLs is coupled to a gate of a first plurality of GAA transistors of the memory cell. The memory device may include a set of BLs, wherein a BL in the set of BLs is coupled to a second plurality of GAA transistors of the memory cell. The set of BLs may be angled at an angle other than 90 degrees relative to the set of WLs.

[0053] As taught herein, variations of such memory devices and features thereof may include several different embodiments and features that may be combined depending on the application of such memory devices, the format of such memory devices, and / or the architecture in which such memory devices are implemented. Variations of such memory devices may include control logic and sensing circuitry above the array. The control logic and sensing circuitry and the memory cell array may be arranged in a wafer-to-wafer interconnect architecture. The wafer-to-wafer interconnect architecture may include a wafer-on-wafer architecture.

[0054] Variations of this memory device and features thereof may include shield lines between adjacent BLs in the set of BLs. The shield lines may extend vertically from the body shield. Variations may include a channel structure and active area of ​​a GAA transistor structured as a vertical nanowire. Variations may include a digit line positioned on a side of a dielectric region opposite to a side of the dielectric region on which an access line is placed, the dielectric region may contain a vertical channel structured as a pillar of epitaxial semiconductor material. Variations of this memory device may include a 4F 2 A memory cell array of a cell configuration.

[0055] Fig.24is a schematic diagram of an electrical arrangement of components of an embodiment of an example DRAM device 2400, which may include an architecture having an array of memory cells arranged as hexagonal cells, wherein each of the memory cells has a GAA transistor coupled to a capacitor, wherein the memory cell is coupled to a WL and a BL, wherein the BL is angled at an angle other than 90 degrees relative to the WL, and Figures 1 to 23 DRAM device 2400 may include memory cells 2425 arranged in rows 2454-1, 2454-2, 2454-3, and 2454-4 and columns 2456-1, 2456-2, 2456-3, and 2456-4 (for ease of presentation, the memory cells 2425 are shown in FIG. Fig.24 2454-1, 2454-2, 2454-3, and 2454-4 and four columns 2456-1, 2456-2, 2456-3, and 2456-4 of four memory cells are illustrated, a DRAM device such as DRAM device 2400 may have significantly more memory cells 2425 per row or column (e.g., tens, hundreds, or thousands of memory cells).

[0056] Each memory cell 2425 may include a single transistor 2421 and a single capacitor 2429, which is often referred to as a 1T1C (single transistor-single capacitor cell). One plate of the capacitor 2429, which may be referred to as a "node plate," is connected to the drain terminal of the transistor 2421, while the other plate of the capacitor 2429 is connected to ground 2424 or other reference node. Each capacitor 2429 within an array of 1T1C memory cells 2425 is typically used to store one bit of data, and a corresponding transistor 2421 is used as an access device to write to or read from the storage capacitor 2429. Each transistor 2421 may be implemented by a GAA nanowire transistor.

[0057] The transistor gate terminals within each of the rows 2454-1, 2454-2, 2454-3, and 2454-4 are part of the respective WLs 2430-1, 2430-2, 2430-3, and 2430-4, and the transistor source terminals within each of the columns 2456-1, 2456-2, 2456-3, and 2456-4 are electrically connected to the respective BLs 2435-1, 2435-2, 2435-3, and 2435-4. The row decoder 2432 may selectively drive the individual WLs 2430-1, 2430-2, 2430-3, and 2430-4 in response to a row address signal 2431 input to the row decoder 2432. The row decoder 2432 may include one or more SWD and address decoder circuits. Driving a given WL at a high voltage turns on the access transistors within the corresponding row, connecting the storage capacitors within the row to the corresponding data lines so that charge can be transferred between the data lines and the storage capacitors for read or write operations. Both read and write operations can be performed via the SA circuitry 2440, which can transfer bit values ​​between the memory cells 2425 of the selected row in rows 2454-1, 2454-2, 2454-3, and 2454-4 and the input / output buffer 2446 (for write / read operations) or the external input / output data bus 2448.

[0058] The column decoder 2442 responsive to the column address signal 2441 can select which memory cells 2425 within the selected row are read or written. Alternatively, for a read operation, the storage capacitors 2429 within the selected row can be read and latched simultaneously, and the column decoder 2442 can then select which latched bits are connected to the output data bus 2448. Since the readout of the storage capacitors destroys the stored information, the read operation is accompanied by a simultaneous rewrite of the capacitor charge. In addition, between read / write operations, the capacitor charge is repeatedly refreshed to prevent data loss. The details of the read / rewrite, write, and refresh operations are well known to those of ordinary skill in the art.

[0059] DRAM device 2400 may be implemented as an IC within a package that includes pins for receiving supply voltages (eg, to provide source and gate voltages for transistor 2421) and signals (including data, address, and control signals). Fig.24DRAM device 2400 is depicted in simplified form to illustrate basic structural components, omitting many details of memory cells 2425 and associated WLs 2430-1, 2430-2, 2430-3, and 2430-4 and BLs 2435-1, 2435-2, 2435-3, and 2435-4 and peripheral circuitry. For example, in addition to row decoder 2432, column decoder 2442, SA circuitry 2440, and buffer 2446, DRAM device 2400 may also include another peripheral circuitry, such as a memory control unit that controls memory operations based on control signals (e.g., provided by an external processor), additional input / output circuitry, or other features associated with a memory device. The details of this peripheral circuitry are generally known to those of ordinary skill in the art and are not discussed further herein. The peripheral circuitry can be positioned above the array of memory cells 2425 using a CoA architecture of a wafer-to-wafer interconnect architecture.

[0060] In a two-dimensional (2D) DRAM array, the rows 2454-1, 2454-2, 2454-3, and 2454-4 and columns 2456-1, 2456-2, 2456-3, and 2456-4 of memory cells 2425 may be arranged along a single horizontal plane of the semiconductor substrate (i.e., a plane parallel to the layers), for example, in a rectangular lattice with horizontal WLs 2430-1, 2430-2, 2430-3, and 2430-4 on one plane and angled BLs 2435-1, 2435-2, 2435-3, and 2435-4 on another plane. In a 3D DRAM array, the memory cells 2425 may be arranged in a 3D lattice, with one set of memory cells and associated WLs and BLs at a level above another set of memory cells and their associated WLs and BLs.

[0061] Having the same or similar features as the example DRAM device 2400 and Figures 1 to 23The memory device of the associated structure can be implemented in various electronic devices. Electronic devices such as mobile electronic devices (such as smart phones, tablet computers and other similar communication-related devices), electronic devices used in automotive applications (such as automotive sensors, control units, driver assistance systems, passenger safety, comfort systems or other similar systems) and Internet connection devices or devices (such as Internet of Things (IoT) devices or other network-related devices) have different storage requirements, especially depending on the type of electronic device, the use environment, performance expectations or other criteria. Such electronic devices can be divided into several main components: a processor (such as a central processing unit (CPU) or other main processor); a memory (such as one or more volatile or non-volatile RAM memory devices, such as DRAM, mobile or low-power double data rate synchronous DRAM (DDR SDRAM), or other similar memory devices); and a storage device (such as a non-volatile memory (NVM) device, such as flash memory, ROM, solid-state drive (SSD), multimedia card (MMC), other memory card structures or assemblies or other similar storage devices). In some examples, the electronic device may include a user interface (e.g., a display, a touch screen, a keyboard, one or more buttons, or other similar docking structures), a graphics processing unit (GPU), a power management circuit, a baseband processor, one or more transceiver circuits, or other similar devices. As used herein, "processor device" means any type of computing circuitry, such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit (including a processor group or multi-core device).

[0062] The following examples are example embodiments of devices and methods according to the teachings herein.

[0063] An example memory device 1 may include an array of memory cells, wherein each of the memory cells has a GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor, the capacitor having a hexagonal arrangement; a group of WLs having a WL in the group of WLs coupled to gates of a first group of multiple GAA transistors of the memory cells; and a group of BLs having a BL in the group of BLs coupled to a second group of multiple GAA transistors of the memory cells, the group of BLs being angled at an angle different from 90 degrees relative to the group of WLs.

[0064] Example memory device 2 may include features of example memory device 1, and may include control logic, decoders, drivers, and sensing circuitry above the array.

[0065] Example memory device 3 may include features of example memory device 2 and any of the previous example memory devices, and may include control logic and sensing circuitry and a memory cell array arranged in a die-to-die interconnect architecture.

[0066] Example memory device 4 may include features of any of the aforementioned example memory devices, and may include shielding lines between adjacent BLs in the set of BLs.

[0067] Example memory device 5 may include features of example memory device 4 and any of the preceding example memory devices and may include a shield line having a height equal to or greater than the height of the BL.

[0068] Example memory device 6 may include features of example memory device 4 and any of the aforementioned example memory devices and may include a shield line extending vertically from a body shield.

[0069] Example memory device 7 may include features of any of the aforementioned example memory devices, and may include a 4F 2 A memory cell array of a cell configuration.

[0070] The example memory device 8 may include features of any of the aforementioned example memory devices and may include a channel structure and active region of a GAA transistor structured as a vertical nanowire.

[0071] Example memory device 9 may include features of any of the foregoing example memory devices and may include digit lines positioned on a side of a dielectric region opposite the side of the dielectric region on which access lines are placed, the dielectric region containing vertical channels structured as pillars of epitaxial semiconductor material.

[0072] In example memory device 10, any of the memory devices of example memory devices 1-9 may include a memory device incorporated into an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0073] In example memory device 11, any of the memory devices of example memory devices 1-10 may be modified to include any structure presented in another of example memory devices 1-10.

[0074] In example memory device 12, any apparatus associated with the memory devices of example memory devices 1-11 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0075] In example memory device 13, any of the memory devices of example memory devices 1-12 may be formed according to any of the following example methods 1-10 of forming a memory device or example methods 11-20 of forming a memory device.

[0076] An example method 1 of forming a memory device may include forming a memory cell array, comprising forming each of the memory cells having a gate all around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor, the capacitor having a hexagonal arrangement; forming a set of WLs having WLs in the set of WLs coupled to gates of a first set of multiple GAA transistors of the memory cells; and forming a set of BLs, the set of BLs being angled at an angle different from 90 degrees relative to the set of WLs, the set of digit lines having BLs in the set of BLs coupled to a second set of multiple GAA transistors of the memory cells.

[0077] Example method 2 of forming a memory device may include features of example method 1 of forming a memory device, and may include forming control logic, decoders, drivers, and sensing circuitry over the array.

[0078] Example method 3 of forming a memory device may include features of any of the preceding example methods of forming a memory device, and may include forming a metal shield line between adjacent BLs in the set of BLs.

[0079] Example method 4 of forming a memory device may include features of example method 3 of forming a memory device and any of the foregoing example methods of forming a memory device, and may include forming a metal shield line to include forming the metal shield line extending vertically from a metal body shield.

[0080] Example method 5 of forming a memory device may include features of any of the foregoing example methods of forming a memory device, and may include forming a vertical nanowire extending over a substrate, wherein the vertical nanowire has a channel structure around which a gate of a GAA transistor is formed.

[0081] Example method 6 of forming a memory device may include features of any of the preceding example methods of forming a memory device, and may include forming a BL in a subtractive process.

[0082] Example method 7 of forming a memory device may include features of any of the preceding example methods of forming a memory device, and may include forming the set of digit lines angled at 60 degrees relative to the set of access lines.

[0083] In example method 8 of forming a memory device, any of example methods 1-7 of forming a memory device may be performed in forming an electronic device further comprising a host processor and a communication bus extending between the host processor and the memory device.

[0084] In example method 9 of forming a memory device, any of the example methods 1-8 of forming a memory device may be modified to include operations set forth in any other of the example methods 1-8 of forming a memory device.

[0085] In example method 10 of forming a memory device, any of example methods 1-9 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0086] Example method 11 of forming a memory device may include features of any of the foregoing example methods 1-10 of forming a memory device, and may include performing functions associated with forming any of the features of example memory devices 1-13.

[0087] An example method 12 of forming a memory device may include: preparing an array wafer in which a GAA transistor array is connected to a WL and a BL, and in which the BL is angled at an angle other than 90 degrees relative to the WL; preparing a control circuit system wafer; bonding the array wafer and the control circuit system wafer together; and performing BEOL processing on the control circuit system wafer after bonding the array wafer and the control circuit system wafer together.

[0088] Example method 13 of forming a memory device may include features of example method 12 of forming a memory device, and may include forming the GAA transistor as a thin film transistor.

[0089] An example method 14 of forming a memory device may include features of any of the aforementioned example methods 12 to 13 of forming a memory device, and may include preparing an array wafer to include, after forming GAA transistors and WLs to the GAA transistors: forming capacitors vertically coupled to the GAA transistors; flipping the array wafer and bonding the array wafer to a carrier wafer; thinning the carrier wafer; and forming digit lines coupled to the capacitors with shield lines between the BLs.

[0090] An example method 15 of forming a memory device may include features of any of the aforementioned example methods 12 to 14 of forming a memory device, and may include preparing an array wafer to include forming bonding interconnects in preparation for bonding the array wafer to a control circuit system wafer, and preparing a control circuit system wafer to include forming bonding contacts to couple to the bonding interconnects.

[0091] Example method 16 of forming a memory device may include features of any of the foregoing example methods 12-15 of forming a memory device, and may include forming an array tile having triangular WL slots at edges of the array tile.

[0092] Example method 17 of forming a memory device may include features of example method 16 of forming a memory device and any of the aforementioned example methods 12 to 15 of forming a memory device, and may include forming a bonding interconnect between a WL on an array wafer and a SWD on a control circuit system wafer through a triangular WL slot structure placed at an edge of an array tile.

[0093] Example method 18 of forming a memory device may include features of any of the aforementioned example methods 12-17 of forming a memory device and may include bonding an array wafer and a control circuitry wafer together to include fusing oxide regions on the array wafer with oxide regions on the control circuitry wafer.

[0094] An example method 19 for forming a memory device may include features of any of the aforementioned example methods 12 to 18 for forming a memory device, and may include bonding an array wafer to a control circuit system to include aligning one or more SA circuits on the control circuit system wafer over BL slots placed on the array wafer, and aligning one or more SWD circuits on the control circuit system wafer over WL slots on the array wafer.

[0095] The example method 20 of forming a memory device may include features of any of the foregoing example methods 12-19 of forming a memory device, and may include efficiently distributing BL and WL connections within the BL and WL exit slot areas to reduce interconnect parasitics and congestion.

[0096] Example method 21 of forming a memory device may include features of any of the foregoing example methods 12-20 of forming a memory device, and may include forming an array of GGA transistors as a 4F 2 Hexagonal memory cells in the architecture.

[0097] Example method 22 of forming a memory device may include features of example method 21 of forming a memory device and any of the foregoing example methods 12-21 of forming a memory device, and may include converting 4F 2 The architecture is configured as a parallelogram with an angle between BL and WL, which allows word lines to be shared by adjacent GAA vertical transistors, thereby reducing overall word line resistance and achieving scaling or die size savings.

[0098] In example method 23 of forming a memory device, any of example methods 12-12 of forming a memory device may be performed in forming an electronic device further including a host processor and a communication bus extending between the host processor and the memory device.

[0099] In example method 24 of forming a memory device, any of example methods 12-23 of forming a memory device may be modified to include operations set forth in any other of example methods 11-17 of forming a memory device.

[0100] In example method 25 of forming a memory device, any of example methods 12-24 of forming a memory device may be implemented at least in part by using instructions stored as a physical state in one or more machine-readable storage devices.

[0101] Example method 26 of forming a memory device may include features of any of the foregoing example methods 12-25 of forming a memory device, and may include performing functions associated with any of the features of example memory devices 1-13.

[0102] The example method of operating a memory device may include performing functions associated with any features of the example memory devices 1-13 as well as the functions of the memory devices formed by the example methods 1-26.

[0103] An example machine-readable storage device storing instructions that, when executed by one or more processors, cause the machine to perform operations may include instructions to perform functions associated with any feature of the example memory devices 1-13 or to perform methods associated with any feature of the example methods 1-26 of forming a memory device.

[0104] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. Various embodiments utilize permutations and / or combinations of the embodiments described herein. It should be understood that the above description is intended to be illustrative and not limiting, and that the words or terminology employed herein are for descriptive purposes.

Claims

1. A memory device, comprising: a memory cell array wherein each of the memory cells has a gate-all-around GAA transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor, the capacitor having a hexagonal arrangement; a set of access lines having an access line of the set of access lines coupled to gates of a first plurality of GAA transistors of the memory cell; and A set of digit lines having digit lines of the set of digit lines coupled to a second plurality of GAA transistors of the memory cell, the set of digit lines being angled at an angle other than 90 degrees relative to the set of access lines.

2. The memory device of claim 1, wherein the memory device includes control logic, decoders, drivers, and sensing circuitry above the array.

3. The memory device of claim 2, wherein the control logic and sensing circuitry and the memory cell array are arranged in a wafer-to-wafer interconnect architecture.

4. The memory device of claim 1, wherein the memory device includes shielding lines between adjacent digit lines in the set of digit lines. The memory device of claim 4 , wherein the shield line extends vertically from a body shield.

6. The memory device of claim 1, wherein the memory cell array has a 4F 2 Unit configuration.

7. The memory device of claim 1, wherein a channel structure and an active area of ​​the GAA transistor are structured into vertical nanowires.

8. The memory device of claim 1, wherein the digit line is positioned on a side of a dielectric region opposite a side of the dielectric region on which the access line is placed, the dielectric region containing vertical channels structured as pillars of epitaxial semiconductor material.

9. A method of forming a memory device, the method comprising: forming a memory cell array including forming each of the memory cells as a gate-all-around GAA transistor having a hexagonal vertical channel transistor arranged to be coupled to a capacitor, the capacitor having a hexagonal arrangement; forming a set of access lines having an access line of the set of access lines coupled to gates of a first plurality of GAA transistors of the memory cell; and A set of digit lines angled at an angle other than 90 degrees relative to the set of access lines is formed, the set of digit lines having digit lines in the set of digit lines coupled to a second plurality of GAA transistors of the memory cell.

10. The method of claim 9, wherein the method includes forming control logic, decoders, drivers, and sensing circuitry over the array.

11. The method of claim 9, wherein the method includes forming a metal shield line between adjacent digit lines in the set of digit lines.

12. The method of claim 11, wherein forming the metal shield wire comprises forming the metal shield wire extending vertically from a metal body shield.

13. The method of claim 9, wherein the method comprises forming a vertical nanowire extending above a substrate, wherein the vertical nanowire has a channel structure around which a gate of the GAA transistor is formed.

14. The method of claim 9, wherein the method includes forming the set of digit lines angled at a 60 degree angle relative to the set of access lines.

15. A method of forming a memory device, the method comprising: preparing an array wafer having an array of gate-all-around GAA transistors connected to access lines and digit lines, and having the digit lines angled at an angle other than 90 degrees relative to the access lines; Prepare control circuit system chip; Bonding the array chip and the control circuit system chip together; and After the array wafer and the control circuit system wafer are bonded together, a back-end process is performed on the control circuit system wafer.

16. The method of claim 15, wherein the method comprises forming the GAA transistor as a thin film transistor.

17. The method of claim 15, wherein preparing the array wafer comprises, after forming the GAA transistors and access lines to the GAA transistors: forming a capacitor vertically coupled to the GAA transistor; flipping the array wafer and bonding the array wafer to a carrier wafer; thinning the carrier wafer; and The digit lines are formed coupled to the capacitors with a shield line between the digit lines.

18. The method of claim 15, wherein preparing the array wafer includes forming bonding interconnects in preparation for bonding the array wafer and the control circuitry wafer together, and preparing the control circuitry wafer includes forming bonding contacts to couple to the bonding interconnects.

19. The method of claim 15, wherein bonding the array wafer and the control circuitry wafer together comprises fusing oxide regions on the array wafer with oxide regions on the control circuitry wafer.

20. The method of claim 15, wherein the method comprises forming the array of GAA transistors into a 4F 2 Hexagonal memory cells in the architecture.

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