Memory device and manufacturing method thereof

Abstract

The invention discloses a storage device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing an array substrate; forming a switching device on the first surface of the array substrate; after a switching device is formed on the first surface, bonding a control chip on the first surface; after a control chip is bonded on the first surface, a storage capacitor is formed on a second surface of the array substrate, and the second surface and the first surface are arranged oppositely. After the control chip is bonded, the storage capacitor is formed, so that the manufacturing process steps before the storage capacitor is formed can be effectively increased, the limitation of materials in the storage capacitor in more process steps can be eliminated, the manufacturing process difficulty of the storage device can be effectively reduced, and the manufacturing process window of the storage device can be effectively expanded; and after the control chip is bonded, mechanical support is provided by the control chip to form the storage capacitor, so that an additionally provided bearing wafer can be omitted, and the manufacturing cost of the storage device can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a storage device and a manufacturing method thereof. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration. For storage devices, people's requirements for storage density and read / write speed of storage devices are becoming higher and higher.

[0003] In order to improve integration and reduce costs, the size of storage cells is getting smaller and smaller, and the circuit density inside the storage device is getting higher and higher. The reduction in the size of storage cells and the increase in the circuit density inside the storage device make it more difficult to further increase the storage density and the read and write speed; in addition, the manufacturing difficulty of high storage density and high read and write speed storage devices is also increasing, and the process window is also shrinking. Summary of the invention

[0004] The problem solved by the present invention is how to reduce the manufacturing difficulty and expand the process window in manufacturing a storage device with high storage density and high read and write speed.

[0005] In order to solve the above problems, the present invention provides a method for manufacturing a storage device, comprising:

[0006] An array substrate is provided; a switching device is formed on a first surface of the array substrate; after the switching device is formed on the first surface, a control chip is bonded on the first surface; after the control chip is bonded on the first surface, a storage capacitor is formed on a second surface of the array substrate, wherein the second surface and the first surface are arranged opposite to each other.

[0007] Optionally, the method further includes: forming a bit line on the first surface after forming a switching device on the first surface and before bonding a control chip on the first surface.

[0008] Optionally, the step of forming a switching device on the first surface includes: forming a switching device on the first surface, and the gate structures of the switching devices arranged along the second direction are connected; the step of forming a bit line on the first surface includes: forming a bit line on the first surface, and the extension direction of the bit line is perpendicular to the second direction.

[0009] Optionally, the step of forming switching devices on the first surface includes: forming switching devices arranged in a densely packed array on the first surface; the step of forming bit lines on the first surface includes: forming bit lines on the first surface, and the same bit lines are connected one by one to switching devices arranged along the extension direction of the bit lines.

[0010] Optionally, the step of forming switching devices on the first surface includes: forming switching devices arranged in an orthogonal array on the first surface; the step of forming bit lines on the first surface includes: forming bit lines on the first surface, the same bit lines are connected to the switching devices arranged along the extension direction of the bit lines at intervals, and adjacent bit lines are connected to the switching devices arranged along the extension direction of the bit lines in an alternating manner.

[0011] Optionally, it also includes: after forming a switching device on the first surface and before forming a bit line on the first surface, forming a bit line connection plug on the switching device; the step of forming a bit line on the first surface includes: forming a bit line connected to the bit line connection plug on the first surface.

[0012] Optionally, it also includes: after bonding the control chip on the first surface and before forming the storage capacitor on the second surface, thinning the array substrate through the second surface to expose the switching device; the step of forming the storage capacitor on the second surface includes: forming the storage capacitor on the thinned second surface.

[0013] Optionally, the step of forming a switching device on the first surface includes: forming a device column located at a position surrounded by an isolation groove pattern and a gate groove pattern; the step of thinning the array substrate to expose the switching device includes: thinning the array substrate to expose the isolation groove pattern and the gate groove pattern.

[0014] Optionally, the step of forming a switching device on the first surface includes: forming a switching device with a fully surrounded gate structure on the first surface.

[0015] Optionally, the step of forming a switch device with a fully enclosed gate structure on the first surface includes: forming a switch device with a fully enclosed gate structure with a vertical channel on the first surface.

[0016] Optionally, the step of forming a switching device on the first surface includes: forming a device column axially perpendicular to the first surface; and forming a gate structure circumferentially surrounding the device column.

[0017] Optionally, in the step of forming device pillars on the first surface, the device pillars are arranged in a close-packed array, or the device pillars are arranged in an orthogonal array.

[0018] Optionally, the step of forming a device column axially perpendicular to the first surface includes: forming at least two isolation groove patterns in the first surface; forming at least two gate groove patterns in the first surface, wherein the gate groove pattern extends along a second direction, and the isolation groove pattern extends along a first direction, and the first direction and the second direction form a preset angle; and forming the device column at a position surrounded by the isolation groove pattern and the gate groove pattern.

[0019] Optionally, at least one of the steps of forming at least two isolation groove patterns in the first surface and the step of forming at least two gate groove patterns in the first surface includes: etching the first surface to form a groove in the first surface, wherein the extension direction of the groove is one of the second direction and the first direction; and filling the groove with a dielectric material.

[0020] Optionally, the step of forming a device column axially perpendicular to the first surface includes: forming a device column located at a position surrounded by an isolation groove pattern and a gate groove pattern; the step of forming a gate structure circumferentially surrounding the device column includes: removing a portion of the thickness of the dielectric material of the isolation groove pattern and the dielectric material of the gate groove pattern to expose the side wall of the device column; and forming a gate structure on the partially exposed side wall of the device column.

[0021] Optionally, the step of forming a gate structure on the partially exposed side wall of the device column includes: forming a prefabricated gate layer on the dielectric material of the remaining isolation groove pattern and the dielectric material of the remaining gate groove pattern, the prefabricated gate layer is located on the side wall of part of the device column; forming a filling layer on the prefabricated gate layer; forming a cutting groove pattern in the filling layer and the prefabricated gate layer, the cutting groove pattern cuts off the prefabricated gate layer along the thickness direction, and the cutting groove pattern is located on the gate groove pattern.

[0022] Optionally, in the step of forming a cutting groove pattern in the filling layer and the prefabricated gate layer, the cutting groove pattern also extends into the dielectric material of the remaining gate groove pattern.

[0023] Optionally, the method further includes: forming a word line connection plug on the first surface after forming a switching device on the first surface and before forming a bonding interconnection layer on the bit line.

[0024] Optionally, the step of forming a switching device on the first surface includes: forming a switching device on the first surface, and connecting the gate structures of the switching devices arranged along the second direction; the step of forming a word line connection plug on the first surface includes: forming a word line connection plug on the first surface, and the word line connection plug is located on one side of the switching device arranged along the second direction, and the switching device is connected to the gate structure of the switching device arranged along the second direction.

[0025] Optionally, after forming the switching device on the first surface and before bonding the control chip on the first surface, a bonding interconnection layer is formed on the first surface; in the step of bonding the control chip on the first surface, the control chip is bonded on the surface of the bonding interconnection layer.

[0026] Optionally, the step of forming a storage capacitor on the second surface includes: forming a storage capacitor on the second surface, wherein a material of the storage capacitor includes a high-K dielectric material.

[0027] Optionally, the step of forming storage capacitors on the second surface includes: forming storage capacitors on the second surface, the storage capacitors being electrically connected to the switching devices in a one-to-one correspondence.

[0028] Optionally, the step of forming a storage capacitor on the second surface includes: forming a first electrode layer and a second electrode layer on the second surface; a capacitor dielectric layer on the second surface, wherein the material of the capacitor dielectric layer includes a high-K dielectric material, and the capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

[0029] Optionally, the method further includes: after forming the storage capacitor on the second surface, forming a lead connection structure on the second surface of the array substrate, the lead connection structure including: a through silicon via substructure penetrating the array substrate.

[0030] Optionally, the method further includes: before forming a storage capacitor on the second surface of the array substrate, forming a doped region in the array substrate.

[0031] In addition, the present invention also provides a storage device, which is manufactured by the manufacturing method of the present invention.

[0032] Optionally, the storage device includes: a storage unit, wherein the storage unit includes: a device column, the device column having a first end and a second end opposite to each other along the axial direction of the device column; a gate structure, the gate structure circumferentially surrounding the device column; a storage capacitor, along the axial direction of the device column, the storage capacitor is located on a side of the device column close to the first end, and the storage capacitor is electrically connected to the first end of the device column.

[0033] Optionally, the width of the first end of the device column is greater than the width of the second end of the device column, wherein the width is a dimension in a plane perpendicular to the axial direction of the device column.

[0034] Optionally, the width of the device column gradually increases in a direction from the second end to the first end.

[0035] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0036] In the technical solution of the present invention, after the switch device is formed on the first surface, a control chip is bonded on the first surface; after the control chip is bonded on the first surface, a storage capacitor is formed on the second surface. After the switch device is formed, the control chip is directly bonded on the switch device; after the control chip is bonded, the storage capacitor is formed, which can effectively increase the manufacturing process steps before the storage capacitor is formed, so that more process steps can remove the material restrictions in the storage capacitor, which can effectively reduce the difficulty of the manufacturing process of the storage device and can effectively expand the manufacturing process window of the storage device; and after the control chip is bonded, the storage capacitor is formed by providing mechanical support with the control chip, which can save the need for an additional carrier wafer and can effectively reduce the manufacturing cost of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1 to 21 is a schematic diagram of the structure of each step of a method for manufacturing a storage device in some embodiments of the present invention;

[0038] Figures 22 to 40 is a schematic structural diagram of each step of a method for manufacturing a storage device in other embodiments of the present invention;

[0039] Fig.41 is a schematic diagram of a three-dimensional structure of a storage unit of a storage device in some embodiments of the present invention;

[0040] Fig.42 is a schematic cross-sectional structural diagram of a storage unit of a storage device in some embodiments of the present invention;

[0041] Fig.43 Schematic diagram of the circuit structure of the storage device in some embodiments of the present invention. DETAILED DESCRIPTION

[0042] As can be seen from the background art, in the prior art, manufacturing storage devices with high storage density and high read / write speed has the problems of high process difficulty and small process window.

[0043] The storage capacitor of the storage device includes: a switch device and a storage capacitor, wherein the switch device has two connection terminals and a control terminal for controlling conduction and disconnection between the two connection terminals, and one electrode of the storage capacitor is connected to one of the connection terminals.

[0044] In storage devices with high storage density and high read / write speed, the capacitor dielectric between the two electrodes of the storage capacitor is generally a high-K dielectric material. High-K dielectric materials are difficult to withstand high temperatures, and high-temperature processes will cause the K value of high-K dielectric materials to decrease, affecting the sense margin. High-K dielectric materials will limit the temperature of the process steps, that is, in the process of manufacturing the storage device, the process temperature of the process steps performed after the capacitor dielectric of the high-K dielectric material is formed cannot be too high.

[0045] The manufacturing process of a storage device with high storage density and high read / write speed includes: forming a switching device in one surface of an array wafer; forming a storage capacitor on the switching device; after forming the storage capacitor, bonding an operating wafer on the storage capacitor; then flipping the array wafer through the operating wafer; after flipping the array wafer, thinning the array wafer through another surface of the array wafer to expose the switching device in the array wafer; forming a bit line and a bonding interconnect layer on the exposed switching device; and then bonding a control chip (CMOS chip) through the bonding interconnect layer.

[0046] It can be seen that in the manufacturing process of the storage device, the storage capacitor is formed before the switching device is formed. The steps before the storage capacitor is formed only include process steps related to the switching device. The steps after the storage capacitor is formed include: forming bit lines, forming bonding interconnect layers and bonding control chips, etc.

[0047] All steps performed after the storage capacitor is formed will be subject to the process restrictions of the high-K dielectric material. Only the steps performed before the storage capacitor is formed will not be subject to the process restrictions of the high-K dielectric material. The fewer the steps before the storage capacitor is formed, the more restrictions the high-K dielectric material will have on the storage device manufacturing process, the fewer options for high-temperature process steps, the greater the process difficulty of the manufacturing process, and the smaller the process window.

[0048] In particular, after the doping process step of forming the doped region, there is often an annealing process step for activation and diffusion. There are fewer steps before the storage capacitor is formed, which seriously limits the selectivity of the sites of the doping process step and the annealing process step in the storage device manufacturing process. The manufacturing process is more difficult and the process window is smaller.

[0049] In order to solve the above technical problem, the present invention provides a method for manufacturing a storage device, comprising:

[0050] Providing an array substrate; forming a switching device on the first surface; bonding a control chip on the first surface after the switching device is formed on the first surface; and forming a storage capacitor on the second surface after the control chip is bonded on the first surface, wherein the second surface and the first surface are arranged opposite to each other.

[0051] According to the technical solution of the present invention, a storage capacitor is formed after bonding the control chip, which can effectively increase the manufacturing process steps before the storage capacitor is formed, so that more process steps can remove the restrictions of the materials in the storage capacitor, which can effectively reduce the difficulty of the manufacturing process of the storage device and effectively expand the manufacturing process window of the storage device; and after bonding the control chip, the storage capacitor is formed by providing mechanical support with the control chip, which can save the need for an additional carrier wafer, and can effectively reduce the manufacturing cost of the storage device.

[0052] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0053] refer to Figures 1 to 21 , showing a schematic structural diagram of each step of a method for manufacturing a storage device in some embodiments of the present invention.

[0054] The manufacturing method of the storage device comprises:

[0055] like Figure 1 As shown, an array substrate 100 is provided; Figures 1 to 11 , forming a switching device 110 on the first surface 101; Figures 12 to 15 After forming the switch device 110 on the first surface 101, a control chip CMOS is bonded on the first surface 101; Figures 16 to 21 After bonding the control chip CMOS on the first surface 101 , a storage capacitor 130 is formed on the second surface 102 of the array substrate 100 , wherein the second surface 102 and the first surface 101 are arranged opposite to each other.

[0056] An embodiment of a method for manufacturing a storage device according to the present invention will be described in detail below with reference to the accompanying drawings.

[0057] First, refer to Figure 1 , providing an array substrate 100.

[0058] The array substrate 100 is used to store an array in a storage device. Figure 1 As shown, the array substrate 100 has a first surface 101 and a second surface 102 that are disposed opposite to each other.

[0059] Specifically, the material of the array substrate 100 is silicon. For example, the material of the array substrate 100 can be selected from single crystal silicon, polycrystalline silicon or amorphous silicon. In other embodiments of the present invention, the material of the array substrate can also be other semiconductor materials. For example, the material of the array substrate can also be a IV group semiconductor material such as germanium, silicon germanium, etc.; the material of the array substrate can also be a III-V group semiconductor material such as gallium arsenide; even, the material of the array substrate can also be a II-VI group semiconductor material. The material of the array substrate can be selected from any material suitable for forming a switching device.

[0060] Next, refer to Figures 1 to 11 After providing the array substrate 100, a switching device 110 (such as Fig.11 as shown).

[0061] in, Figure 1 is a schematic diagram of a top view of the first surface of the array substrate 100 in some embodiments of the present invention; Figure 2 The array substrate 100 in some embodiments of the present invention is Figure 1 A schematic diagram of the cross-sectional structure at the midpoint dash line A1A2; Figure 3 The array substrate 100 and the Figure 1 A schematic diagram of the structure viewed from above in the corresponding direction; Figure 4 The array substrate 100 in some embodiments of the present invention is Figure 3 A schematic diagram of the cross-sectional structure at the midpoint dash line B1B2; Figure 5 The array substrate 100 and the Figure 1 A schematic diagram of the structure viewed from above in the corresponding direction; Figure 6 The array substrate 100 and the Figure 4 Schematic diagram of the cross-sectional structure at the corresponding position; Figure 7 The array substrate 100 and the Figure 1 A schematic diagram of the structure viewed from above in the corresponding direction; Figure 8 The array substrate 100 and the Figure 4 Schematic diagram of the cross-sectional structure at the corresponding position; Fig. 9 The array substrate 100 and the Figure 1 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.10 The array substrate 100 in some embodiments of the present invention is Fig. 9 A schematic diagram of the cross-sectional structure at the position of the midpoint dash line C1C2; Fig.11 The array substrate 100 in some embodiments of the present invention is Fig. 9 Schematic diagram of the cross-sectional structure at the midpoint line D1D2.

[0062] The switch device 110 is used to turn on and off a single memory cell of a memory array in the memory device.

[0063] In some embodiments of the present invention, the step of forming a switching device 110 on the first surface 101 includes: forming a switching device 110 with a fully surrounded gate structure on the first surface 101. The two source-drain doping regions of the switching device 110 are located on both sides of the channel along the extension direction, and the gate structure is used to control the conduction and cutoff of the channel between the two source-drain doping regions. In the switching device 110, the gate structure 112 fully surrounds the channel, which can effectively ensure the control ability of the gate structure over the channel. The gate control ability of the switching device 110 is strong, which can effectively improve the performance of the constituted storage unit.

[0064] In some embodiments, the step of forming a switch device 110 with a gate all around structure on the first surface 101 includes: forming a switch device with a gate all around (GAA) structure with a vertical channel on the first surface 101 .

[0065] The channel of the switching device 110 is along a direction z (eg, Fig.10 or Fig.11 The two source-drain doping regions are located on both sides of the channel along the extension direction. In the direction z perpendicular to the first surface 101, the two source-drain doping regions are located on both sides of the channel. One source-drain doping region, the fully surrounded gate structure and another source-drain doping region are stacked in sequence along the direction z perpendicular to the first surface 101. Within the first surface 101, the occupied area of ​​the switching device 110 is small, which can effectively reduce the occupied area of ​​a single storage cell in the storage array of the storage device, and can effectively improve the storage density of the storage array including the storage cell.

[0066] In some embodiments, the step of forming the switch device 110 on the first surface 101 includes: Figures 1 to 4 , forming a device column 111 axially perpendicular to the first surface 101; Figures 5 to 11 , forming a gate structure 112 surrounding the device pillar 111 in a circumferential direction.

[0067] The device pillar 111 is used to form a channel of the switching device.

[0068] Specifically, the material of the device column 111 is silicon. For example, the material of the device column 111 can be selected from single crystal silicon, polycrystalline silicon or amorphous silicon. In other embodiments of the present invention, the material of the device column can also be other semiconductor materials. For example, the material of the device column can also be IV group semiconductor materials such as germanium and silicon germanium; the material of the device column can also be III-V group semiconductor materials such as gallium arsenide; even, the material of the device column can also be II-VI group semiconductor materials. The material of the device column can be selected from any material suitable for forming a switching device.

[0069] In some embodiments of the present invention, the device column 111 is prismatic. In a cross section perpendicular to the axis (a plane parallel to the first surface 101), the cross section of the device column 111 is square. In other embodiments of the present invention, the device column may also be cylindrical or elliptical. In a cross section perpendicular to the axis, the cross section of the device column is circular or elliptical.

[0070] The device column 111 has an axial direction, and the device column 111 extends along the axial direction, and the axial direction of the device column 111 is perpendicular to the first surface 101. Along the axial direction of the device column 111, the device column 111 has two ends, one of which is suitable for connecting to the storage capacitor of the memory cell, and the other end is suitable for connecting to the bit line BL of the memory array.

[0071] In some embodiments of the present invention, the step of forming the switch device 110 on the first surface 101 includes: forming the switch device 110 in the first surface 101. Figures 1 to 4 The step of forming a device column 111 axially perpendicular to the first surface 101 includes: etching the first surface 101 to form the device column 111 in the first surface 101 .

[0072] In some embodiments, the step of forming a device column 111 axially perpendicular to the first surface 101 includes: forming at least two isolation groove patterns 113 in the first surface 101; forming at least two gate groove patterns 114 in the first surface 101, wherein the gate groove pattern 114 extends along the second direction y, and the isolation groove pattern 113 extends along the first direction x, and the first direction x and the second direction y form a preset angle; and forming the device column 111 at a position surrounded by the isolation groove pattern 113 and the gate groove pattern 114.

[0073] The isolation trench pattern 113 is used to define an active area, and the area between adjacent isolation trench patterns 113 is defined as an active area; the gate trench pattern 114 is used to define the size and position of a gate structure.

[0074] In some exemplary embodiments, at least one of the steps of forming at least two isolation groove patterns in the first surface and the step of forming at least two gate groove patterns in the first surface includes: etching the first surface 101 to form a groove in the first surface 101, wherein the extension direction of the groove is one of the second direction and the first direction; and filling the groove with a dielectric material.

[0075] Specifically, the step of etching the first surface 101 includes: forming a patterned layer (not shown in the figure) on the first surface 101; using the patterned layer as a mask, etching the array substrate 100 to form the substrate (not shown in the figure) and the device column 110.

[0076] The patterning layer is suitable for defining the size and position of the grooves.

[0077] The patterned layer may be a patterned photoresist layer, which may be formed by exposing and developing a spin-coated photoresist; the patterned layer may also be a hard mask layer, which may be formed by etching a mask material layer formed by deposition.

[0078] In the step of etching the array substrate 100 , a partial thickness of the array substrate 100 is etched, and the remaining thickness of the array substrate 100 that has not been etched is suitable for forming the substrate, and the remaining array substrate 100 that has been etched is suitable for forming the device pillar 111 .

[0079] The dielectric material is filled in the groove to provide mechanical support and to achieve electrical insulation between adjacent switching devices.

[0080] For example, the dielectric material filled in the trench may be silicon oxide. In other embodiments of the present invention, the dielectric material may also be a low-K dielectric material, or even an ultra-low-K dielectric material.

[0081] In some exemplary embodiments, the step of forming the device pillar 111 axially perpendicular to the first surface 101 includes: Figure 1 and Figure 2 As shown, the first surface 101 is etched to form an isolation groove (not marked in the figure) in the first surface 101, the isolation groove extends along the first direction x, and a plurality of the isolation grooves are arranged in parallel along the second direction y; a dielectric material is filled in the isolation groove, and the dielectric material also covers the first surface 101; the dielectric material above the first surface 101 is removed to form the isolation groove pattern 113; as shown Figure 3 and Figure 4As shown, the first surface 101 is etched to form a gate trench (not marked in the figure) in the first surface 101, wherein the gate trench extends along the second direction y, and a plurality of isolation trenches are arranged in parallel along the first direction x; a dielectric material is filled in the gate trench, and the dielectric material also covers the first surface 101; and the dielectric material above the first surface 101 is removed to form the gate trench pattern 114.

[0082] The isolation groove pattern 113 and the gate groove pattern 114 are staggeredly distributed in a plane parallel to the first surface 101, and the step of forming a device column 111 axially perpendicular to the first surface 101 also includes: forming the device column 111 at a position surrounded by the isolation groove pattern 113 and the gate groove pattern 114.

[0083] In some embodiments of the present invention, the step of forming the switch devices 110 on the first surface 101 includes: forming the switch devices 110 arranged in an orthogonal array on the first surface 101. The arrangement of the device pillars 111 in the first surface 101 is the same as the arrangement of the switch devices in the first surface of the array substrate 100.

[0084] In some embodiments, in the step of forming the device pillars 111 on the first surface 101, the device pillars 111 are arranged in an orthogonal array. Specifically, the first direction x is perpendicular to the second direction y. The extension direction of the isolation groove pattern 113 and the extension direction of the gate groove pattern 114 are perpendicular to each other. In the step of forming the device pillars 111 at the position surrounded by the isolation groove pattern 113 and the gate groove pattern 114, the material of the array substrate remaining at the position surrounded by the isolation groove pattern 113 and the gate groove pattern 114 forms the device pillars 111.

[0085] It should be noted that in the step of forming the device pillar 111 axially perpendicular to the first surface 101, the depth of the formed gate trench can be equal to the depth of the isolation trench. In the direction z perpendicular to the first surface 101, the size of the isolation trench pattern 113 and the size of the gate trench pattern 114 can be equal.

[0086] In other embodiments of the present invention, the depth of the formed gate trench may also be different from (greater than or less than) the depth of the isolation trench. In the direction z perpendicular to the first surface 101, the size of the isolation trench pattern 113 may also be different from (greater than or less than) the size of the gate trench pattern 114. The relative size of the depth of the formed gate trench and the depth of the isolation trench is determined by the required size of the inversion layer channel formed by the memory cell in the memory array of the memory device.

[0087] refer to Figures 5 to 11 After forming the device pillar 111 , a gate structure 112 surrounding the device pillar 111 is formed.

[0088] Specifically, the switch device 110 is a switch device with a fully enclosed gate structure with a vertical channel. A device column 111 perpendicular to the first surface 101 is used to provide a channel of the switch device; in a plane parallel to the first surface 101, the gate structure 112 surrounds the device column 111. The gate structure 112 is located on the sidewall of the device column 111.

[0089] In some embodiments of the present invention, the step of forming a device pillar 111 axially perpendicular to the first surface 101 includes: forming the device pillar 111 located at a position surrounded by the isolation trench pattern 113 and the gate trench pattern 114; and forming a gate structure 112 circumferentially surrounding the device pillar 111 includes: Figure 5 and Figure 6 As shown, a portion of the dielectric material of the isolation trench pattern 113 and the dielectric material of the gate trench pattern 114 is removed to expose the sidewall of the device pillar 111; Figures 5 to 11 As shown, a gate structure 112 is formed on the partially exposed sidewall of the device pillar 111 (eg, Fig.11 as shown).

[0090] The step of removing a portion of the thickness of the dielectric material of the isolation trench pattern 113 and the dielectric material of the gate trench pattern 114 is used to expose the sidewall of the device pillar 111, thereby providing a basis for the formation of a gate structure.

[0091] The dielectric material of the isolation groove pattern 113 and the dielectric material of the gate groove pattern 114 are not completely removed, and the remaining dielectric material 115 is used to expose the end of the device pillar 111 away from the first surface 101 from the side of the gate structure 112, thereby providing a basis for the formation of the source and drain doping regions of the switching device. The sidewalls of the exposed device pillar 111 and the top of the remaining dielectric material 115 form a gate groove (not marked in the figure).

[0092] Illustratively, the step of removing a portion of the thickness of the dielectric material of the isolation trench pattern 113 and the dielectric material of the gate trench pattern 114 includes: etching the dielectric material of the isolation trench pattern 113 and the dielectric material of the gate trench pattern 114 by one of wet etching and dry etching.

[0093] After removing a portion of the dielectric material of the isolation trench pattern 113 and the dielectric material of the gate trench pattern 114 to form a gate trench, a gate structure 112 (such as Fig.11 as shown).

[0094] In some embodiments, the step of forming the gate structure 112 on the partially exposed sidewall of the device pillar 111 includes: Figures 5 to 8 As shown, a prefabricated gate layer 112c is formed on the dielectric material 115 of the remaining isolation trench pattern and the dielectric material 115 of the remaining gate trench pattern, and the prefabricated gate layer 112c is located on the sidewall of part of the device pillar 111; Figure 7 and Figure 8 As shown, a filling layer 116 is formed on the prefabricated gate layer 112c, and the top of the filling layer 116 is flush with the top of the device column 111; Figures 9 to 11 As shown, a cutting groove pattern 117 is formed in the filling layer 116 and the prefabricated gate layer 112c, and the cutting groove pattern 117 cuts the prefabricated gate layer 112c along the thickness direction. The cutting groove pattern 112c is located at the gate groove pattern 114 (as shown in FIG. Figure 3 and Figure 4 shown).

[0095] In some embodiments, the gate structure 112 includes: a gate electrode 112 a and a gate dielectric layer 112 b , and the gate dielectric layer 112 b is located between the gate electrode 112 a and the device pillar 111 .

[0096] In some embodiments, the gate structure 112 is one of a polysilicon gate structure and a metal gate structure. For example, the material of the gate electrode 112a is polysilicon or metal; the material of the gate dielectric layer 112b is oxide, for example, the oxide can be silicon oxide or a high-K gate dielectric layer.

[0097] Specifically, the step of forming the gate structure 112 on the partially exposed sidewall of the device column 111 includes: forming a gate dielectric layer 112b on the partially exposed sidewall of the device column 111; and forming a gate electrode 112a on a side of the gate dielectric layer 112b away from the device column 111.

[0098] For example, Figure 5 and Figure 6 As shown, the step of forming a gate dielectric layer 112b on the partially exposed side wall of the device column 111 includes: removing a portion of the thickness of the dielectric material of the isolation groove pattern 113 and the dielectric material of the gate groove pattern 114 to expose the side wall of the device column 111, and then forming a gate dielectric material 112f on the exposed side wall surface of the device column 111.

[0099] The gate dielectric material 112f is used to form a gate dielectric layer 112b (eg Figures 9 to 11The exposed sidewalls of the device pillar 111 and the top of the remaining dielectric material 115 form a gate trench (not shown in the figure); the gate dielectric material 112f is located on the exposed sidewalls of the device pillar 111.

[0100] In some embodiments, the step of forming the gate dielectric material 112 f on the exposed sidewall surface of the device pillar 111 includes: forming the gate dielectric material 112 f on the exposed sidewall surface of the device pillar 111 by deposition.

[0101] In some embodiments, the gate dielectric layer 112 b is made of silicon oxide. The step of forming the gate dielectric layer 112 b on the exposed sidewall surface of the device pillar 111 may further include: forming the gate dielectric material 112 f by oxidizing the sidewall of the device pillar 111 .

[0102] The prefabricated gate layer 112c is used to form a gate electrode 112a. The step of forming the prefabricated gate layer 112c on the dielectric material 115 of the remaining isolation trench pattern 113 and the dielectric material 115 of the remaining gate trench pattern 114 includes: after forming a gate dielectric material 112f on the exposed sidewall surface of the device pillar 111, filling the remaining dielectric material 115 with a gate electrode material 112e.

[0103] The exposed sidewalls of the device pillar 111 and the top of the remaining dielectric material 115 form a gate trench (not shown in the figure); the gate dielectric material 112f is located on the sidewalls of the exposed device pillar 111; and the gate electrode material 112e fills the gate trench with the gate dielectric material 112f on the sidewalls.

[0104] Specifically, the step of filling the gate electrode material 112e on the remaining dielectric material 115 includes: after forming the gate dielectric material 112f on the exposed side wall surface of the device column 111, filling the gate groove with electrode material (not shown in the figure), and the electrode material also covers the first surface 101; removing the electrode material on the first surface 101 to form the gate electrode material 112e.

[0105] like Figure 7 and Figure 8 As shown, the gate structure 112a is only located on a portion of the side wall in the middle position of the device column 111; the prefabricated gate layer 112c is only located on a portion of the side wall in the middle position of the device column 111; after forming the gate electrode material 112e, a portion of the thickness of the gate electrode material 112e is removed to form the prefabricated gate layer 112c, so that one end of the device column 111 close to the first surface 101 is exposed from the formed gate structure, thereby providing a basis for the formation of the source and drain doping regions of the switching device.

[0106] It should be noted that, in some embodiments, while partially removing the gate electrode material 112e, partially removing the gate dielectric material 112f to form the gate dielectric layer 112b. In other embodiments of the present invention, partially removing the gate electrode material 112e may also be performed.

[0107] Continue to refer Figure 7 and Figure 8 After forming the prefabricated gate layer 112c, a filling layer 112c is formed on the prefabricated gate layer 112c, and the top of the filling layer 112c is flush with the first surface 101. The filling layer 116 is used to fill the gaps on the prefabricated gate layer 112c, providing a good process foundation for subsequent processes.

[0108] In some embodiments of the present invention, the material of the filling layer 116 may be silicon oxide. In other embodiments of the present invention, the filling layer may also be a low-K dielectric material, or even an ultra-low-K dielectric material.

[0109] Specifically, the step of forming the filling layer 112c on the prefabricated gate layer 112c includes: forming a filling material on the prefabricated gate layer 112c, wherein the filling material also covers the first surface 101; and removing the filling material on the first surface 101 to form the filling layer 116.

[0110] like Figure 7 and Figure 8 As shown, since the gate groove is formed by removing a portion of the thickness of the dielectric material of the isolation groove pattern 113 and the dielectric material of the gate groove pattern 114, and the prefabricated gate layer 112c is formed by filling the gate groove, the prefabricated gate layer 112c is connected in the first direction x and the second direction y; the cutting groove pattern 117 is used to cut off the gate groove pattern 114 to form the gate structure 112.

[0111] In some embodiments of the present invention, the switch devices 110 are arranged in an orthogonal array in the first surface 101; the device pillars 111 are arranged in an orthogonal array in the first surface 101; Figures 9 to 11 As shown, the gate structures 112 adjacent to each other along the second direction y are extended and connected; the cutting groove pattern 117 extends along the second direction y. A plurality of the cutting groove patterns 116 are arranged in parallel along the first direction x.

[0112] Specifically, the gate electrodes 112a adjacent to each other along the second direction y are extended and connected to form a gate electrode layer 112g (eg, Fig. 9 The prefabricated gate layer 112c is divided into a gate electrode layer 112g by the cutting groove pattern 116.

[0113] The cutting groove pattern 117 corresponds to the gate groove pattern 114 one by one, and the cutting groove pattern 117 cuts off part of the prefabricated gate layer 112c on the corresponding gate groove pattern 114 to form two gate electrode layers 112g. The gate electrode layer 112g surrounds a plurality of device pillars 111 arranged along the second direction y.

[0114] In some exemplary embodiments, in the step of forming a cutting groove pattern 117 in the filling layer 116 and the prefabricated gate layer 112c, the cutting groove pattern 117 also extends into the dielectric material 115 of the remaining gate groove pattern 114 to ensure that the cutting groove pattern 117 penetrates the prefabricated gate layer 112c along a direction z perpendicular to the first surface 101.

[0115] In some embodiments of the present invention, after the switch device 110 is formed on the first surface 101, Fig.12 and Fig.13 , a bit line BL is formed on the first surface 101 .

[0116] in, Fig.12 The array substrate 100 and the Figure 1 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.13 The array substrate 100 in some embodiments of the present invention is Fig.12 Schematic diagram of the cross-sectional structure at the midpoint line E1E2.

[0117] The bit line BL is used to be connected to a source-drain doping region of the switch device 110 to implement the operation of data in a storage cell in the storage array of the storage device.

[0118] In some embodiments of the present invention, the step of forming a switching device 110 on the first surface 101 includes: forming a switching device 110 on the first surface 101, and the gate structures 112 of the switching devices 110 arranged along the second direction are connected; the step of forming a bit line BL on the first surface 101 includes: forming a bit line BL on the first surface 101, and the extension direction of the bit line BL is perpendicular to the second direction y.

[0119] Fig.12 and Fig.13 In some of the test positions shown, the bit line BL extends along the second direction y. A plurality of the bit lines BL are arranged in parallel along the first direction x. The extending direction of the bit line BL is perpendicular to the direction in which the gate structure 112 is connected. The extending direction of the bit line BL is perpendicular to the extending direction of the gate electrode layer 112g. The extending direction of the bit line BL is perpendicular to the extending direction of the cutting groove pattern 117.

[0120] In some embodiments of the present invention, the step of forming switching devices 110 on the first surface 101 includes: forming switching devices 110 arranged in an orthogonal array on the first surface 101; the step of forming bit lines BL on the first surface 101 includes: forming bit lines BL on the first surface 101, the same bit lines BL are connected to the switching devices 110 arranged along the extension direction of the bit lines BL at intervals, and adjacent bit lines BL are connected to the switching devices 110 arranged along the extension direction of the bit lines BL in an alternating manner.

[0121] The adjacent bit lines BL are alternately connected to the switch devices 110 arranged along the extending direction of the bit lines BL, which means that two adjacent bit lines BL are alternately connected to the two columns of switch devices 110 arranged along the extending direction of the bit lines BL.

[0122] The switch devices 110 arranged along the extending direction of the bit line BL are led out through the same bit line BL at intervals, and the switch devices 110 arranged perpendicular to the extending direction of the bit line BL are led out through multiple bit lines BL at intervals. In any direction along the extending direction of the bit line BL and in a direction perpendicular to the extending direction of the bit line BL, only one of the two adjacent switch devices 110 is led out through the corresponding bit line BL. The switch devices 110 arranged in an orthogonal array are led out through multiple bit lines BL at intervals.

[0123] Specifically, Fig.12 and Fig.13 As shown, the device pillars 111 arranged along the first direction x are connected to the same bit line BL at intervals, and the device pillars 111 arranged along the second direction y are connected to the corresponding bit lines BL at intervals. In either direction of the first direction x or the second direction y, only one of the two adjacent device pillars is connected to the corresponding bit line BL.

[0124] Among the device pillars 111 arranged in an orthogonal array, a portion of the device pillars 111 are connected to the bit line BL; wherein, among the device pillars 111 connected to the bit line BL, other device pillars surrounding one of the device pillars 111 are distributed in a honeycomb shape (e.g. Fig.12 (shown by the red dashed line).

[0125] In some embodiments, the manufacturing method further comprises: after forming the switch device 110 on the first surface 101 and before forming the bit line BL on the first surface 101, Fig.12 and Fig.13 As shown, a bit line connection plug BCT is formed on the switching device 110 ; the step of forming a bit line BL on the first surface 101 includes: forming a bit line BL connected to the bit line connection plug BCT on the first surface 101 .

[0126] The bit line connection plug BCT is used to realize the connection between the switch device 110 and the bit line BL. Fig.12 and Fig.13 As shown, the bit line BL is located on the first surface 101 , and the bit line BL is located between one end of the device pillar 111 close to the first surface 101 to connect the two.

[0127] The bit line connection plugs BCT are distributed on the switch device 110 at intervals in any direction along the extending direction of the bit line BL and in a direction perpendicular to the extending direction of the bit line BL.

[0128] Specifically, Fig.12 and Fig.13 As shown, along any direction of the first direction x and the second direction y, the bit line connection plugs BCT are spaced apart and distributed on the device pillars 111 arranged in an orthogonal array. In the first surface 101, other bit line connection plugs BCT surrounding one bit line connection plug BCT are distributed in a honeycomb shape (such as Fig.12 (shown by the red dashed line).

[0129] It should be noted that the method of achieving the spaced lead-out of the switch devices 110 arranged in an orthogonal array by distributing the bit line connection plugs BCT is only an example. In other embodiments of the present invention, after all the switch devices are connected to the bit lines, the spaced lead-out of the switch devices can be achieved by cutting the bit lines and other interconnection structures.

[0130] It should also be noted that the adjacent bit lines BL and the adjacent bit line connection plugs BCT are electrically insulated by dielectric materials. Fig.12 The dielectric material is not shown in the figure for clarity.

[0131] In some exemplary embodiments, after the switching device 110 is formed on the first surface 101, a dielectric material (not marked in the figure) is formed on the first surface 101; the step of forming a bit line connection plug BCT on at least a portion of the switching devices 110 arranged along the extension direction of the bit line BL includes: forming a via in the dielectric material, the bottom of the via exposing the end surface of the device column 111 close to the first surface 101; filling the via with a sacrificial material, the top surface of the sacrificial material being flush with the top surface of the dielectric material; after filling with the sacrificial material, forming a bit line groove (not marked in the figure) in the dielectric material, the bottom of the bit line groove exposing the sacrificial material in the via; removing the sacrificial material exposed at the bottom of the bit line groove; filling the bit line groove and the via exposed by removing the sacrificial material with a conductive material to form the bit line BL and the bit line connection plug BCT.

[0132] It should be noted that the method of forming the via hole first and then the bit line trench and forming the bit line BL and the bit line connecting plug BCT by filling the conductive material once is only an example. In other embodiments of the present invention, the process of forming the bit line BL and the bit line connecting plug BCT may also be in other orders.

[0133] like Fig.14 As shown, in some embodiments of the present invention, the manufacturing method further includes: after forming the switch device 110 on the first surface 101, forming a word line connection plug WCT on the first surface 101. Fig.14 The array substrate 100 and the Figure 1 Schematic diagram of the top view structure in the corresponding direction.

[0134] The word line connection plug WCT is located between the gate structure 112 of the switch device 110 and the word line, so as to realize the connection between the gate structure 112 of the switch device 110 and the word line.

[0135] In some embodiments, the step of forming a switching device 110 on the first surface 101 includes: forming a switching device 110 on the first surface 101, and connecting a gate structure 112 of the switching device 110 arranged along the second direction y; the step of forming a word line connection plug WCT on the first surface 101 includes: forming a word line connection plug WCT on the first surface 101, and the word line connection plug WCT is located on one side of the switching device 110 arranged along the second direction y, and the switching device 110 is connected to the gate structure 112 of the switching device 110 arranged along the second direction y.

[0136] Specifically, the gate electrodes 112a adjacent to each other along the second direction y are extended and connected to form a gate electrode layer 112g; the word line connection plug WCT is located at one end of the gate electrode layer 112g and connected to the gate electrode layer 112g.

[0137] In some embodiments, the word line connection plugs WCT are staggered along the direction in which the vertical gate structures 112 are connected. Specifically, the gate electrode layer 112g extends along the second direction y and is arranged along the first direction x; a plurality of the word line connection plugs WCT are staggered along the second direction y. Two adjacent word line connection plugs WCT along the second direction y are respectively connected to two ends of the corresponding gate electrode layer 112g.

[0138] It should be noted that, in some embodiments, the manufacturing method may further include: forming a word line (not shown in the figure) connected to the word line connection plug WCT.

[0139] Continue to refer Fig.14 and Fig.15The manufacturing method further includes: forming a bonding interconnection layer 118 on the first surface 101. Fig.15 The array substrate 100 and the Fig.13 Schematic diagram of the cross-sectional structure at the corresponding position.

[0140] The bonding interconnection layer 118 is used to achieve bonding connection with the control chip CMOS.

[0141] In some embodiments, the manufacturing method further includes: forming a back-end interconnection layer (not shown in the figure) on the first surface, the back-end interconnection layer including bit lines BL and word line connection plugs WCT; the step of forming a bonding interconnection layer 118 on the first surface 101 includes: after the back-end interconnection layer is formed on the first surface, forming the bonding interconnection layer 118 on the surface of the back-end interconnection layer.

[0142] The bonding interconnection layer 118 includes: an interconnection structure and a dielectric material filled between the interconnection structures. The interconnection structure is suitable for realizing the electrical connection between the switch device and the control chip CMOS; the dielectric material is suitable for realizing the connection between the array substrate 100 and the control chip CMOS.

[0143] Continue to refer Fig.15 The manufacturing method further includes: bonding a control chip CMOS on the first surface 101 .

[0144] The control chip CMOS is used to control the storage array in the storage device.

[0145] Specifically, the manufacturing method further includes: forming the control chip CMOS; bonding the control chip CMOS on the first surface 101. The step of forming the control chip CMOS is independent of the step of forming the switch device; and the order of the step of forming the control chip CMOS and the step of forming the switch device is not limited.

[0146] In some embodiments, such as Fig.15 As shown, a bonding interconnection layer 118 is formed on the first surface 101 ; in the step of bonding the control chip CMOS on the first surface 101 , the control chip CMOS is bonded to the surface of the bonding interconnection layer 118 .

[0147] It should be noted that if Fig.15 In some of the embodiments shown, the manufacturing method also includes: forming a bonding interconnection layer 121 on the surface of the control chip CMOS; the step of bonding the control chip CMOS on the first surface 101 includes: bonding the bonding interconnection layer 118 on the first surface 101 to the bonding interconnection layer 121 on the surface of the control chip CMOS relative to each other.

[0148] The bonding interconnection layer 121 on the CMOS surface of the control chip is used to achieve bonding connection with the bonding interconnection layer 118 formed on the first surface 101 .

[0149] The bonding interconnection layer 121 on the surface of the control chip CMOS includes: an interconnection structure and a dielectric material filled between the interconnection structures. The interconnection structure is suitable for realizing the electrical connection between the control chip CMOS and the bonding interconnection layer 118 on the first surface 101; and the dielectric material is suitable for realizing the connection between the array substrate 100 and the control chip CMOS.

[0150] refer to Fig.16 The manufacturing method further comprises: after bonding the control chip CMOS on the first surface 101, thinning the array substrate 100 through the second surface 102 to expose the switch device 110. Fig.16 The array substrate 100 and the Fig.15 Schematic diagram of the cross-sectional structure at the corresponding position.

[0151] The step of thinning the array substrate 100 is used to expose the switching device 110 formed in the array substrate 100 , thereby providing a basis for the subsequent formation of storage capacitors.

[0152] Specifically, the step of thinning the array substrate 100 to expose the switch device 110 includes: removing part of the material of the array substrate 100 through the second surface 102 to thin the array substrate 100 .

[0153] For example, Fig.15 and Fig.16 As shown, after the control chip CMOS is bonded on the first surface 101 , the bonded array substrate 100 is flipped over to use the control wafer including the control chip CMOS as a carrier wafer, and the second surface of the array substrate 100 is masked or etched to thin the array substrate 100 .

[0154] In some embodiments, the step of forming a switching device 110 on the first surface 101 includes: forming a device column 111 axially perpendicular to the first surface 101 ; the step of thinning the array substrate 100 includes: thinning the array substrate 100 to expose an end of the device column 111 away from the first surface 101 .

[0155] In some embodiments, the device column 111 is located at a position surrounded by an isolation groove pattern 113 and a gate groove pattern 114; the step of thinning the array substrate 100 to expose the switching device 101 includes: thinning the array substrate 100 to expose the isolation groove pattern 113 and the gate groove pattern 114.

[0156] The device pillar 111 is located at a position surrounded by the isolation trench pattern 113 and the gate trench pattern 114 .

[0157] The minimum value of the pattern depth of the isolation groove pattern 113 and the pattern depth of the gate groove pattern 114 is related to the position of the end of the device pillar 111 away from the first surface 101 (close to the second surface 102), wherein the pattern depth refers to the size of any one of the isolation groove pattern 113 and the gate groove pattern 114 in the direction z perpendicular to the first surface 101. The step of thinning the array substrate 100 to expose the switch device 101 includes: thinning the array substrate 100 to expose the groove pattern with the smallest pattern depth, the groove pattern being one of the isolation groove pattern 113 and the gate groove pattern 114.

[0158] like Fig.17 In some embodiments shown in the figure, the pattern depth of the isolation trench pattern 113 is equal to the pattern depth of the gate trench pattern 114 (eg, Fig.17 ), in the step of thinning the array substrate 100, the thickness of the array substrate 100 is thinned to be greater than the distance between the end surface of the isolation groove pattern 113 and the gate groove pattern 114 close to the second surface 102 and the second surface 102 (as shown by the blue dotted line in the figure). Fig.17 green dashed line in the middle).

[0159] like Fig.18 In some embodiments shown in the figure, the pattern depth of the isolation trench pattern 113 is greater than the pattern depth of the gate trench pattern 114 (eg, Fig.18 In the step of thinning the array substrate 100, the thickness of the array substrate 100 is thinned to be greater than the distance between the end surface of the gate groove pattern 114 close to the second surface 102 and the second surface 102 (as shown by the blue dotted line in the middle). Fig.18 green dashed line in the middle).

[0160] like Fig.19 In some embodiments shown in the figure, the pattern depth of the isolation trench pattern 113 is less than the pattern depth of the gate trench pattern 114 (eg, Fig.19 In the step of thinning the array substrate 100, the thickness of the array substrate 100 is thinned to be greater than the distance between the end surface of the isolation groove pattern 113 close to the second surface 102 and the second surface 102 (as shown by the blue dotted line in the middle). Fig.19 green dashed line in the middle).

[0161] refer to Fig. 20 After bonding the control chip CMOS on the first surface 101, a storage capacitor 130 is formed on the second surface 102. Fig. 20 The array substrate 100 and the Fig.16 Schematic diagram of the cross-sectional structure at the corresponding position.

[0162] After the control chip is bonded, a storage capacitor is formed, which can effectively increase the manufacturing process steps before the storage capacitor is formed, so that more process steps can remove the material restrictions in the storage capacitor, which can effectively reduce the difficulty of the manufacturing process of the storage device and effectively expand the manufacturing process window of the storage device; and after the control chip is bonded, the control chip provides mechanical support to form the storage capacitor, which can save the need for an additional carrier wafer, and can effectively reduce the manufacturing cost of the storage device.

[0163] It should be noted that, in some embodiments, the manufacturing method includes: before forming the storage capacitor 130 on the second surface 102, thinning the array substrate 100 through the second surface 102 to expose the switching device 110; the step of forming the storage capacitor 130 on the second surface 102 includes: forming the storage capacitor 130 on the thinned second surface 102.

[0164] In some embodiments of the present invention, the step of forming the storage capacitor 130 on the second surface 102 of the array substrate 100 includes: forming the storage capacitor 130 on the second surface 102 of the array substrate 100, wherein the material of the storage capacitor includes a high-K dielectric material.

[0165] After the control chip is bonded, a storage capacitor is formed, which can effectively increase the manufacturing process steps before the storage capacitor is formed, so that more process steps can remove the limitation of the high-K dielectric material in the storage capacitor on the process temperature, which can effectively increase the selectivity of the high-temperature process steps, effectively reduce the difficulty of the manufacturing process of the storage device, and effectively expand the manufacturing process window of the storage device; and after the control chip is bonded, the storage capacitor is formed by providing mechanical support with the control chip, which can save the need for an additional carrier wafer, and can effectively reduce the manufacturing cost of the storage device.

[0166] It should be noted that, in some embodiments of the present invention, the manufacturing method further includes: before forming the storage capacitor 130 on the second surface 102 of the array substrate 100 , forming a doped region in the array substrate 100 .

[0167] In some embodiments, the doped region may be a source-drain doped region of the switch device. In other embodiments of the present invention, the doped region may also be other doped regions in the array substrate. In some exemplary embodiments, the step of forming the doped region in the array substrate 100 includes: doping the array substrate 100; and annealing the doped array substrate 100.

[0168] The step of doping the array substrate 100 may include: doping the array substrate 100 by ion implantation. The step of annealing the doped array substrate 100 may include: annealing the doped array substrate 100 to activate the doped region.

[0169] Before forming the storage capacitor 130 on the second surface 102 of the array substrate 100, a doped region is formed in the array substrate 100. The step of forming the doped region can remove the limitation of the high-K dielectric material on the process temperature. The process temperature for forming the doped region is relatively high, and the annealing temperature for activating the doped region is relatively high, which can effectively ensure the performance of the formed doped region.

[0170] Moreover, there are more process steps before forming the storage capacitor 130, and the sites for the steps of doping the array substrate 100 and annealing the doped array substrate 100 are more selective, which can effectively expand the process window for forming the doped region in the array substrate 100 and effectively reduce the difficulty of the manufacturing process of the storage device.

[0171] In some embodiments, such as Fig. 20 As shown, the step of forming a storage capacitor 130 on the second surface 102 of the array substrate 100 includes: forming a first electrode layer 131 and a second electrode layer 132 on the second surface 102; forming a capacitor dielectric layer 133 on the second surface 102, wherein the material of the capacitor dielectric layer 133 includes a high-K dielectric material, and the capacitor dielectric layer 133 is located between the first electrode layer 131 and the second electrode layer 132.

[0172] The capacitor dielectric layer 133 is suitable for achieving electrical insulation between the first electrode layer 131 and the second electrode layer 132. The material of the capacitor dielectric layer 133 includes a high-K dielectric material, which can effectively increase the capacitance value of the storage capacitor 130.

[0173] In some exemplary embodiments, the storage capacitor 130 further includes: a support column 135, and the first electrode layer 131 is located on the surface of the support column 135. The first electrode layer 131 covers the sidewall of the support column 135 and the surface of the support column 135 facing the second surface 102. By forming the first electrode layer 131 through the support column 135, the area of ​​the first electrode layer 131 can be effectively increased, so as to increase the relative area between the first electrode layer 131 and the second electrode layer 132, so as to increase the capacitance value of the storage capacitor 130.

[0174] In some embodiments, the step of forming the storage capacitor 130 on the second surface 102 includes: forming the storage capacitor 130 on the second surface 102 , and the storage capacitor 130 is electrically connected to the switch device 110 in a one-to-one correspondence.

[0175] In some embodiments, the storage capacitor 130 is located on an end of the device column 111 of the corresponding switch device 110 away from the first surface 101 , and is connected to an end of the device column 111 away from the first surface 101 .

[0176] As an example, the manufacturing method includes: thinning the array substrate 100 to expose an end of the device pillar 111 away from the first surface 101. The end of the device pillar 111 away from the first surface 101 is exposed at the second surface 102. The first electrode layer 131 of the storage capacitor 131 is located on the surface of the device pillar 111 exposed on the second surface 102, and is electrically connected to the device pillar 111 exposed on the second surface 102.

[0177] like Fig. 20 In some embodiments shown, the manufacturing method includes: forming an interconnection (not marked in the figure) in the surface of the device pillar 111 exposed by the second surface 102; forming a first electrode layer 131 located on the device pillar 111 exposed by the second surface 102, wherein the first electrode layer 131 is electrically connected to the interconnection and the device pillar 111. For example, the support pillar 135 is located on the corresponding device pillar 111 exposed by the second surface 102, and the first electrode layer 131 is located between the support pillar 135 and the device pillar 111.

[0178] The support column 135 extends along a direction z perpendicular to the second surface 102. In some exemplary embodiments, the storage capacitor 130 further includes: at least one support layer 134; the support layer 134 extends along an extension direction perpendicular to the support column 135. The second electrode layer 132 and the capacitor dielectric layer 133 are stacked between the support layer 134 and the support column 135. By providing the support layer 134, the extension size of the support column 135 can be effectively increased, and the area of ​​the first electrode layer 131 can be effectively increased, which is beneficial to increasing the capacitance value of the storage capacitor 130.

[0179] refer to Fig.21 In some embodiments of the present invention, the manufacturing method further comprises: after forming the storage capacitor 130 on the second surface 102 of the array substrate 100, forming a lead connection structure 140 on the second surface 102 of the array substrate 100, the lead connection structure 140 comprising: a silicon through-hole substructure 141 penetrating the array substrate 100. Fig.21 The array substrate 100 and the Fig. 20 Schematic diagram of the cross-sectional structure at the corresponding position.

[0180] The lead connection structure 140 is used to realize the connection between the storage unit including the storage capacitor 130 and the switch device 110 and an external circuit.

[0181] In some embodiments, the lead connection structure 140 includes: a through silicon via structure 141 and a lead pad 142. The lead pad 142 is located on the surface of the storage capacitor 130 away from the switch device 110, and is connected to one end of the through silicon via structure 141. Along the direction z perpendicular to the first surface 101, the through silicon via structure 141 extends from the side of the storage capacitor 130 away from the switch device 110 to the first surface 101 until the other end is connected to the back-end interconnect layer located on the first surface.

[0182] In the above embodiment, Fig.12 and Fig.14 As shown, the step of forming the switch devices 110 on the first surface 101 includes: forming the switch devices 110 arranged in an orthogonal array on the first surface 101; the switch devices 110 arranged in an orthogonal array are led out at intervals through a plurality of bit lines BL. This arrangement of the switch devices 110 is only an example. In other embodiments of the present invention, in the first surface 101, the switch devices 110 may also be arranged in other ways.

[0183] refer to Figures 22 to 40 , showing a structural schematic diagram of each step of a method for manufacturing a storage device in other embodiments of the present invention.

[0184] The present invention will not repeat the same points as the above embodiments. The difference from the above embodiments is that in some embodiments of the present invention, in a plane parallel to the first surface, the switch devices 101 are arranged in a close-packed array.

[0185] refer to Figure 22 to Figure 32 In some embodiments of the present invention, the step of forming the switching devices 210 on the first surface 201 includes: forming the switching devices 210 arranged in a close-packed array on the first surface 201 .

[0186] in, Fig. 22 The first surface 201 (eg, Fig.23 A schematic diagram of a top view structure of FIG. Fig.23 The array substrate 200 in some embodiments of the present invention is Fig. 22 A schematic diagram of the cross-sectional structure at the midpoint dash line F1F2; Fig.24 The array substrate 200 and the Fig. 22 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.25 The array substrate 200 in some embodiments of the present invention is Fig.24 A schematic diagram of the cross-sectional structure at the position of the midpoint dash line G1G2; Fig.26 The array substrate 200 and the Fig. 22 A schematic diagram of the structure viewed from above in the corresponding direction; Fig. 27 The array substrate 200 and the Fig.25 Schematic diagram of the cross-sectional structure at the corresponding position; Fig.28 The array substrate 200 and the Fig. 22 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.29 The array substrate 200 and the Fig.25 Schematic diagram of the cross-sectional structure at the corresponding position; Fig.30 The array substrate 200 and the Fig. 22 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.31 The array substrate 200 in some embodiments of the present invention is Fig.30 A schematic diagram of the cross-sectional structure at the position of the midpoint dash line H1H2; Fig.32 The array substrate 200 in some embodiments of the present invention is Fig.30 Schematic diagram of the cross-sectional structure at the midpoint line J1J2.

[0187] Specifically, in some embodiments, the step of forming the switch device 210 on the first surface 201 includes: forming a switch device 210 with a gate all around (GAA) structure with a vertical channel on the first surface 201 .

[0188] It should be noted that the specific technical solution of the step of forming a switch device 210 of a gate allaround (GAA) structure with a vertical channel on the first surface 201 can also refer to the aforementioned embodiment.

[0189] In some embodiments of the present invention, the step of forming the switch device 210 on the first surface 201 includes: Figure 22 to Figure 25 , forming a device column 211 axially perpendicular to the first surface 201; Figure 26 to Figure 32 , forming a gate structure 212 circumferentially surrounding the device pillar 211 .

[0190] In some embodiments of the present invention, the step of forming the switch devices 210 on the first surface 201 includes: forming the switch devices 210 arranged in a close-packed array on the first surface 201. The arrangement of the device pillars 211 in the first surface 201 is the same as the arrangement of the switch devices 210 in the first surface 201 of the array substrate 200.

[0191] For example, in some embodiments, Figure 22 to Figure 25 In the step of forming device pillars 211 axially perpendicular to the first surface 201 , the device pillars 211 are arranged in a close-packed array.

[0192] In some embodiments, the step of forming the device pillar 211 axially perpendicular to the first surface 201 includes: Fig. 22 and Fig.23 As shown, at least two isolation groove patterns 213 extending along the first direction a are formed in the first surface 201; Fig.24 and Fig.25 As shown, at least two gate trench patterns 214 extending along the second direction b are formed in the first surface 201 ; and the device pillar 211 is formed at a position surrounded by the isolation trench pattern 213 and the gate trench pattern 214 .

[0193] Specifically, the second direction b is not perpendicular to the first direction a. The second direction b is at a preset angle to the first direction a so that the device pillars 211 formed are arranged in a densely packed array. The second direction b is at a preset acute angle to the first direction a, for example, 60°. The extension direction of the isolation groove pattern 113 and the extension direction of the gate groove pattern 114 are at a preset angle so that the device pillars 111 formed at the positions surrounded by the isolation groove pattern 113 and the gate groove pattern 114 are arranged in a densely packed array.

[0194] refer to Figure 26 to Figure 32 After forming the device pillar 211 , a gate structure 212 surrounding the device pillar 211 is formed.

[0195] It should be noted that the specific technical solution of the step of forming the gate structure 212 surrounding the device pillar 211 can also refer to the aforementioned embodiment.

[0196] In some embodiments of the present invention, the step of forming the gate structure 212 circumferentially surrounding the device pillar 211 includes: Fig.26 and Fig. 27 As shown, the dielectric material 215 of the isolation trench pattern 213 and the dielectric material of the gate trench pattern 214 are removed by a portion of the thickness to expose the sidewall of the device pillar 211; Figure 26 to Figure 32 As shown, a gate structure 212 is formed on the partially exposed sidewall of the device pillar 211 (eg, Fig.32 as shown).

[0197] In some embodiments, the step of forming the gate structure 212 on the partially exposed sidewall of the device pillar 211 includes: Figure 26 to Figure 29 As shown, a prefabricated gate layer 212c is formed on the dielectric material 115 of the remaining isolation trench pattern and the dielectric material 115 of the remaining gate trench pattern, and the prefabricated gate layer 212c is located on the sidewall of part of the device pillar 211; Fig.28 and Fig.29 As shown, a filling layer 216 is formed on the prefabricated gate layer 212c; Figure 30 to Figure 32 As shown, a cutting groove pattern 217 is formed in the filling layer 216 and the prefabricated gate layer 212c, and the cutting groove pattern 217 cuts through the prefabricated gate layer 212c along the thickness direction. The cutting groove pattern 212c is located at the gate groove pattern 214 (as shown in FIG. Fig.24 and Fig.25 shown).

[0198] It should be noted that if Fig.26In some embodiments shown, the device pillar 211 is a cylindrical shape without edges, such as a circular cylinder or an elliptical cylinder. In a cross section perpendicular to the axis, the cross section of the device pillar 211 is a two-dimensional shape without edges, such as a circle or an ellipse.

[0199] In some exemplary embodiments, the manufacturing method further comprises: Fig.26 and Fig. 27 As shown, after removing a portion of the dielectric material of the isolation trench pattern 213 and the dielectric material of the gate trench pattern 214 to expose the sidewall of the device pillar 211 , the exposed device pillar 211 is chamfered to remove the edge of the device pillar 211 .

[0200] In some embodiments, the step of forming a gate structure 212 on the partially exposed sidewall of the device pillar 211 includes: forming a gate dielectric layer 212b on the partially exposed sidewall of the device pillar 211; and forming a gate electrode 212a on a side of the gate dielectric layer 212b away from the device pillar 211.

[0201] The step of forming a gate dielectric layer 212b on the partially exposed sidewall of the device pillar 211 includes: forming a gate dielectric material 212f on the exposed sidewall surface of the device pillar 211. Specifically, the step of forming a gate dielectric material 212f on the exposed sidewall surface of the device pillar 211 includes: performing an oxidation treatment on the exposed sidewall of the device pillar 211 to form the gate dielectric material 212f. In the process of performing an oxidation treatment on the exposed sidewall of the device pillar 211, while forming the gate dielectric material 112f, the exposed device pillar 211 is chamfered to remove the edges of the device pillar 211.

[0202] In other embodiments of the present invention, the step of chamfering the exposed device pillar to remove the edges of the device pillar may also include: etching the exposed sidewalls of the device pillar to remove the edges of the device pillar.

[0203] also, Fig.26 and Fig. 27 In some embodiments shown, the step of forming a prefabricated gate layer 212c on the dielectric material 215 of the remaining isolation trench pattern 213 and the dielectric material 215 of the remaining gate trench pattern 214 includes: after forming a gate dielectric material 212f on the exposed sidewall surface of the device pillar 121, a gate electrode material 212e is filled on the remaining dielectric material 215. The top surface of the gate electrode material 212e is flush with the top surface of the device pillar 211. The top surface of the gate electrode material 212e is flush with the first surface 201.

[0204] like Fig.28 and Fig.29 In some of the illustrated embodiments, the step of forming a prefabricated gate layer 212c on the dielectric material 215 of the remaining isolation trench pattern 213 and the dielectric material 215 of the remaining gate trench pattern 214 further includes: removing a portion of the thickness of the gate electrode material 212e to form the prefabricated gate layer 212c.

[0205] It should be noted that, in some embodiments, while removing a portion of the thickness of the gate electrode material 212e, a portion of the thickness of the gate dielectric material 212f is removed to form the gate dielectric layer 212b. In other embodiments of the present invention, a portion of the thickness of the gate electrode material 212e may also be removed.

[0206] Continue to refer Fig.28 and Fig.29 After forming the prefabricated gate layer 212c, a filling layer 212c is formed on the prefabricated gate layer 212c, and the top of the filling layer 216 is higher than the top of the device pillar 211. Specifically, the filling layer 216 fills the groove surrounded by the prefabricated gate layer 212c and the adjacent device pillar 211, and the filling layer 212 also extends to the top of the device pillar 211.

[0207] Figure 30 to Figure 32 In some embodiments shown in the figure, the manufacturing method further includes: after forming the filling layer 216, forming a cutting groove pattern 217 in the filling layer 216 and the prefabricated gate layer 212c, wherein the cutting groove pattern 217 cuts off the prefabricated gate layer 212c along the thickness direction, and the cutting groove pattern 212c is located at the gate groove pattern 214 (such as Fig.24 and Fig.25 shown).

[0208] The cutting groove pattern 217 corresponds to the gate groove pattern 214 one by one, and the cutting groove pattern 217 cuts off part of the prefabricated gate layer 112c on the corresponding gate groove pattern 214 to form two gate electrode layers 212g. The gate electrode layer 212g surrounds a plurality of device pillars 211 arranged along the second direction b.

[0209] In some embodiments of the present invention, the switch devices 110 are arranged in a densely packed array on the first surface 101; the device pillars 111 are arranged in a densely packed array on the first surface 101; Figure 30 to Figure 32 As shown, the gate structures 212 adjacent to each other along the second direction b are extended and connected, and the cutting groove pattern 217 extends along the second direction b. A plurality of the cutting groove patterns 216 are arranged in parallel along a direction perpendicular to the second direction b.

[0210] In some embodiments of the present invention, after the switch device 210 is formed on the first surface 201, Fig.33 and Fig.34 , forming a bit line BL2 on the first surface 201. Fig.33 The array substrate 200 and the Fig.30 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.34 In some embodiments of the present invention, the array substrate 200 is Fig.33 Schematic diagram of the cross-sectional structure at the midpoint line K1K2.

[0211] It should be noted that the specific technical solution of the step of forming the bit line BL2 on the first surface 201 may also refer to the aforementioned embodiment.

[0212] In some embodiments of the present invention, the step of forming a switching device 210 on the first surface 201 includes: forming a switching device 210 on the first surface 201, and the gate structures 212 of the switching devices 210 arranged along the second direction b are connected; the step of forming a bit line BL2 on the first surface 201 includes: forming a bit line BL2 on the first surface 201, and the extension direction of the bit line BL2 is perpendicular to the second direction b.

[0213] The extending direction of the bit line BL2 is perpendicular to the direction connected to the gate structure 212. The extending direction of the bit line BL2 is perpendicular to the extending direction of the gate electrode layer 212g. The extending direction of the bit line BL is perpendicular to the extending direction of the cutting groove pattern 217.

[0214] It should be noted that, in some embodiments of the present invention, the switch devices 210 are arranged in a densely packed array in the first surface 201; the first direction a is not perpendicular to the second direction b; the extending direction of the bit line BL2 is only perpendicular to the second direction b and forms a preset angle with the first direction a. The angle formed between the extending direction of the bit line BL2 and the first direction a is complementary to the angle formed between the first direction a and the second direction b.

[0215] In some embodiments, the step of forming the switch devices 210 on the first surface 201 includes: forming the switch devices 210 arranged in a close-packed array on the first surface 201; Fig.33 and Fig.34 As shown, the step of forming the bit line BL2 on the first surface 201 includes: forming the bit line BL2 on the first surface 201, and connecting the same bit line BL2 to the switching devices 210 arranged along the extending direction of the bit line BL2 one by one.

[0216] The switch devices 210 arranged along the extension direction of the bit line BL2 are all led out through the same bit line BL2. Along the extension direction of the bit line BL, any two adjacent switch devices 210 are all led out through the same bit line BL2. The switch devices 210 arranged in a densely packed array are all led out through multiple bit lines BL2.

[0217] Specifically, Fig.33 and Fig.34 As shown, the device pillars 211 arranged in a direction perpendicular to the second direction b are all connected to the same bit line BL2; the device pillars 211 arranged in the second direction b are connected to the corresponding bit lines BL2 one by one. The device pillars 211 arranged in a densely packed array are all led out through multiple bit lines BL2, thereby effectively saving the occupied wafer area and effectively improving the storage density.

[0218] In the device pillars 211 arranged in a densely packed array, all the device pillars 211 are connected to the bit line BL2; the other device pillars 211 surrounding one of the device pillars 211 are distributed in a honeycomb shape (eg Fig.33 (shown by the red dashed line).

[0219] In some embodiments, the manufacturing method further comprises: after forming the switch device 210 on the first surface 201 and before forming the bit line BL2 on the first surface 201, Fig.33 and Fig.34 As shown, a bit line connection plug BCT2 is formed on the switching device 210 ; the step of forming a bit line BL2 on the first surface 201 includes: forming a bit line BL2 connected to the bit line connection plug BCT2 on the first surface 201 .

[0220] Specifically, Fig.33 and Fig.34 As shown, the bit line BL2 is located on the first surface 201 , and the bit line BL2 is located between one end of the device pillar 211 close to the first surface 201 to connect the two.

[0221] In a plane parallel to the first surface 201 , the bit line connection plugs BCT2 are distributed on each of the switch devices 110 .

[0222] Specifically, Fig.33 and Fig.34 As shown, in a plane parallel to the first surface 201, the bit line connection plugs BCT2 are distributed on the device pillars 211 arranged in a densely packed array. In the first surface 201, other bit line connection plugs BCT2 surrounding one bit line connection plug BCT2 are distributed in a honeycomb shape (such as Fig.12 (shown by the red dashed line).

[0223] refer to Fig.35 and Fig.36 As shown, in some embodiments of the present invention, the manufacturing method further includes: after forming the switch device 210 on the first surface 201, forming a word line connection plug WCT2 on the first surface 201; forming a bonding interconnection layer 218 on the first surface 201; and bonding a control chip CMOS on the first surface 201. Fig.35 The array substrate 200 and the Fig.33 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.36 The array substrate 200 and the Fig.34 Schematic diagram of the cross-sectional structure at the corresponding position.

[0224] It should be noted that the specific technical solutions of any of the steps of forming the word line connection plug WCT2 on the first surface 201, forming the bonding interconnection layer 218 on the first surface 201, and bonding the control chip CMOS on the first surface 201 can also refer to the aforementioned embodiments.

[0225] Among them, in some embodiments, the gate structures 212 of the switching devices 210 arranged along the second direction b are connected; the step of forming a word line connection plug WCT2 on the first surface 201 includes: forming a word line connection plug WCT2 on the first surface 201, the word line connection plug WCT2 is located on one side of the switching device 210 arranged along the second direction b, and the switching device 210 is connected to the gate structure 212 of the switching device 210 arranged along the second direction b.

[0226] refer to Fig.37 The manufacturing method further comprises: after bonding the control chip CMOS on the first surface 201, thinning the array substrate 200 through the second surface 202 to expose the switch device 210. Fig.37 The array substrate 200 and the Fig.36 Schematic diagram of the cross-sectional structure at the corresponding position.

[0227] It should be noted that the specific technical solution of the step of thinning the array substrate 200 to expose the switch device 210 can also refer to the above-mentioned embodiment.

[0228] refer to Figures 38 to 40 After bonding the control chip CMOS on the first surface 201, a storage capacitor 230 is formed on the second surface 202. Fig.38 The array substrate 200 and the Fig.37 Schematic diagram of the cross-sectional structure at the corresponding position; Fig.39The array substrate 200 and the Fig.35 A schematic diagram of the structure viewed from above in the corresponding direction; Fig.40 The array substrate 200 and the Fig.38 Schematic diagram of the cross-sectional structure at the corresponding position.

[0229] It should be noted that the specific technical solution of the step of forming the storage capacitor 230 on the second surface 202 can also refer to the aforementioned embodiment.

[0230] In some embodiments, the step of forming the storage capacitor 130 on the second surface 102 of the array substrate 100 includes: Fig.38 As shown, at least two support layers 234 and sacrificial materials (not shown in the figure) are formed on the second surface 202, and the sacrificial materials are filled between adjacent support layers 234; a first opening (not shown in the figure) is formed in the support layer 234 and the sacrificial material, and the bottom of the first opening exposes the switching device 210; a first electrode layer 231 is formed in the first opening, and the first electrode layer 231 covers the bottom and side walls of the first opening; a support material is filled in the first opening with the first electrode layer 231 formed on the bottom and side walls to form a support column 235; Fig.38 and Fig.39 As shown, after the support column 235 is formed, a second opening 209 is formed in the support layer 234 and the sacrificial material, and the bottom of the second opening 209 is at least located in the portion of the sacrificial material closest to the second surface 202; the sacrificial material is removed through the second opening 209 to form a cavity between adjacent support layers 234; Fig.40 As shown, the capacitor dielectric layer 233 and the second electrode layer 232 are formed through the second opening 209, the capacitor dielectric layer 233 is located on the side walls of the cavity and the bottom and side walls of the second opening 209, the second electrode layer 232 fills the cavity with the capacitor dielectric layer 233 on the side walls and the second opening 209 with the capacitor dielectric layer 233 on the bottom and side walls, the capacitor support and the second electrode layer 232 also extend to the top of the support column 235.

[0231] In some exemplary embodiments, in the step of forming the second opening 209 in the support layer 234 and the sacrificial material, the second opening 209 is located between the plurality of device pillars 211 that are closest to each other. Fig.39In some embodiments shown, the device pillars 211 are arranged in a close-packed array; the second opening 209 is located between the three closest device pillars 211. The projection of the second opening 209 on the second surface is located between the three closest device pillars 211. The bottom of the second opening 209 exposes the three closest device pillars 211.

[0232] refer to Fig.40 In some embodiments of the present invention, the manufacturing method further includes: after forming the storage capacitor 230 on the second surface 202, forming a lead connection structure 240 on the second surface 202, and the lead connection structure 240 includes: a silicon through-hole substructure 241 that penetrates the array substrate 200.

[0233] It should be noted that the specific technical solution of the step of forming the lead connection structure 240 on the second surface 202 can also refer to the aforementioned embodiment.

[0234] Correspondingly, the present invention further provides a storage device, which is manufactured by the manufacturing method of the present invention.

[0235] Specifically, the storage device is manufactured by the manufacturing method of the present invention. The specific technical solution of the storage device can refer to the embodiment of the manufacturing method of the storage device mentioned above.

[0236] refer to Fig.41 and Fig.42 In some embodiments of the present invention, the storage device includes: a storage unit 301, the storage unit 301 includes: a device column 311, the device column 311 has a first end 311a and a second end 311b opposite to each other along the axial direction of the device column 311; a gate structure 312, the gate structure 312 circumferentially surrounds the device column 311; a storage capacitor 330, along the axial direction of the device column 311, the storage capacitor 330 is located on a side of the device column 311 close to the first end 311a, and the storage capacitor 330 is electrically connected to the first end 311a of the device column 311.

[0237] in, Fig.41 is a schematic diagram of a three-dimensional structure of a storage unit in some embodiments of the present invention; Fig.42 Schematic diagram of the cross-sectional structure of a storage unit in some embodiments of the present invention.

[0238] In the manufacturing method of the present invention, after forming the switch device, the control chip is first bonded, and then the storage capacitor 330 is formed; therefore, in the step of forming the switch device, the array substrate is etched along the direction from the control chip to the storage capacitor 330 to form the device column 311. In the step of forming the switch device, the array substrate is etched along the direction from the control chip to the storage capacitor 330 to form the device column 311

[0239] In some embodiments of the present invention, the width da of the first end 311a of the device pillar 311 is greater than the width db of the second end 311b of the device pillar 311, where the width is the dimension in a plane perpendicular to the axial direction of the device pillar 311. Fig.42 In some of the embodiments shown, the width of the device pillar 311 gradually increases along the direction from the second end 311 b to the first end 311 a .

[0240] In some embodiments of the present invention, the device columns are arranged in an orthogonal array in a plane perpendicular to the axial direction of the device columns; the same bit line is connected to switching devices arranged along the extension direction of the bit line at intervals, and adjacent bit lines are connected to switching devices arranged along the extension direction of the bit line in an alternating manner.

[0241] Among the device pillars arranged in an orthogonal array, a portion of the device pillars are connected to the bit lines; wherein, among the device pillars connected to the bit lines, other device pillars surrounding one of the device pillars are distributed in a honeycomb shape (e.g. Fig.12 (shown by the red dashed line).

[0242] In some other embodiments of the present invention, the device pillars are arranged in a densely packed array in a plane perpendicular to the axial direction of the device pillars; and the same bit line is connected one by one to the switch devices arranged along the extension direction of the bit line.

[0243] In the device pillars arranged in a densely packed array, all the device pillars are connected to the bit lines; other device pillars surrounding the device pillars are distributed in a honeycomb shape (such as Fig.33 (shown by the red dashed line).

[0244] refer to Fig.43 In some embodiments of the present invention, the memory cells 401 in adjacent rows are staggered along the row direction R; the memory cells 401 in adjacent columns are staggered along the column direction L. In the column direction L, a memory cell 401 is located between two adjacent memory cells 401 in adjacent rows; in the row direction R, a memory cell 401 is located between two adjacent memory cells 401 in adjacent columns.

[0245] In the row direction R, a memory cell 401 is located between two adjacent memory cells 401 in adjacent rows; in the column direction L, a memory cell 401 is located between two adjacent memory cells 401 in adjacent columns.

[0246] Specifically, the storage cells have a 1st row, a 2nd row, ..., an mth row arranged in sequence along a column direction L, where m is the number of rows of storage cells in the storage array; the storage cells have a 1st column, a 2nd column, ..., an nth column arranged in sequence along a row direction R, where n is the number of columns of storage cells in the storage array; the storage cells in the i-th row are staggered with the storage cells in the i+1-th row along the row direction R; the storage cells in the j-th column are staggered with the storage cells in the j+1-th column along the column direction L, where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n.

[0247] The bit line BL4 extends along a column direction L in a plane perpendicular to the axial direction of the device column.

[0248] The storage cells in the same column are connected to the same bit line BL4. In a plane perpendicular to the axial direction of the device column, the bit line BL4 extends along the column direction L and is arranged in sequence along the row direction R; along the column direction L, the bit line BL4 spans across multiple rows of storage cells 401 and is connected to multiple rows of storage cells 401. Specifically, the storage cell has n bit lines BL4, which are the first bit line, the second bit line, ..., the nth bit line, and the n bit lines correspond to the n columns of storage cells 401 in sequence.

[0249] The memory cells 401 of adjacent columns L are staggered along the column direction L; in a plane perpendicular to the axial direction of the device column 311 , the bit line BL4 extends along the column direction L; the memory cells 401 of adjacent columns are staggeredly connected to two adjacent bit lines BL4 .

[0250] The word line WL4 extends along a row direction R in a plane perpendicular to the axial direction of the device pillar.

[0251] The memory cells 401 in the same row are connected to the same word line WL4. In a plane perpendicular to the axial direction of the device column, the word line WL4 extends along the row direction R and is arranged in sequence along the column direction L; along the row direction R, the word line WL4 spans across multiple columns of the memory cells 401 and is connected to multiple columns of the memory cells 401. Specifically, the memory cell has m word lines WL4, which are the first word line, the second word line, ..., the mth word line, and the m word lines correspond to the m rows of memory cells in sequence.

[0252] The memory cells 401 in adjacent rows are arranged in a staggered manner along the row direction R; in a plane perpendicular to the axial direction of the device column, the word line WL4 extends along the row direction R; the memory cells 401 in adjacent rows are staggeredly connected to two adjacent word lines WL4.

[0253] Specifically, the memory cells in the odd columns (or even columns) in the bth row and the bth word line (such as Fig.42 The storage cells in the even columns (or odd columns) in the b+1th row are connected to the b+1th word line (shown as the red solid line in the middle). Fig.42 The red dotted line in the figure shows that they are connected, where b is an integer greater than or equal to 1 and less than or equal to m-1.

[0254] The present invention also provides a control method for a storage array. The storage array is a storage array manufactured by the manufacturing method of the present invention. The control method comprises: while applying a first voltage to a bit line, applying a second voltage to an adjacent bit line, wherein the second voltage is not equal to the first voltage.

[0255] In some exemplary embodiments, the storage array includes a 1st bit line, a 2nd bit line, ..., an nth bit line arranged in sequence, where n is the number of bit lines; the step of loading a first voltage to a bit line and a second voltage to an adjacent bit line includes: loading a first voltage to the 2p-1th bit line and the 2p+1th bit line and loading a second voltage to the 2pth bit line, where p is an integer greater than 0.

[0256] For example, during a read operation, the first voltage is a read voltage; during a write operation, the first voltage is a write voltage; during an erase operation, the first voltage is an erase voltage; for example, the second voltage is a default voltage.

[0257] In summary, after forming the switching device on the first surface, the control chip is bonded on the first surface; after bonding the control chip on the first surface, the storage capacitor is formed on the second surface. After forming the switching device, the control chip is directly bonded on the switching device; after bonding the control chip, the storage capacitor is formed, which can effectively increase the manufacturing process steps before the storage capacitor is formed, so that more process steps can remove the material restrictions in the storage capacitor, which can effectively reduce the difficulty of the manufacturing process of the storage device and can effectively expand the manufacturing process window of the storage device; and after bonding the control chip, the storage capacitor is formed by providing mechanical support with the control chip, which can save the need for an additional carrier wafer and can effectively reduce the manufacturing cost of the storage device.

[0258] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for manufacturing a storage device, characterized in that: include: providing an array substrate; forming a switching device on a first surface of the array substrate; After forming the switch device on the first surface, bonding the control chip on the first surface; After bonding the control chip on the first surface, a storage capacitor is formed on the second surface of the array substrate, wherein the second surface and the first surface are arranged opposite to each other.

2. The manufacturing method according to claim 1, characterized in that Also includes: After forming the switch device on the first surface and before bonding the control chip on the first surface, a bit line is formed on the first surface.

3. The manufacturing method according to claim 2, characterized in that: The step of forming switching devices on the first surface includes: forming switching devices on the first surface, wherein gate structures of the switching devices arranged along the second direction are connected; The step of forming a bit line on the first surface includes: forming a bit line on the first surface, wherein an extending direction of the bit line is perpendicular to the second direction.

4. The manufacturing method according to claim 2, characterized in that: The step of forming switch devices on the first surface includes: forming switch devices arranged in a close-packed array on the first surface; The step of forming a bit line on the first surface includes: forming a bit line on the first surface, and connecting the same bit line to switching devices arranged along the extending direction of the bit line one by one.

5. The manufacturing method according to claim 2, characterized in that: The step of forming switch devices on the first surface includes: forming switch devices arranged in an orthogonal array on the first surface; The step of forming bit lines on the first surface includes: forming bit lines on the first surface, the same bit lines are connected to switching devices arranged along the extension direction of the bit lines at intervals, and adjacent bit lines are connected to switching devices arranged along the extension direction of the bit lines in an alternating manner.

6. The manufacturing method according to claim 2, characterized in that: Also includes: After forming a switching device on the first surface and before forming a bit line on the first surface, forming a bit line connection plug on the switching device; The step of forming a bit line on the first surface includes forming a bit line connected to the bit line connection plug on the first surface.

7. The manufacturing method according to claim 1, characterized in that: Also includes: After bonding the control chip on the first surface and before forming the storage capacitor on the second surface, thinning the array substrate through the second surface to expose the switch device; The step of forming a storage capacitor on the second surface includes: forming the storage capacitor on the thinned second surface.

8. The manufacturing method according to claim 7, characterized in that: The step of forming a switch device on the first surface includes: forming a device column located at a position surrounded by the isolation trench pattern and the gate trench pattern; The step of thinning the array substrate to expose the switch device includes: thinning the array substrate to expose the isolation trench pattern and the gate trench pattern.

9. The manufacturing method according to claim 1, characterized in that: The step of forming a switching device on the first surface includes: forming a switching device with a fully surrounded gate structure on the first surface.

10. The manufacturing method according to claim 9, characterized in that: The step of forming a switch device with a fully enclosed gate structure on the first surface includes: forming a switch device with a fully enclosed gate structure with a vertical channel on the first surface.

11. The manufacturing method according to claim 9, characterized in that: The step of forming a switching device on the first surface comprises: forming a device column with an axial direction perpendicular to the first surface; A gate structure is formed circumferentially surrounding the device pillar.

12. The manufacturing method according to claim 11, characterized in that: In the step of forming device pillars on the first surface, the device pillars are arranged in a close-packed array, or the device pillars are arranged in an orthogonal array.

13. The manufacturing method according to claim 11, characterized in that: The step of forming a device column axially perpendicular to the first surface comprises: forming at least two isolation groove patterns in the first surface; forming at least two gate trench patterns in the first surface, Wherein, the gate trench pattern extends along the second direction, the isolation trench pattern extends along the first direction, and the first direction and the second direction form a preset angle; The device pillar is formed at a position surrounded by the isolation trench pattern and the gate trench pattern.

14. The manufacturing method according to claim 13, characterized in that: At least one of the steps of forming at least two isolation trench patterns in the first surface and the step of forming at least two gate trench patterns in the first surface comprises: Etching the first surface to form a groove in the first surface, wherein the groove extends in one of the second direction and the first direction; The trench is filled with a dielectric material.

15. The manufacturing method according to claim 11, characterized in that: The step of forming a device column axially perpendicular to the first surface includes: forming a device column located at a position surrounded by the isolation trench pattern and the gate trench pattern; The step of forming a gate structure circumferentially surrounding the device pillar comprises: Removing a portion of the thickness of the dielectric material of the isolation trench pattern and the dielectric material of the gate trench pattern to expose the sidewall of the device column; A gate structure is formed on the partially exposed sidewall of the device column.

16. The manufacturing method according to claim 15, characterized in that: The step of forming a gate structure on the partially exposed sidewall of the device column comprises: Forming a prefabricated gate layer on the remaining dielectric material of the isolation trench pattern and the remaining dielectric material of the gate trench pattern, wherein the prefabricated gate layer is located on the sidewalls of a portion of the device pillars; forming a filling layer on the prefabricated gate layer; A cutting groove pattern is formed in the filling layer and the prefabricated gate layer, wherein the cutting groove pattern cuts through the prefabricated gate layer along a thickness direction and is located on the gate groove pattern.

17. The manufacturing method according to claim 16, characterized in that: In the step of forming a cutting groove pattern in the filling layer and the prefabricated gate layer, the cutting groove pattern also extends into the dielectric material of the remaining gate groove pattern.

18. The manufacturing method according to claim 2, characterized in that: Also includes: After forming a switching device on the first surface and before forming a bonding interconnection layer on the bit line, a word line connection plug is formed on the first surface.

19. The manufacturing method according to claim 18, characterized in that: The step of forming switching devices on the first surface includes: forming switching devices on the first surface, wherein gate structures of the switching devices arranged along the second direction are connected; The step of forming a word line connection plug on the first surface includes: forming a word line connection plug on the first surface, the word line connection plug is located on one side of the switching device arranged along the second direction, and the switching device is connected to the gate structure of the switching device arranged along the second direction.

20. The manufacturing method according to claim 1, characterized in that: After forming a switch device on the first surface and before bonding a control chip on the first surface, forming a bonding interconnection layer on the first surface; In the step of bonding the control chip on the first surface, the control chip is bonded on the surface of the bonding interconnection layer.

21. The manufacturing method according to claim 1, characterized in that: The step of forming a storage capacitor on the second surface includes: forming a storage capacitor on the second surface, wherein a material of the storage capacitor includes a high-K dielectric material.

22. The manufacturing method according to claim 21, characterized in that: The step of forming storage capacitors on the second surface includes: forming storage capacitors on the second surface, the storage capacitors being electrically connected to the switching devices in a one-to-one correspondence.

23. The manufacturing method according to claim 21, characterized in that: The step of forming a storage capacitor on the second surface comprises: forming a first electrode layer and a second electrode layer on the second surface; A capacitor dielectric layer is disposed on the second surface. The material of the capacitor dielectric layer includes a high-K dielectric material. The capacitor dielectric layer is located between the first electrode layer and the second electrode layer.

24. The manufacturing method according to claim 1, characterized in that: Also includes: After forming the storage capacitor on the second surface, a lead connection structure is formed on the second surface of the array substrate, wherein the lead connection structure includes a through silicon via substructure penetrating the array substrate.

25. The manufacturing method according to any one of claims 1 to 24, characterized in that: Also includes: Before forming a storage capacitor on the second surface of the array substrate, a doped region is formed in the array substrate.

26. A storage device, characterized in that: The storage device is manufactured by the manufacturing method according to any one of claims 1 to 25.

27. The storage device according to claim 26, wherein: The storage device comprises: a storage unit, wherein the storage unit comprises: A device column, wherein the device column has a first end and a second end opposite to each other in an axial direction of the device column; A gate structure, wherein the gate structure circumferentially surrounds the device column; A storage capacitor is located along the axial direction of the device column on a side of the device column close to the first end, and the storage capacitor is electrically connected to the first end of the device column.

28. The storage device according to claim 27, wherein: The width of the first end of the device column is greater than the width of the second end of the device column, wherein the width refers to a dimension in a plane perpendicular to the axial direction of the device column.

29. The storage device according to claim 28, characterized in that The width of the device column gradually increases along a direction from the second end to the first end.

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