Semiconductor storage structure and manufacturing method thereof

Abstract

The invention provides a semiconductor storage structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the problem of low storage density. The semiconductor storage structure comprises a first dielectric layer and a storage unit, the top surface of the first dielectric layer is provided with a groove extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer; the storage unit comprises a first storage unit and a second storage unit; wherein the first storage unit is arranged in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; the second storage unit is arranged on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are formed through synchronous deposition. According to the semiconductor storage structure, the storage density can be improved by utilizing three-dimensional space arrangement.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor storage structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor technology, magnetic random access memory (MRAM) has the characteristics of non-volatility, high read and write speed, and long life, showing broad application prospects in the fields of Internet of Things, edge AI devices, high-performance computing and automobiles. MRAM has evolved from the first generation of Toggle MRAM, the second generation of STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory), to the third generation of SOT-MRAM (Spin-Orbit Torque Magnetic Random Access Memory).

[0003] SOT-MRAM includes a magnetic tunnel junction (MTJ) and a heavy metal layer. The magnetic tunnel junction includes a free layer, a tunnel layer and a fixed layer, wherein the free layer and the fixed layer are magnetic materials, and the tunnel layer is an oxide material. The working principle of SOT-MRAM is to use the spin-orbit torque effect generated by the heavy metal layer when current is passed through it to flip the magnetic domain of the adjacent magnetic layer (free layer), so that the direction of the magnetic domain of the free layer is flipped. After the magnetic domain is flipped, the direction of the magnetic domain in the free layer is opposite to that of the fixed layer, showing the characteristics of high magnetic resistance to the outside; the magnetic domain of the free layer is the same as that of the fixed layer, showing the characteristics of low magnetic resistance to the outside. The difference between high and low magnetic resistance can represent "0" and "1" in binary for information storage.

[0004] Compared with the previous two generations, SOT-MRAM has lower flip current and the read current does not pass through the MTJ, so it has a longer lifespan. However, SOT-MRAM occupies a large area and has a low storage density. Summary of the invention

[0005] In view of the above problems, an embodiment of the present application provides a semiconductor storage structure and a manufacturing method thereof, which are used to improve the storage density of the semiconductor storage structure.

[0006] According to some embodiments, the present application provides a semiconductor storage structure, including: a first dielectric layer and a storage unit, the top surface of the first dielectric layer is provided with a groove extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer; the storage unit includes a first storage unit and a second storage unit; wherein the first storage unit is arranged in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; the second storage unit is arranged on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are formed by synchronous deposition.

[0007] In some possible embodiments, the first storage unit includes a first heavy metal layer and a first magnetic tunnel junction stacked in sequence, and the second storage unit includes a second heavy metal layer and a second magnetic tunnel junction stacked in sequence; the first heavy metal layer and the second heavy metal layer are formed by synchronous deposition, and the first magnetic tunnel junction and the second magnetic tunnel junction are formed by synchronous deposition.

[0008] In some possible embodiments, along the second direction, the size of the top of the groove is smaller than the size of the bottom of the groove, so as to cut the deposited storage unit film layer along the third direction to form the first storage unit and the second storage unit; wherein the second direction is parallel to the height direction of the first dielectric layer; and the third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction.

[0009] In some possible embodiments, along a third direction, a plurality of the first magnetic tunnel junctions and a plurality of the second magnetic tunnel junctions are alternately arranged, and the third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction; along the first direction, a plurality of the first magnetic tunnel junctions and a plurality of the second magnetic tunnel junctions are independently arranged from each other.

[0010] In some possible embodiments, among several first magnetic tunnel junctions independently arranged along the first direction, the first heavy metal layer under at least some of the first magnetic tunnel junctions is an integrated structure; among several second magnetic tunnel junctions independently arranged along the first direction, the second heavy metal layer under at least some of the second magnetic tunnel junctions is an integrated structure.

[0011] In some possible implementations, a second dielectric layer is further disposed in the groove, and the second dielectric layer is at least filled between the first storage unit and the first dielectric layer.

[0012] In some possible implementations, a method for synchronously depositing the first storage unit and the second storage unit includes physical vapor deposition or ion beam deposition.

[0013] The embodiment of the present application provides a semiconductor storage structure, including a first dielectric layer and a storage unit, wherein the top surface of the first dielectric layer is provided with a groove extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer. The storage unit includes a first storage unit arranged in the groove, and a second storage unit arranged on the top surface of the first dielectric layer, wherein the top surface of the first storage unit is lower than the top surface of the first dielectric layer, and the first storage unit and the second storage unit are formed by synchronous deposition. In the height direction parallel to the first dielectric layer, the first storage unit and the second storage unit are staggered, and the number of storage units can be increased in the 3D scale to obtain a higher number of storage units, thereby obtaining a greater storage density. At the same time, the first storage unit and the second storage unit are also formed by synchronous deposition, and the storage unit can be obtained in two planes by depositing the storage unit film layer once, which saves the storage unit film layer and reduces the manufacturing cost.

[0014] According to some embodiments, the present application also provides a method for manufacturing a semiconductor storage structure, which includes: forming a groove extending along a first direction on the top surface of a first dielectric layer, the first direction being a direction parallel to the top surface of the first dielectric layer; forming a storage unit, the storage unit including a first storage unit and a second storage unit; wherein the first storage unit is formed in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; the second storage unit is formed on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are formed by synchronous deposition.

[0015] In some possible embodiments, along the second direction, the size of the top of the groove is smaller than the size of the bottom of the groove, and the second direction is parallel to the height direction of the first dielectric layer; a storage unit film layer is deposited, and the groove cuts the storage unit film layer along a third direction to form the first storage unit and the second storage unit; wherein the third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction.

[0016] In some possible implementations, forming a groove extending along a first direction on a top surface of a first dielectric layer comprises: depositing the first dielectric layer, wherein at least two sacrificial structures extending along the first direction and arranged at intervals along a third direction are formed in the first dielectric layer, wherein the third direction is parallel to a direction of a top surface of the first dielectric layer and has an angle with the first direction, and a top surface of the sacrificial structure is flush with a top surface of the first dielectric layer; and removing the sacrificial structure to form the groove;

[0017] Alternatively, forming a groove extending along a first direction on the top surface of the first dielectric layer includes: depositing a first layer of the first dielectric layer and depositing a second layer of the first dielectric layer on the first layer; removing a portion of the second layer along the first direction to expose a portion of the top surface of the first layer; and etching the first layer using the remaining second layer as a mask to form the groove.

[0018] The method for manufacturing a semiconductor storage structure in an embodiment of the present application forms a groove on the top surface of the first dielectric layer, and forms a first storage unit and a second storage unit in the groove and on the first dielectric layer respectively, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer. The first storage unit and the second storage unit are staggered along the height direction parallel to the first dielectric layer, and the number of storage units can be increased in the 3D scale to obtain a higher number of storage units, thereby obtaining a greater storage density. The first storage unit and the second storage unit are also formed by synchronous deposition, and the storage units can be obtained in two planes by deposition once, which saves the storage unit film layer and reduces the manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a semiconductor storage structure in an embodiment of the present application;

[0020] Figure 2 for Figure 1 The cross-sectional view at A in the middle;

[0021] Figure 3 for Figure 1 The cross-sectional view at B in the middle;

[0022] Figure 4 is a flow chart of a method for manufacturing a semiconductor storage structure in an embodiment of the present application;

[0023] Figure 5 is a schematic diagram of a groove in an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram after forming a heavy metal material layer and a magnetic tunnel junction stacking layer in an embodiment of the present application;

[0025] Figure 7 for Figure 6 A top view of

[0026] Figure 8 It is a schematic diagram after forming the second initial dielectric layer in the embodiment of the present application;

[0027] Fig. 9 for Figure 8 A top view of

[0028] Fig.10This is a schematic diagram after the second initial dielectric layer is etched back in an embodiment of the present application;

[0029] Fig.11 It is a schematic diagram after forming a photoresist layer in an embodiment of the present application;

[0030] Fig.12 for Fig.11 A top view of

[0031] Fig.13 It is a schematic diagram after forming a first storage unit and a second storage unit in an embodiment of the present application;

[0032] Fig.14 for Fig.13 The cross-sectional view at A in the middle;

[0033] Fig.15 for Fig.13 The cross-sectional view at B in the middle;

[0034] Fig.16 It is a schematic diagram after forming the third dielectric layer in the embodiment of the present application;

[0035] Fig.17 for Fig.16 The cross-sectional view at A in the middle;

[0036] Fig.18 for Fig.16 The cross-sectional view at B in the middle;

[0037] Fig.19 This is a first schematic diagram after the first layer is formed in an embodiment of the present application;

[0038] Fig. 20 This is a first schematic diagram after forming the first bottom electrode in the embodiment of the present application;

[0039] Fig.21 This is a first schematic diagram after forming a sacrificial material in an embodiment of the present application;

[0040] Fig. 22 This is a first schematic diagram after forming a sacrificial structure in an embodiment of the present application;

[0041] Fig.23 This is a first schematic diagram after the second layer is formed in an embodiment of the present application;

[0042] Fig.24 This is a first schematic diagram after the groove is formed in the embodiment of the present application;

[0043] Fig.25 This is a first schematic diagram after forming the second bottom electrode in the embodiment of the present application;

[0044] Fig.26This is a second schematic diagram after the first layer is formed in the embodiment of the present application;

[0045] Fig. 27 for Fig.26 A top view of

[0046] Fig.28 This is a second schematic diagram after forming a sacrificial material in an embodiment of the present application;

[0047] Fig.29 This is a second schematic diagram after forming a sacrificial structure in an embodiment of the present application;

[0048] Fig.30 for Fig.29 A top view of

[0049] Fig.31 This is a second schematic diagram after the second layer is formed in the embodiment of the present application;

[0050] Fig.32 for Fig.31 A top view of

[0051] Fig.33 This is a second schematic diagram after forming the second bottom electrode in the embodiment of the present application;

[0052] Fig.34 for Fig.33 A top view of

[0053] Fig.35 This is a second schematic diagram after the groove is formed in the embodiment of the present application;

[0054] Fig.36 for Fig.35 A top view of

[0055] Fig.37 A diagram showing a forming process of a portion of a groove in an embodiment of the present application;

[0056] Fig.38 A diagram showing a formation process of the groove and the second bottom electrode in an embodiment of the present application;

[0057] Fig.39 is a diagram showing the formation process of the second bottom electrode in an embodiment of the present application;

[0058] Fig.40 A diagram showing the formation process of a groove in an embodiment of the present application;

[0059] Fig.41 Another diagram of forming a partial groove in an embodiment of the present application;

[0060] Fig.42 This is another process for forming the groove and the second bottom electrode in the embodiment of the present application.

[0061] Description of reference numerals:

[0062] 10-substrate; 20-first dielectric layer; 21-first layer; 22-second layer; 23-first bottom electrode; 24-second bottom electrode; 25-second dielectric layer; 26-third dielectric layer; 27-second initial dielectric layer; 30-sacrificial structure; 31-sacrificial material; 40-groove; 51-first heavy metal layer; 52-second heavy metal layer; 61-first magnetic tunnel junction; 62-second magnetic tunnel junction; 63-magnetic tunnel junction stacking layer; 71-first connection layer; 72-second connection layer; 73-connection material layer; 81-first top electrode; 82-second top electrode; 90-photoresist layer. DETAILED DESCRIPTION

[0063] The semiconductor storage structure in the related art has low storage density and low integration. In order to improve the storage density of the semiconductor storage structure, one way is to reduce the size of the storage unit, especially the size of the magnetic tunnel junction. In this way, more storage units can be accommodated per unit area, thereby increasing the storage density. Reducing the size of the storage unit can be achieved through advanced photolithography technology or by using a multiple exposure process. However, the former relies on the use of advanced photolithography machines, and the latter reduces the yield rate. Another way is to increase the number of storage units in three dimensions, thereby increasing the storage density, which is usually achieved by stacking storage units. Stacked storage units are combined with peripheral read circuits to achieve high integration density. However, the stacked storage units are spaced relatively large in the same plane, and the corresponding film layers are not fully utilized.

[0064] To this end, the embodiment of the present application provides a semiconductor storage structure, by arranging a first storage unit in a groove of a first dielectric layer, and arranging a second storage unit on the top surface of the first dielectric layer, the top surface of the first storage unit is lower than the top surface of the first dielectric layer, so that the number of storage units is increased in a three-dimensional scale, thereby improving the storage density and integration. In addition, the first storage unit and the second storage unit are deposited and formed synchronously by using film layer filling, and the storage unit film layer can be deposited once to obtain the storage unit in two planes, which saves the storage unit film layer, improves the utilization rate of the relevant film layer, and reduces the manufacturing cost.

[0065] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of this application.

[0066] The present application provides a semiconductor storage structure, which is a magnetic storage device. Figures 1 to 3 The semiconductor storage structure includes a first dielectric layer 20 and a storage unit, wherein the first dielectric layer 20 supports and isolates the storage unit, and the storage unit stores data. The first dielectric layer 20 is, for example, disposed on a substrate 10, and a circuit for controlling the storage unit is disposed in the substrate 10. The substrate 10 is a semiconductor substrate, and the material of the substrate 10 may include, but is not limited to, any one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds, gallium arsenic compounds, gallium phosphorus compounds, gallium sulfur compounds, etc., or other materials known to those skilled in the art.

[0067] The top surface of the first dielectric layer 20 is provided with a groove 40 extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer 20. Figure 2 and Figure 3 The first direction is the length direction of the groove 40. Figure 1 As shown, the groove 40 is opened on the top surface of the first dielectric layer 20 and is located in the first dielectric layer 20. The groove 40 does not extend to the bottom surface of the first dielectric layer 20, that is, the groove 40 does not penetrate the first dielectric layer 20. In other examples, the groove 40 can also penetrate the first dielectric layer 20.

[0068] In some possible examples, along the second direction, the size of the top of the groove 40 is smaller than the size of the bottom of the groove 40, wherein the second direction is parallel to the height direction of the first dielectric layer 20, such as Figure 1 The second direction is the Z direction shown in FIG. 4 , and the second direction is the depth direction of the groove 40. In this way, the groove 40 is formed into a shape that is small at the top and large at the bottom, and the sidewall of the groove 40 is inclined and forms an acute angle with the top surface of the first dielectric layer 20, so that the groove 40 can cut off the corresponding film layer formed on the first dielectric layer 20.

[0069] The first dielectric layer 20 is also formed with bottom electrodes, which include a first bottom electrode 23 and a second bottom electrode 24. The first electrode and the second electrode can both be made of metal materials. The first bottom electrode 23 is exposed in the groove 40, that is, one end of the first bottom electrode 23 is located at the bottom of the groove 40, and the other end of the first bottom electrode 23 is located at the bottom surface of the first dielectric layer 20. Along the second direction, the bottom surface of the first dielectric layer 20 and the top surface of the first dielectric layer 20 are arranged opposite to each other.

[0070] The second bottom electrode 24 is disposed beside the groove 40, and the second bottom electrode 24 is not exposed in the groove 40. One end of the second bottom electrode 24 is located on the top surface of the first dielectric layer 20, and the other end of the second bottom electrode 24 is located on the bottom surface of the first dielectric layer 20. The second bottom electrode 24 and the first bottom electrode 23 have different heights to connect storage cells at different heights. The second bottom electrode 24 and the first bottom electrode 23 are spaced apart along the first direction and spaced apart along the third direction, and the third direction is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction (e.g., perpendicular), such as Figure 1 For example, the second bottom electrodes 24 and the first bottom electrodes 23 are alternately arranged in sequence along the third direction.

[0071] Continue reading Figures 1 to 3 The storage unit includes a first storage unit and a second storage unit, wherein the first storage unit is arranged in the groove 40, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer 20. The second storage unit is arranged on the top surface of the first dielectric layer 20, and the first storage unit and the second storage unit are deposited and formed simultaneously. In this way, the top surface of the first storage unit is lower than the bottom surface of the second storage unit, and the first storage unit and the second storage unit are staggered along the height direction parallel to the first dielectric layer 20, so that the number of storage units can be increased in the 3D scale to obtain more storage units, thereby obtaining a greater storage density.

[0072] At the same time, the first storage unit and the second storage unit are also formed by deposition, and the first storage unit and the second storage unit are formed synchronously. In this way, the storage unit can be obtained in two planes (the plane where the bottom wall of the groove 40 is located and the plane where the top surface of the first dielectric layer 20 is located) by depositing the storage unit film layer once, thereby saving the storage unit film layer and reducing the manufacturing cost.

[0073] The synchronous deposition method of the first storage unit and the second storage unit includes physical vapor deposition (PVD) or ion beam deposition (IBD). The film layers of the first storage unit and the second storage unit are sequentially deposited by PVD or IBD. In this way, the first storage unit and the second storage unit can be formed by utilizing the structure of the groove 40 itself without controlling the deposition angle, thereby reducing the manufacturing difficulty; and the above film layers will not adhere to the sidewall of the groove when deposited in the groove, thereby facilitating the subsequent process manufacturing.

[0074] In some possible embodiments, the first storage unit includes a first heavy metal layer 51 and a first magnetic tunnel junction 61 stacked in sequence, and the second storage unit includes a second heavy metal layer 52 and a second magnetic tunnel junction 62 stacked in sequence, the first heavy metal layer 51 and the second heavy metal layer 52 are formed by synchronous deposition, and the first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 are formed by synchronous deposition.

[0075] Specifically, the first heavy metal layer 51 is arranged in the groove 40, and the second heavy metal layer 52 is arranged on the top surface of the first dielectric layer 20. The first heavy metal layer 51 is in contact with the first bottom electrode 23, and the second heavy metal layer 52 is in contact with the second bottom electrode 24. The first heavy metal layer 51 and the second heavy metal layer 52 are made of the same material, including materials with spin-orbit torque effect such as tungsten, tungsten nitride, and tantalum, and the first heavy metal layer 51 and the second heavy metal layer 52 are deposited and formed synchronously. The first magnetic tunnel junction 61 is arranged on the first heavy metal layer 51, and the second magnetic tunnel junction 62 is arranged on the second heavy metal layer 52. The first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 have the same structure, and the corresponding film layers have the same material.

[0076] Exemplarily, the first magnetic tunnel junction 61 includes a first free layer, a first tunnel layer and a first fixed layer stacked in sequence, and the first free layer is in contact with the first heavy metal layer 51. The second magnetic tunnel junction 62 includes a second free layer, a second tunnel layer and a second fixed layer stacked in sequence. The second free layer is in contact with the second heavy metal layer 52. The magnetic moment directions of the second free layer and the first free layer can change with the film layer below them, and the two are deposited and formed synchronously. The second tunnel layer and the first tunnel layer are used to isolate the film layers on both sides, and the two are deposited and formed synchronously. The magnetic moment directions of the second fixed layer and the first fixed layer are fixed, and the two are deposited and formed synchronously.

[0077] The first storage unit further includes a first connection layer 71 disposed on the first magnetic tunnel junction 61, and the second storage unit further includes a second connection layer 72 disposed on the second magnetic tunnel junction 62. The materials of the second connection layer 72 and the first connection layer 71 can both be metal materials, and the second connection layer 72 and the first connection layer 71 are used for external connection, and the two are deposited and formed simultaneously. The top surface of the first connection layer 71 is lower than the top surface of the second free layer, and the material of the above-mentioned film layer can be a material known to those skilled in the art, which will not be repeated here.

[0078] In some possible implementations, the size of the top of the groove 40 is smaller than the size of the bottom of the groove 40, and the groove 40 can cut the deposited memory cell film layer along the third direction to form the first memory cell and the second memory cell, and the third direction is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction. Specifically, when the memory cell film layer is deposited, the memory cell film layer enters the groove 40 and does not adhere to the side wall of the groove 40, that is, the memory cell film layer in the groove 40 is spaced from the side wall of the groove 40. In this way, the memory cell film layer in the groove 40 is naturally disconnected from the memory cell film layer on the first dielectric layer 20, and the memory cell film layer in the groove 40 and on the first dielectric layer 20 can be separated along the third direction without etching to form the first memory cell and the second memory cell, which can avoid the problems of side wall damage or side wall re-deposition of the first memory cell and the second memory cell, and improve the yield and performance of the semiconductor storage structure.

[0079] Continue reading Figures 1 to 3 , along the third direction, a plurality of first magnetic tunnel junctions 61 and a plurality of second magnetic tunnel junctions 62 are arranged alternately, the third direction is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction; along the first direction, a plurality of first magnetic tunnel junctions 61 and a plurality of second magnetic tunnel junctions 62 are arranged independently of each other. In this way, the space on the top surface of the first dielectric layer 20 and in the groove 40 can be utilized to the maximum extent, and the storage unit film layer can be utilized to the maximum extent, thereby improving the storage density. Figure 1 As shown, the third direction is the width direction of the groove 40. Along the third direction, the first magnetic tunnel junctions 61 and the second magnetic tunnel junctions 62 are arranged alternately in sequence, that is, the first magnetic tunnel junctions 61 and the second magnetic tunnel junctions 62 are staggered. A second magnetic tunnel junction 62 is arranged between two adjacent first magnetic tunnel junctions 61, and a first magnetic tunnel junction 61 is arranged between two adjacent second magnetic tunnel junctions 62. The first magnetic tunnel junctions 61 and the second magnetic tunnel junctions 62 are aligned along the third direction. Specifically, as Figure 1 As shown, along the third direction, adjacent storage units are located on different planes, and the spaced storage units are located on the same plane. Figure 2 and Figure 3 As shown, along the first direction, the first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 are independently arranged. Along the first direction, the first magnetic tunnel junction 61 is independently arranged in a column, and the second magnetic tunnel junction 62 is independently arranged in a column, that is, along the first direction, adjacent storage cells are located in the same plane.

[0080] Continue reading Figures 1 to 3, among the first magnetic tunnel junctions 61 independently arranged along the first direction, at least part of the first heavy metal layer 51 under the first magnetic tunnel junctions 61 is an integrated structure; among the second magnetic tunnel junctions 62 independently arranged along the first direction, at least part of the second heavy metal layer 52 under the second magnetic tunnel junctions 62 is an integrated structure. In this way, at least part of the first magnetic tunnel junctions 61 are connected to a first heavy metal layer 51, and at least part of the second magnetic tunnel junctions 62 are connected to a second heavy metal layer 52, which can reduce the number of bottom electrodes and simplify the semiconductor storage structure.

[0081] For example, Figure 2 As shown, all the first magnetic tunnel junctions 61 located in the same column along the first direction are located on one first heavy metal layer 51, that is, the first heavy metal layer 51 is in the shape of a strip extending along the first direction, and the corresponding first magnetic tunnel junctions 61 are located on the same first heavy metal layer 51. In this way, along the first direction, two first bottom electrodes 23 are provided to reduce the number of first bottom electrodes 23.

[0082] For example, Figure 3 As shown, all the second magnetic tunnel junctions 62 located in the same column along the first direction are located on one second heavy metal layer 52, that is, the second heavy metal layer 52 is in the shape of a strip extending along the first direction, and the corresponding second magnetic tunnel junctions 62 are located on the same second heavy metal layer 52. In this way, along the first direction, only two second bottom electrodes 24 are required to be provided, so as to reduce the number of second bottom electrodes 24.

[0083] Continue reading Figures 1 to 3 , a second dielectric layer 25 is also provided in the groove 40, and the second dielectric layer 25 is at least filled between the first storage unit and the first dielectric layer 20. The second dielectric layer 25 covers the first storage unit and fills the groove 40 to isolate and protect the first storage unit. The materials of the second dielectric layer 25 and the first dielectric layer 20 are both insulating materials, and the insulating materials include, for example, silicon nitride, silicon oxynitride, silicon oxide, silicon carbide, etc. The materials of the second dielectric layer 25 and the first dielectric layer 20 can be the same or different. Exemplarily, the top surface of the second dielectric layer 25 is flush with the top surface of the first dielectric layer 20. Another exemplary embodiment, the second dielectric layer 25 is located in the groove 40 and covers the second storage unit, and the second dielectric layer 25 covers the top surface and side surfaces of the first storage unit, and covers the top surface and side surfaces of the second storage unit, for example, the second dielectric layer 25 extends along the third direction.

[0084] Continue reading Figure 2 and Figure 3As shown, the semiconductor storage structure further includes a third dielectric layer 26, and the top surface of the third dielectric layer 26 is a plane. The third dielectric layer 26 is located on the second dielectric layer 25, and is filled between adjacent first magnetic tunnel junctions 61 and adjacent second magnetic tunnel junctions 62. The material of the third dielectric layer 26 is an insulating material, and the materials of the third dielectric layer 26, the first dielectric layer 20, and the second dielectric layer 25 can be the same, partially the same, or different.

[0085] Continue reading Figures 1 to 3 The semiconductor storage structure further includes a first top electrode 81 and a second top electrode 82, and the first top electrode 81 penetrates the film layer above the first magnetic tunnel junction 61. For example, the first top electrode 81 penetrates the second dielectric layer 25 and the third dielectric layer 26 to connect the first magnetic tunnel junction 61. The first top electrode 81 corresponds to the first magnetic tunnel junction 61 one by one, that is, each first magnetic tunnel junction 61 is connected to a first top electrode 81 to realize the external connection of each first magnetic tunnel junction 61.

[0086] The second top electrode 82 penetrates the film layer above the second magnetic tunnel junction 62, for example, the second top electrode 82 penetrates the second dielectric layer 25 and the third dielectric layer 26 to connect the second magnetic tunnel junction 62. The second top electrode 82 corresponds to the second magnetic tunnel junction 62 one by one, that is, each second magnetic tunnel junction 62 is connected to a corresponding second top electrode 82 to achieve the external connection of each second magnetic tunnel junction 62. Exemplarily, the top surfaces of the second top electrode 82, the first top electrode 81 and the third dielectric layer 26 are flush. The materials of the second top electrode 82 and the first top electrode 81 can both be metal materials, and the materials of the second top electrode 82, the first top electrode 81, the second bottom electrode 24 and the first bottom electrode 23 can be the same.

[0087] The semiconductor storage structure in the embodiment of the present application includes a first dielectric layer 20 and a storage unit, and the top surface of the first dielectric layer 20 is provided with a groove 40 extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer 20. The storage unit includes a first storage unit arranged in the groove 40, and a second storage unit arranged on the top surface of the first dielectric layer 20, the top surface of the first storage unit is lower than the top surface of the first dielectric layer 20, and the first storage unit and the second storage unit are deposited and formed synchronously. Along the height direction parallel to the first dielectric layer 20, the first storage unit and the second storage unit are staggered, and the number of storage units can be increased in the 3D scale to obtain a higher number of storage units, thereby obtaining a greater storage density. At the same time, the first storage unit and the second storage unit are formed by synchronous deposition, and the storage unit can be obtained in two planes by deposition once, which saves the storage unit film layer and reduces the manufacturing cost.

[0088] In addition, along the second direction parallel to the height direction of the first dielectric layer 20, the size of the top of the groove 40 is smaller than the size of the bottom of the groove 40, and the storage unit film layer in the groove 40 and on the first dielectric layer 20 can be separated along the third direction without etching, thereby avoiding problems such as sidewall damage or sidewall re-deposition of the first storage unit and the second storage unit, thereby improving the yield and performance of the semiconductor storage structure.

[0089] The present application also provides a method for manufacturing a semiconductor storage structure. Figure 4 , the production method specifically includes the following steps:

[0090] Step S100: forming a groove extending along a first direction on a top surface of a first dielectric layer, wherein the first direction is a direction parallel to the top surface of the first dielectric layer.

[0091] See also Figure 5 The first dielectric layer 20 is, for example, disposed on the substrate 10. The material of the first dielectric layer 20 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. The top surface of the first dielectric layer 20 is provided with a groove 40 extending along a first direction. The first direction is a direction parallel to the top surface of the first dielectric layer 20. Specifically, Figure 5 The direction perpendicular to the paper surface is Figure 7 The X direction shown is the length direction of the first groove 40. Figure 5 As shown, the groove 40 is opened on the top surface of the first dielectric layer 20 and is located in the first dielectric layer 20. The groove 40 does not extend to the bottom surface of the first dielectric layer 20, that is, the groove 40 does not penetrate the first dielectric layer 20. In other examples, the groove 40 can also penetrate the first dielectric layer 20.

[0092] In some possible examples, along the second direction, the size of the top of the groove 40 is smaller than the size of the bottom of the groove 40, wherein the second direction is parallel to the height direction of the first dielectric layer 20, such as Figure 5 The second direction is the Z direction shown in FIG. 4 , and the second direction is the depth direction of the groove 40. In this way, the groove 40 is formed into a shape that is small at the top and large at the bottom, and the sidewall of the groove 40 is inclined and forms an acute angle with the top surface of the first dielectric layer 20, so that the groove 40 can cut off the corresponding film layer formed on the first dielectric layer 20.

[0093] The first dielectric layer 20 is also formed with bottom electrodes, which include a first bottom electrode 23 and a second bottom electrode 24. The first bottom electrode 23 and the second bottom electrode 24 can both be made of metal materials. The first bottom electrode 23 is exposed in the groove 40, that is, one end of the first bottom electrode 23 is located at the bottom of the groove 40, and the other end of the first bottom electrode 23 is located at the bottom surface of the first dielectric layer 20. Along the second direction, the bottom surface of the first dielectric layer 20 and the top surface of the first dielectric layer 20 are arranged opposite to each other.

[0094] The second bottom electrode 24 is disposed beside the groove 40, and the second bottom electrode 24 is not exposed in the groove 40. One end of the second bottom electrode 24 is located on the top surface of the first dielectric layer 20, and the other end of the second bottom electrode 24 is located on the bottom surface of the first dielectric layer 20. The second bottom electrode 24 and the first bottom electrode 23 have different heights to connect storage cells at different heights.

[0095] Step S200: forming a storage unit, the storage unit comprising a first storage unit and a second storage unit; wherein the first storage unit is formed in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; the second storage unit is formed on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are formed by synchronous deposition.

[0096] See also Figure 6 and Figure 7 The storage unit includes a first storage unit and a second storage unit, wherein the first storage unit is arranged in the groove 40, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer 20. The second storage unit is arranged on the top surface of the first dielectric layer 20, and the first storage unit and the second storage unit are deposited and formed simultaneously. In this way, the top surface of the first storage unit is lower than the bottom surface of the second storage unit, and the first storage unit and the second storage unit are staggered along the height direction parallel to the first dielectric layer 20, so that the number of storage units can be increased in the 3D scale to obtain a higher number of storage units, thereby obtaining a greater storage density.

[0097] At the same time, the first storage unit and the second storage unit are also formed by deposition, and the first storage unit and the second storage unit are also formed synchronously. In this way, the storage unit can be obtained in two planes (the plane where the bottom wall of the groove 40 is located and the plane where the top surface of the first dielectric layer 20 is located) by depositing the storage unit film layer once, thereby saving the storage unit film layer and reducing the manufacturing cost.

[0098] Specifically, the synchronous deposition method of the first storage unit and the second storage unit includes physical vapor deposition or ion beam deposition. The film layers of the first storage unit and the second storage unit are sequentially deposited by PVD or IBD. In this way, the first storage unit and the second storage unit can be formed by utilizing the structure of the groove 40 itself without controlling the deposition angle, thereby reducing the manufacturing difficulty; and the above film layers will not adhere to the sidewalls of the groove when deposited in the groove, thereby facilitating the subsequent process manufacturing.

[0099] In some possible embodiments, the first storage unit includes a first heavy metal layer 51 and a first magnetic tunnel junction 61 stacked in sequence, and the second storage unit includes a second heavy metal layer 52 and a second magnetic tunnel junction 62 stacked in sequence, the first heavy metal layer 51 and the second heavy metal layer 52 are formed by synchronous deposition, and the first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 are formed by synchronous deposition.

[0100] Specifically, the first heavy metal layer 51 is disposed in the groove 40, and the second heavy metal layer 52 is disposed on the top surface of the first dielectric layer 20. The first heavy metal layer 51 is in contact with the first bottom electrode 23, and the second heavy metal layer 52 is in contact with the second bottom electrode 24. The first heavy metal layer 51 and the second heavy metal layer 52 are made of the same material, including tungsten, tungsten nitride, tantalum and other materials having a spin-orbit torque effect, so that the first heavy metal layer 51 and the second heavy metal layer 52 can be deposited and formed synchronously.

[0101] The first magnetic tunnel junction 61 is arranged on the first heavy metal layer 51, and the second magnetic tunnel junction 62 is arranged on the second heavy metal layer 52. The first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 have the same structure, and the corresponding film layers are made of the same material. Exemplarily, the first magnetic tunnel junction 61 includes a first free layer, a first tunnel layer, and a first fixed layer stacked in sequence, and the first free layer contacts the first heavy metal layer 51. The second magnetic tunnel junction 62 includes a second free layer, a second tunnel layer, and a second fixed layer stacked in sequence, and the second free layer contacts the second heavy metal layer 52.

[0102] The magnetic moment directions of the second free layer and the first free layer can change with the film layer below them, and the two are deposited synchronously. The second tunneling layer and the first tunneling layer are used to isolate the film layers on both sides, and the two are deposited synchronously. The magnetic moment directions of the second fixed layer and the first fixed layer are fixed, and the two are deposited synchronously. The second connection layer and the first connection layer are used for external connection, and the two are deposited synchronously.

[0103] The first storage unit includes a first connection layer 71 disposed on the first magnetic tunnel junction 61, and the second storage unit includes a second connection layer 72 disposed on the second magnetic tunnel junction 62. The top surface of the first connection layer 71 is lower than the top surface of the second free layer, and the second connection layer 72 and the first connection layer 71 are used for external connection, and the two are deposited and formed simultaneously. The material of the above-mentioned film layer can be a material known to those skilled in the art, and will not be repeated here.

[0104] In some possible implementations, the size of the top of the groove 40 is smaller than the size of the bottom of the groove 40, and the second direction is parallel to the height direction of the first dielectric layer 20. The formation of the storage unit includes: depositing a storage unit film layer, and the groove 40 cuts the storage unit film layer along a third direction to form a first storage unit and a second storage unit; wherein the third direction is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction, such as Figure 6 and Figure 7 Center Y direction.

[0105] Specifically, when depositing the memory cell film layer, part of the memory cell film layer falls into the groove 40 and does not adhere to the side wall of the groove 40, that is, the memory cell film layer in the groove 40 is spaced from the side wall of the groove 40. In this way, the memory cell film layer in the groove 40 is naturally disconnected from the memory cell film layer on the first dielectric layer 20, and the memory cell film layer in the groove 40 and on the first dielectric layer 20 can be divided into two parts without etching to form the first memory cell and the second memory cell, which can avoid problems such as damage to the side wall of the first memory cell and the second memory cell or redeposition of the side wall, thereby improving the yield and performance of the semiconductor memory structure.

[0106] In some possible implementations, depositing a memory cell film layer may include the following process:

[0107] See also Figure 5 and Figure 6 , a heavy metal material layer and a magnetic tunnel junction stacking layer 63 are deposited, and the heavy metal material layer and the magnetic tunnel junction stacking layer 63 are located on the bottom surface of the groove 40 and the top surface of the first dielectric layer 20. The heavy metal material layer in the groove 40 and the heavy metal material layer on the first dielectric layer 20 are disconnected to form a first heavy metal layer 51 and a second heavy metal layer 52, respectively. The magnetic tunnel junction stacking layer 63 in the groove 40 and the magnetic tunnel junction stacking layer 63 on the first dielectric layer 20 are disconnected, and the first magnetic tunnel junction 61 and the second magnetic tunnel junction 62 will be formed respectively later. The total thickness of the first heavy metal layer 51 in the groove 40 and the magnetic tunnel junction stacking layer thereon is less than the height of the groove 40.

[0108] See also Figure 6 and Figure 7 After depositing the heavy metal material layer and the magnetic tunnel junction stack layer 63, a connection material layer 73 is also deposited. The connection material layer 73 in the groove 40 and the connection material layer 73 on the first dielectric layer 20 are disconnected to form a first connection layer 71 and a second connection layer 72 respectively.

[0109] See also Figure 8 and Fig. 9 , forming a second initial dielectric layer 27, the second initial dielectric layer 27 covers the magnetic tunnel junction stack layer 63 and fills the groove 40. The deposition thickness of the second initial dielectric layer 27 is greater than or equal to the depth of the groove 40. Fig.10 , the second initial dielectric layer 27 is etched back so that the top surface of the second initial dielectric layer 27 is flush with the top surface of the first dielectric layer 20, or refer to Fig.11 , the top surface of the second initial dielectric layer 27 is higher than the top surface of the first dielectric layer 20 .

[0110] See also Figures 11 to 15 , patterning the second initial dielectric layer 27 to form a plurality of second dielectric layers 25 extending along the third direction and spaced apart along the first direction. Fig.11 and Fig.12 As shown, a photoresist layer 90 is formed on the second initial dielectric layer 27, and the photoresist layer 90 is exposed and developed to form a preset pattern. Figures 13 to 15 As shown, the pattern of the photoresist layer 90 is transferred to the second initial dielectric layer 27 to form the second dielectric layer 25. The magnetic tunnel junction stacking layer is etched using the second dielectric layer 25 as a mask, for example, by IBE or RIE. The etching stops at the first heavy metal layer 51 and the second heavy metal layer 52, and the magnetic tunnel junction stacking layer 63 on the first heavy metal layer 51 forms a plurality of first magnetic tunnel junctions 61 spaced apart along the first direction, and the magnetic tunnel junction stacking layer on the second heavy metal layer 52 forms a plurality of second magnetic tunnel junctions 62 spaced apart along the first direction. The first heavy metal layer 51 and the first magnetic tunnel junction 61 form a first storage unit, and the second heavy metal layer 52 and the second magnetic tunnel junction 62 form a second storage unit.

[0111] After depositing the memory cell film layer, the following processes can also be performed:

[0112] See also Figures 16 to 18 , depositing a third dielectric layer 26, the third dielectric layer 26 fills between adjacent first magnetic tunnel junctions 61 and between adjacent second magnetic tunnel junctions 62, and also covers the second dielectric layer 25. The top surface of the third dielectric layer 26 can be a plane, for example, the third dielectric layer 26 is formed by deposition and planarization.

[0113] See also Figures 1 to 3 , holes are opened in the third dielectric layer 26 and the second dielectric layer 25 to expose the first magnetic tunnel junctions 61 and the second magnetic tunnel junctions 62 respectively, and then a third electrode material is deposited to form a top electrode (including a first top electrode 81 and a second top electrode 82).

[0114] The method for manufacturing the semiconductor storage structure in the embodiment of the present application forms a groove 40 on the top surface of the first dielectric layer 20, and forms a first storage unit and a second storage unit in the groove 40 and on the first dielectric layer 20 respectively, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer 20. In the height direction parallel to the first dielectric layer 20, the first storage unit and the second storage unit are staggered, and the number of storage units can be increased in the 3D scale to obtain a higher number of storage units, thereby obtaining a greater storage density. The first storage unit and the second storage unit are also formed by synchronous deposition, and the storage units can be obtained in two planes by deposition once, which saves the storage unit film layer and reduces the manufacturing cost.

[0115] In some possible embodiments, see Figures 19 to 25, forming a groove 40 extending along the first direction on the top surface of the first dielectric layer 20 (step S100), including: depositing the first dielectric layer 20, forming at least two sacrificial structures 30 extending along the first direction and arranged at intervals along a third direction in the first dielectric layer 20, the third direction is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction, and the top surface of the sacrificial structure 30 is flush with the top surface of the first dielectric layer 20; removing the sacrificial structure 30 to form the groove 40.

[0116] The first dielectric layer 20 is deposited on the substrate 10, and at least two sacrificial structures 30 are formed in the first dielectric layer 20. These sacrificial structures 30 extend along the first direction and are arranged at intervals along the third direction, which is parallel to the direction of the top surface of the first dielectric layer 20 and has an angle with the first direction (for example, perpendicular). The third direction is Fig.23 The Y direction shown, the first direction is Fig.23 In the direction perpendicular to the paper surface.

[0117] The material of the sacrificial structure 30 is different from that of the first dielectric layer 20, so that the sacrificial structure 30 can be easily removed. The top surface of the sacrificial structure 30 is also flush with the top surface of the first dielectric layer 20, so that the top surface of the sacrificial structure 30 is exposed, which facilitates the processing of the sacrificial structure 30. The sacrificial structure 30 is removed by utilizing the selectivity of the sacrificial structure 30 and the first dielectric layer 20 to form a groove 40 in the first dielectric layer 20. The sacrificial structure 30 is removed, for example, by plasma etching. By controlling the shape of the sacrificial structure 30, the shape of the groove 40 can be adjusted, such as Fig.24 As shown, after removing the sacrificial structure 30, a groove 40 with a small top and a large bottom is formed. The first bottom electrode 23 is exposed in the groove 40, but the second bottom electrode 24 is not exposed.

[0118] In some possible implementations, the first dielectric layer 20 further includes a first bottom electrode 23 and a second bottom electrode 24. Depositing the first dielectric layer 20 may specifically include the following process:

[0119] See also Fig.19 and Fig. 20 , deposit the first layer 21 on the substrate 10, and open a hole in the first layer 21. Deposit the first electrode material, the first electrode material fills the hole and covers the first layer 21. Then, planarize the first electrode material until the first layer 21 is exposed, remove the excess metal, and the remaining first electrode material forms the first electrode, which is the first bottom electrode 23.

[0120] See also Fig.21 , depositing a sacrificial material 31, wherein the sacrificial material 31 is made of a material different from that of the first layer 21. Fig. 22, patterning the sacrificial material 31, patterning the sacrificial material 31 into a strip extending along the first direction, forming a sacrificial structure 30, the sacrificial structure 30 has a small size at the top and a large size at the bottom. At least two first bottom electrodes 23 are correspondingly arranged under each sacrificial structure 30, and only the first layer 21 is exposed between adjacent sacrificial structures 30, and no first bottom electrode 23 is exposed.

[0121] See also Fig.23 , deposit the second layer 22 to cover the sacrificial structure 30 and the first layer 21, the deposition thickness of the second layer 22 is greater than the height of the sacrificial structure, and the second layer 22 and the first layer 21 can be made of the same material. Then, the second layer 22 is planarized until the sacrificial structure 30 is exposed, and the remaining second layer 22 and the first layer 21 form the first dielectric layer 20.

[0122] See also Fig.23 and Fig.24 , and then remove the sacrificial structure 30 to form a groove 40. Open a hole in the first dielectric layer 20, deposit the second electrode material, and fill the hole with the second electrode material and cover the first dielectric layer 20. Fig.25 , and then planarizing the second electrode material until the first dielectric layer 20 is exposed, removing excess metal, and the remaining second electrode material forms the second bottom electrode 24 .

[0123] For other possible implementations, see Fig.26 and Fig. 27 , depositing a first layer 21 on the substrate 10, and opening a hole in the first layer 21. Depositing a first electrode material, the first electrode material fills the hole and covers the first layer 21. Then, the first electrode material is planarized until the first layer 21 is exposed, removing excess metal, and the remaining first electrode material forms a first electrode, wherein part of the first electrode is a first bottom electrode 23, and part of the first electrode is used to form a second bottom electrode.

[0124] See also Fig.28 , depositing a sacrificial material 31, wherein the sacrificial material 31 is made of a material different from that of the first layer 21. Fig.29 and Fig.30 , patterning the sacrificial material 31, patterning the sacrificial material 31 into a strip extending along the first direction, forming a sacrificial structure 30, the sacrificial structure 30 has a small size at the top and a large size at the bottom. At least two first electrodes are correspondingly arranged below each sacrificial structure 30, the first electrodes forming the first bottom electrode 23, and a portion of the first electrode is exposed between adjacent sacrificial structures 30.

[0125] See also Fig.31 and Fig.32, deposit the second layer 22 to cover the sacrificial structure 30 and the first layer 21, the deposition thickness of the second layer 22 is greater than the height of the sacrificial structure, and the second layer 22 and the first layer 21 can be made of the same material. Then, the second layer 22 is planarized until the sacrificial structure 30 is exposed, and the remaining second layer 22 and the first layer 21 form the first dielectric layer 20.

[0126] See also Fig.31 , Fig.33 and Fig.34 Then, a hole is opened in the second layer 22, and a second electrode material is deposited to connect the first electrode. The second electrode material fills the hole and covers the first dielectric layer 20. The second electrode material is then planarized until the first dielectric layer 20 is exposed, and the excess metal is removed. The remaining second electrode material and the first electrode connected thereto form a second bottom electrode 24, completing the construction of the bottom electrode. Figure 34 to Figure 36 , the sacrificial structure 30 is removed to form a groove 40. The first bottom electrode 23 is exposed in the groove 40, and the second bottom electrode 24 is exposed beside the groove 40.

[0127] In some other possible embodiments, see Figures 37 to 41 , forming a groove 40 extending along the first direction on the top surface of the first dielectric layer 20 (step S100), specifically comprising: depositing a first layer 21 of the first dielectric layer 20, and depositing a second layer 22 of the first dielectric layer 20 on the first layer 21; removing a portion of the second layer 22 along the first direction to expose a portion of the top surface of the first layer 21; using the remaining second layer 22 as a mask, etching the first layer 21 to form the groove 40. The first dielectric layer 20 is formed by two depositions, and the first layer 21 and the second layer 22 are made of different materials and have different etching rates, so as to form the desired shape of the groove 40.

[0128] For some possible implementations, see Fig.37 , deposit the first layer 21 on the substrate 10, and open a hole in the first layer 21. Deposit the first electrode material, the first electrode material fills the hole and covers the first layer 21. Then planarize the first electrode material until the first layer 21 is exposed, remove the excess metal, and the remaining first electrode material forms the first electrode, which is the first bottom electrode 23. Deposit the second layer 22, the second layer 22 is made of a different material from the first layer 21, and the thickness of the second layer 22 along the second direction is less than the thickness of the first layer 21. Pattern the second layer 22 to form a groove 40 extending along the first direction. At least two first bottom electrodes 23 are correspondingly exposed in each groove 40.

[0129] See also Fig.38, the first layer 21 is etched with the second layer 22 as a mask. The etching can be plasma dry etching or wet etching. The groove 40 is extended to the first layer 21. The remaining second layer 22 and the first layer 21 form the first dielectric layer 20. Then, a hole is opened in the first dielectric layer 20, and the second electrode material is deposited. The second electrode material fills the hole and covers the first dielectric layer 20. Then, the second electrode material is planarized until the first dielectric layer 20 is exposed, and the excess metal is removed. The remaining second electrode material forms the second bottom electrode 24, which is located on the side of the groove 40.

[0130] For other possible implementations, see Fig.39 , depositing a first layer 21 on the substrate 10, and opening a hole in the first layer 21. Depositing a first electrode material, the first electrode material fills the hole and covers the first layer 21. Then flattening the first electrode material until the first layer 21 is exposed, removing excess metal, and the remaining first electrode material forms the first electrode. Depositing a second layer 22, the second layer 22 covers the first electrode. The second layer 22 is made of a different material from the first layer 21, and along the second direction, the thickness of the second layer 22 is less than the thickness of the first layer 21. The second layer 22 opens a hole to expose a portion of the first electrode, and depositing a second electrode material, the second electrode material fills the hole and covers the second layer 22. Then flattening the second electrode material, the remaining second electrode material and the contacting first electrode form a second bottom electrode 24.

[0131] See also Fig.40 , patterning the second layer 22 to form a groove 40 extending along the first direction. At least two first electrodes are correspondingly exposed in each groove 40, and the exposed first electrodes form the first bottom electrode 23. The first layer 21 is etched using the second layer 22 as a mask, and the etching can be plasma dry etching or wet etching, and the groove 40 is extended to the first layer 21, and the remaining second layer 22 and the first layer 21 form the first dielectric layer 20.

[0132] For other possible examples, see Fig.41 , depositing a first layer 21 on the substrate 10, and opening a hole in the first layer 21. Depositing a first electrode material, the first electrode material fills the hole and covers the first layer 21. Then, the first electrode material is planarized until the first layer 21 is exposed, removing excess metal, and the remaining first electrode material forms a first electrode. Depositing a second layer 22, the second layer 22 covers the first electrode. The second layer 22 is made of a different material from the first layer 21, and the thickness of the second layer 22 along the second direction is less than the thickness of the first layer 21.

[0133] See also Fig.42, patterning the second layer 22 to form a groove 40 extending along the first direction. At least two first electrodes are correspondingly exposed in each groove 40, and the exposed first electrodes form the first bottom electrode 23. The second layer 22 is opened to expose the remaining first electrodes, and the second electrode material is deposited, and the second electrode material fills the gap and covers the second layer 22. The second electrode material is then planarized, and the remaining second electrode material and the contacting first electrode form the second bottom electrode 24. The first layer 21 is etched using the second layer 22 as a mask, and the etching can be plasma dry etching or wet etching, and the groove 40 is extended to the first layer 21, and the remaining second layer 22 and the first layer 21 form the first dielectric layer 20.

[0134] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor storage structure, characterized in that: include: A first dielectric layer and a storage unit, wherein a top surface of the first dielectric layer is provided with a groove extending along a first direction, and the first direction is a direction parallel to the top surface of the first dielectric layer; The storage unit includes a first storage unit and a second storage unit; Wherein, the first storage unit is disposed in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; The second storage unit is disposed on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are deposited and formed synchronously.

2. The semiconductor storage structure according to claim 1, characterized in that: The first storage unit includes a first heavy metal layer and a first magnetic tunnel junction stacked in sequence, and the second storage unit includes a second heavy metal layer and a second magnetic tunnel junction stacked in sequence; The first heavy metal layer and the second heavy metal layer are formed by synchronous deposition, and the first magnetic tunnel junction and the second magnetic tunnel junction are formed by synchronous deposition.

3. The semiconductor storage structure according to claim 1 or 2, characterized in that: Along the second direction, the size of the top of the groove is smaller than the size of the bottom of the groove, so that the deposited memory cell film layer is cut along the third direction to form the first memory cell and the second memory cell; Wherein, the second direction is parallel to the height direction of the first dielectric layer; The third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction.

4. The semiconductor storage structure according to claim 2, characterized in that: Along a third direction, a plurality of the first magnetic tunnel junctions and a plurality of the second magnetic tunnel junctions are alternately arranged, and the third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction; Along the first direction, a plurality of the first magnetic tunnel junctions and a plurality of the second magnetic tunnel junctions are arranged independently of each other.

5. The semiconductor storage structure according to claim 4, characterized in that: Among the plurality of first magnetic tunnel junctions independently arranged along the first direction, the first heavy metal layer below at least some of the first magnetic tunnel junctions is an integrated structure; Among the plurality of second magnetic tunnel junctions independently arranged along the first direction, the second heavy metal layer below at least a portion of the second magnetic tunnel junctions is an integrated structure.

6. The semiconductor storage structure according to claim 1 or 2, characterized in that: A second dielectric layer is also disposed in the groove, and the second dielectric layer is at least filled between the first storage unit and the first dielectric layer.

7. The semiconductor storage structure according to claim 1 or 2, characterized in that: The synchronous deposition method of the first memory unit and the second memory unit includes physical vapor deposition or ion beam deposition.

8. A method for manufacturing a semiconductor storage structure, characterized in that: include: A groove extending along a first direction is formed on the top surface of the first dielectric layer, wherein the first direction is a direction parallel to the top surface of the first dielectric layer; forming a storage unit, the storage unit comprising a first storage unit and a second storage unit; Wherein, the first storage unit is formed in the groove, and the top surface of the first storage unit is lower than the top surface of the first dielectric layer; The second storage unit is formed on the top surface of the first dielectric layer, and the first storage unit and the second storage unit are deposited and formed simultaneously.

9. The manufacturing method according to claim 8, characterized in that: Along the second direction, the size of the top of the groove is smaller than the size of the bottom of the groove, and the second direction is parallel to the height direction of the first dielectric layer; Depositing a memory cell film layer, wherein the groove cuts the memory cell film layer along a third direction to form the first memory cell and the second memory cell; The third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction.

10. The production method according to claim 8 or 9, characterized in that: A groove extending along a first direction is formed on the top surface of the first dielectric layer, comprising: Depositing the first dielectric layer, wherein at least two sacrificial structures extending along the first direction and arranged at intervals along a third direction are formed in the first dielectric layer, the third direction is parallel to the direction of the top surface of the first dielectric layer and has an angle with the first direction, and the top surface of the sacrificial structure is flush with the top surface of the first dielectric layer; removing the sacrificial structure to form the groove; Alternatively, forming a groove extending along a first direction on the top surface of the first dielectric layer comprises: Depositing a first layer of the first dielectric layer, and depositing a second layer of the first dielectric layer on the first layer; removing a portion of the second layer along the first direction to expose a portion of the top surface of the first layer; The remaining second layer is used as a mask to etch the first layer to form the groove.

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