Reverse conducting insulated gate bipolar transistor, forming method thereof, chip and vehicle

Abstract

According to the reverse conducting insulated gate bipolar transistor, the forming method thereof, the chip and the vehicle provided by the invention, after the dielectric layer is formed, the dielectric layer is utilized to protect the insulated gate bipolar transistor region, so that the carrier lifetime control region can be formed only in the fast recovery diode region; and meanwhile, the influence on the service life of carriers in an insulated gate bipolar transistor region is reduced. The reverse recovery time of the fast recovery diode region can be shortened, the softness of the device can be improved, the leakage current of the device can be reduced, the device has better high-temperature stability and reliability, and the overall performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a reverse conducting insulated gate bipolar transistor and a method for forming the same, a chip and a vehicle. Background Art

[0002] The reverse conducting insulated gate bipolar transistor (RC-IGBT) is a new type of insulated gate bipolar transistor (IGBT) device with high integration, which integrates the fast recovery diode (FRD) and the insulated gate bipolar transistor on the same chip. Compared with the traditional insulated gate bipolar transistor device, the reverse conducting insulated gate bipolar transistor improves the device power density, reduces the chip area, manufacturing cost and packaging cost, and improves the reliability of the insulated gate bipolar transistor.

[0003] Carrier lifetime control is the key to achieving high-performance fast recovery diodes. By controlling carrier lifetime and introducing recombination centers in the base region of the fast recovery diode, the carrier lifetime can be reduced, the total amount of stored charge in the base region during forward conduction can be reduced, and the recombination of minority carriers during reverse shutdown can be accelerated.

[0004] However, the current carrier lifetime control process will affect the performance of the insulated gate bipolar transistor, thereby affecting the comprehensive performance of the reverse conducting insulated gate bipolar transistor. Summary of the invention

[0005] The purpose of the present application is to provide a reverse-conducting insulated gate bipolar transistor and a method for forming the same, a chip and a vehicle, aiming to control the carrier lifetime of a fast recovery diode region (1102) while reducing the impact on the carrier lifetime of an insulated gate bipolar transistor region (1101).

[0006] The present invention provides a method for forming a reverse conducting insulated gate bipolar transistor, comprising:

[0007] A substrate is formed, the substrate comprising a first surface and a second surface opposite to each other, and the substrate comprises an insulated gate bipolar transistor region and a fast recovery diode region; a dielectric layer is formed on the first surface of the insulated gate bipolar transistor region, the dielectric layer exposing the first surface of the fast recovery diode region; after the dielectric layer is formed, a carrier lifetime control region is formed in the substrate of the fast recovery diode region.

[0008] In some embodiments, the method for forming a dielectric layer on the first surface of the insulated gate bipolar transistor region includes: forming an initial dielectric layer on the first surfaces of the insulated gate bipolar transistor region and the fast recovery diode region; removing the initial dielectric layer on the first surface of the fast recovery diode region to form the dielectric layer located in the insulated gate bipolar transistor region.

[0009] In some embodiments, the method for forming a carrier lifetime control region in the substrate of the fast recovery diode region includes: depositing a platinum layer on the dielectric layer and the first surface of the fast recovery diode region; removing the platinum layer on the surface of the dielectric layer and the first surface; after removing the platinum layer, performing proton irradiation on one side of the first surface of the substrate; and performing annealing to form a platinum-doped carrier lifetime control region with a local concentration distribution in the fast recovery diode region.

[0010] In some embodiments, the method for forming a carrier lifetime control region in the substrate of the fast recovery diode region also includes: before performing the proton irradiation, depositing a sacrificial layer on the surface of the dielectric layer and the first surface; removing the sacrificial layer on the first surface to retain the sacrificial layer located on the surface of the dielectric layer; before performing the annealing treatment, removing the sacrificial layer on the surface of the dielectric layer.

[0011] In some embodiments, a method for forming a substrate includes: providing an initial substrate, the initial substrate including the first surface and the second surface relative to each other; forming a carrier storage region in the initial substrate, a portion of the initial substrate located in the carrier storage region away from the first surface forms a drift region; and forming a well region in the initial substrate, a surface of the well region away from the carrier storage region being the first surface.

[0012] In some embodiments, the initial substrate includes an insulated gate bipolar transistor region and a fast recovery diode region; the method for forming a well region in the initial substrate includes: forming a first well region located in the insulating gate bipolar transistor region and a second well region located in the fast recovery diode region, the ion concentration of the first well region being greater than the ion concentration of the second well region.

[0013] In some embodiments, the method for forming the first well region and the second well region includes: performing a first ion implantation on the initial substrate of the IGBT region and the fast recovery diode region; and performing a second ion implantation on the initial substrate of the IGBT region.

[0014] In some embodiments, the method further includes: before forming the well region, forming a gate trench penetrating a portion of the substrate on one side of the first surface, the gate trench being located in the insulated gate bipolar transistor region; and forming a gate structure in the gate trench.

[0015] In some embodiments, the method further includes: forming an emitter region on the sidewall of the gate trench by ion implantation.

[0016] In some embodiments, it also includes: after forming the carrier lifetime control region, etching the dielectric layer of the insulated gate bipolar transistor region to form a first contact hole exposing the emitter region; forming an ohmic contact region at the bottom of the first contact hole, the ohmic contact region is connected to the emitter region; and forming the first contact structure in the first contact hole.

[0017] In some embodiments, it also includes: before forming the well region, forming a first virtual trench, a second virtual trench and a third virtual trench penetrating a portion of the substrate on one side of the first surface, the first virtual trench and the second virtual trench are located in the insulated gate bipolar transistor region, and the third virtual trench is located in the fast recovery diode region; forming a first virtual gate structure in the first virtual trench, forming a second virtual gate structure in the second virtual trench, and forming a third virtual gate structure in the third virtual trench.

[0018] In some embodiments, it also includes: after forming the carrier lifetime control region, etching the dielectric layer of the insulated gate bipolar transistor region to form a second contact hole exposing the first virtual gate structure; forming a second contact structure in the second contact hole, and the second contact structure is connected to the first virtual gate structure.

[0019] In some embodiments, the method further includes: forming an emitter electrode layer on the surface of the dielectric layer and the first surface of the fast recovery diode region.

[0020] In some embodiments, it also includes: performing ion implantation on the second surface of the substrate to form a collector region located in the insulated gate bipolar transistor region and a short-circuit region located in the fast recovery diode region; performing ion implantation on the second surface of the substrate to form a field termination region, and the surface of the collector region and the short-circuit region away from the field termination region is the second surface; and forming a collector layer on the second surface of the substrate.

[0021] The embodiment of the present application also provides a reverse conducting insulated gate bipolar transistor, comprising: a substrate, comprising a first surface and a second surface relative to each other, and the substrate comprises an insulated gate bipolar transistor region and a fast recovery diode region; a dielectric layer, covering the first surface of the insulated gate bipolar transistor region and exposing the first surface of the fast recovery diode region; a carrier lifetime control region, located in the substrate of the fast recovery diode region.

[0022] In some embodiments, the IGBT region includes an ohmic contact region; the reverse conducting IGBT further includes: a first contact structure, located in the IGBT region, penetrating the dielectric layer and connected to the ohmic contact region.

[0023] In some embodiments, it also includes: an emitter electrode layer covering the dielectric layer and the first surface of the fast recovery diode region; wherein one end of the first contact structure is connected to the ohmic contact region, and the other end of the first contact structure is connected to the emitter electrode layer.

[0024] In some embodiments, the substrate includes a drift region, a carrier storage region, and a well region stacked in sequence, and the surface of the well region away from the drift region is the first surface; the carrier lifetime control region is located in at least one of the drift region, the carrier storage region, and the well region.

[0025] In some embodiments, it also includes: a gate structure, located in the insulated gate bipolar transistor region and penetrating a portion of the substrate, the dielectric layer covering the end of the gate structure; an emitter region, located on the side wall of the gate structure and connected to the ohmic contact region.

[0026] In some embodiments, it also includes: a first virtual gate structure, located in the insulated gate bipolar transistor region and penetrating a portion of the substrate, and the dielectric layer covers the end of the first virtual gate structure; a second contact structure, located in the insulated gate bipolar transistor region, penetrating the dielectric layer and connected to the first virtual gate structure.

[0027] In some embodiments, the method further includes: a second dummy gate structure, which is located in the insulated gate bipolar transistor region and penetrates a portion of the substrate, and the dielectric layer covers an end portion of the second dummy gate structure.

[0028] In some embodiments, the method further includes: a third virtual gate structure, which is located in the fast recovery diode region and penetrates a portion of the substrate, and the emitter electrode layer covers an end portion of the third virtual gate structure.

[0029] In some embodiments, the carrier lifetime control region is doped with platinum.

[0030] An embodiment of the present application also provides a chip, comprising the reverse conducting insulated gate bipolar transistor described in any of the above embodiments.

[0031] An embodiment of the present application also provides a vehicle, comprising the chip as described above.

[0032] The present application provides a reverse-conducting insulated gate bipolar transistor and a method for forming the same, a chip and a vehicle. After forming a dielectric layer, the dielectric layer is used to protect the insulated gate bipolar transistor region, so that a carrier lifetime control region can be formed only in the fast recovery diode region, while reducing the impact on the carrier lifetime of the insulated gate bipolar transistor region. Not only can the reverse recovery time of the fast recovery diode region be reduced and the device softness be improved, but also the leakage current of the device can be reduced, so that the device has better high-temperature stability and reliability, and the overall performance of the device is improved.

[0033] In some embodiments, after the gate structure and the emitter electrode layer are formed, the dielectric layer can be used to isolate the gate structure from the emitter electrode layer in the insulated gate bipolar transistor region.

[0034] In some embodiments, since the initial dielectric layer on the first surface of the fast recovery diode region is removed, that is, the fast recovery diode region has no dielectric layer, the formed emitter electrode layer can be in contact with the substrate of the fast recovery diode region and serve as the positive electrode of the fast recovery diode. In addition, since the initial dielectric layer of the fast recovery diode region is removed, the fast recovery diode region can be fully opened, which is beneficial to the formation process of the carrier lifetime control region, the range of the carrier lifetime control region can be larger, and the effect of reducing the carrier lifetime of the fast recovery diode region is better.

[0035] In some embodiments, proton irradiation and annealing processes are performed after forming the dielectric layer to form a carrier lifetime control region in the substrate of the fast recovery diode region. This is to utilize the dielectric layer to reduce the impact of proton radiation on the insulated gate bipolar transistor region without adding additional process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0037] Figure 1 is a schematic flow chart of a method for forming a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application;

[0038] Figure 2 to Figure 7 is a schematic structural diagram of a reverse conducting insulated gate bipolar transistor during a formation process provided by some embodiments of the present application;

[0039] Figure 8is a schematic diagram of a cross-sectional structure of a reverse conducting insulated gate bipolar transistor in an insulated gate bipolar transistor region provided by some embodiments of the present application;

[0040] Fig. 9 It is a schematic diagram of the cross-sectional structure of a reverse conducting insulated gate bipolar transistor in a fast recovery diode region provided in some embodiments of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0042] The carrier lifetime control methods are mainly divided into overall lifetime control and local lifetime control. Platinum diffusion, as a type of overall lifetime control technology, achieves lifetime control by forming approximately uniformly distributed recombination centers in the device body. However, the introduction of equal recombination centers in the device space charge region does not contribute much to the reduction of the turn-off time, and will also increase the forward voltage drop and reverse leakage to a certain extent, and even lead to a decrease in the softness factor. The proton irradiation method is a type of longitudinal local lifetime control. Although this method can achieve local lifetime control, it causes the leakage current generated by the insulated gate bipolar transistor to be larger.

[0043] The embodiment of the present application provides a method for forming a reverse conducting insulated gate bipolar transistor to solve the above technical problems.

[0044] See also Figure 1 , Figure 1 The figure is a schematic flow chart of a method for forming a reverse conducting insulated gate bipolar transistor provided in some embodiments of the present application. The method for forming a reverse conducting insulated gate bipolar transistor comprises the following steps S1 to S3.

[0045] Step S1: forming a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other, and the substrate comprises an insulated gate bipolar transistor region and a fast recovery diode region.

[0046] Step S2: forming a dielectric layer on the first surface of the insulated gate bipolar transistor region, wherein the dielectric layer exposes the first surface of the fast recovery diode region.

[0047] Step S3: after forming the dielectric layer, forming a carrier lifetime control region in the substrate of the fast recovery diode region.

[0048] In the method for forming the reverse-conducting insulated gate bipolar transistor, after forming the dielectric layer, the dielectric layer is used to protect the insulated gate bipolar transistor region, so that the carrier lifetime control region can be formed only in the fast recovery diode region, while reducing the impact on the carrier lifetime of the insulated gate bipolar transistor region. Not only can the reverse recovery time of the fast recovery diode region be reduced and the device softness be improved, but also the leakage current of the device can be reduced, so that the device has better high-temperature stability and reliability, and the overall performance of the device is improved.

[0049] The method for forming the reverse conducting insulated gate bipolar transistor will be described in detail below with reference to the accompanying drawings.

[0050] Please refer to Figure 2 to Figure 7 , Figure 2 to Figure 7 It is a schematic structural diagram of a reverse conducting insulated gate bipolar transistor during the formation process provided by some embodiments of the present application. The method for forming the reverse conducting insulated gate bipolar transistor includes the following steps S1 to S3.

[0051] Step S1: forming a substrate 100, wherein the substrate 100 comprises a first surface 101 and a second surface 102 opposite to each other, and the substrate 100 comprises an insulated gate bipolar transistor region 1101 and a fast recovery diode region 1102. Figure 2 and Figure 3 , Figure 2 is a schematic diagram showing the top view of a reverse conducting insulated gate bipolar transistor, Figure 3 Show Figure 2 Schematic diagram of the cross-sectional structure of the reverse-conducting insulated gate bipolar transistor at A-A1.

[0052] In some embodiments, step S1 may include the following steps.

[0053] 1) See Figure 3 , providing an initial substrate, the initial substrate comprising the first surface 101 and the second surface 102 opposite to each other. The material of the initial substrate may include at least one of Si, SiC, GaAs or GaN, and the initial substrate may have lightly doped ions of the first conductivity type.

[0054] It should be noted that the first conductivity type and the second conductivity type in the present application are opposite, the first conductivity type is N-type, and the first conductivity type may also be P-type. When the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. In addition, the doped element type of the P-type doping region may be boron (B) and boron fluoride (BF2), etc., and the doped element type of the N-type doping region may be phosphorus (P), arsenic (As) and hydrogen (H), etc., and neither is specifically limited.

[0055] like Figure 3 As shown, the initial substrate may include an insulated gate bipolar transistor region 1101 and a fast recovery diode region 1102 , wherein the insulated gate bipolar transistor region 1101 is used to form an insulated gate bipolar transistor device, and the fast recovery diode region 1102 is used to form a fast recovery diode device.

[0056] See also Figure 2 The initial substrate may include multiple insulated gate bipolar transistor regions 1101 and multiple fast recovery diode regions 1102, and the insulated gate bipolar transistor regions 1101 and the fast recovery diode regions 1102 may be arranged alternately, that is, one insulated gate bipolar transistor region 1101 may be arranged adjacent to two fast recovery diode regions 1102, and one fast recovery diode region 1102 may be arranged adjacent to two insulated gate bipolar transistor regions 1101.

[0057] 2) See Figure 3 A carrier storage region 1 is formed in the initial substrate, and a drift region 2 is formed in a portion of the initial substrate located in the carrier storage region 1 away from the first surface 101 .

[0058] In some specific embodiments, the first conductive type ion doping and high temperature well driving process may be performed on the first surface 101 of the initial substrate to form a first conductive type carrier storage region 1 in the initial substrate, and the undoped portion of the initial substrate away from the first surface 101 forms a drift region 2. If the initial substrate is lightly doped with the first conductive type ions, a first conductive type drift region 2 may be formed, and the concentration of the first conductive type ions in the carrier storage region 1 is greater than the doping concentration of the first conductive type ions in the drift region 2.

[0059] like Figure 2 As shown, before forming the carrier storage region 1 , ion implantation may be performed in the initial substrate to form a field limiting ring 110 , and the field limiting ring 110 defines an internal active region 120 .

[0060] In some embodiments, the area ratio of the IGBT region 1101 to the fast recovery diode region 1102 may be 1:1 to 10:1. It should be noted that the area ratio of the IGBT region 1101 to the fast recovery diode region 1102 may be adjusted according to actual conditions.

[0061] 3) See Figure 3 , a well region 3 is formed in the initial substrate, and a surface of the well region 3 away from the carrier storage region 1 is the first surface 101 .

[0062] The first surface 101 of the initial substrate may be doped with second conductivity type ions to form a well region 3 located on the side of the carrier storage region 1 away from the first surface 101 , that is, the carrier storage region 1 is located between the well region 3 and the drift region 2 .

[0063] In some embodiments, the method for forming the well region 3 in the initial substrate may include: forming a first well region 31 located in the gate bipolar transistor region of the insulating layer 5 and a second well region 32 located in the fast recovery diode region 1102, wherein the ion concentration of the first well region 31 is greater than the ion concentration of the second well region 32. The higher ion concentration of the insulated gate bipolar transistor region 1101 is conducive to the generation of channel inversion and conductivity modulation effects, and the lower ion concentration of the fast recovery diode region 1102 is conducive to reducing the reverse recovery time of the device.

[0064] In some embodiments, the concentration of the second conductive type ions in the first well region 31 is

[0065] 1e 13 cm -2 ~5e 13 cm -2 , the concentration of the second conductive type ions in the second well region 32 is 1e 12 cm -2 ~8e 12 cm -2 .

[0066] It should be noted that the ion doping dosage (or concentration) in the first well region 31 and the second well region 32 can be adjusted according to actual conditions.

[0067] Specifically, the initial substrate of the IGBT region 1101 and the fast recovery diode region 1102 may be firstly subjected to a first ion implantation; and then the initial substrate of the IGBT region 1101 may be subjected to a second ion implantation, so that the ion concentration of the IGBT region 1101 is higher. The concentration of the second conductive type ions implanted in the first ion implantation is

[0068] 2e 13 cm -2 ~3e 13 cm -2 The concentration of the second conductivity type ions in the second ion implantation is 2e 13 cm -2 ~3e 13 cm -2 .

[0069] In some embodiments, the method for forming the reverse conducting insulated gate bipolar transistor may further include: before forming the well region 3, forming a gate trench 41 penetrating a portion of the substrate 100 on one side of the first surface 101, the gate trench 41 being located in the insulated gate bipolar transistor region 1101; and forming a gate structure 41a in the gate trench 41.

[0070] In some embodiments, the method for forming the reverse conducting insulated gate bipolar transistor may further include: before forming the well region 3, forming a first virtual trench 42, a second virtual trench 43 and a third virtual trench 44 that penetrate a portion of the substrate 100 on one side of the first surface 101, the first virtual trench 42 and the second virtual trench 43 being located in the insulated gate bipolar transistor region 1101, and the third virtual trench 44 being located in the fast recovery diode region 1102; forming a first virtual gate structure 42a in the first virtual trench 42, forming a second virtual gate structure 43a in the second virtual trench 43, and forming a third virtual gate structure 44a in the third virtual trench 44.

[0071] Specifically, the gate trench 41, the first dummy trench 42, the second dummy trench 43, and the third dummy trench 44 can be formed in the same process. For example, the first surface 101 of the substrate 100 is etched to form the gate trench 41, the first dummy trench 42, the second dummy trench 43 located in the insulated gate bipolar transistor region 1101, and the third dummy trench 44 located in the fast recovery diode region 1102. Among them, the gate trench 41, the first dummy trench 42, the second dummy trench 43, and the third dummy trench 44 can be arranged at intervals, and the trenches can be arranged at equal intervals or at unequal intervals.

[0072] Specifically, an insulating layer 5 is first formed on the inner wall of these grooves, and then a conductive layer 6 is formed on the surface of the insulating layer 5. The process of forming the insulating layer 5 can be: first, a sacrificial oxide layer is grown on the inner wall of each groove by high temperature oxidation; the sacrificial oxide layer is etched away by wet method, so as to reduce the crystal defects and impurities on the inner wall of the groove, and expose the substrate 100 material with better quality; and a layer of oxide layer is grown on the inner wall of each groove area by high temperature oxidation to form the insulating layer 5. This process can form an insulating layer 5 with good density. The thickness of the insulating layer 5 can be

[0073] Afterwards, a layer of polysilicon doped with the first conductivity type ions may be deposited on the surface of the insulating layer 5 as the conductive layer 6. Specifically, the conductive layer 6 is formed by depositing polysilicon in the trenches through a high-temperature furnace tube and performing in-situ doping.

[0074] In some embodiments, the method for forming the reverse conducting insulated gate bipolar transistor may further include: forming an emitter region 7 on the sidewall of the gate trench 41 by ion implantation.

[0075] Specifically, an injection window (or a patterned mask layer) of the emitter region 7 is formed on the first surface 101 by a photolithography process, and the injection window corresponds to both sides of the gate trench 41; high-energy first conductive type ions are injected into the injection window of the emitter region 7 and pushed out at high temperature, thereby forming a first conductive type highly doped emitter region 7 on the sidewall of the gate trench 41. The concentration of the first conductive type ions is 1e 15 cm -2 ~5e 15 cm -2 .

[0076] Step S2: forming a dielectric layer 8 on the first surface 101 of the insulated gate bipolar transistor region 1101, wherein the dielectric layer 8 exposes the first surface 101 of the fast recovery diode region 1102. Figure 4 .

[0077] In some embodiments, step S2 may include: forming an initial dielectric layer on the first surface 101 of the insulated gate bipolar transistor region 1101 and the fast recovery diode region 1102; removing the initial dielectric layer on the first surface 101 of the fast recovery diode region 1102 to form the dielectric layer 8 located in the insulated gate bipolar transistor region 1101. The material of the initial dielectric layer may include one or more combinations of oxides and nitrides, and the initial dielectric layer may also be other insulating materials. After forming the gate structure 41a and the subsequent emitter electrode layer 15, the dielectric layer 8 in the insulated gate bipolar transistor region 1101 can be used to isolate the gate structure 41a from the emitter electrode layer 15.

[0078] Since the initial dielectric layer of the first surface 101 of the fast recovery diode region 1102 is removed, that is, the fast recovery diode region 1102 has no dielectric layer 8, the subsequently formed emitter electrode layer 15 can contact the fast recovery diode region 1102 substrate 100 and serve as the anode of the fast recovery diode region 1102 device.

[0079] Specifically, the initial dielectric layer of all fast recovery diode regions 1102 can be removed so that the first surface 101 of the fast recovery diode region 1102 is completely exposed. This is beneficial to the formation process of the carrier lifetime control region 9. The range of the carrier lifetime control region 9 can be larger, and the effect of reducing the carrier lifetime of the fast recovery diode region 1102 is better.

[0080] Step S3: After forming the dielectric layer 8, a carrier lifetime control region 9 is formed in the substrate 100 of the fast recovery diode region 1102. Figure 5 .

[0081] In some embodiments, step S3 may include: depositing a platinum layer 10 on the dielectric layer 8 and the first surface 101 of the fast recovery diode region 1102; removing the platinum layer 10 on the surface of the dielectric layer 8 and the first surface 101; after removing the platinum layer 10, performing proton (H+) irradiation on one side of the first surface 101 of the substrate 100, and the concentration of H+ may be 1e 11 cm -2 ~5e 13 cm -2 ; Annealing treatment is performed to form a platinum-doped carrier lifetime control region 9 having a local concentration distribution in the fast recovery diode region 1102.

[0082] It should be noted that a high temperature deposition process can be used to deposit platinum material to accelerate the diffusion of platinum, so that a portion of platinum diffuses from the first surface 101 into a portion of the substrate 100, so that a portion of platinum metal still exists in the substrate 100 after removing the platinum layer 10 on the first surface 101. Since the dielectric layer 8 is first formed on the first surface 101 of the insulated gate bipolar transistor region 1101 and then the platinum layer 10 is deposited, the diffusion of platinum in the insulated gate bipolar transistor region 1101 can be reduced, thereby reducing the impact on the devices in the insulated gate bipolar transistor region 1101.

[0083] After H+ is injected into the appropriate local position of the fast recovery diode region 1102, a defect distribution with a high concentration will be induced at the end of its range, which is called a defect peak, and the defect density between the irradiated surface and the defect peak is only 10% to 20% of the defect peak, so an induced defect with a local concentration distribution can be formed. After annealing, the platinum in the substrate 100 is absorbed by the induced defects, and a carrier lifetime control region 9 with a local concentration distribution is formed in the substrate 100 of the fast recovery diode region 1102. The embodiment of the present application achieves a better lifetime control effect by introducing a platinum-doped recombination center at an appropriate local position of the fast recovery diode region 1102, and not introducing or introducing very few recombination centers at other positions in the axial direction (the direction parallel to the second surface 102).

[0084] Since the dielectric layer 8 covers the first surface 101 of the insulated gate bipolar transistor region 1101, proton injection into the insulated gate bipolar transistor region 1101 can be reduced. That is, the embodiment of the present application utilizes the dielectric layer 8 to protect the insulated gate bipolar transistor region 1101 from proton radiation without adding additional process steps.

[0085] It should be noted that the process of removing the initial dielectric layer of the fast recovery diode region 1102 to form the dielectric layer 8 can make the subsequently formed emitter electrode layer 15 contact the second well region 32 and serve as the positive electrode of the fast recovery diode device. The embodiment of the present application uses the dielectric layer 8 as a barrier layer of the insulated gate bipolar transistor region 1101 during the proton irradiation process, which can not only reduce the carrier lifetime of the fast recovery diode region 1102, but also reduce the impact on the carrier lifetime of the insulated gate bipolar transistor region 1101, and does not need to add additional process steps.

[0086] like Figure 5 As shown, the method for forming the carrier lifetime control region 9 also includes: before the proton irradiation, depositing a sacrificial layer 11 on the surface of the dielectric layer 8 and the first surface 101; removing the sacrificial layer 11 on the first surface 101 to retain the sacrificial layer 11 on the surface of the dielectric layer 8; before the annealing treatment, removing the sacrificial layer 11 on the surface of the dielectric layer 8. Thus, the sacrificial layer 11 on the surface of the dielectric layer 8 can enhance the protection of the insulated gate bipolar transistor region 1101, further reduce the protons injected into the insulated gate bipolar transistor region 1101, and reduce the carrier lifetime in the fast recovery diode region 1102, while further reducing the impact on the carrier lifetime in the insulated gate bipolar transistor region 1101, reducing the leakage current of the device, and improving the device performance.

[0087] In some embodiments, the material of the sacrificial layer 11 may include photoresist, may include a mask layer (eg, silicon nitride), or may include a stack of a mask layer and a photoresist.

[0088] In some embodiments, the dielectric layer 8 may be formed by a photolithography process, that is, an initial photoresist layer is first formed on the initial dielectric layer, and then the initial photoresist layer of the fast recovery diode region 1102 is removed by a photolithography process, and then the initial dielectric layer of the fast recovery diode region 1102 is removed by an etching process, so that the initial photoresist layer of the insulated gate bipolar transistor region 1101 forms the photoresist layer, and the initial dielectric layer of the insulated gate bipolar transistor region 1101 forms the dielectric layer 8. Therefore, the embodiment of the present application uses the formation process of the dielectric layer 8 to form the photoresist layer, and no additional process is required.

[0089] Similarly, the dielectric layer 8 may also be formed by using a photolithography process and an etching process, that is, firstly forming an initial mask layer and an initial photoresist layer on the initial dielectric layer in sequence, then using a photolithography process to remove the initial photoresist layer of the fast recovery diode region 1102, and then using an etching process to remove the initial mask layer and the initial dielectric layer of the fast recovery diode region 1102. Therefore, the initial photoresist layer of the insulated gate bipolar transistor region 1101 forms the photoresist layer, the initial mask layer of the insulated gate bipolar transistor region 1101 forms the mask layer, and the initial dielectric layer of the insulated gate bipolar transistor region 1101 forms the dielectric layer 8. Therefore, the embodiment of the present application uses the process for forming the dielectric layer 8 to form the photoresist layer and the mask layer, and no additional process is required.

[0090] See also Figure 6 The method for forming the reverse conducting insulated gate bipolar transistor may also include: after forming the carrier lifetime control region 9, etching the dielectric layer 8 of the insulated gate bipolar transistor region 1101 to form a first contact hole exposing the emitter region 7; forming an ohmic contact region 12 at the bottom of the first contact hole, the ohmic contact region 12 being connected to the emitter region 7; and forming the first contact structure 13 in the first contact hole.

[0091] Specifically, the second conductive type doped ohmic contact region 12 may be formed by injecting the second conductive type ions into the first contact hole, thereby reducing the contact resistance.

[0092] The method for forming the reverse conducting insulated gate bipolar transistor may further include: after forming the carrier lifetime control region 9, etching the dielectric layer 8 of the insulated gate bipolar transistor region 1101 to form a second contact hole exposing the first virtual gate structure 42a; forming a second contact structure 141 in the second contact hole, and the second contact structure 141 is connected to the first virtual gate structure 42a.

[0093] The method for forming the reverse conducting insulated gate bipolar transistor may further include: forming an emitter electrode layer 15 on the surface of the dielectric layer 8 and the first surface 101 of the fast recovery diode region 1102 .

[0094] Specifically, a layer of metal with a thickness of 1um to 5um can be deposited to form the emitter electrode layer 15. The metal can be an aluminum / silicon alloy or an aluminum / silicon / copper alloy or other materials. By heating, a good ohmic contact is formed between the ohmic contact area 12 and the emitter electrode layer 15, thereby further reducing the contact resistance and making the various metals of the alloy better combined.

[0095] Specifically, the first contact hole and the second contact hole can be formed in the same etching process, that is, the first contact hole and the second contact hole can be formed by etching the dielectric layer 8. The cross-sectional shape of the first contact hole and the second contact hole along the direction perpendicular to the second surface 102 can be a rectangular groove, a trapezoidal groove, a conical groove or a special-shaped groove.

[0096] Specifically, the first contact structure 13 and the second contact structure 141 may be formed in the process of forming the emitter electrode layer 15 , that is, the deposited metal forms the first contact structure 13 and the second contact structure 141 in the first contact hole and the second contact hole, respectively.

[0097] The first contact structure 13 can realize the connection between the ohmic contact area 12 and the emitter electrode layer 15, thereby leading the emitter area 7 out to connect with the outside. The second contact structure 141 can realize the connection between the first virtual gate structure 42a and the emitter electrode layer 15, thereby forming a floating area, so that the hole concentration in the first well region 31 of the insulated gate bipolar transistor region 1101 increases. Due to the existence of the conductivity modulation effect, the electron concentration will also increase, thereby reducing the forward conduction voltage drop of the device. The second virtual gate structure 43a can reduce the channel electron current, thereby reducing the short-circuit current of the device. The third virtual gate structure 44a can balance the overall structure and prevent uneven stress distribution from causing cracks. Among them, Figure 6 As shown, a third contact structure 142 and an ohmic contact region 12 located at the bottom of the third contact structure 142 are formed between the first dummy gate structure 42a and the second dummy gate structure 43a, thereby facilitating the upward extraction of holes.

[0098] See also Figure 7 The method for forming the reverse conducting insulated gate bipolar transistor may further include: performing ion implantation on the second surface 102 of the substrate 100 to form a collector region 16 located in the insulated gate bipolar transistor region 1101 and a short-circuit region 17 located in the fast recovery diode region 1102; performing ion implantation on the second surface 102 of the substrate 100 to form a field termination region 18, and the surfaces of the collector region 16 and the short-circuit region 17 away from the field termination region 18 are the second surface 102; and forming a collector layer 19 on the second surface 102 of the substrate 100.

[0099] Specifically, the substrate 100 (i.e., the drift region 2) on the second surface 102 may be thinned first, and then the second conductive type ion implantation and high temperature well driving process may be performed on the second surface 102 to form a collector region 16 doped with a high concentration of the second conductive type in the insulated gate bipolar transistor region 1101. The ion doping concentration of the collector region 16 may be 1e 18 cm -3 ~5e19 cm -3 The junction depth is 0.5um~1um, which can control the emission injection efficiency.

[0100] Specifically, a first conductive type high-concentration doped short-circuit region 17 is formed in the fast recovery diode region 1102 by first conductive type ion implantation and high-temperature well-driving process on the second surface 102. The doping concentration of the short-circuit region 17 can be 1e 18 cm -3 ~5e 19 cm -3 .

[0101] Specifically, a first conductive type doped field stop region 18 is formed on the second surface 102 by ion implantation, and the ion implantation dose is 5e 12 cm -2 ~8e 13 cm -2 The ion implantation process of the field stop region 18 may be performed after the ion implantation process of the collector region 16 and the short-circuit region 17 , or may be performed before the ion implantation process of the collector region 16 and the short-circuit region 17 .

[0102] In some embodiments, the cross-sectional shape of the short-circuit region 17 along a direction perpendicular to the second surface 102 may be circular, triangular, rectangular, trapezoidal, annular, star-shaped, or polygonal.

[0103] The present application also provides a reverse conducting insulated gate bipolar transistor. The reverse conducting insulated gate bipolar transistor can be prepared by the formation method of any of the above embodiments. Figure 7 .

[0104] The reverse conducting insulated gate bipolar transistor comprises: a substrate 100, comprising a first surface 101 and a second surface 102 opposite to each other, and the substrate 100 comprises an insulated gate bipolar transistor region 1101 and a fast recovery diode region 1102; a dielectric layer 8, covering the first surface 101 of the insulated gate bipolar transistor region 1101 and exposing the first surface 101 of the fast recovery diode region 1102; and a carrier lifetime control region 9, located in the substrate 100 in the fast recovery diode region 1102.

[0105] The embodiment of the present application utilizes the dielectric layer 8 to protect the insulated gate bipolar transistor region 1101, so that the carrier lifetime control region 9 can be formed only in the fast recovery diode region 1102, while reducing the impact on the carrier lifetime of the insulated gate bipolar transistor region 1101. Not only can the reverse recovery time of the fast recovery diode region 1102 be reduced and the device softness be improved, but also the leakage current of the device can be reduced, so that the device has better high temperature stability and reliability, and the overall performance of the device is improved.

[0106] Can be combined Figure 8 and Fig. 9 , Figure 8 is a schematic diagram of a cross-sectional structure of a reverse conducting insulated gate bipolar transistor in an insulated gate bipolar transistor region provided by some embodiments of the present application, Fig. 9 It is a schematic diagram of the cross-sectional structure of a reverse conducting insulated gate bipolar transistor in a fast recovery diode region provided in some embodiments of the present application.

[0107] In some embodiments, the substrate 100 includes a drift region 2, a carrier storage region 1, and a well region 3 stacked in sequence, and the surface of the well region 3 away from the drift region 2 is the first surface 101. The conductivity type of the doped ions in the drift region 2 and the carrier storage region 1 is the same, and the conductivity type of the doped ions in the well region 3 is opposite to the conductivity type of the doped ions in the carrier storage region 1.

[0108] The substrate 100 may further include a collector region 16, a short-circuit region 17, a field stop region 18 and a collector layer 19, wherein the collector region 16 is located in the insulated gate bipolar transistor region 1101, the short-circuit region 17 is located in the fast recovery diode region 1102, the surfaces of the collector region 16 and the short-circuit region 17 away from the field stop region 18 are the second surface 102, and the collector layer 19 is located in the second surface 102 of the substrate 100. The conductivity type of the doped ions in the collector region 16 is the same as the conductivity type of the doped ions in the well region 3, the conductivity type of the doped ions in the collector region 16 is opposite to the conductivity type of the doped ions in the short-circuit region 17, and the conductivity type of the doped ions in the field stop region 18 is the same as the conductivity type of the doped ions in the drift region 2.

[0109] In some embodiments, the carrier lifetime control region 9 is located in at least one of the drift region 2 , the carrier storage region 1 and the well region 3 .

[0110] In some embodiments, the carrier lifetime control region 9 is doped with platinum.

[0111] In some embodiments, the insulated gate bipolar transistor region 1101 includes an ohmic contact region 12, and the reverse conducting insulated gate bipolar transistor also includes a first contact structure 13, which is located in the insulated gate bipolar transistor region 1101 and penetrates the dielectric layer 8 to connect with the ohmic contact region 12.

[0112] The reverse conducting insulated gate bipolar transistor may further include an emitter electrode layer 15, and the emitter electrode layer 15 covers the dielectric layer 8 and the first surface 101 of the fast recovery diode region 1102. One end of the first contact structure 13 is connected to the ohmic contact region 12, and the other end of the first contact structure 13 is connected to the emitter electrode layer 15.

[0113] The reverse conducting insulated gate bipolar transistor may further include a gate structure 41a and an emitter region 7, wherein the gate structure 41a is located in the insulated gate bipolar transistor region 1101 and penetrates a portion of the substrate 100, and the dielectric layer 8 covers an end of the gate structure 41a. The emitter region 7 is located on a sidewall of the gate structure 41a and is connected to the ohmic contact region 12.

[0114] The reverse-conducting insulated gate bipolar transistor has a conversion process from unipolar to bipolar conduction mode. When the gate is turned on, the channel in the first well region 31 is inverted to form an electronic channel, and the electrons migrate to the collector layer 19 under the drive of the electric field; due to the built-in electric field of the PN junction formed by the collector region 16 and the field termination region 18, the electrons are more inclined to flow into the collector layer 19 through the short-circuit region 17; when the current is small, the electrons all flow into the collector layer 19 through the short-circuit region 17; as the current increases, the voltage drop generated by the electronic current on the field termination region 18 gradually increases, and when it increases to the turn-on voltage of the PN junction, the device is in a critical state of switching from unipolar to bipolar; at this time, the electrons injected into the collector region 16 begin to become active, and a large amount of hole current is injected into the field termination region 18 and the drift region 2, resulting in the generation of conductivity modulation, and the device enters the bipolar working mode.

[0115] Among them, the fast recovery diode of the fast recovery diode area 1102 includes a second well area 32 and a short-circuit area 17, and the emitter electrode layer 15 serves as the positive electrode of the second well area 32, and the collector layer 19 serves as the negative electrode of the short-circuit area 17. The fast recovery diode plays the role of reverse conduction and freewheeling in the reverse conducting insulated gate bipolar transistor.

[0116] The reverse conducting insulated gate bipolar transistor may further include a first dummy gate structure 42a and a second contact structure 141, wherein the first dummy gate structure 42a is located in the insulated gate bipolar transistor region 1101 and penetrates a portion of the substrate 100, and the dielectric layer 8 covers the end of the first dummy gate structure 42a. The second contact structure 141 is located in the insulated gate bipolar transistor region 1101 and penetrates the dielectric layer 8 to connect with the first dummy gate structure 42a.

[0117] The reverse conducting insulated gate bipolar transistor may further include a second dummy gate structure 43a, which is located in the insulated gate bipolar transistor region 1101 and penetrates a portion of the substrate 100, and the dielectric layer 8 covers an end of the second dummy gate structure 43a.

[0118] The reverse conducting insulated gate bipolar transistor may further include a third dummy gate structure 44a, which is located in the fast recovery diode region 1102 and penetrates a portion of the substrate 100, and the emitter electrode layer 15 covers an end of the third dummy gate structure 44a.

[0119] The emitter region 7 is not formed next to the first dummy gate structure 42 a , the end of the second dummy gate structure 43 a is not connected to the emitter electrode layer 15 , and the third dummy gate structure 44 a is connected to the emitter electrode layer 15 but is located in the fast recovery diode region 1102 .

[0120] In some embodiments, Figure 8 As shown, the cell structure of the insulated gate bipolar transistor may include a gate structure 41a and three dummy gate structures (including a first dummy gate structure 42a and a second dummy gate structure 43a). Fig. 9 As shown, the cell structure of the fast recovery diode may include four virtual gate structures (including the second virtual gate structure 43a or the combination of the second virtual gate structure 43a and the third virtual gate structure 44a). It should be noted that the embodiment of the present application does not limit the number of gate structures and virtual gate structures in the cell structure.

[0121] An embodiment of the present application also provides a chip, which includes the reverse conducting insulated gate bipolar transistor in any of the above embodiments. The chip has all the beneficial effects of the above reverse conducting insulated gate bipolar transistor, which will not be described in detail in the present application.

[0122] According to a fourth aspect of the present application, a vehicle is provided, which includes a chip in any one of the above embodiments. The vehicle has all the beneficial effects of the above chips, which will not be described in detail in the present application.

[0123] The vehicle may be a fuel vehicle, a plug-in hybrid vehicle or a new energy vehicle, etc., and this application does not make any specific limitation on this.

[0124] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0125] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0127] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A method for forming a reverse conducting insulated gate bipolar transistor, characterized in that: include: Forming a substrate (100), wherein the substrate (100) comprises a first surface (101) and a second surface (102) opposite to each other, and the substrate (100) comprises an insulated gate bipolar transistor region (1101) and a fast recovery diode region (1102); forming a dielectric layer (8) on the first surface (101) of the insulated gate bipolar transistor region (1101), wherein the dielectric layer (8) exposes the first surface (101) of the fast recovery diode region (1102); After forming the dielectric layer (8), a carrier lifetime control region (9) is formed in the substrate (100) of the fast recovery diode region (1102).

2. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 1, wherein: The method for forming a dielectric layer (8) on the first surface (101) of the insulated gate bipolar transistor region (1101) comprises: forming an initial dielectric layer on the first surface (101) of the insulated gate bipolar transistor region (1101) and the fast recovery diode region (1102); The initial dielectric layer on the first surface (101) of the fast recovery diode region (1102) is removed to form the dielectric layer (8) located in the insulated gate bipolar transistor region (1101).

3. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 1, wherein: The method for forming a carrier lifetime control region (9) in the substrate (100) of the fast recovery diode region (1102) comprises: Depositing a platinum layer (10) on the dielectric layer (8) and the first surface (101) of the fast recovery diode region (1102); removing the platinum layer (10) on the surface of the dielectric layer (8) and the first surface (101); After removing the platinum layer (10), performing proton irradiation on one side of the first surface (101) of the substrate (100); Annealing is performed to form a platinum-doped carrier lifetime control region (9) having a local concentration distribution in the fast recovery diode region (1102).

4. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 3, characterized in that: The method for forming a carrier lifetime control region (9) in the substrate (100) of the fast recovery diode region (1102) further comprises: Before the proton irradiation is performed, a sacrificial layer (11) is deposited on the surface of the dielectric layer (8) and the first surface (101); removing the sacrificial layer (11) on the first surface (101) to retain the sacrificial layer (11) located on the surface of the dielectric layer (8); Before the annealing process is performed, the sacrificial layer (11) on the surface of the dielectric layer (8) is removed.

5. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 1, wherein: A method of forming a substrate (100) comprises: Providing an initial substrate, the initial substrate comprising the first surface (101) and the second surface (102) opposite to each other; A carrier storage region (1) is formed in the initial substrate, and a drift region (2) is formed in a portion of the initial substrate located away from the first surface (101) and away from the carrier storage region (1); A well region (3) is formed in the initial substrate, and a surface of the well region (3) away from the carrier storage region (1) is the first surface (101).

6. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 5, characterized in that: The initial substrate includes an insulated gate bipolar transistor region (1101) and a fast recovery diode region (1102); The method for forming a well region (3) in the initial substrate comprises: forming a first well region (31) located in the insulated gate bipolar transistor region (1101) and a second well region (32) located in the fast recovery diode region (1102), wherein the ion concentration of the first well region (31) is greater than the ion concentration of the second well region (32).

7. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 6, wherein: The method for forming the first well region (31) and the second well region (32) comprises: Performing a first ion implantation on the initial substrate of the insulated gate bipolar transistor region (1101) and the fast recovery diode region (1102); A second ion implantation is performed on the initial substrate of the insulated gate bipolar transistor region (1101).

8. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 5, characterized in that: Also includes: Before forming the well region (3), forming a gate trench (41) penetrating a portion of the substrate (100) on one side of the first surface (101), the gate trench (41) being located in the insulated gate bipolar transistor region (1101); A gate structure (41a) is formed in the gate trench (41).

9. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 8, characterized in that: Also includes: An emission region (7) is formed on the side wall of the gate trench (41) by ion implantation.

10. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 9, characterized in that: Also includes: After forming the carrier lifetime control region (9), etching the dielectric layer (8) of the insulated gate bipolar transistor region (1101) to form a first contact hole exposing the emitter region (7); An ohmic contact region (12) is formed at the bottom of the first contact hole, wherein the ohmic contact region (12) is connected to the emitter region (7); A first contact structure (13) is formed in the first contact hole.

11. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 5, wherein: Also includes: Before forming the well region (3), a first virtual trench (42), a second virtual trench (43) and a third virtual trench (44) penetrating a portion of the substrate (100) are formed on one side of the first surface (101), the first virtual trench (42) and the second virtual trench (43) being located in the insulated gate bipolar transistor region (1101), and the third virtual trench (44) being located in the fast recovery diode region (1102); A first dummy gate structure (42a) is formed in the first dummy trench (42), a second dummy gate structure (43a) is formed in the second dummy trench (43), and a third dummy gate structure (44a) is formed in the third dummy trench (44).

12. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 11, characterized in that: Also includes: After forming the carrier lifetime control region (9), etching the dielectric layer (8) of the insulated gate bipolar transistor region (1101) to form a second contact hole exposing the first dummy gate structure (42a); A second contact structure (141) is formed in the second contact hole, and the second contact structure (141) is connected to the first dummy gate structure (42a).

13. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 1, wherein: Also includes: An emitter electrode layer (15) is formed on the surface of the dielectric layer (8) and the first surface (101) of the fast recovery diode region (1102).

14. The method for forming a reverse conducting insulated gate bipolar transistor according to claim 1, wherein: Also includes: Performing ion implantation on the second surface (102) of the substrate (100) to form a collector region (16) located in the insulated gate bipolar transistor region (1101) and a short-circuit region (17) located in the fast recovery diode region (1102); Ion implantation is performed on the second surface (102) of the substrate (100) to form a field termination region (18), and the surfaces of the collector region (16) and the short-circuit region (17) away from the field termination region (18) are the second surface (102); A collector layer (19) is formed on the second surface (102) of the substrate (100).

15. A reverse conducting insulated gate bipolar transistor, characterized in that: include: A substrate (100) comprising a first surface (101) and a second surface (102) opposite to each other, and the substrate (100) comprises an insulated gate bipolar transistor region (1101) and a fast recovery diode region (1102); A dielectric layer (8), covering the first surface (101) of the insulated gate bipolar transistor region (1101) and exposing the first surface (101) of the fast recovery diode region (1102); A carrier lifetime control region (9) is located in the substrate (100) of the fast recovery diode region (1102).

16. The reverse conducting insulated gate bipolar transistor according to claim 15, characterized in that: The insulated gate bipolar transistor region (1101) includes an ohmic contact region (12); the reverse conducting insulated gate bipolar transistor also includes: The first contact structure (13) is located in the insulated gate bipolar transistor region (1101) and penetrates the dielectric layer (8) to be connected to the ohmic contact region (12).

17. The reverse conducting insulated gate bipolar transistor according to claim 16, characterized in that: Also includes: An emitter electrode layer (15), covering the dielectric layer (8) and the first surface (101) of the fast recovery diode region (1102); One end of the first contact structure (13) is connected to the ohmic contact region (12), and the other end of the first contact structure (13) is connected to the emitter electrode layer (15).

18. The reverse conducting insulated gate bipolar transistor according to claim 15, characterized in that: The substrate (100) comprises a drift region (2), a carrier storage region (1) and a well region (3) stacked in sequence, wherein a surface of the well region (3) away from the drift region (2) is the first surface (101); The carrier lifetime control region (9) is located in at least one of the drift region (2), the carrier storage region (1) and the well region (3).

19. The reverse conducting insulated gate bipolar transistor according to claim 16, characterized in that: Also includes: A gate structure (41a) is located in the insulated gate bipolar transistor region (1101) and penetrates a portion of the substrate (100), and the dielectric layer (8) covers an end portion of the gate structure (41a); The emission region (7) is located on the side wall of the gate structure (41a) and is connected to the ohmic contact region (12).

20. The reverse conducting insulated gate bipolar transistor according to claim 15, characterized in that: Also includes: A first dummy gate structure (42a) is located in the insulated gate bipolar transistor region (1101) and penetrates a portion of the substrate (100), and the dielectric layer (8) covers an end portion of the first dummy gate structure (42a); The second contact structure (141) is located in the insulated gate bipolar transistor region (1101) and penetrates the dielectric layer (8) to be connected to the first dummy gate structure (42a).

21. The reverse conducting insulated gate bipolar transistor according to claim 15, characterized in that: Also includes: The second dummy gate structure (43a) is located in the insulated gate bipolar transistor region (1101) and penetrates a portion of the substrate (100), and the dielectric layer (8) covers the end of the second dummy gate structure (43a).

22. The reverse conducting insulated gate bipolar transistor according to claim 17, characterized in that: Also includes: The third virtual gate structure (44a) is located in the fast recovery diode region (1102) and penetrates a portion of the substrate (100), and the emitter electrode layer (15) covers the end of the third virtual gate structure (44a).

23. The reverse conducting insulated gate bipolar transistor according to claim 15, characterized in that: The carrier lifetime control region (9) is doped with platinum.

24. A chip, characterized in that: It comprises the reverse conducting insulated gate bipolar transistor as claimed in any one of claims 15 to 23.

25. A vehicle, characterized in that: Comprising the chip as claimed in claim 24.

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